Updated Environment Variables

flist/nanosoc/nanosoc_chip_ip.flist

@@ -34,6 +34,6 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
 
-//$(NANOSOC_TECH_DIR)/system/aes/src/nanosoc_exp_wrapper.v
-//+incdir+$(PROJECT_DIR)/secworks-aes/src/rtl
-//$(NANOSOC_TECH_DIR)/system/aes/src/soclabs_ahb_aes128_ctrl.v
+//$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/src/nanosoc_exp_wrapper.v
+//+incdir+$(SOCLABS_PROJECT_DIR)/secworks-aes/src/rtl
+//$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/src/soclabs_ahb_aes128_ctrl.v

flist/project/accelerator.flist

@@ -12,6 +12,6 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-$(PROJECT_DIR)/system/src/nanosoc_exp_wrapper.v
-+incdir+$(PROJECT_DIR)/secworks-aes/src/rtl
-$(PROJECT_DIR)/system/src/soclabs_ahb_aes128_ctrl.v
+$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp_wrapper.v
++incdir+$(SOCLABS_PROJECT_DIR)/secworks-aes/src/rtl
+$(SOCLABS_PROJECT_DIR)/system/src/soclabs_ahb_aes128_ctrl.v

flist/project/system_tb.flist

@@ -16,20 +16,20 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/system/verif/verilog/
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/
 
 // - Top-level project-specific testbench
-$(PROJECT_DIR)/system/verif/verilog/nanosoc_tb.v
-$(PROJECT_DIR)/system/verif/verilog/aes128_log_to_file.v
+$(SOCLABS_PROJECT_DIR)/system/verif/verilog/nanosoc_tb.v
+$(SOCLABS_PROJECT_DIR)/system/verif/verilog/aes128_log_to_file.v
 
 // - Testbench components
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
 
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_acc_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_acc_log_to_file.v

system/cpu_software/aes128_tests/makefile

@@ -32,7 +32,7 @@
 CPU_PRODUCT = CORTEX_M0
 
 # Shared software directory
-SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
 CMSIS_DIR    = $(SOFTWARE_DIR)/cmsis
 CORE_DIR     = $(CMSIS_DIR)/CMSIS/Include