Re-played changes from commit revert on Accelerator Project

flist/nanosoc/nanosoc_chip_ip.flist

@@ -31,4 +31,5 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
 
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -30,4 +30,5 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streami
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/verif/aes128_log_to_file.v
\ No newline at end of file

simulate/socsim/system_secworks_aes128.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+cd $PROJECT_DIR/simulate/sim/$PROJECT_DIR
+
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+echo ${2}
+make -C $NANOSOC_TECH_DIR/system run_mti \
+    SIM_DIR=$SIM_DIR \
+    ${@:2}
+

wrapper/src/wrapper_accelerator.sv

@@ -14,7 +14,8 @@ module wrapper_accelerator #(
   parameter INPACKETWIDTH=512,
   parameter CFGSIZEWIDTH=64,
   parameter CFGSCHEMEWIDTH=2,
-  parameter OUTPACKETWIDTH=256
+  parameter OUTPACKETWIDTH=256,
+  parameter CFGNUMIRQ=4
   ) (
     input  logic                     HCLK,       // Clock
     input  logic                     HRESETn,    // Reset
@@ -34,10 +35,15 @@ module wrapper_accelerator #(
     output logic  [31:0]             HRDATAS,
 
     // Input Data Request Signal to DMAC
-    output logic                     in_data_req,
+    output logic                     in_data_drq,
+    input  logic                     in_data_dlast,
 
     // Output Data Request Signal to DMAC
-    output logic                     out_data_req
+    output logic                     out_data_drq,
+    input  logic                     out_data_dlast,
+
+    output logic [CFGNUMIRQ-1:0]     int_irq
+    
   );
   
 
@@ -430,17 +436,17 @@ module wrapper_accelerator #(
     .req_act_ch4 (1'b0),
 
     // DMA Request Output
-    .drq_ch0     (in_data_req),
-    .drq_ch1     (out_data_req),
+    .drq_ch0     (in_data_drq),
+    .drq_ch1     (out_data_drq),
     .drq_ch2     (),
     .drq_ch3     (),
     .drq_ch4     (),
 
     // Interrupt Request Output
-    .irq_ch0     (),
-    .irq_ch1     (),
-    .irq_ch2     (),
-    .irq_ch3     (),
+    .irq_ch0     (int_irq[0]),
+    .irq_ch1     (int_irq[1]),
+    .irq_ch2     (int_irq[2]),
+    .irq_ch3     (int_irq[3]),
     .irq_ch4     (),
     .irq_merged  ()
   );