Update filelists for generaic acc_to_log

flist/nanosoc/nanosoc_chip_ip.flist

@@ -32,4 +32,8 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
 
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/src/nanosoc_exp_wrapper.v
++incdir+$(PROJECT_DIR)/secworks-aes/src/rtl
+$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/src/soclabs_ahb_aes128_ctrl.v

flist/nanosoc/nanosoc_tb.flist

@@ -31,4 +31,5 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/verif/aes128_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_acc_log_to_file.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/verif/aes128_log_to_file.v

simulate/socsim/system_secworks_aes128.sh

@@ -24,7 +24,7 @@ cd $PROJECT_DIR/simulate/sim/$PROJECT_DIR
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
 echo ${2}
-make -C $NANOSOC_TECH_DIR/system run_mti \
+make -C $NANOSOC_TECH_DIR/system run_xm \
     SIM_DIR=$SIM_DIR \
     ${@:2}
 

socsim_flow @ 93edf21c

+Subproject commit 93edf21c102f6267d34c0ff6b5175104b3354902