- 05 Jul, 2021 1 commit
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Minyong Li authored
The top level should pass all parameter down.
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- 25 Jun, 2021 1 commit
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Minyong Li authored
- add a companion object for less verbose cw decl - add a read port for pm - test improvements - naming improvements
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- 24 Jun, 2021 1 commit
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Minyong Li authored
This allows switching between Mem (usually synthesized into register groups) and SyncReadMem (usually synthesized into FPGA block memories).
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- 17 Jun, 2021 1 commit
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Minyong Li authored
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- 13 Jun, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
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