core.*Round: add quarter round type configs

src/main/scala/uk/ac/soton/ecs/can/config/CanCoreConfiguration.scala

@@ -10,5 +10,6 @@ case class CanCoreConfiguration(
     syncReadMemory: Boolean,
     regAfterBlockInitializer: Boolean,
     regBetweenRounds: Boolean,
-    regAfterAdder: Boolean
+    regAfterAdder: Boolean,
+    quarterRoundType: Int
 )

src/main/scala/uk/ac/soton/ecs/can/core/BaseRound.scala

@@ -4,8 +4,10 @@
 package uk.ac.soton.ecs.can.core
 
 import chisel3._
+import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 
-abstract class BaseRound extends MultiIOModule {
+abstract class BaseRound(implicit cfg: CanCoreConfiguration)
+    extends MultiIOModule {
   val in = IO(Input(UInt(512.W)))
   val out = IO(Output(UInt(512.W)))
 
@@ -15,7 +17,13 @@ abstract class BaseRound extends MultiIOModule {
 
   protected def wire(wireBox: Seq[Seq[Int]]): Unit = wireBox.foreach {
     wireSeq =>
-      val quarterRound = Module(new CombinationalQuarterRound)
+      val quarterRound = cfg.quarterRoundType match {
+        case 1 => Module(new CombinationalQuarterRound)
+        case 2 => Module(new TwoStageQuarterRound)
+        case 8 => Module(new EightStageQuarterRound)
+        case _ =>
+          throw new Exception("quarterRoundType should be either 1, 2, or 8")
+      }
       quarterRound.in.zip(quarterRound.out).zip(wireSeq).foreach {
         case ((i, o), w) =>
           i := _in(w)

src/main/scala/uk/ac/soton/ecs/can/core/ColumnarRound.scala

@@ -3,7 +3,9 @@
 
 package uk.ac.soton.ecs.can.core
 
-class ColumnarRound extends BaseRound {
+import uk.ac.soton.ecs.can.config.CanCoreConfiguration
+
+class ColumnarRound(implicit cfg: CanCoreConfiguration) extends BaseRound {
   wire(
     Seq(
       Seq(0, 4, 8, 12),

src/main/scala/uk/ac/soton/ecs/can/core/DiagonalRound.scala

@@ -3,7 +3,9 @@
 
 package uk.ac.soton.ecs.can.core
 
-class DiagonalRound extends BaseRound {
+import uk.ac.soton.ecs.can.config.CanCoreConfiguration
+
+class DiagonalRound(implicit cfg: CanCoreConfiguration) extends BaseRound {
   wire(
     Seq(
       Seq(0, 5, 10, 15),