x2go push

INCA_libs/history

+//
+// File created by:  irun
+// Do not modify this file
+
+s1::(03Sep2020:15:33:56):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s2::(03Sep2020:15:35:12):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s3::(03Sep2020:21:33:20):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s4::(03Sep2020:21:36:23):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s5::(03Sep2020:21:39:17):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s6::(03Sep2020:21:41:11):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s7::(03Sep2020:21:44:33):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s8::(03Sep2020:21:46:45):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s9::(03Sep2020:21:48:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s10::(03Sep2020:22:35:38):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s11::(03Sep2020:22:38:11):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s12::(04Sep2020:01:40:54):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s13::(04Sep2020:15:56:48):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s14::(04Sep2020:18:16:02):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s15::(04Sep2020:18:30:44):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s16::(05Sep2020:15:35:49):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s17::(05Sep2020:15:38:19):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s18::(05Sep2020:16:50:11):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s19::(05Sep2020:16:52:02):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s20::(05Sep2020:17:28:28):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s21::(05Sep2020:17:30:12):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s22::(05Sep2020:17:54:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s23::(05Sep2020:18:00:23):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s24::(05Sep2020:18:02:14):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s25::(05Sep2020:18:03:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s26::(05Sep2020:18:09:48):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s27::(05Sep2020:21:01:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s28::(05Sep2020:21:05:34):( ncverilog ahb_pixel_memory.sv )
+s29::(05Sep2020:21:09:18):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s30::(05Sep2020:21:14:07):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s31::(06Sep2020:19:14:40):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s32::(07Sep2020:10:21:18):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s33::(07Sep2020:11:42:50):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s34::(07Sep2020:11:43:10):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s35::(07Sep2020:11:55:39):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s36::(07Sep2020:15:44:35):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s37::(07Sep2020:15:44:54):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s38::(07Sep2020:15:46:06):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s39::(08Sep2020:09:15:18):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s40::(08Sep2020:09:15:54):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s41::(08Sep2020:09:32:20):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s42::(08Sep2020:09:33:05):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s43::(08Sep2020:09:37:46):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s44::(08Sep2020:09:39:13):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s45::(08Sep2020:09:40:08):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s46::(08Sep2020:11:11:28):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s47::(08Sep2020:11:27:25):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +define+prog_file=software/code.hex -s  )
+s48::(08Sep2020:11:41:12):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s49::(09Sep2020:13:14:30):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s50::(09Sep2020:13:29:21):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s51::(10Sep2020:14:33:58):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s52::(10Sep2020:18:11:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s53::(10Sep2020:18:17:03):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s54::(10Sep2020:18:20:34):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s55::(10Sep2020:18:21:59):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s56::(12Sep2020:14:39:59):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s57::(12Sep2020:14:41:17):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s58::(12Sep2020:14:42:41):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s59::(12Sep2020:14:43:46):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s60::(13Sep2020:14:53:12):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s61::(13Sep2020:15:01:16):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s62::(13Sep2020:15:08:22):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s63::(13Sep2020:15:09:49):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s64::(14Sep2020:11:21:49):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s65::(14Sep2020:11:59:10):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s66::(14Sep2020:12:01:26):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s67::(14Sep2020:12:37:17):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s68::(14Sep2020:13:30:29):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s69::(14Sep2020:13:34:21):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s70::(14Sep2020:13:37:44):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s71::(14Sep2020:16:17:41):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s72::(14Sep2020:22:05:56):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s73::(15Sep2020:11:21:49):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s74::(15Sep2020:11:29:13):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +define+prog_file=software/code.hex -s  )
+s75::(15Sep2020:11:39:36):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +define+prog_file=software/code.hex -s )
+s76::(17Sep2020:10:09:34):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s77::(17Sep2020:10:10:39):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s78::(17Sep2020:10:11:43):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s79::(17Sep2020:14:31:27):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s80::(17Sep2020:16:48:39):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
+s81::(17Sep2020:16:57:17):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )

INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts

+1581871298 /home/ks6n19/Documents/project/behavioural/ahb_switches.sv
+1581871483 /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv
+1562613351 /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv
+1600333835 /home/ks6n19/Documents/project/testbench/arm_soc_stim.sv
+1599064789 /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv
+1599554396 /home/ks6n19/Documents/project/behavioural/ahb_ram.sv
+1599325330 /home/ks6n19/Documents/project/behavioural/ahb_out.sv
+1600333901 /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv
+1600333305 /home/ks6n19/Documents/project/behavioural/arm_soc.sv

INCA_libs/irun.lnx8664.15.20.nc/OVMHOME

+(null)

INCA_libs/irun.lnx8664.15.20.nc/UVMHOME

+(null)

INCA_libs/irun.lnx8664.15.20.nc/cds.lib

+include ./cdsrun.lib
+include ./xllibs/cds.lib

INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/files.ts

+1600333835 /home/ks6n19/Documents/project/testbench/arm_soc_stim.sv

INCA_libs/irun.lnx8664.15.20.nc/hdl.var

+define NCSIMRC	( /eda/cadence/incisiv/tools/inca/files/ncsimrc, ~/.ncsimrc )
+include ./hdlrun.var
+include ./xllibs/hdl.var
+define SNAPSHOT worklib.arm_soc_stim:sv
+DEFINE RUNMODEDEFAULT 1
+DEFINE LIB_MAP ($LIB_MAP, + => worklib )
+define ELAB_SNAPSHOT
+define SNAPSHOT worklib.arm_soc_stim:sv

INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)
+define ELAB_SNAPSHOT
+define SNAPSHOT worklib.arm_soc_stim:sv

INCA_libs/irun.lnx8664.15.20.nc/ncelab.args

+//
+// File created by:  ncverilog
+// Do not modify this file
+//
++libext+.sv
++gui
++ncaccess+r
++tcl+testbench/arm_soc.tcl
++define+prog_file=software/code.hex
+-noshowtop
+-ACCESS
++r
+-MESSAGES
+-XLMODE
+./INCA_libs/irun.lnx8664.15.20.nc
+-RUNMODE
+-CDSLIB
+./INCA_libs/irun.lnx8664.15.20.nc/cds.lib
+-HDLVAR
+./INCA_libs/irun.lnx8664.15.20.nc/hdl.var
+-WORK
+worklib
+-HASXLMODE

INCA_libs/irun.lnx8664.15.20.nc/ncelab.env

+#!/bin/csh
+#
+# File created by:  ncverilog
+# Do not modify this file
+#
+#<< :  <#3 ncverilog:/home/ks6n19/Documents/project/INCA_libs/irun.lnx8664.15.20.nc>#> <#3 ncverilog:./INCA_libs/irun.lnx8664.15.20.nc>#>
+setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.20.nc"
+#<< :  <#3 TRUE>#>
+setenv IRUNBATCH "TRUE"

INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd

+//
+// File created by:  ncverilog
+// Do not modify this file
+//
+-ACCESS
++r