Skip to content
Snippets Groups Projects
Commit 4dc49816 authored by ks6n19's avatar ks6n19
Browse files

removed pragma and put stdbool

parent 6b809782
Branches
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 693 additions and 73 deletions
.nfs000000004ff0ee0f0000663e 0 → 100644
+ 94
− 0
View file @ 4dc49816
ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
TOOL: ncverilog 15.20-s058: Started on Oct 10, 2020 at 16:21:48 BST
ncverilog
-sv
+gui
+ncaccess+r
-y
behavioural
+libext+.sv
+define+prog_file=software/code.hex
testbench/de1_soc_wrapper_stim.sv
-s
Caching library 'behavioural' ....... Done
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
de1_soc_wrapper dut(.CLOCK_50, .LEDR, .SW, .KEY, .HEX0, .HEX1, .HEX2, .HEX3,.VGA_R, .VGA_G, .VGA_B, .VGA_HS, .VGA_VS, .VGA_CLK, .VGA_BLANK_N);
|
ncelab: *W,CUVMPW (./testbench/de1_soc_wrapper_stim.sv,20|48): port sizes differ in port connection (3/4).
Building instance overlay tables: .................... Done
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 10 10
Registers: 919 919
Scalar wires: 11159 -
Expanded wires: 122 6
Vectored wires: 51 -
Always blocks: 858 858
Initial blocks: 3 3
Cont. assignments: 973 11132
Pseudo assignments: 22 22
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.de1_soc_wrapper_stim:sv
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim>
ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
ncsim>
-------------------------------------
Relinquished control to SimVision...
# Restoring simulation environment...
ncsim> input {testbench/de0_wrapper.tcl}
ncsim> # SimVision command script arm_soc.tcl
ncsim>
ncsim> simvision {
>
> # Open new waveform window
>
> window new WaveWindow -name "Waves for ARM SoC Example"
> waveform using "Waves for ARM SoC Example"
>
> # Add Waves
>
> waveform add -signals de1_soc_wrapper_stim.CLOCK_50
> waveform add -signals de1_soc_wrapper_stim.KEY
> waveform add -signals de1_soc_wrapper_stim.SW
> waveform add -signals de1_soc_wrapper_stim.LEDR
> waveform add -signals de1_soc_wrapper_stim.HEX0
> waveform add -signals de1_soc_wrapper_stim.HEX1
> waveform add -signals de1_soc_wrapper_stim.HEX2
> waveform add -signals de1_soc_wrapper_stim.HEX3
> waveform add -signals de1_soc_wrapper_stim.VGA_R
> waveform add -signals de1_soc_wrapper_stim.VGA_G
> waveform add -signals de1_soc_wrapper_stim.VGA_B
> waveform add -signals de1_soc_wrapper_stim.VGA_HS
> waveform add -signals de1_soc_wrapper_stim.VGA_VS
> waveform add -signals de1_soc_wrapper_stim.VGA_CLK
> waveform add -signals de1_soc_wrapper_stim.VGA_BLANK_N
> waveform add -signals de1_soc_wrapper_stim.dut.soc_inst.HADDR
> waveform add -signals de1_soc_wrapper_stim.dut.soc_inst.HWRITE
> waveform add -signals de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
> waveform add -signals de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
> waveform add -signals de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
>
> }
ncsim>
ncsim> input -quiet .reinvoke.sim
ncsim> file delete .reinvoke.sim
ncsim> run
Simulation stopped via $stop(1) at time 40354010 NS + 0
ncsim> run
Simulation complete via $finish(1) at time 40354010 NS + 0
./testbench/de1_soc_wrapper_stim.sv:95 $finish;
ncsim> run
ncsim: *E,RNFNSH: Cannot continue simulation due to a previous $finish.
ncsim> run
ncsim: *E,RNFNSH: Cannot continue simulation due to a previous $finish.
ncsim> reset
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loaded snapshot worklib.de1_soc_wrapper_stim:sv
ncsim> run
Simulation stopped via $stop(1) at time 40354010 NS + 0
ncsim>
\ No newline at end of file
.nfs0000000053e75a6d0000663d 0 → 100644
+ 10
− 0
View file @ 4dc49816
# Restoring simulation environment...
input {testbench/de0_wrapper.tcl}
input -quiet .reinvoke.sim
file delete .reinvoke.sim
run
run
run
run
reset
run
.simvision/17087_ks6n19__autosave.tcl 0 → 100644
+ 57
− 0
View file @ 4dc49816
# NC-Sim Command File
# TOOL: ncsim(64) 15.20-s058
#
set tcl_prompt1 {puts -nonewline "ncsim> "}
set tcl_prompt2 {puts -nonewline "> "}
set vlog_format %h
set vhdl_format %v
set real_precision 6
set display_unit auto
set time_unit module
set heap_garbage_size -200
set heap_garbage_time 0
set assert_report_level note
set assert_stop_level error
set autoscope yes
set assert_1164_warnings yes
set pack_assert_off {}
set severity_pack_assert_off {note warning}
set assert_output_stop_level failed
set tcl_debug_level 0
set relax_path_name 1
set vhdl_vcdmap XX01ZX01X
set intovf_severity_level ERROR
set probe_screen_format 0
set rangecnst_severity_level ERROR
set textio_severity_level ERROR
set vital_timing_checks_on 1
set vlog_code_show_force 0
set assert_count_attempts 1
set tcl_all64 false
set tcl_runerror_exit false
set assert_report_incompletes 0
set show_force 1
set force_reset_by_reinvoke 0
set tcl_relaxed_literal 0
set probe_exclude_patterns {}
set probe_packed_limit 4k
set probe_unpacked_limit 16k
set assert_internal_msg no
set svseed 1
set assert_reporting_mode 0
alias . run
alias iprof profile
alias quit exit
database -open -shm -into waves.shm waves
database -open -shm -into memory.shm memory -default
probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_x de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_y
simvision -input /home/ks6n19/Documents/project/.simvision/17087_ks6n19__autosave.tcl.svcf
.simvision/17087_ks6n19__autosave.tcl.svcf 0 → 100644
+ 178
− 0
View file @ 4dc49816
#
# Preferences
#
preferences set toolbar-CursorControl-MemViewer {
usual
position -row 0 -anchor e
}
preferences set toolbar-Standard-MemViewer {
usual
position -row 1
}
preferences set plugin-enable-svdatabrowser-new 1
preferences set toolbar-sendToIndago-WaveWindow {
usual
position -pos 1
}
preferences set toolbar-Standard-Console {
usual
position -pos 1
}
preferences set toolbar-Search-Console {
usual
position -pos 2
}
preferences set plugin-enable-groupscope 0
preferences set plugin-enable-interleaveandcompare 0
preferences set plugin-enable-waveformfrequencyplot 0
preferences set toolbar-Windows-MemViewer {
usual
position -row 1 -pos 1
}
preferences set toolbar-TimeSearch-MemViewer {
usual
position -row 2 -pos 0
}
preferences set whats-new-dont-show-at-startup 1
preferences set toolbar-SimControl-MemViewer {
usual
position -row 3 -pos 0
}
#
# Mnemonic Maps
#
mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
{%c=TRUE -edgepriority 1 -shape high}}
mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
{%x=* -label %x -linecolor gray -shape bus}}
#
# Design Browser windows
#
if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
window geometry "Design Browser 1" 730x500+261+33
}
window target "Design Browser 1" on
browser using {Design Browser 1}
browser set -scope simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1
browser set \
-signalsort name
browser yview see simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1
browser timecontrol set -lock 0
#
# Waveform windows
#
if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1010x600+4+49}] != ""} {
window geometry "Waves for ARM SoC Example" 1010x600+4+49
}
window target "Waves for ARM SoC Example" on
waveform using {Waves for ARM SoC Example}
waveform sidebar visibility partial
waveform set \
-primarycursor TimeA \
-signalnames name \
-signalwidth 175 \
-units ps \
-valuewidth 75
waveform baseline set -time 0
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.CLOCK_50
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.KEY[2:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.SW[9:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.LEDR[9:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.HEX0[6:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.HEX1[6:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.HEX2[6:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.HEX3[6:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.VGA_HS
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.VGA_VS
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.VGA_CLK
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.VGA_BLANK_N
} ]
set id [waveform add -signals {
{simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
} ]
set id [waveform add -signals {
simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
} ]
waveform xview limits 0 40354010000ps
#
# Waveform Window Links
#
#
# Memory Viewer windows
#
if {[catch {window new MemViewer -name "Memory Viewer 1" -geometry 700x500+8+73}] != ""} {
window geometry "Memory Viewer 1" 700x500+8+73
}
window target "Memory Viewer 1" on
memviewer using {Memory Viewer 1}
memviewer set \
-primarycursor TimeA \
-units ps \
-radix default \
-addressradix default \
-addressorder MSBtoLSB
memviewer add {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]}
memviewer sidebar visibility partial
#
# Console windows
#
console set -windowname Console
window geometry Console 730x250+0+431
#
# Layout selection
#
INCA_libs/irun.lnx8664.15.20.nc/.nfs000000005ed55f200000663a 0 → 100644
+ 0
− 0
View file @ 4dc49816
INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060/ncsim.args 0 → 100644
+ 31
− 0
View file @ 4dc49816
//
// File created by: ncverilog
// Do not modify this file
//
+gui
+ncaccess+r
+tcl+testbench/de0_wrapper.tcl
+libext+.sv
+define+prog_file=software/code.hex
-gui
-INPUT
testbench/de0_wrapper.tcl
-MESSAGES
+EMGRLOG
ncverilog.log
-XLSTIME
1602177249
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
-RUNMODE
-CDSLIB
./INCA_libs/irun.lnx8664.15.20.nc/cds.lib
-HDLVAR
./INCA_libs/irun.lnx8664.15.20.nc/hdl.var
-XLNAME
ncverilog
-XLVERSION
"TOOL: ncverilog 15.20-s058"
-XLNAME
./INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060
INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060/ncsim.env 0 → 100644
+ 9
− 0
View file @ 4dc49816
#!/bin/csh
#
# File created by: ncverilog
# Do not modify this file
#
#<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.20.nc>#>
setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.20.nc"
#<< : <#3 FALSE>#>
setenv IRUNBATCH "FALSE"
INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060/ncverilog.args 0 → 100644
+ 13
− 0
View file @ 4dc49816
//
// File created by: ncverilog
// Do not modify this file
//
-sv
+gui
+ncaccess+r
+tcl+testbench/de0_wrapper.tcl
-y
behavioural
+libext+.sv
+define+prog_file=software/code.hex
testbench/de1_soc_wrapper_stim.sv
INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060_cdsrun.lib 0 → 100644
+ 2
− 0
View file @ 4dc49816
SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
define worklib ../worklib
INCA_libs/irun.lnx8664.15.20.nc/srv02749_17060_hdlrun.var 0 → 100644
+ 89
− 0
View file @ 4dc49816
DEFINE LANG_MAP (\
.v => verilog,\
.vp => verilog,\
.vs => verilog,\
.V => verilog,\
.VP => verilog,\
.VS => verilog,\
.v95 => verilog95,\
.v95p => verilog95,\
.V95 => verilog95,\
.V95P => verilog95,\
.vhd => vhdl,\
.vhdp => vhdl,\
.vhdl => vhdl,\
.vhdlp => vhdl,\
.VHDL => vhdl,\
.VHDLP => vhdl,\
.VHD => vhdl,\
.VHDP => vhdl,\
.e => e,\
.E => e,\
.elib => elib,\
.ELIB => elib,\
.viplib => elib,\
.VIPLIB => elib,\
.sv => systemverilog,\
.svp => systemverilog,\
.SV => systemverilog,\
.SVP => systemverilog,\
.svi => systemverilog,\
.svh => systemverilog,\
.vlib => systemverilog,\
.VLIB => systemverilog,\
.vams => verilog-ams,\
.VAMS => verilog-ams,\
.svams => sv-ams,\
.SVAMS => sv-ams,\
.svms => sv-ams,\
.SVMS => sv-ams,\
.vha => vhdl-ams,\
.VHA => vhdl-ams,\
.vhams => vhdl-ams,\
.VHAMS => vhdl-ams,\
.vhms => vhdl-ams,\
.VHMS => vhdl-ams,\
.scs => scs,\
.sp => scs,\
.s => assembly,\
.c => c,\
.o => o,\
.cpp => cpp,\
.cc => cpp,\
.a => a,\
.so => so,\
.sl => so,\
.pslvlog => psl_vlog,\
.pslvhdl => psl_vhdl,\
.pslsc => psl_sc,\
.vhcfg => vhcfg,\
.vhcfgp => vhcfg,\
.sv.gz => systemverilog,\
.sv.Z => systemverilog,\
DEF => verilog\
)
define VIEW_MAP ( $VIEW_MAP, * => verilog)
define VIEW_MAP ( $VIEW_MAP \
, .v => v \
, .vp => vp \
, .vs => vs \
, .V => V \
, .VP => VP \
, .VS => VS \
, .sv => sv \
, .svp => svp \
, .SV => SV \
, .SVP => SVP \
, .svi => svi \
, .svh => svh \
, .vlib => vlib \
, .VLIB => VLIB \
, .vams => vams \
, .VAMS => VAMS \
, .svams => svams \
, .SVAMS => SVAMS \
, .svms => svms \
, .SVMS => SVMS \
, .sv.gz => sv \
, .sv.Z => sv \
)
INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336/ncsim.args 0 → 100644
+ 29
− 0
View file @ 4dc49816
//
// File created by: ncverilog
// Do not modify this file
//
+gui
+ncaccess+r
+libext+.sv
+define+prog_file=software/code.hex
-gui
-TCL
-MESSAGES
+EMGRLOG
ncverilog.log
-XLSTIME
1602343308
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
-RUNMODE
-CDSLIB
./INCA_libs/irun.lnx8664.15.20.nc/cds.lib
-HDLVAR
./INCA_libs/irun.lnx8664.15.20.nc/hdl.var
-XLNAME
ncverilog
-XLVERSION
"TOOL: ncverilog 15.20-s058"
-XLNAME
./INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336
INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336/ncsim.env 0 → 100644
+ 9
− 0
View file @ 4dc49816
#!/bin/csh
#
# File created by: ncverilog
# Do not modify this file
#
#<< : <#3 ncverilog:./INCA_libs/irun.lnx8664.15.20.nc>#>
setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.20.nc"
#<< : <#3 FALSE>#>
setenv IRUNBATCH "FALSE"
INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336/ncverilog.args 0 → 100644
+ 13
− 0
View file @ 4dc49816
//
// File created by: ncverilog
// Do not modify this file
//
-sv
+gui
+ncaccess+r
-y
behavioural
+libext+.sv
+define+prog_file=software/code.hex
testbench/de1_soc_wrapper_stim.sv
-s
INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336_cdsrun.lib 0 → 100644
+ 2
− 0
View file @ 4dc49816
SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
define worklib ../worklib
INCA_libs/irun.lnx8664.15.20.nc/srv02749_38336_hdlrun.var 0 → 100644
+ 89
− 0
View file @ 4dc49816
DEFINE LANG_MAP (\
.v => verilog,\
.vp => verilog,\
.vs => verilog,\
.V => verilog,\
.VP => verilog,\
.VS => verilog,\
.v95 => verilog95,\
.v95p => verilog95,\
.V95 => verilog95,\
.V95P => verilog95,\
.vhd => vhdl,\
.vhdp => vhdl,\
.vhdl => vhdl,\
.vhdlp => vhdl,\
.VHDL => vhdl,\
.VHDLP => vhdl,\
.VHD => vhdl,\
.VHDP => vhdl,\
.e => e,\
.E => e,\
.elib => elib,\
.ELIB => elib,\
.viplib => elib,\
.VIPLIB => elib,\
.sv => systemverilog,\
.svp => systemverilog,\
.SV => systemverilog,\
.SVP => systemverilog,\
.svi => systemverilog,\
.svh => systemverilog,\
.vlib => systemverilog,\
.VLIB => systemverilog,\
.vams => verilog-ams,\
.VAMS => verilog-ams,\
.svams => sv-ams,\
.SVAMS => sv-ams,\
.svms => sv-ams,\
.SVMS => sv-ams,\
.vha => vhdl-ams,\
.VHA => vhdl-ams,\
.vhams => vhdl-ams,\
.VHAMS => vhdl-ams,\
.vhms => vhdl-ams,\
.VHMS => vhdl-ams,\
.scs => scs,\
.sp => scs,\
.s => assembly,\
.c => c,\
.o => o,\
.cpp => cpp,\
.cc => cpp,\
.a => a,\
.so => so,\
.sl => so,\
.pslvlog => psl_vlog,\
.pslvhdl => psl_vhdl,\
.pslsc => psl_sc,\
.vhcfg => vhcfg,\
.vhcfgp => vhcfg,\
.sv.gz => systemverilog,\
.sv.Z => systemverilog,\
DEF => verilog\
)
define VIEW_MAP ( $VIEW_MAP, * => verilog)
define VIEW_MAP ( $VIEW_MAP \
, .v => v \
, .vp => vp \
, .vs => vs \
, .V => V \
, .VP => VP \
, .VS => VS \
, .sv => sv \
, .svp => svp \
, .SV => SV \
, .SVP => SVP \
, .svi => svi \
, .svh => svh \
, .vlib => vlib \
, .VLIB => VLIB \
, .vams => vams \
, .VAMS => VAMS \
, .svams => svams \
, .SVAMS => SVAMS \
, .svms => svms \
, .SVMS => SVMS \
, .sv.gz => sv \
, .sv.Z => sv \
)
db/project24_09.quiproj.60727.rdr.flock 0 → 100644
+ 0
− 0
View file @ 4dc49816
memory.shm/.nfs0000000068b1ee700000663b 0 → 100644
+ 0
− 0
View file @ 4dc49816
File added
memory.shm/.nfs000000006b33093b0000663c 0 → 100644
+ 0
− 0
View file @ 4dc49816
File added
simvision17087.diag 0 → 100644
+ 67
− 0
View file @ 4dc49816
*** Message Type: info ***
When: Thu Oct 08 18:14:10 BST 2020
SimVision started.
Version: TOOL: simvision(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Platform: Linux/x86_64/3.10.0-1127.19.1.el7.x86_64
Started: Thu Oct 08 18:14:10 BST 2020
Command: /eda/cadence/incisiv/tools.lnx86/simvision/bin/64bit/simvision.exe -connect dc:srv02749.soton.ac.uk:39646 -64BIT -nocopyright
Work Directory: /home/ks6n19/Documents/project
*** Message Type: info ***
When: Thu Oct 08 18:14:11 BST 2020
Create browser window: "Design Browser 1"
*** Message Type: info ***
When: Thu Oct 08 18:14:12 BST 2020
Create console window: "Console"
*** Message Type: info ***
When: Thu Oct 08 18:14:13 BST 2020
Connect to Simulator
Design: worklib.de1_soc_wrapper_stim:sv
Languages: verilog
Simulator: NC-Sim
Version: TOOL: ncsim(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Time Started: Thu Oct 08 18:14:10 BST 2020
Process ID: 17060
Directory: /home/ks6n19/Documents/project
Command: ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv
*** Message Type: info ***
When: Thu Oct 08 18:14:14 BST 2020
Create utility window: "Properties"
*** Message Type: info ***
When: Thu Oct 08 18:14:15 BST 2020
Create waveform window: "Waves for ARM SoC Example"
*** Message Type: info ***
When: Thu Oct 08 18:15:08 BST 2020
Create memviewer window: "Memory Viewer 1"
*** Message Type: error ***
When: Sat Oct 10 16:21:49 BST 2020
can't read "state(state)": no such element in array
can't read "state(state)": no such element in array
while executing
"if { $state(state) == "running" } {
_clearValueChanges
}"
("!state.kernel" arm line 6)
invoked from within
"switch $info(event) {
!state.kernel {
# When we start running, clear the value change colors in
# the memory viewer widget, in preparation ..."
(object "::.memViewer0" method "::MemViewer::_stateEventCB" body line 7)
invoked from within
"::.memViewer0 _stateEventCB event !state.kernel handle @public@180f state idle kernel digital"
(in namespace inscope "::MemViewer" script line 1)
invoked from within
"namespace inscope ::MemViewer {::.memViewer0 _stateEventCB} event !state.kernel handle @public@180f state idle kernel digital"
software/.dep/main.o.d
+ 1
− 73
View file @ 4dc49816
......@@ -6,31 +6,7 @@ code/main.o: code/main.c \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/_newlib_version.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_intsup.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_stdint.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/stdio.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/_ansi.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/newlib.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/config.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/ieeefp.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/cdefs.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stddef.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdarg.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/reent.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/_ansi.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_types.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/_types.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/lock.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/types.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/endian.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/_endian.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/select.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_sigset.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_timeval.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/timespec.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_timespec.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/types.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/stdio.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdbool.h \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/math.h
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdbool.h
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdint.h:
......@@ -46,52 +22,4 @@ code/main.o: code/main.c \
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_stdint.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/stdio.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/_ansi.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/newlib.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/config.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/ieeefp.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/cdefs.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stddef.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdarg.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/reent.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/_ansi.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_types.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/_types.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/lock.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/types.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/endian.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/_endian.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/select.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_sigset.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_timeval.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/timespec.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/_timespec.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/machine/types.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/sys/stdio.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/lib/gcc/arm-none-eabi/5.4.1/include/stdbool.h:
/srv/gcc-arm-none-eabi-5_4-2016q3/arm-none-eabi/include/math.h:
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment