Update behavioural/ahb_out.sv, behavioural/arm_soc.sv, behavioural/de1_soc_wrapper.sv files

behavioural/ahb_out.sv

@@ -43,14 +43,13 @@ module ahb_out(
   //Non-AHB signals 
   input logic [9:0] pixel_x ,
   input logic [8:0] pixel_y ,
-  input logic [10:0] x1, x2, y1, y2, x3, y3,
   // AHB Signals from Slave to Master
   output logic [31:0] HRDATA,
   output HREADYOUT,
 
   //Non-AHB Signals
-  output logic pixel
-
+  output logic pixel,
+  output logic [10:0] x1, x2, y1, y2, x3, y3
 );
 
 timeunit 1ns;
@@ -62,12 +61,15 @@ timeprecision 100ps;
   //control signals are stored in registers
   logic write_enable, read_enable;
   logic [2:0] word_address  ;
-  logic [18:0] word_address_memory;
-  logic [18:0] pixel_address ;
-
+  
   //memory
   logic [0:0] memory [0:307199] ;
- 
+  logic [18:0] memory_address;
+  logic [18:0] pixel_address ;
+  logic [10:0] x,y ;
+
+  
+  // Unused registers 
   logic NextDataValid;
   logic [15:0] Status;
 
@@ -78,15 +80,12 @@ timeprecision 100ps;
         write_enable <= '0;
         read_enable <= '0;
         word_address <= '0;
-        word_address_memory <= '0;
-
       end
     else if ( HREADY && HSEL && (HTRANS != No_Transfer) )
       begin
         write_enable <= HWRITE;
         read_enable <= ! HWRITE;
         word_address <= HADDR[4:2];
-        word_address_memory <= HADDR[23:5] ;
 
      end
     else
@@ -94,42 +93,40 @@ timeprecision 100ps;
         write_enable <= '0;
         read_enable <= '0;
         word_address <= '0;
-        word_address_memory <= '0;
      end
 
-  //Act on control signals in the data phase
-
-  // write
+  // Act on control signals in the data phase
+  // Write pixel coordinates 
   always_ff @(posedge HCLK, negedge HRESETn)
     if ( ! HRESETn )
       begin
         x1 <= '0;
-    		x2 <= '0;
+    	x2 <= '0;
         x3 <= '0;
-    		y1 <= '0;
-    		y2 <= '0;
+    	y1 <= '0;
+    	y2 <= '0;
         y3 <= '0;
 
       end
     // x1 write     
     else if ( write_enable && (word_address==0))
-      x1 <= HWDATA[15:0];
+      x1 <= HWDATA;
 
     // y1 write     
     else if ( write_enable && (word_address==1))
-      y1 <= HWDATA[15:0];
+      y1 <= HWDATA;
 
     // x2 write     
     else if ( write_enable && (word_address==2))
-      x2 <= HWDATA[15:0];
+      x2 <= HWDATA;
 
     // y2 write     
     else if ( write_enable && (word_address==3))
-      y2 <= HWDATA[15:0];
+      y2 <= HWDATA;
 
     // x3 write     
     else if ( write_enable && (word_address==4))
-      x3 <= HWDATA[15:0];
+      x3 <= HWDATA;
 
     // y3 write     
     else if ( write_enable && (word_address==5))
@@ -143,20 +140,60 @@ memory = '{307200{0}};
   always_ff @(posedge HCLK)
     begin 
       if( write_enable )
-        memory[word_address_memory] <= HWDATA ; 
+        memory[memory_address] <= x + (640*y) ; 
     end 
   
   always_comb 
-    pixel_address = (pixel_y * 640) + pixel_x  ;
+    pixel_address = (pixel_y * 640) + pixel_x   ;
     
    
-   always_ff @(posedge HCLK)  
-     begin
-      pixel <= memory[pixel_address] ;
-     end
-          
+  always_ff @(posedge HCLK)  
+    begin
+		pixel <= memory[pixel_address] ;
+    end
+	
+// memory_address increments from 0 to 307199 
+  always_ff @(posedge HCLK)
+    begin 
+		if( !HRESETn )
+			memory_address <= '0;
+			
+		else if(memory_address >= 307200)
+			memory_address <= '0;
+		
+		else 	
+			memory_address <= memory_address + 1 ;
+	
+	end 	
+// x increments from 0 to 639 
+  always_ff @(posedge HCLK)
+    begin 
+		if( !HRESETn )
+			x <= '0;
+			
+		else if(x >= 639)
+			x <= '0;
+		
+		else 	
+			x <= x + 1 ;
+	
+	end 	
+
+// y increments from 0 to 479
+  always_ff @(posedge HCLK)
+    begin 
+		if( !HRESETn )
+			y <= '0;
+			
+		else if(y >= 479)
+			y <= '0;
+		
+		else 	
+			y <= y + 1 ;
+	
+	end 	
+ 
 // Read not allowed
-
 assign HRDATA = '0; // read is not permitted mode
    
     

behavioural/arm_soc.sv

@@ -6,10 +6,10 @@ module arm_soc(
   input HCLK, HRESETn,
   input logic [9:0] pixel_x ,
   input logic [8:0] pixel_y,
-  input logic [10:0] x1, x2, y1, y2, x3, y3, 	
   input [15:0] Switches, 
   input [1:0] Buttons, 
   output logic pixel,
+  output logic [10:0] x1, x2, y1, y2, x3, y3, 	
   output LOCKUP
 
 );
@@ -94,7 +94,7 @@ timeprecision 100ps;
     .HSEL(HSEL_DOUT),
     .HRDATA(HRDATA_DOUT), .HREADYOUT(HREADYOUT_DOUT),
 
-    .x1(x1), .x2(x2), .y1(y1), .y2(y2), .x3(x3), .y3(y3) .pixel_x(pixel_x), .pixel_y(pixel_y) , .pixel(pixel)
+    .x1(x1), .x2(x2), .y1(y1), .y2(y2), .x3(x3), .y3(y3), .pixel_x(pixel_x), .pixel_y(pixel_y) , .pixel(pixel)
 
   );
   

behavioural/de1_soc_wrapper.sv

@@ -35,11 +35,12 @@ timeprecision 100ps;
   logic pixel ;
   logic [9:0] pixel_x ;
   logic [8:0] pixel_y ; 
+  logic [10:0] x1,y1,x2,y2,x3,y3 ;
   assign Switches = { 6'd0, SW }; // DE1-SoC has just 10 switches
   
   assign Buttons = ~KEY[1:0];
  
-  arm_soc soc_inst(.HCLK, .HRESETn, .Switches, .pixel(pixel), .pixel_x(pixel_x), .pixel_y(pixel_y), .Buttons, .LOCKUP);
+  arm_soc soc_inst(.HCLK, .HRESETn, .Switches, .pixel(pixel), .pixel_x(pixel_x), .pixel_y(pixel_y), .x1(x1), .y1(y1), .x2(x2), .y2(y2), .x3(x3), .y3(y3), .Buttons, .LOCKUP);
   
   razzle raz_inst  (
         .CLOCK_50(CLOCK_50), .KEY(KEY), .pixel_x(pixel_x), .pixel_y(pixel_y), .pixel(pixel),