Update behavioural/razzle.sv, behavioural/ahb_out.sv files

behavioural/ahb_out.sv

@@ -46,7 +46,7 @@ module ahb_out(
   output HREADYOUT,
 
   //Non-AHB Signals
-  output logic [8:0] x1, x2, y1, y2
+  output logic [8:0] x1, x2, y1, y2, x3, y3
 );
 
 timeunit 1ns;
@@ -57,7 +57,7 @@ timeprecision 100ps;
 
   //control signals are stored in registers
   logic write_enable, read_enable;
-  logic [1:0] word_address  ;
+  logic [2:0] word_address  ;
 
  
   logic NextDataValid;
@@ -76,7 +76,7 @@ timeprecision 100ps;
       begin
         write_enable <= HWRITE;
         read_enable <= ! HWRITE;
-        word_address <= HADDR[3:2];
+        word_address <= HADDR[4:2];
 
      end
     else
@@ -94,8 +94,10 @@ timeprecision 100ps;
       begin
         x1 <= '0;
     		x2 <= '0;
+        x3 <= '0;
     		y1 <= '0;
     		y2 <= '0;
+        y3 <= '0;
 
       end
     // x1 write     
@@ -114,6 +116,16 @@ timeprecision 100ps;
     else if ( write_enable && (word_address==3))
       y2 <= HWDATA[15:0];
 
+    // x3 write     
+    else if ( write_enable && (word_address==4))
+      x3 <= HWDATA[15:0];
+
+    // y3 write     
+    else if ( write_enable && (word_address==5))
+      y3 <= HWDATA[15:0];
+
+      
+
 
   //read
   always_comb
@@ -127,7 +139,9 @@ timeprecision 100ps;
         0 : HRDATA = { 23'd0, x1 };
         1 : HRDATA = { 23'd0, y1 };
         2 : HRDATA = { 23'd0, x2 };
-        3 : HRDATA = { 23'd0, y2 };                
+        3 : HRDATA = { 23'd0, y2 };   
+        4 : HRDATA = { 23'd0, x3 };
+        5 : HRDATA = { 23'd0, y3 };                        
         // unused address - returns zero
         default : HRDATA = '0;
       endcase

behavioural/razzle.sv

-module razzle (
+// Description:
+// This code generates a VGA output for ARM SoC based 
+// on razzle code modified by Iain Mcnally <ECS, University of Soutampton>
+// Maintainer: Karthik Sathyanarayanan <ks6n19@soton.ac.uk>
+// Revision : $Revision$
 
-        input logic CLOCK_50,
-        input logic [3:0] KEY,
-        input logic [10:0] x1, x2, y1, y2,
-        output logic [9:0] LEDR ;
-)
+ 
+module razzle ( 
+ 
+	input logic CLOCK_50, 
+	input logic [3:0] KEY,
+	input logic  pixel,
+    	output logic [7:0] VGA_R,VGA_G,VGA_B, 
+	output logic [9:0] pixel_x,
+	output logic [8:0] pixel_y ,
+    	output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N); 
+       		 
+// Video Display Signals    
+logic [10:0] H_count,V_count; 
+
+logic video_on, video_on_H, video_on_V, clock_enable; 
+
+timeunit 1ns;
+timeprecision 100ps;
+
+// Map internal signals to external busses
 
 logic nReset;
-logic [9:0] L1_detT ;
-logic [9:0] L2_detT ;
-logic [9:0] detT ;
-logic [9:0] L1_positive;
-logic [9:0] L2_positive,
-logic [9:0] L3_positive ;
+logic Red,Green,Blue; 
 
 assign nReset=KEY[2]; // Keys are active low?
 
-always_comb
+assign VGA_R = Red ? 255 : 0;
+assign VGA_G = Green ? 255 : 0;
+assign VGA_B = Blue ? 255 : 0;
+
+assign VGA_CLK = clock_enable;
+assign VGA_BLANK_N = video_on;
+
+
+// Colors for pixel data on video signal 
+//assign Red_Data = 0 ; 
+assign Green_Data = 0; 
+assign Blue_Data = 0; 
+
+// turn off color (black) at screen edges and during retrace with video_on 
+assign Red =   pixel && video_on; 
+assign Green = Green_Data && video_on; 
+assign Blue =  Blue_Data && video_on; 
+
+// video_on turns off pixel color data when not in the pixel view area 
+assign video_on = video_on_H && video_on_V; 
+
+assign pixel_x =video_on_H ? H_count : '0 ;
+assign pixel_y = video_on_V ? V_count : '0 ;
+
+    
+// Generate Horizontal and Vertical Timing Signals for Video Signal 
+//VIDEO_DISPLAY 
+
+always @(posedge CLOCK_50, negedge nReset)
+  if ( ! nReset) 
+    begin
+		clock_enable = 0; 
+		H_count = 0; 
+		V_count = 0; 
+		video_on_H = 0; 
+		video_on_V = 0; 
+    end
+	
+	else
+	
+	begin : VIDEO_DISPLAY
+	    // Clock enable used for a 24Mhz video clock rate 
+	    // 640 by 480 display mode needs close to a 25Mhz pixel clock 
+	    // 24Mhz should work on most new monitors 
+
+	    clock_enable = ! clock_enable; 
+
+	    // H_count counts pixels (640 + extra time for sync signals) 
+	    // 
+	    //   <-Clock out RGB Pixel Row Data ->   <-H Sync-> 
+	    //   ------------------------------------__________-------- 
+	    //   0                           640   659       755    799 
+	    // 
 
-          L1_detT   =   ((y2-y3) *  (x-x3)) + ((x3-x2) *  (y-y3)) ;
-          L2_detT   =   ((y3-y1) *  (x-x3)) + ((x1-x3) *  (y-y3)) ;
-          detT      =   ((y2-y3) * (x1-x3)) + ((x3-x2) * (y1-y3)) ;
-          L1_positive = ((L1_detT >= 0) == (detT >= 0)) ;
-          L2_positive = ((L2_detT >= 0) == (detT >= 0)) ;
-          L3_positive = (((L1_detT + L2_detT) <= detT) == (detT >= 0)) ;
-          if(L1_positive && L2_positive && L3_positive)
-                write_pix(x,y,1);
+	      if ( clock_enable )
+	      begin
 
 
+		      if (H_count >= 799)
+			      H_count = 0; 
+		      else 
+			      H_count = H_count + 1; 
+
+		// Generate Horizontal Sync Signal 
+
+		      if ((H_count <= 755) && (H_count >= 659))
+	                      VGA_HS = 0; 
+		      else 
+	                      VGA_HS = 1; 
+
+		// V_count counts rows of pixels (480 + extra time for sync signals) 
+		// 
+		//  <---- 480 Horizontal Syncs (pixel rows) -->  ->V Sync<- 
+		//  -----------------------------------------------_______------------ 
+		//  0                                       480    493-494          524 
+		// 
+		      if ((V_count >= 524) && (H_count >= 699))
+			      V_count = 0; 
+		      else if (H_count == 699)
+			      V_count = V_count + 1; 
+
+
+		// Generate Vertical Sync Signal 
+		      if ((V_count <= 494) && (V_count >= 493))
+			      VGA_VS = 0; 
+		      else 
+			      VGA_VS = 1; 
+
+
+		// Generate Video on Screen Signals for Pixel Data 
+		      if (H_count <= 639) 
+			      video_on_H = 1; 
+		      else 
+			      video_on_H = 0; 
+
+
+		      if (V_count <= 479)
+			      video_on_V = 1; 
+		      else 
+			      video_on_V = 0; 
+
+	      end 
+
+	end : VIDEO_DISPLAY
+
 endmodule
+ 
+ 
+
+