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Commit 84fa4883 authored by K.Sathyanarayanan's avatar K.Sathyanarayanan
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while(1) code

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INCA_libs/history
+ 3
− 0
View file @ 84fa4883
......@@ -6,3 +6,6 @@ s1::(06Aug2020:03:09:54):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioura
s2::(06Aug2020:03:11:12):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
s3::(06Aug2020:03:18:18):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
s4::(06Aug2020:03:19:07):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
s5::(08Aug2020:21:05:54):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
s6::(08Aug2020:21:15:27):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
s7::(08Aug2020:21:23:02):( ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex )
INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var
+ 4
− 0
View file @ 84fa4883
......@@ -87,3 +87,7 @@ define VIEW_MAP ( $VIEW_MAP \
, .sv.gz => sv \
, .sv.Z => sv \
)
define ELAB_SNAPSHOT
define SNAPSHOT worklib.arm_soc_stim:sv
define ELAB_SNAPSHOT
define SNAPSHOT worklib.arm_soc_stim:sv
INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
+ 1
− 1
View file @ 84fa4883
......@@ -14,7 +14,7 @@ testbench/arm_soc.tcl
+EMGRLOG
ncverilog.log
-XLSTIME
1596680347
1596918182
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
......
INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
+ 2
− 2
View file @ 84fa4883
......@@ -14,7 +14,7 @@ testbench/arm_soc.tcl
+EMGRLOG
ncverilog.log
-XLSTIME
1596680347
1596918182
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
......@@ -28,4 +28,4 @@ ncverilog
-XLVERSION
"TOOL: ncverilog 15.20-s058"
-XLNAME
./INCA_libs/irun.lnx8664.15.20.nc/srv02749_95064
./INCA_libs/irun.lnx8664.15.20.nc/srv02749_35708
INCA_libs/irun.lnx8664.15.20.nc/srv02749_34586_cdsrun.lib 0 → 100644
+ 2
− 0
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SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
define worklib ../worklib
INCA_libs/irun.lnx8664.15.20.nc/srv02749_34586_hdlrun.var 0 → 100644
+ 89
− 0
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DEFINE LANG_MAP (\
.v => verilog,\
.vp => verilog,\
.vs => verilog,\
.V => verilog,\
.VP => verilog,\
.VS => verilog,\
.v95 => verilog95,\
.v95p => verilog95,\
.V95 => verilog95,\
.V95P => verilog95,\
.vhd => vhdl,\
.vhdp => vhdl,\
.vhdl => vhdl,\
.vhdlp => vhdl,\
.VHDL => vhdl,\
.VHDLP => vhdl,\
.VHD => vhdl,\
.VHDP => vhdl,\
.e => e,\
.E => e,\
.elib => elib,\
.ELIB => elib,\
.viplib => elib,\
.VIPLIB => elib,\
.sv => systemverilog,\
.svp => systemverilog,\
.SV => systemverilog,\
.SVP => systemverilog,\
.svi => systemverilog,\
.svh => systemverilog,\
.vlib => systemverilog,\
.VLIB => systemverilog,\
.vams => verilog-ams,\
.VAMS => verilog-ams,\
.svams => sv-ams,\
.SVAMS => sv-ams,\
.svms => sv-ams,\
.SVMS => sv-ams,\
.vha => vhdl-ams,\
.VHA => vhdl-ams,\
.vhams => vhdl-ams,\
.VHAMS => vhdl-ams,\
.vhms => vhdl-ams,\
.VHMS => vhdl-ams,\
.scs => scs,\
.sp => scs,\
.s => assembly,\
.c => c,\
.o => o,\
.cpp => cpp,\
.cc => cpp,\
.a => a,\
.so => so,\
.sl => so,\
.pslvlog => psl_vlog,\
.pslvhdl => psl_vhdl,\
.pslsc => psl_sc,\
.vhcfg => vhcfg,\
.vhcfgp => vhcfg,\
.sv.gz => systemverilog,\
.sv.Z => systemverilog,\
DEF => verilog\
)
define VIEW_MAP ( $VIEW_MAP, * => verilog)
define VIEW_MAP ( $VIEW_MAP \
, .v => v \
, .vp => vp \
, .vs => vs \
, .V => V \
, .VP => VP \
, .VS => VS \
, .sv => sv \
, .svp => svp \
, .SV => SV \
, .SVP => SVP \
, .svi => svi \
, .svh => svh \
, .vlib => vlib \
, .VLIB => VLIB \
, .vams => vams \
, .VAMS => VAMS \
, .svams => svams \
, .SVAMS => SVAMS \
, .svms => svms \
, .SVMS => SVMS \
, .sv.gz => sv \
, .sv.Z => sv \
)
INCA_libs/irun.lnx8664.15.20.nc/srv02749_35224_cdsrun.lib 0 → 100644
+ 2
− 0
View file @ 84fa4883
SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
define worklib ../worklib
INCA_libs/irun.lnx8664.15.20.nc/srv02749_35224_hdlrun.var 0 → 100644
+ 89
− 0
View file @ 84fa4883
DEFINE LANG_MAP (\
.v => verilog,\
.vp => verilog,\
.vs => verilog,\
.V => verilog,\
.VP => verilog,\
.VS => verilog,\
.v95 => verilog95,\
.v95p => verilog95,\
.V95 => verilog95,\
.V95P => verilog95,\
.vhd => vhdl,\
.vhdp => vhdl,\
.vhdl => vhdl,\
.vhdlp => vhdl,\
.VHDL => vhdl,\
.VHDLP => vhdl,\
.VHD => vhdl,\
.VHDP => vhdl,\
.e => e,\
.E => e,\
.elib => elib,\
.ELIB => elib,\
.viplib => elib,\
.VIPLIB => elib,\
.sv => systemverilog,\
.svp => systemverilog,\
.SV => systemverilog,\
.SVP => systemverilog,\
.svi => systemverilog,\
.svh => systemverilog,\
.vlib => systemverilog,\
.VLIB => systemverilog,\
.vams => verilog-ams,\
.VAMS => verilog-ams,\
.svams => sv-ams,\
.SVAMS => sv-ams,\
.svms => sv-ams,\
.SVMS => sv-ams,\
.vha => vhdl-ams,\
.VHA => vhdl-ams,\
.vhams => vhdl-ams,\
.VHAMS => vhdl-ams,\
.vhms => vhdl-ams,\
.VHMS => vhdl-ams,\
.scs => scs,\
.sp => scs,\
.s => assembly,\
.c => c,\
.o => o,\
.cpp => cpp,\
.cc => cpp,\
.a => a,\
.so => so,\
.sl => so,\
.pslvlog => psl_vlog,\
.pslvhdl => psl_vhdl,\
.pslsc => psl_sc,\
.vhcfg => vhcfg,\
.vhcfgp => vhcfg,\
.sv.gz => systemverilog,\
.sv.Z => systemverilog,\
DEF => verilog\
)
define VIEW_MAP ( $VIEW_MAP, * => verilog)
define VIEW_MAP ( $VIEW_MAP \
, .v => v \
, .vp => vp \
, .vs => vs \
, .V => V \
, .VP => VP \
, .VS => VS \
, .sv => sv \
, .svp => svp \
, .SV => SV \
, .SVP => SVP \
, .svi => svi \
, .svh => svh \
, .vlib => vlib \
, .VLIB => VLIB \
, .vams => vams \
, .VAMS => VAMS \
, .svams => svams \
, .SVAMS => SVAMS \
, .svms => svms \
, .SVMS => SVMS \
, .sv.gz => sv \
, .sv.Z => sv \
)
INCA_libs/irun.lnx8664.15.20.nc/srv02749_35708_cdsrun.lib 0 → 100644
+ 2
− 0
View file @ 84fa4883
SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
define worklib ../worklib
INCA_libs/irun.lnx8664.15.20.nc/srv02749_35708_hdlrun.var 0 → 100644
+ 89
− 0
View file @ 84fa4883
DEFINE LANG_MAP (\
.v => verilog,\
.vp => verilog,\
.vs => verilog,\
.V => verilog,\
.VP => verilog,\
.VS => verilog,\
.v95 => verilog95,\
.v95p => verilog95,\
.V95 => verilog95,\
.V95P => verilog95,\
.vhd => vhdl,\
.vhdp => vhdl,\
.vhdl => vhdl,\
.vhdlp => vhdl,\
.VHDL => vhdl,\
.VHDLP => vhdl,\
.VHD => vhdl,\
.VHDP => vhdl,\
.e => e,\
.E => e,\
.elib => elib,\
.ELIB => elib,\
.viplib => elib,\
.VIPLIB => elib,\
.sv => systemverilog,\
.svp => systemverilog,\
.SV => systemverilog,\
.SVP => systemverilog,\
.svi => systemverilog,\
.svh => systemverilog,\
.vlib => systemverilog,\
.VLIB => systemverilog,\
.vams => verilog-ams,\
.VAMS => verilog-ams,\
.svams => sv-ams,\
.SVAMS => sv-ams,\
.svms => sv-ams,\
.SVMS => sv-ams,\
.vha => vhdl-ams,\
.VHA => vhdl-ams,\
.vhams => vhdl-ams,\
.VHAMS => vhdl-ams,\
.vhms => vhdl-ams,\
.VHMS => vhdl-ams,\
.scs => scs,\
.sp => scs,\
.s => assembly,\
.c => c,\
.o => o,\
.cpp => cpp,\
.cc => cpp,\
.a => a,\
.so => so,\
.sl => so,\
.pslvlog => psl_vlog,\
.pslvhdl => psl_vhdl,\
.pslsc => psl_sc,\
.vhcfg => vhcfg,\
.vhcfgp => vhcfg,\
.sv.gz => systemverilog,\
.sv.Z => systemverilog,\
DEF => verilog\
)
define VIEW_MAP ( $VIEW_MAP, * => verilog)
define VIEW_MAP ( $VIEW_MAP \
, .v => v \
, .vp => vp \
, .vs => vs \
, .V => V \
, .VP => VP \
, .VS => VS \
, .sv => sv \
, .svp => svp \
, .SV => SV \
, .SVP => SVP \
, .svi => svi \
, .svh => svh \
, .vlib => vlib \
, .VLIB => VLIB \
, .vams => vams \
, .VAMS => VAMS \
, .svams => svams \
, .SVAMS => SVAMS \
, .svms => svms \
, .SVMS => SVMS \
, .sv.gz => sv \
, .sv.Z => sv \
)
INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
+ 1
− 1
View file @ 84fa4883
1596679188 behavioural
1596915536 behavioural
ncverilog.history
+ 3
− 0
View file @ 84fa4883
......@@ -2,3 +2,6 @@ s1(06Aug2020:03:09:54): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural
s2(06Aug2020:03:11:12): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
s3(06Aug2020:03:18:18): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
s4(06Aug2020:03:19:07): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
s5(08Aug2020:21:05:54): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
s6(08Aug2020:21:15:27): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
s7(08Aug2020:21:23:02): ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
ncverilog.key
+ 0
− 1
View file @ 84fa4883
database -open waves -into waves.shm -default
probe -create -shm arm_soc_stim.HCLK arm_soc_stim.HRESETn arm_soc_stim.Switches arm_soc_stim.Buttons arm_soc_stim.DataValid arm_soc_stim.LOCKUP arm_soc_stim.dut.HADDR arm_soc_stim.dut.HWRITE arm_soc_stim.dut.HSEL_RAM arm_soc_stim.dut.HSEL_SW arm_soc_stim.dut.HSEL_DOUT
run
exit
ncverilog.log
+ 3
− 51
View file @ 84fa4883
ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
TOOL: ncverilog 15.20-s058: Started on Aug 06, 2020 at 03:19:07 BST
TOOL: ncverilog 15.20-s058: Started on Aug 08, 2020 at 21:23:02 BST
ncverilog
-sv
testbench/arm_soc_stim.sv
......@@ -10,52 +10,6 @@ ncverilog
+ncaccess+r
+tcl+testbench/arm_soc.tcl
+define+prog_file=software/code.hex
Recompiling... reason: file './testbench/arm_soc_stim.sv' is newer than expected.
expected: Sun Feb 16 16:49:36 2020
actual: Thu Aug 6 03:18:58 2020
file: testbench/arm_soc_stim.sv
module worklib.arm_soc_stim:sv
errors: 0, warnings: 0
file: behavioural/arm_soc.sv
module behavioural.arm_soc:sv
errors: 0, warnings: 0
Caching library 'behavioural' ....... Done
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: .................... Done
Generating native compiled code:
behavioural.CORTEXM0DS:sv <0x11995c2d>
streams: 6, words: 1013
behavioural.ahb_interconnect:sv <0x10ed16eb>
streams: 4, words: 3059
behavioural.ahb_out:sv <0x09e4aee2>
streams: 17, words: 14203
behavioural.ahb_ram:sv <0x6de7ab0e>
streams: 15, words: 8478
behavioural.ahb_switches:sv <0x5aac1ebe>
streams: 16, words: 6047
behavioural.arm_soc:sv <0x059532c7>
streams: 6, words: 2347
behavioural.cortexm0ds_logic:sv <0x71afefff>
streams: 2204, words: 795278
worklib.arm_soc_stim:sv <0x4a8925f9>
streams: 7, words: 12814
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 8 8
Registers: 895 895
Scalar wires: 11128 -
Expanded wires: 119 5
Vectored wires: 38 -
Always blocks: 855 855
Initial blocks: 2 2
Cont. assignments: 955 11109
Pseudo assignments: 9 9
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.arm_soc_stim:sv
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
-------------------------------------
......@@ -94,10 +48,8 @@ ncsim> probe -create -shm arm_soc_stim.HCLK arm_soc_stim.HRESETn arm_soc_stim.Sw
Created probe 1
ncsim> run
x1:--Invalid-- @ 1045
x1:--Invalid-- @ 1505
x1:--Invalid-- @ 1545
x1:--Invalid-- @ 2005
x1:--Invalid-- @ 2505
Simulation stopped via $stop(1) at time 404010 NS + 0
ncsim> ^C
ncsim> exit
TOOL: ncverilog 15.20-s058: Exiting on Aug 06, 2020 at 03:19:53 BST (total: 00:00:46)
ncsim> TOOL: ncverilog 15.20-s058: Exiting on Aug 08, 2020 at 21:29:10 BST (total: 00:06:08)
simvision35714.diag 0 → 100644
+ 96
− 0
View file @ 84fa4883
*** Message Type: info ***
When: Sat Aug 08 21:23:03 BST 2020
SimVision started.
Version: TOOL: simvision(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Platform: Linux/x86_64/3.10.0-1127.13.1.el7.x86_64
Started: Sat Aug 08 21:23:03 BST 2020
Command: /eda/cadence/incisiv/tools.lnx86/simvision/bin/64bit/simvision.exe -connect dc:srv02749.soton.ac.uk:42697 -64BIT -nocopyright
Work Directory: /home/ks6n19/design/system_on_chip/example
*** Message Type: info ***
When: Sat Aug 08 21:23:03 BST 2020
Create browser window: "Design Browser 1"
*** Message Type: info ***
When: Sat Aug 08 21:23:06 BST 2020
Create console window: "Console"
*** Message Type: info ***
When: Sat Aug 08 21:23:08 BST 2020
Connect to Simulator
Design: worklib.arm_soc_stim:sv
Languages: verilog
Simulator: NC-Sim
Version: TOOL: ncsim(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Time Started: Sat Aug 08 21:23:02 BST 2020
Process ID: 35708
Directory: /home/ks6n19/design/system_on_chip/example
Command: ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
*** Message Type: info ***
When: Sat Aug 08 21:23:09 BST 2020
Create utility window: "Properties"
*** Message Type: info ***
When: Sat Aug 08 21:23:10 BST 2020
Create waveform window: "Waves for ARM SoC Example"
*** Message Type: info ***
When: Sat Aug 08 21:29:06 BST 2020
Delete browser window: "Design Browser 1"
*** Message Type: info ***
When: Sat Aug 08 21:29:08 BST 2020
Delete waveform window: "Waves for ARM SoC Example"
*** Message Type: info ***
When: Sat Aug 08 21:29:10 BST 2020
Exit NC-Sim: user
Design: worklib.arm_soc_stim:sv
Languages: verilog
Simulator: NC-Sim
Version: TOOL: ncsim(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Time Started: Sat Aug 08 21:23:02 BST 2020
Process ID: 35708
Directory: /home/ks6n19/design/system_on_chip/example
Command: ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
*** Message Type: error ***
When: Sat Aug 08 21:29:10 BST 2020
NC-Sim Crashed:
Design: worklib.arm_soc_stim:sv
Languages: verilog
Simulator: NC-Sim
Version: TOOL: ncsim(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Time Started: Sat Aug 08 21:23:02 BST 2020
Process ID: 35708
Directory: /home/ks6n19/design/system_on_chip/example
Command: ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
Design: worklib.arm_soc_stim:sv
Languages: verilog
Simulator: NC-Sim
Version: TOOL: ncsim(64) 15.20-s058
User: ks6n19
Host: srv02749.soton.ac.uk
Time Started: Sat Aug 08 21:23:02 BST 2020
Process ID: 35708
Directory: /home/ks6n19/design/system_on_chip/example
Command: ncverilog -sv testbench/arm_soc_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/arm_soc.tcl +define+prog_file=software/code.hex
Outstanding STRAP Requests:
strap::report enable out
*** Message Type: info ***
When: Sat Aug 08 21:29:14 BST 2020
SimVision Exit.
software/code.hex
+ 14
− 15
View file @ 84fa4883
......@@ -56,8 +56,8 @@
@0036 D3F6429A
@0037 F8BCF000
@0038 46C0E7FE
@0039 00000288
@003A 00000288
@0039 00000284
@003A 00000284
@003B 46C0E7FE
@003C 46C0E7FE
@003D 46C0E7FE
......@@ -89,25 +89,25 @@
@0057 601A9A01
@0058 B00246C0
@0059 46C04770
@005A 00000284
@005A 00000280
@005B 9001B082
@005C 681B4B03
@005D 9A013308
@005E 46C0601A
@005F 4770B002
@0060 00000284
@0060 00000280
@0061 9001B082
@0062 681B4B03
@0063 9A013310
@0064 46C0601A
@0065 4770B002
@0066 00000284
@0066 00000280
@0067 9001B082
@0068 681B4B03
@0069 9A013318
@006A 46C0601A
@006B 4770B002
@006C 00000284
@006C 00000280
@006D 681B4B0A
@006E 22003318
@006F 4B08601A
......@@ -119,18 +119,18 @@
@0075 2200681B
@0076 46C0601A
@0077 46C04770
@0078 00000284
@0078 00000280
@0079 681B4B02
@007A 0018681B
@007B 46C04770
@007C 00000284
@007C 00000280
@007D 9001B082
@007E 681A4B04
@007F 009B9B01
@0080 681B18D3
@0081 B0020018
@0082 46C04770
@0083 00000280
@0083 0000027C
@0084 9001B084
@0085 681B4B09
@0086 681B3308
......@@ -142,13 +142,13 @@
@008C 4153425A
@008D 0018B2DB
@008E 4770B004
@008F 00000280
@008F 0000027C
@0090 4B0446C0
@0091 3308681B
@0092 2B00681B
@0093 46C0D0F9
@0094 46C04770
@0095 00000280
@0095 0000027C
@0096 2000B510
@0097 FF7AF7FF
@0098 005B23A0
......@@ -157,7 +157,6 @@
@009B FF8AF7FF
@009C 005B23A0
@009D F7FF0018
@009E 2300FF91
@009F BD100018
@00A0 40000000
@00A1 50000000
@009E E7EEFF91
@009F 40000000
@00A0 50000000
software/code.vmem
+ 14
− 15
View file @ 84fa4883
......@@ -56,8 +56,8 @@
assign memory[ 54 ] = 32'hD3F6429A;
assign memory[ 55 ] = 32'hF8BCF000;
assign memory[ 56 ] = 32'h46C0E7FE;
assign memory[ 57 ] = 32'h00000288;
assign memory[ 58 ] = 32'h00000288;
assign memory[ 57 ] = 32'h00000284;
assign memory[ 58 ] = 32'h00000284;
assign memory[ 59 ] = 32'h46C0E7FE;
assign memory[ 60 ] = 32'h46C0E7FE;
assign memory[ 61 ] = 32'h46C0E7FE;
......@@ -89,25 +89,25 @@
assign memory[ 87 ] = 32'h601A9A01;
assign memory[ 88 ] = 32'hB00246C0;
assign memory[ 89 ] = 32'h46C04770;
assign memory[ 90 ] = 32'h00000284;
assign memory[ 90 ] = 32'h00000280;
assign memory[ 91 ] = 32'h9001B082;
assign memory[ 92 ] = 32'h681B4B03;
assign memory[ 93 ] = 32'h9A013308;
assign memory[ 94 ] = 32'h46C0601A;
assign memory[ 95 ] = 32'h4770B002;
assign memory[ 96 ] = 32'h00000284;
assign memory[ 96 ] = 32'h00000280;
assign memory[ 97 ] = 32'h9001B082;
assign memory[ 98 ] = 32'h681B4B03;
assign memory[ 99 ] = 32'h9A013310;
assign memory[ 100 ] = 32'h46C0601A;
assign memory[ 101 ] = 32'h4770B002;
assign memory[ 102 ] = 32'h00000284;
assign memory[ 102 ] = 32'h00000280;
assign memory[ 103 ] = 32'h9001B082;
assign memory[ 104 ] = 32'h681B4B03;
assign memory[ 105 ] = 32'h9A013318;
assign memory[ 106 ] = 32'h46C0601A;
assign memory[ 107 ] = 32'h4770B002;
assign memory[ 108 ] = 32'h00000284;
assign memory[ 108 ] = 32'h00000280;
assign memory[ 109 ] = 32'h681B4B0A;
assign memory[ 110 ] = 32'h22003318;
assign memory[ 111 ] = 32'h4B08601A;
......@@ -119,18 +119,18 @@
assign memory[ 117 ] = 32'h2200681B;
assign memory[ 118 ] = 32'h46C0601A;
assign memory[ 119 ] = 32'h46C04770;
assign memory[ 120 ] = 32'h00000284;
assign memory[ 120 ] = 32'h00000280;
assign memory[ 121 ] = 32'h681B4B02;
assign memory[ 122 ] = 32'h0018681B;
assign memory[ 123 ] = 32'h46C04770;
assign memory[ 124 ] = 32'h00000284;
assign memory[ 124 ] = 32'h00000280;
assign memory[ 125 ] = 32'h9001B082;
assign memory[ 126 ] = 32'h681A4B04;
assign memory[ 127 ] = 32'h009B9B01;
assign memory[ 128 ] = 32'h681B18D3;
assign memory[ 129 ] = 32'hB0020018;
assign memory[ 130 ] = 32'h46C04770;
assign memory[ 131 ] = 32'h00000280;
assign memory[ 131 ] = 32'h0000027C;
assign memory[ 132 ] = 32'h9001B084;
assign memory[ 133 ] = 32'h681B4B09;
assign memory[ 134 ] = 32'h681B3308;
......@@ -142,13 +142,13 @@
assign memory[ 140 ] = 32'h4153425A;
assign memory[ 141 ] = 32'h0018B2DB;
assign memory[ 142 ] = 32'h4770B004;
assign memory[ 143 ] = 32'h00000280;
assign memory[ 143 ] = 32'h0000027C;
assign memory[ 144 ] = 32'h4B0446C0;
assign memory[ 145 ] = 32'h3308681B;
assign memory[ 146 ] = 32'h2B00681B;
assign memory[ 147 ] = 32'h46C0D0F9;
assign memory[ 148 ] = 32'h46C04770;
assign memory[ 149 ] = 32'h00000280;
assign memory[ 149 ] = 32'h0000027C;
assign memory[ 150 ] = 32'h2000B510;
assign memory[ 151 ] = 32'hFF7AF7FF;
assign memory[ 152 ] = 32'h005B23A0;
......@@ -157,7 +157,6 @@
assign memory[ 155 ] = 32'hFF8AF7FF;
assign memory[ 156 ] = 32'h005B23A0;
assign memory[ 157 ] = 32'hF7FF0018;
assign memory[ 158 ] = 32'h2300FF91;
assign memory[ 159 ] = 32'hBD100018;
assign memory[ 160 ] = 32'h40000000;
assign memory[ 161 ] = 32'h50000000;
assign memory[ 158 ] = 32'hE7EEFF91;
assign memory[ 159 ] = 32'h40000000;
assign memory[ 160 ] = 32'h50000000;
software/code/main.lst
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software/code/main.o
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software/test_designstart.elf
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