Select Git revision
SimpleCameraController.cs
build_mcu_fpga_ip.tcl 5.65 KiB
###-----------------------------------------------------------------------------
### example: build_mcu_fpga_ip.tcl
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
###
### David Flynn (d.w.flynn@soton.ac.uk)
###
### Copyright � 2022, SoC Labs (www.soclabs.org)
###-----------------------------------------------------------------------------
#
# developed & tested using vivado_version 2021.1
#
# usage:
# vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
#
# STEP#0: define output directory area.
#
set outputDir ./vivado/built_mcu_fpga
file mkdir $outputDir
#
# STEP#1: setup design sources and constraints
#
# local search path for configurations
set search_path ../verilog
set cortexm0_vlog ../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
source scripts/rtl_source_cm0.tcl
set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
# Arm unmodified CMSDK RTL
set cmsdk_vlog ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
source scripts/rtl_source_cmsdk.tcl
set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
set search_path [ concat $search_path ../verilog ]
set dma230_vlog ../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
source scripts/rtl_source_dma230.tcl
# ADP, FT1248 and streamio IP
source scripts/rtl_source_soclabs_ip.tcl
## FPGA-specific pads
#source scripts/rtl_source_fpga_ip.tcl
# soclabs modified mcu system
set_property verilog_define {NOEXP} [current_fileset]
set soc_vlog ../src
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v