build_mcu_fpga_ip.tcl

###-----------------------------------------------------------------------------
### example: build_mcu_fpga_ip.tcl
### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
###
### Contributors
###
### David Flynn (d.w.flynn@soton.ac.uk)
###
### Copyright � 2022, SoC Labs (www.soclabs.org)
###-----------------------------------------------------------------------------
#
# developed & tested using vivado_version 2021.1
#
# usage:
# vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl

#
# STEP#0: define output directory area.
#

set outputDir ./vivado/built_mcu_fpga
file mkdir $outputDir
#
# STEP#1: setup design sources and constraints
#

# local search path for configurations
set search_path ../verilog

set cortexm0_vlog    ../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
source scripts/rtl_source_cm0.tcl

set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
read_verilog  [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
read_verilog  [ glob $cortexm0_vlog/models/cells/*.v ]

# Arm unmodified CMSDK RTL
set cmsdk_vlog    ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
source scripts/rtl_source_cmsdk.tcl

set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v

# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
set search_path [ concat $search_path ../verilog ]
set dma230_vlog    ../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
source scripts/rtl_source_dma230.tcl

# ADP, FT1248 and streamio IP
source scripts/rtl_source_soclabs_ip.tcl

## FPGA-specific pads
#source scripts/rtl_source_fpga_ip.tcl

# soclabs modified mcu system 

set soc_vlog ../src
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v 
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v 
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v
read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v
read_verilog  $soc_vlog/verilog/nanosoc_ahb_bootrom.v
read_verilog  $soc_vlog/verilog/nanosoc_apb_subsystem.v
read_verilog  $soc_vlog/bootrom/verilog/bootrom.v 
read_verilog  $soc_vlog/verilog/nanosoc_ahb_cs_rom_table.v
read_verilog  $soc_vlog/verilog/nanosoc_apb_usrt.v
##read_verilog  $soc_vlog/cmsdk_clkreset.v
read_verilog  ../test_io/verilog/nanosoc_ft1248x1_adpio.v  
read_verilog  $soc_vlog/verilog/nanosoc_mcu_clkctrl.v
read_verilog  $soc_vlog/verilog/nanosoc_mcu_pin_mux.v
read_verilog  $soc_vlog/verilog/nanosoc_mcu_stclkctrl.v
read_verilog  $soc_vlog/verilog/nanosoc_mcu_sysctrl.v
##read_verilog  $soc_vlog/cmsdk_uart_capture.v
read_verilog  $soc_vlog/verilog/nanosoc_cpu.v
read_verilog  $soc_vlog/verilog/nanosoc_sys_ahb_decode.v
read_verilog  $soc_vlog/verilog/nanosoc_sysio.v
read_verilog  ../aes/src/soclabs_ahb_aes128_ctrl.v 
read_verilog  $soc_vlog/verilog/nanosoc_chip.v
read_verilog  $soc_vlog/verilog/nanosoc_chip_pads.v

set_property top nanosoc_chip [current_fileset]

# FPGA specific timing constraints
#read_xdc target_fpga/fpga_timing.xdc

## FPGA board specific pin constraints
#read_xdc target_fpga/fpga_pinmap.xdc

#
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#

update_compile_order -fileset sources_1

set mculib_ip  $outputDir/MCULIB

ipx::package_project -root_dir $mculib_ip -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order

ipx::unload_core  $mculib_ip/component.xml
ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory  $mculib_ip  $mculib_ip/component.xml

update_compile_order -fileset sources_1
set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
ipx::merge_project_changes files [ipx::current_core]

set_property core_revision 2 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]

ipx::save_core [ipx::current_core]
ipx::check_integrity -quiet -xrt [ipx::current_core]
ipx::archive_core  $mculib_ip/soclabs.org_user_nanosoc_chip_1.0.zip [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
#close_project -delete
close_project

set_property  ip_repo_paths { ip_repo $mculib_ip} [current_project]
update_ip_catalog
close_project