moved LUT to the port list for more flexibility

DA.sv

@@ -49,6 +49,7 @@ always_ff@(posedge ck, posedge rst)
 
 
 // ==== DA accumulator ==== 
+<<<<<<< HEAD
 always_ff @(posedge ck)
   if (reset_accumulator)
   begin
@@ -68,9 +69,30 @@ always_ff @(posedge ck)
         begin
             shifted_out <= {partial_sum[0], shifted_out[N-1:1]};     									  
             partial_sum <= {partial_sum[(N-1)+8],partial_sum[(N-1)+8:1]} - multiplication_coefficients[multiplication_addresses[address]]; 
+=======
+always_ff @(posedge ck, posedge rst)
+    if (reset_accumulator)
+    begin
+        partial_sum <= '0;
+        shifted_out <= '0;
+    end
+    else
+    begin
+        if(compute)
+        begin 
+            if(address < N-1)
+            begin
+                shifted_out <= {partial_sum[0], shifted_out[N-1:1]};     									 
+                partial_sum <= {partial_sum[(N-1)+8],partial_sum[(N-1)+8:1]} + multiplication_coefficients[multiplication_addresses[address]]; 
+            end
+            else
+            begin
+                shifted_out <= {partial_sum[0], shifted_out[N-1:1]};     									  
+                partial_sum <= {partial_sum[(N-1)+8],partial_sum[(N-1)+8:1]} - multiplication_coefficients[multiplication_addresses[address]]; 
+            end
+>>>>>>> c3e2c38a62bbbf0555b4b676ad01f703f9b1ee10
         end
     end
-  end
 // ==== DA accumulator ====
 
 
@@ -96,15 +118,15 @@ always_ff @(posedge ck, posedge rst)
 
 // === state machine to control the MAC ====
 always_ff @(posedge ck, posedge rst)
-  begin: SEQ
-  if(rst)
-	state <= waiting;
-  else 
-	state <= next_state;
-  end: SEQ
+begin: SEQ
+    if(rst)
+        state <= waiting;
+    else 
+        state <= next_state;
+end: SEQ
 
 always_comb
-	begin: COM
+begin: COM
     load = '0;
     reset_accumulator = '0;
     output_ready = '0;
@@ -138,7 +160,7 @@ always_comb
 	end
     default : next_state = waiting;
     endcase
-    end: COM
+end: COM
 // ==== state machine to control the FIR ====
 
 endmodule
\ No newline at end of file