Fixed some typos and added more explanation for how to use

DA.sv

 /*
 ======= Signed DA MAC =======
 - This is a Signed MAC block based on a distributed arithmetic architechture
-- The input is an [N*BW] unpacked array of packed array of arrays
+- The input is an size N unpacked array of packed arrays of size BW
 - The LUT corresponding to coefficients with which each value is multiplied is specified in DA_LUT.sv
 - This LUT must be specified for the number of input bits
 - The output is of size 2N (+ 8 guard bits)
@@ -10,7 +10,7 @@
 
 import DA_LUT::clog2;
 
-module DA_MAC #(parameter BW = DA_LUT::BW, parameter N = DA_LUT::N)
+module DA_MAC #(parameter BW = 16, parameter N = 16)
                (input logic signed [BW-1:0] in [0:N-1],
                 input logic input_ready, ck, rst,
                 input logic [(N-1)+8:0] multiplication_coefficients [0:2**N-1],
@@ -18,19 +18,18 @@ module DA_MAC #(parameter BW = DA_LUT::BW, parameter N = DA_LUT::N)
                 output logic output_ready);
 
 // ==== Local Variables ==== 
-logic signed [BW-1:0]       shifted_out;
-logic signed [(N-1)+8:0]   partial_sum; 
+logic signed [BW-1:0]    shifted_out;
+logic signed [(N-1)+8:0] partial_sum; 
 
 typedef enum logic [1:0] {waiting, loading, processing, saving} state_type;
 state_type               state, next_state;
 logic                    load, reset_accumulator, compute, count;
 logic [clog2(BW):0]      address;
+logic unsigned [N-1:0]   multiplication_addresses [0:BW-1];  
 // ==== Local Variables ==== 
 
 
 // ==== generate the multiplication addresses ====
-logic unsigned [N-1:0] multiplication_addresses [0:BW-1];   
-
 always_ff@(posedge ck, posedge rst)  
 	if(rst)
 		multiplication_addresses <= '{default:'0};
@@ -69,6 +68,7 @@ always_ff @(posedge ck)
             partial_sum <= {partial_sum[(N-1)+8],partial_sum[(N-1)+8:1]} - multiplication_coefficients[multiplication_addresses[address]]; 
         end
     end
+  end
 // ==== DA accumulator ====
 
 

DA_LUT.sv

@@ -16,15 +16,10 @@ function int clog2(input int n);
 endfunction
 /*
-- The input to the LUT is an N Bit input vector (hence 2^N - 1 inputs)
-- The maximum value of the output would be N*(2^BW-1) assuming a BW sized coefficients and all an input vector of all 1's
-- Hence, this required log2(N*(2^BW-1))+1 (+1 for sign bit) bits to store = log2(N) + log2(2^BW-1) + 1 = (BW) + log2(N)
-
-   N  |  BW   | log2(N)  | output size
----------------------------------------
-  16  |  16   |    4     |     20         <----- this implementation
-  32  |  16   |    5     |     21
-  32  |  32   |    5     |     37s
+- The input to the LUT is an N Bit input vector (hence 2^N - 1 possible inputs)
+- The maximum value of the output would be N*(2^BW-1) assuming a BW sized coefficients and an input vector of all 1's
+- Hence, this required log2(N*(2^BW-1))+1 bits to store = log2(N) + log2(2^BW-1) + 1 = (BW) + log2(N)
+- In reality, I have chosen to just use (N+8) bits for the size of the multiplication_coefficients as this matches the size of partial_sum
 */
 const logic signed [(N-1)+8:0] multiplication_coefficients [0:2**N-1] = '{
 24'd0, -24'd79, -24'd136, -24'd215, 24'd312, 24'd233, 24'd176, 24'd97, 24'd654, 

DA_test.sv

+import DA_LUT::N;
+import DA_LUT::BW;
+import DA_LUT::multiplication_coefficients;
+
 module DA_test;
 
 timeunit 1ns;
 timeprecision 100ps;
 
-logic signed [DA_LUT::BW-1:0] in [0:DA_LUT::N-1] = '{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
+logic signed [BW-1:0] in [0:N-1] = '{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
 logic input_ready, ck, rst;
-logic signed [(2*DA_LUT::N-1)+8:0] out;
+logic signed [(2*N-1)+8:0] out;
 logic output_ready;
 
 const int input_frequency = 5000;
 
-DA_MAC #(.BW(DA_LUT::BW), .N(DA_LUT::N))  DA  (.*, .multiplication_coefficients(DA_LUT::multiplication_coefficients));
+DA_MAC #(.BW(BW), .N(N))  DA  (.*, .multiplication_coefficients(multiplication_coefficients));
 
 // clock generator
 // generates a 1 MHz clock
@@ -33,7 +37,6 @@ initial
   #10ns rst = '1;
   #10ns rst = '0;
   end
-  
-  
+
 endmodule