Commits · 37fa394f50a7fb4f484a53b073e916f8e26fafe0 · dwf1m12 / soclabs-cortexm0-mcu

Jan 08, 2022
- rebuild ahb_bootrom__mangled to support alternative ROM synthesis · 37fa394f
  dwf1m12 authored 3 years ago
  
  37fa394f
Jan 07, 2022
- reference log files for CPU trace and UART2 added · cac739f9
  dwf1m12 authored 3 years ago
  
  cac739f9
- added header and date stamp to bootrom.v generator · 8e53e93e
  dwf1m12 authored 3 years ago
  
  8e53e93e
- program baudrate for 4800 buad @ 1MHz and update uart capture testbench · 8bc02fe7
  dwf1m12 authored 3 years ago
  
  8bc02fe7
Jan 04, 2022
- verilog changes for bootrom generation and prep for IO pads · c778f75a
  dwf1m12 authored 3 years ago
  
  c778f75a
- bootrom generation and prep for IO pads · a32c8bff
  dwf1m12 authored 3 years ago
  
  a32c8bff
Nov 25, 2021
- documentation update · b35a8975
  dwf1m12 authored 3 years ago
  
  Merge branch 'master' of git.soton.ac.uk:dwf1m12/soclabs-cortexm0-mcu
  b35a8975
- fix dma configuration to pass tests · 0e40afa4
  dwf1m12 authored 3 years ago
  
  0e40afa4
Nov 24, 2021
- Update GetStarted.md to add simulation instructions · ffa1fcef
  dwf1m12 authored 3 years ago
  
  ffa1fcef
- Update GetStarted.md · 5bd895c4
  dwf1m12 authored 3 years ago
  
  5bd895c4
- add initial GetStarted doc · 1b89ae04
  dwf1m12 authored 3 years ago
  
  1b89ae04
- update build from DesignStart Pro to full AAA IP bundles · 2589e336
  dwf1m12 authored 3 years ago
  
  2589e336
- Initial commit · b99de5a2
  dwf1m12 authored 3 years ago
  
  b99de5a2