Skip to content

GitLab

Explore

Sign in
Register

Primary navigation

Project

S

soclabs-cortexm0-mcu
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Terraform modules
- Incidents

Snippets Groups Projects

cac739f9

Commit cac739f9 authored 3 years ago by dwf1m12

Downloads
- Patches
- Plain Diff

reference log files for CPU trace and UART2 added

parent 8e53e93e

No related branches found

No related tags found

Loading

Changes 2

Hide whitespace changes

Inline Side-by-side

Showing

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/tarmac0.log_ref 206821 additions, 0 deletions

...oclabs_demo/systems/cortex_m0_mcu/rtl_sim/tarmac0.log_ref
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/uart2.log_ref 8 additions, 0 deletions

.../soclabs_demo/systems/cortex_m0_mcu/rtl_sim/uart2.log_ref

with 206829 additions and 0 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment