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Census2022-CER-mixed_model_0910.R
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Ben Anderson authoredBen Anderson authored
nic400_top.v 24.27 KiB
module nic400_top #
(
parameter DATA_WIDTH = 64,
parameter SYS_ADDR_WIDTH= 32,
parameter STRB_WIDTH = (DATA_WIDTH/8),
parameter ID_WIDTH = 4
)(
input wire clk,
input wire rst,
output wire dma_active,
inout wire [ID_WIDTH-1:0] axi_awid,
inout wire [SYS_ADDR_WIDTH-1:0] axi_awaddr,
inout wire [7:0] axi_awlen,
inout wire [2:0] axi_awsize,
inout wire [1:0] axi_awburst,
inout wire axi_awlock,
inout wire [3:0] axi_awcache,
inout wire [2:0] axi_awprot,
inout wire [3:0] axi_awqos,
inout wire [3:0] axi_awregion,
inout wire axi_awvalid,
inout wire axi_awready,
inout wire [DATA_WIDTH-1:0] axi_wdata,
inout wire [STRB_WIDTH-1:0] axi_wstrb,
inout wire axi_wlast,
inout wire axi_wvalid,
inout wire axi_wready,
inout wire [ID_WIDTH-1:0] axi_bid,
inout wire [1:0] axi_bresp,
inout wire axi_bvalid,
inout wire axi_bready,
inout wire [ID_WIDTH-1:0] axi_arid,
inout wire [SYS_ADDR_WIDTH-1:0] axi_araddr,
inout wire [7:0] axi_arlen,
inout wire [2:0] axi_arsize,
inout wire [1:0] axi_arburst,
inout wire axi_arlock,
inout wire [3:0] axi_arcache,
inout wire [2:0] axi_arprot,
inout wire [3:0] axi_arqos,
inout wire [3:0] axi_arregion,
inout wire axi_arvalid,
inout wire axi_arready,
inout wire [ID_WIDTH-1:0] axi_rid,
inout wire [DATA_WIDTH-1:0] axi_rdata,
inout wire [1:0] axi_rresp,
inout wire axi_rlast,
inout wire axi_rvalid,
inout wire axi_rready,
// DMA APB interface
inout wire APB_PSEL,
inout wire APB_PWRITE,
inout wire APB_PENABLE,
inout wire [12:0] APB_PADDR,
inout wire [31:0] APB_PWDATA,
inout wire [31:0] APB_PRDATA,
inout wire APB_PREADY,
inout wire APB_PSLVERR,
inout wire [3:0] APB_PSTRB
);
parameter MEM_ID_WIDTH=6;
defparam u_sram_0.ID_WIDTH=MEM_ID_WIDTH;
defparam u_sram_1.ID_WIDTH=MEM_ID_WIDTH;
// IntMem Axi signals - AXI_MASTER_0
wire [MEM_ID_WIDTH-1:0] AWID_AXI_Master_0;
wire [SYS_ADDR_WIDTH-1:0] AWADDR_AXI_Master_0;
wire [3:0] AWLEN_AXI_Master_0;
wire [2:0] AWSIZE_AXI_Master_0;
wire [1:0] AWBURST_AXI_Master_0;
wire [1:0] AWLOCK_AXI_Master_0;
wire [3:0] AWCACHE_AXI_Master_0;
wire [2:0] AWPROT_AXI_Master_0;
wire AWVALID_AXI_Master_0;
wire AWREADY_AXI_Master_0;
wire [MEM_ID_WIDTH-1:0] WID_AXI_Master_0;
wire [DATA_WIDTH-1:0] WDATA_AXI_Master_0;
wire [STRB_WIDTH-1:0] WSTRB_AXI_Master_0;
wire WLAST_AXI_Master_0;
wire WVALID_AXI_Master_0;
wire WREADY_AXI_Master_0;
wire [MEM_ID_WIDTH-1:0] BID_AXI_Master_0;
wire [1:0] BRESP_AXI_Master_0;
wire BVALID_AXI_Master_0;
wire BREADY_AXI_Master_0;
wire [MEM_ID_WIDTH-1:0] ARID_AXI_Master_0;
wire [SYS_ADDR_WIDTH-1:0] ARADDR_AXI_Master_0;
wire [3:0] ARLEN_AXI_Master_0;
wire [2:0] ARSIZE_AXI_Master_0;
wire [1:0] ARBURST_AXI_Master_0;
wire [1:0] ARLOCK_AXI_Master_0;
wire [3:0] ARCACHE_AXI_Master_0;
wire [2:0] ARPROT_AXI_Master_0;
wire [3:0] ARQOS_AXI_Master_0;
wire [3:0] ARREGION_AXI_Master_0;
wire ARVALID_AXI_Master_0;
wire ARREADY_AXI_Master_0;
wire [MEM_ID_WIDTH-1:0] RID_AXI_Master_0;
wire [DATA_WIDTH-1:0] RDATA_AXI_Master_0;
wire [1:0] RRESP_AXI_Master_0;
wire RLAST_AXI_Master_0;
wire RVALID_AXI_Master_0;
wire RREADY_AXI_Master_0;
// IntMem 1 Axi signals - AXI_MASTER_1
wire [MEM_ID_WIDTH-1:0] AWID_AXI_Master_1;
wire [SYS_ADDR_WIDTH-1:0] AWADDR_AXI_Master_1;
wire [3:0] AWLEN_AXI_Master_1;
wire [2:0] AWSIZE_AXI_Master_1;
wire [1:0] AWBURST_AXI_Master_1;
wire [1:0] AWLOCK_AXI_Master_1;
wire [3:0] AWCACHE_AXI_Master_1;
wire [2:0] AWPROT_AXI_Master_1;
wire AWVALID_AXI_Master_1;
wire AWREADY_AXI_Master_1;
wire [MEM_ID_WIDTH-1:0] WID_AXI_Master_1;
wire [DATA_WIDTH-1:0] WDATA_AXI_Master_1;
wire [STRB_WIDTH-1:0] WSTRB_AXI_Master_1;
wire WLAST_AXI_Master_1;
wire WVALID_AXI_Master_1;
wire WREADY_AXI_Master_1;
wire [MEM_ID_WIDTH-1:0] BID_AXI_Master_1;
wire [1:0] BRESP_AXI_Master_1;
wire BVALID_AXI_Master_1;
wire BREADY_AXI_Master_1;
wire [MEM_ID_WIDTH-1:0] ARID_AXI_Master_1;
wire [SYS_ADDR_WIDTH-1:0] ARADDR_AXI_Master_1;
wire [3:0] ARLEN_AXI_Master_1;
wire [2:0] ARSIZE_AXI_Master_1;
wire [1:0] ARBURST_AXI_Master_1;
wire [1:0] ARLOCK_AXI_Master_1;
wire [3:0] ARCACHE_AXI_Master_1;
wire [2:0] ARPROT_AXI_Master_1;
wire [3:0] ARQOS_AXI_Master_1;
wire [3:0] ARREGION_AXI_Master_1;
wire ARVALID_AXI_Master_1;wire ARREADY_AXI_Master_1;
wire [MEM_ID_WIDTH-1:0] RID_AXI_Master_1;
wire [DATA_WIDTH-1:0] RDATA_AXI_Master_1;
wire [1:0] RRESP_AXI_Master_1;
wire RLAST_AXI_Master_1;
wire RVALID_AXI_Master_1;
wire RREADY_AXI_Master_1;
// Internal wiring to DMA M0
wire [3:0] AWID_AXI4_Slave_1;
wire [31:0] AWADDR_AXI4_Slave_1;
wire [7:0] AWLEN_AXI4_Slave_1;
wire [2:0] AWSIZE_AXI4_Slave_1;
wire [1:0] AWBURST_AXI4_Slave_1;
wire AWLOCK_AXI4_Slave_1;
wire [3:0] AWCACHE_AXI4_Slave_1;
wire [2:0] AWPROT_AXI4_Slave_1;
wire AWVALID_AXI4_Slave_1;
wire AWREADY_AXI4_Slave_1;
wire [63:0] WDATA_AXI4_Slave_1;
wire [7:0] WSTRB_AXI4_Slave_1;
wire WLAST_AXI4_Slave_1;
wire WVALID_AXI4_Slave_1;
wire WREADY_AXI4_Slave_1;
wire [3:0] BID_AXI4_Slave_1;
wire [1:0] BRESP_AXI4_Slave_1;
wire BVALID_AXI4_Slave_1;
wire BREADY_AXI4_Slave_1;
wire [3:0] ARID_AXI4_Slave_1;
wire [31:0] ARADDR_AXI4_Slave_1;
wire [7:0] ARLEN_AXI4_Slave_1;
wire [2:0] ARSIZE_AXI4_Slave_1;
wire [1:0] ARBURST_AXI4_Slave_1;
wire ARLOCK_AXI4_Slave_1;
wire [3:0] ARCACHE_AXI4_Slave_1;
wire [2:0] ARPROT_AXI4_Slave_1;
wire ARVALID_AXI4_Slave_1;
wire ARREADY_AXI4_Slave_1;
wire [3:0] RID_AXI4_Slave_1;
wire [63:0] RDATA_AXI4_Slave_1;
wire [1:0] RRESP_AXI4_Slave_1;
wire RLAST_AXI4_Slave_1;
wire RVALID_AXI4_Slave_1;
wire RREADY_AXI4_Slave_1;
// Internal wiring to DMA M1
wire [3:0] AWID_AXI4_Slave_2;
wire [31:0] AWADDR_AXI4_Slave_2;
wire [7:0] AWLEN_AXI4_Slave_2;
wire [2:0] AWSIZE_AXI4_Slave_2;
wire [1:0] AWBURST_AXI4_Slave_2;
wire AWLOCK_AXI4_Slave_2;
wire [3:0] AWCACHE_AXI4_Slave_2;
wire [2:0] AWPROT_AXI4_Slave_2;
wire AWVALID_AXI4_Slave_2;
wire AWREADY_AXI4_Slave_2;
wire [63:0] WDATA_AXI4_Slave_2;
wire [7:0] WSTRB_AXI4_Slave_2;
wire WLAST_AXI4_Slave_2;
wire WVALID_AXI4_Slave_2;
wire WREADY_AXI4_Slave_2;
wire [3:0] BID_AXI4_Slave_2;
wire [1:0] BRESP_AXI4_Slave_2;
wire BVALID_AXI4_Slave_2;
wire BREADY_AXI4_Slave_2;
wire [3:0] ARID_AXI4_Slave_2;
wire [31:0] ARADDR_AXI4_Slave_2;
wire [7:0] ARLEN_AXI4_Slave_2;
wire [2:0] ARSIZE_AXI4_Slave_2;
wire [1:0] ARBURST_AXI4_Slave_2;wire ARLOCK_AXI4_Slave_2;
wire [3:0] ARCACHE_AXI4_Slave_2;
wire [2:0] ARPROT_AXI4_Slave_2;
wire ARVALID_AXI4_Slave_2;
wire ARREADY_AXI4_Slave_2;
wire [3:0] RID_AXI4_Slave_2;
wire [63:0] RDATA_AXI4_Slave_2;
wire [1:0] RRESP_AXI4_Slave_2;
wire RLAST_AXI4_Slave_2;
wire RVALID_AXI4_Slave_2;
wire RREADY_AXI4_Slave_2;
nic400_1 u_nic400_1 (
.clk0clk(clk),
.clk0resetn(rst),
// AXI Master 0 to IntMem 0
.AWID_AXI_Master_0(AWID_AXI_Master_0),
.AWADDR_AXI_Master_0(AWADDR_AXI_Master_0),
.AWLEN_AXI_Master_0(AWLEN_AXI_Master_0),
.AWSIZE_AXI_Master_0(AWSIZE_AXI_Master_0),
.AWBURST_AXI_Master_0(AWBURST_AXI_Master_0),
.AWLOCK_AXI_Master_0(AWLOCK_AXI_Master_0),
.AWCACHE_AXI_Master_0(AWCACHE_AXI_Master_0),
.AWPROT_AXI_Master_0(AWPROT_AXI_Master_0),
.AWVALID_AXI_Master_0(AWVALID_AXI_Master_0),
.AWREADY_AXI_Master_0(AWREADY_AXI_Master_0),
.WID_AXI_Master_0(WID_AXI_Master_0),
.WDATA_AXI_Master_0(WDATA_AXI_Master_0),
.WSTRB_AXI_Master_0(WSTRB_AXI_Master_0),
.WLAST_AXI_Master_0(WLAST_AXI_Master_0),
.WVALID_AXI_Master_0(WVALID_AXI_Master_0),
.WREADY_AXI_Master_0(WREADY_AXI_Master_0),
.BID_AXI_Master_0(BID_AXI_Master_0),
.BRESP_AXI_Master_0(BRESP_AXI_Master_0),
.BVALID_AXI_Master_0(BVALID_AXI_Master_0),
.BREADY_AXI_Master_0(BREADY_AXI_Master_0),
.ARID_AXI_Master_0(ARID_AXI_Master_0),
.ARADDR_AXI_Master_0(ARADDR_AXI_Master_0),
.ARLEN_AXI_Master_0(ARLEN_AXI_Master_0),
.ARSIZE_AXI_Master_0(ARSIZE_AXI_Master_0),
.ARBURST_AXI_Master_0(ARBURST_AXI_Master_0),
.ARLOCK_AXI_Master_0(ARLOCK_AXI_Master_0),
.ARCACHE_AXI_Master_0(ARCACHE_AXI_Master_0),
.ARPROT_AXI_Master_0(ARPROT_AXI_Master_0),
.ARVALID_AXI_Master_0(ARVALID_AXI_Master_0),
.ARREADY_AXI_Master_0(ARREADY_AXI_Master_0),
.RID_AXI_Master_0(RID_AXI_Master_0),
.RDATA_AXI_Master_0(RDATA_AXI_Master_0),
.RRESP_AXI_Master_0(RRESP_AXI_Master_0),
.RLAST_AXI_Master_0(RLAST_AXI_Master_0),
.RVALID_AXI_Master_0(RVALID_AXI_Master_0),
.RREADY_AXI_Master_0(RREADY_AXI_Master_0),
// AXI Master 1 to IntMem1
.AWID_AXI_Master_1(AWID_AXI_Master_1),
.AWADDR_AXI_Master_1(AWADDR_AXI_Master_1),
.AWLEN_AXI_Master_1(AWLEN_AXI_Master_1),
.AWSIZE_AXI_Master_1(AWSIZE_AXI_Master_1),
.AWBURST_AXI_Master_1(AWBURST_AXI_Master_1),
.AWLOCK_AXI_Master_1(AWLOCK_AXI_Master_1),
.AWCACHE_AXI_Master_1(AWCACHE_AXI_Master_1),
.AWPROT_AXI_Master_1(AWPROT_AXI_Master_1),
.AWVALID_AXI_Master_1(AWVALID_AXI_Master_1),
.AWREADY_AXI_Master_1(AWREADY_AXI_Master_1),
.WID_AXI_Master_1(WID_AXI_Master_1),
.WDATA_AXI_Master_1(WDATA_AXI_Master_1),
.WSTRB_AXI_Master_1(WSTRB_AXI_Master_1),
.WLAST_AXI_Master_1(WLAST_AXI_Master_1),
.WVALID_AXI_Master_1(WVALID_AXI_Master_1), .WREADY_AXI_Master_1(WREADY_AXI_Master_1),
.BID_AXI_Master_1(BID_AXI_Master_1),
.BRESP_AXI_Master_1(BRESP_AXI_Master_1),
.BVALID_AXI_Master_1(BVALID_AXI_Master_1),
.BREADY_AXI_Master_1(BREADY_AXI_Master_1),
.ARID_AXI_Master_1(ARID_AXI_Master_1),
.ARADDR_AXI_Master_1(ARADDR_AXI_Master_1),
.ARLEN_AXI_Master_1(ARLEN_AXI_Master_1),
.ARSIZE_AXI_Master_1(ARSIZE_AXI_Master_1),
.ARBURST_AXI_Master_1(ARBURST_AXI_Master_1),
.ARLOCK_AXI_Master_1(ARLOCK_AXI_Master_1),
.ARCACHE_AXI_Master_1(ARCACHE_AXI_Master_1),
.ARPROT_AXI_Master_1(ARPROT_AXI_Master_1),
.ARVALID_AXI_Master_1(ARVALID_AXI_Master_1),
.ARREADY_AXI_Master_1(ARREADY_AXI_Master_1),
.RID_AXI_Master_1(RID_AXI_Master_1),
.RDATA_AXI_Master_1(RDATA_AXI_Master_1),
.RRESP_AXI_Master_1(RRESP_AXI_Master_1),
.RLAST_AXI_Master_1(RLAST_AXI_Master_1),
.RVALID_AXI_Master_1(RVALID_AXI_Master_1),
.RREADY_AXI_Master_1(RREADY_AXI_Master_1),
// AXI Slave 0, for debug
.AWID_AXI4_Slave_0(axi_awid),
.AWADDR_AXI4_Slave_0(axi_awaddr),
.AWLEN_AXI4_Slave_0(axi_awlen),
.AWSIZE_AXI4_Slave_0(axi_awsize),
.AWBURST_AXI4_Slave_0(axi_awburst),
.AWLOCK_AXI4_Slave_0(axi_awlock),
.AWCACHE_AXI4_Slave_0(axi_awcache),
.AWPROT_AXI4_Slave_0(axi_awprot),
.AWVALID_AXI4_Slave_0(axi_awvalid),
.AWREADY_AXI4_Slave_0(axi_awready),
.WDATA_AXI4_Slave_0(axi_wdata),
.WSTRB_AXI4_Slave_0(axi_wstrb),
.WLAST_AXI4_Slave_0(axi_wlast),
.WVALID_AXI4_Slave_0(axi_wvalid),
.WREADY_AXI4_Slave_0(axi_wready),
.BID_AXI4_Slave_0(axi_bid),
.BRESP_AXI4_Slave_0(axi_bresp),
.BVALID_AXI4_Slave_0(axi_bvalid),
.BREADY_AXI4_Slave_0(axi_bready),
.ARID_AXI4_Slave_0(axi_arid),
.ARADDR_AXI4_Slave_0(axi_araddr),
.ARLEN_AXI4_Slave_0(axi_arlen),
.ARSIZE_AXI4_Slave_0(axi_arsize),
.ARBURST_AXI4_Slave_0(axi_arburst),
.ARLOCK_AXI4_Slave_0(axi_arlock),
.ARCACHE_AXI4_Slave_0(axi_arcache),
.ARPROT_AXI4_Slave_0(axi_arprot),
.ARVALID_AXI4_Slave_0(axi_arvalid),
.ARREADY_AXI4_Slave_0(axi_arready),
.RID_AXI4_Slave_0(axi_rid),
.RDATA_AXI4_Slave_0(axi_rdata),
.RRESP_AXI4_Slave_0(axi_rresp),
.RLAST_AXI4_Slave_0(axi_rlast),
.RVALID_AXI4_Slave_0(axi_rvalid),
.RREADY_AXI4_Slave_0(axi_rready),
// AXI Slave 1, for DMA M0
.AWID_AXI4_Slave_1(AWID_AXI4_Slave_1),
.AWADDR_AXI4_Slave_1(AWADDR_AXI4_Slave_1),
.AWLEN_AXI4_Slave_1(AWLEN_AXI4_Slave_1),
.AWSIZE_AXI4_Slave_1(AWSIZE_AXI4_Slave_1),
.AWBURST_AXI4_Slave_1(AWBURST_AXI4_Slave_1),
.AWLOCK_AXI4_Slave_1(AWLOCK_AXI4_Slave_1),
.AWCACHE_AXI4_Slave_1(AWCACHE_AXI4_Slave_1),
.AWPROT_AXI4_Slave_1(AWPROT_AXI4_Slave_1),
.AWVALID_AXI4_Slave_1(AWVALID_AXI4_Slave_1),
.AWREADY_AXI4_Slave_1(AWREADY_AXI4_Slave_1),
.WDATA_AXI4_Slave_1(WDATA_AXI4_Slave_1),
.WSTRB_AXI4_Slave_1(WSTRB_AXI4_Slave_1),
.WLAST_AXI4_Slave_1(WLAST_AXI4_Slave_1),
.WVALID_AXI4_Slave_1(WVALID_AXI4_Slave_1),
.WREADY_AXI4_Slave_1(WREADY_AXI4_Slave_1),
.BID_AXI4_Slave_1(BID_AXI4_Slave_1),
.BRESP_AXI4_Slave_1(BRESP_AXI4_Slave_1),
.BVALID_AXI4_Slave_1(BVALID_AXI4_Slave_1),
.BREADY_AXI4_Slave_1(BREADY_AXI4_Slave_1),
.ARID_AXI4_Slave_1(ARID_AXI4_Slave_1),
.ARADDR_AXI4_Slave_1(ARADDR_AXI4_Slave_1),
.ARLEN_AXI4_Slave_1(ARLEN_AXI4_Slave_1),
.ARSIZE_AXI4_Slave_1(ARSIZE_AXI4_Slave_1),
.ARBURST_AXI4_Slave_1(ARBURST_AXI4_Slave_1),
.ARLOCK_AXI4_Slave_1(ARLOCK_AXI4_Slave_1),
.ARCACHE_AXI4_Slave_1(ARCACHE_AXI4_Slave_1),
.ARPROT_AXI4_Slave_1(ARPROT_AXI4_Slave_1),
.ARVALID_AXI4_Slave_1(ARVALID_AXI4_Slave_1),
.ARREADY_AXI4_Slave_1(ARREADY_AXI4_Slave_1),
.RID_AXI4_Slave_1(RID_AXI4_Slave_1),
.RDATA_AXI4_Slave_1(RDATA_AXI4_Slave_1),
.RRESP_AXI4_Slave_1(RRESP_AXI4_Slave_1),
.RLAST_AXI4_Slave_1(RLAST_AXI4_Slave_1),
.RVALID_AXI4_Slave_1(RVALID_AXI4_Slave_1),
.RREADY_AXI4_Slave_1(RREADY_AXI4_Slave_1),
// AXI Slave 1, for DMA M1
.AWID_AXI4_Slave_2(AWID_AXI4_Slave_2),
.AWADDR_AXI4_Slave_2(AWADDR_AXI4_Slave_2),
.AWLEN_AXI4_Slave_2(AWLEN_AXI4_Slave_2),
.AWSIZE_AXI4_Slave_2(AWSIZE_AXI4_Slave_2),
.AWBURST_AXI4_Slave_2(AWBURST_AXI4_Slave_2),
.AWLOCK_AXI4_Slave_2(AWLOCK_AXI4_Slave_2),
.AWCACHE_AXI4_Slave_2(AWCACHE_AXI4_Slave_2),
.AWPROT_AXI4_Slave_2(AWPROT_AXI4_Slave_2),
.AWVALID_AXI4_Slave_2(AWVALID_AXI4_Slave_2),
.AWREADY_AXI4_Slave_2(AWREADY_AXI4_Slave_2),
.WDATA_AXI4_Slave_2(WDATA_AXI4_Slave_2),
.WSTRB_AXI4_Slave_2(WSTRB_AXI4_Slave_2),
.WLAST_AXI4_Slave_2(WLAST_AXI4_Slave_2),
.WVALID_AXI4_Slave_2(WVALID_AXI4_Slave_2),
.WREADY_AXI4_Slave_2(WREADY_AXI4_Slave_2),
.BID_AXI4_Slave_2(BID_AXI4_Slave_2),
.BRESP_AXI4_Slave_2(BRESP_AXI4_Slave_2),
.BVALID_AXI4_Slave_2(BVALID_AXI4_Slave_2),
.BREADY_AXI4_Slave_2(BREADY_AXI4_Slave_2),
.ARID_AXI4_Slave_2(ARID_AXI4_Slave_2),
.ARADDR_AXI4_Slave_2(ARADDR_AXI4_Slave_2),
.ARLEN_AXI4_Slave_2(ARLEN_AXI4_Slave_2),
.ARSIZE_AXI4_Slave_2(ARSIZE_AXI4_Slave_2),
.ARBURST_AXI4_Slave_2(ARBURST_AXI4_Slave_2),
.ARLOCK_AXI4_Slave_2(ARLOCK_AXI4_Slave_2),
.ARCACHE_AXI4_Slave_2(ARCACHE_AXI4_Slave_2),
.ARPROT_AXI4_Slave_2(ARPROT_AXI4_Slave_2),
.ARVALID_AXI4_Slave_2(ARVALID_AXI4_Slave_2),
.ARREADY_AXI4_Slave_2(ARREADY_AXI4_Slave_2),
.RID_AXI4_Slave_2(RID_AXI4_Slave_2),
.RDATA_AXI4_Slave_2(RDATA_AXI4_Slave_2),
.RRESP_AXI4_Slave_2(RRESP_AXI4_Slave_2),
.RLAST_AXI4_Slave_2(RLAST_AXI4_Slave_2),
.RVALID_AXI4_Slave_2(RVALID_AXI4_Slave_2),
.RREADY_AXI4_Slave_2(RREADY_AXI4_Slave_2)
);
IntMemBhavAxi u_sram_0(
// INPUTS
// global signals
.ACLK(clk),
.ARESETn(rst),
// Write Address Channel
.AWVALID(AWVALID_AXI_Master_0),
.AWID(AWID_AXI_Master_0),
.AWADDR(AWADDR_AXI_Master_0),
.AWLEN(AWLEN_AXI_Master_0),
.AWSIZE(AWSIZE_AXI_Master_0),
.AWBURST(AWBURST_AXI_Master_0),
// Write Channel
.WVALID(WVALID_AXI_Master_0),
.WLAST(WLAST_AXI_Master_0),
.WSTRB(WSTRB_AXI_Master_0),
.WDATA(WDATA_AXI_Master_0),
// Write Response Channel
.BREADY(BREADY_AXI_Master_0),
// Read Address Channel
.ARVALID(ARVALID_AXI_Master_0),
.ARID(ARID_AXI_Master_0),
.ARADDR(ARADDR_AXI_Master_0),
.ARLEN(ARLEN_AXI_Master_0),
.ARSIZE(ARSIZE_AXI_Master_0),
.ARBURST(ARBURST_AXI_Master_0),
// Read Channel
.RREADY(RREADY_AXI_Master_0),
// dummy scan pins
.SCANENABLE(1'b0),
.SCANINACLK(),
// OUTPUTS
// Write Address Channel
.AWREADY(AWREADY_AXI_Master_0),
// Write Channel
.WREADY(WREADY_AXI_Master_0),
// Write Response Channel
.BVALID(BVALID_AXI_Master_0),
.BRESP(BRESP_AXI_Master_0),
.BID(BID_AXI_Master_0),
// Read Address Channel
.ARREADY(ARREADY_AXI_Master_0),
// Read Channel
.RVALID(RVALID_AXI_Master_0),
.RID(RID_AXI_Master_0),
.RLAST(RLAST_AXI_Master_0),
.RRESP(RRESP_AXI_Master_0),
.RDATA(RDATA_AXI_Master_0),
// dummy scan pins
.SCANOUTACLK()
);
IntMemBhavAxi u_sram_1(
// INPUTS
// global signals
.ACLK(clk),
.ARESETn(rst),
// Write Address Channel
.AWVALID(AWVALID_AXI_Master_1),
.AWID(AWID_AXI_Master_1),
.AWADDR(AWADDR_AXI_Master_1),
.AWLEN(AWLEN_AXI_Master_1),
.AWSIZE(AWSIZE_AXI_Master_1),
.AWBURST(AWBURST_AXI_Master_1),
// Write Channel
.WVALID(WVALID_AXI_Master_1),
.WLAST(WLAST_AXI_Master_1),
.WSTRB(WSTRB_AXI_Master_1),
.WDATA(WDATA_AXI_Master_1),
// Write Response Channel
.BREADY(BREADY_AXI_Master_1),
// Read Address Channel
.ARVALID(ARVALID_AXI_Master_1),
.ARID(ARID_AXI_Master_1),
.ARADDR(ARADDR_AXI_Master_1),
.ARLEN(ARLEN_AXI_Master_1),
.ARSIZE(ARSIZE_AXI_Master_1),
.ARBURST(ARBURST_AXI_Master_1),
// Read Channel
.RREADY(RREADY_AXI_Master_1),
// dummy scan pins
.SCANENABLE(1'b0),
.SCANINACLK(),
// OUTPUTS
// Write Address Channel
.AWREADY(AWREADY_AXI_Master_1),
// Write Channel
.WREADY(WREADY_AXI_Master_1),
// Write Response Channel
.BVALID(BVALID_AXI_Master_1),
.BRESP(BRESP_AXI_Master_1),
.BID(BID_AXI_Master_1),
// Read Address Channel
.ARREADY(ARREADY_AXI_Master_1),
// Read Channel
.RVALID(RVALID_AXI_Master_1),
.RID(RID_AXI_Master_1),
.RLAST(RLAST_AXI_Master_1),
.RRESP(RRESP_AXI_Master_1),
.RDATA(RDATA_AXI_Master_1),
// dummy scan pins
.SCANOUTACLK()
);
wire [63:0] s_axis_tdata;
wire s_axis_tvalid;
wire s_axis_tready;
wire s_axis_tlast;
wire [7:0] s_axis_tstrb;
wire [63:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tready;
wire m_axis_tlast;
wire [7:0] m_axis_tstrb;wire m_axis_tflush;
wire trig_dma_req;
wire [1:0] trig_dma_type;
wire trig_dma_ack;
wire [1:0] trig_dma_ack_type;
wire trig_acc_req;
wire trig_acc_ack;
axis_pipeline_fifo u_axis_fifo (
.clk(clk),
.rst(~rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast)
);
ada_top_sldma350 u_DMA(
.clk(clk),
.resetn(rst),
.aclken_m0(1'b1),
.aclken_m1(1'b1),
.pclken(1'b1),
.clk_qreqn(1'b1),
.clk_qacceptn(),
.clk_qdeny(),
.clk_qactive(),
.preq(1'b0),
.pstate(4'b1000),
.paccept(),
.pdeny(),
.pactive(),
.pwakeup(1'b1),
.pdebug(1'b0),
.psel(APB_PSEL),
.penable(APB_PENABLE),
.pprot(3'b100),
.pwrite(APB_PWRITE),
.paddr(APB_PADDR),
.pwdata(APB_PWDATA),
.pstrb(APB_PSTRB),
.pready(APB_PREADY),
.pslverr(APB_PSLVERR),
.prdata(APB_PRDATA),
// AXI Signals
.awakeup_m0(),
.awvalid_m0(AWVALID_AXI4_Slave_1),
.awaddr_m0(AWADDR_AXI4_Slave_1),
.awburst_m0(AWBURST_AXI4_Slave_1),
.awlen_m0(AWLEN_AXI4_Slave_1),
.awsize_m0(AWSIZE_AXI4_Slave_1),
.awqos_m0(),
.awprot_m0(AWPROT_AXI4_Slave_1),
.awready_m0(AWREADY_AXI4_Slave_1),
.awcache_m0(AWCACHE_AXI4_Slave_1),
.awinner_m0(),
.awdomain_m0(),
.awchid_m0(AWID_AXI4_Slave_1),
.awchidvalid_m0(),
.arvalid_m0(ARVALID_AXI4_Slave_1), .araddr_m0(ARADDR_AXI4_Slave_1),
.arburst_m0(ARBURST_AXI4_Slave_1),
.arlen_m0(ARLEN_AXI4_Slave_1),
.arsize_m0(ARSIZE_AXI4_Slave_1),
.arqos_m0(),
.arprot_m0(ARPROT_AXI4_Slave_1),
.arready_m0(ARREADY_AXI4_Slave_1),
.arcache_m0(ARCACHE_AXI4_Slave_1),
.arinner_m0(),
.ardomain_m0(),
.archid_m0(ARID_AXI4_Slave_1),
.archidvalid_m0(),
.arcmdlink_m0(),
.wvalid_m0(WVALID_AXI4_Slave_1),
.wlast_m0(WLAST_AXI4_Slave_1),
.wstrb_m0(WSTRB_AXI4_Slave_1),
.wdata_m0(WDATA_AXI4_Slave_1),
.wready_m0(WREADY_AXI4_Slave_1),
.rvalid_m0(RVALID_AXI4_Slave_1),
.rlast_m0(RLAST_AXI4_Slave_1),
.rdata_m0(RDATA_AXI4_Slave_1),
.rpoison_m0(1'b0),
.rresp_m0(RRESP_AXI4_Slave_1),
.rready_m0(RREADY_AXI4_Slave_1),
.bvalid_m0(BVALID_AXI4_Slave_1),
.bresp_m0(BRESP_AXI4_Slave_1),
.bready_m0(BREADY_AXI4_Slave_1),
// AXI Signals
.awakeup_m1(),
.awvalid_m1(AWVALID_AXI4_Slave_2),
.awaddr_m1(AWADDR_AXI4_Slave_2),
.awburst_m1(AWBURST_AXI4_Slave_2),
.awlen_m1(AWLEN_AXI4_Slave_2),
.awsize_m1(AWSIZE_AXI4_Slave_2),
.awqos_m1(),
.awprot_m1(AWPROT_AXI4_Slave_2),
.awready_m1(AWREADY_AXI4_Slave_2),
.awcache_m1(AWCACHE_AXI4_Slave_2),
.awinner_m1(),
.awdomain_m1(),
.awchid_m1(AWID_AXI4_Slave_2),
.awchidvalid_m1(),
.arvalid_m1(ARVALID_AXI4_Slave_2),
.araddr_m1(ARADDR_AXI4_Slave_2),
.arburst_m1(ARBURST_AXI4_Slave_2),
.arlen_m1(ARLEN_AXI4_Slave_2),
.arsize_m1(ARSIZE_AXI4_Slave_2),
.arqos_m1(),
.arprot_m1(ARPROT_AXI4_Slave_2),
.arready_m1(ARREADY_AXI4_Slave_2),
.arcache_m1(ARCACHE_AXI4_Slave_2),
.arinner_m1(),
.ardomain_m1(),
.archid_m1(ARID_AXI4_Slave_2),
.archidvalid_m1(),
.arcmdlink_m1(),
.wvalid_m1(WVALID_AXI4_Slave_2),
.wlast_m1(WLAST_AXI4_Slave_2),
.wstrb_m1(WSTRB_AXI4_Slave_2),
.wdata_m1(WDATA_AXI4_Slave_2),
.wready_m1(WREADY_AXI4_Slave_2),
.rvalid_m1(RVALID_AXI4_Slave_2),
.rlast_m1(RLAST_AXI4_Slave_2), .rdata_m1(RDATA_AXI4_Slave_2),
.rpoison_m1(1'b0),
.rresp_m1(RRESP_AXI4_Slave_2),
.rready_m1(RREADY_AXI4_Slave_2),
.bvalid_m1(BVALID_AXI4_Slave_2),
.bresp_m1(BRESP_AXI4_Slave_2),
.bready_m1(BREADY_AXI4_Slave_2),
.trig_in_0_req(trig_dma_req),
.trig_in_0_req_type(trig_dma_type),
.trig_in_0_ack(trig_dma_ack),
.trig_in_0_ack_type(trig_dma_ack_type),
.trig_out_0_req(trig_acc_req),
.trig_out_0_ack(trig_acc_ack),
.irq_channel(),
.irq_comb_nonsec(),
.str_out_0_tvalid(s_axis_tvalid),
.str_out_0_tready(s_axis_tready),
.str_out_0_tdata(s_axis_tdata),
.str_out_0_tstrb(s_axis_tstrb),
.str_out_0_tlast(s_axis_tlast),
.str_in_0_tvalid(m_axis_tvalid),
.str_in_0_tready(m_axis_tready),
.str_in_0_tdata(m_axis_tdata),
.str_in_0_tstrb(8'hFF),
.str_in_0_tlast(m_axis_tlast),
.str_in_0_flush(m_axis_tflush),
.allch_stop_req_nonsec(1'b0),
.allch_stop_ack_nonsec(),
.allch_pause_req_nonsec(1'b0),
.allch_pause_ack_nonsec(),
.ch_enabled(dma_active),
.ch_err(),
.ch_stopped(),
.ch_paused(),
.ch_priv(),
.halt_req(1'b0),
.restart_req(1'b0),
.halted(),
.boot_en(1'b0),
.boot_addr(),
.boot_memattr(),
.boot_shareattr()
);
endmodule