diff --git a/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv b/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1c573bc7d1b8b54467107339ce99957015d112a9
--- /dev/null
+++ b/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
@@ -0,0 +1,52 @@
+/////////////////////////////////////////////////////////////////////
+// Design unit: Arithmetic Testbench
+// :
+// File name : Arithmetic_tb.sv
+// :
+// Description: Test Posit Adder Arithmetic
+// :
+// Limitations: None
+// :
+// System : SystemVerilog IEEE 1800-2005
+// :
+// Author : Xiaoan He (Jasper)
+// : xh2g20@ecs.soton.ac.uk
+//
+// Revision : Version 1.0 23/11/2022
+/////////////////////////////////////////////////////////////////////
+function [31:0] log2;
+input reg [31:0] value;
+ begin
+ value = value-1;
+ for (log2=0; value>0; log2=log2+1)
+ value = value>>1;
+ end
+endfunction
+
+module Arithmetic_tb;
+parameter N = 8, RS = log2(N), ES = 3;
+
+// input logic
+logic signed [N-2:0] InRemain1, InRemain2;
+logic Sign1, Sign2;
+logic signed [RS:0] RegimeValue1, RegimeValue2;
+logic [ES-1:0] Exponent1, Exponent2;
+logic [N-ES+2:0] Mantissa1, Mantissa2;
+
+// output logic
+logic [N-1:0] Add_Mant
+
+Arithmetic #(.N(N), .ES(ES)) Add1 (.*);
+
+initial
+ begin
+
+ #10ns InRemain1 = '0, InRemain2 = '0, Sign1 = '0, Sign2 = '0, RegimeValue1 = '0, RegimeValue2 = '0,
+ Exponent1 = '0, Exponent2 = '0, Mantissa1 = '0, Mantissa2 = '0;
+
+ #50ns InRemain1 = 7'b1110_010, InRemain2 = 7'b110_111_0, Sign1 = 0, Sign2 = 0, RegimeValue1 = 2, RegimeValue2 = 1,
+ Exponent1 = 3'b010, Exponent2 = 3'b111, Mantissa1 = '0, Mantissa2 = '0;
+
+ end
+
+endmodule
\ No newline at end of file
diff --git a/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv b/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2a706c775285ba1e38ce318124498b335377f31e
--- /dev/null
+++ b/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv
@@ -0,0 +1,87 @@
+/////////////////////////////////////////////////////////////////////
+// Design unit: Posit Adder Arithmetic
+// :
+// File name : Posit_Adder_Arithmetic.sv
+// :
+// Description: Mantissa addition and subtraction
+// : exponent and regime computation
+// :
+// Limitations: None
+// :
+// System : SystemVerilog IEEE 1800-2005
+// :
+// Author : Xiaoan He (Jasper)
+// : xh2g20@ecs.soton.ac.uk
+//
+// Revision : Version 1.0 23/11/2022
+/////////////////////////////////////////////////////////////////////
+
+function [31:0] log2;
+ input reg [31:0] value;
+ begin
+ value = value-1;
+ for (log2=0; value>0; log2=log2+1)
+ value = value>>1;
+ end
+endfunction
+
+module Arithmetic #(parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+ input logic signed [N-2:0] InRemain1, InRemain2,
+ input logic Sign1, Sign2,
+ input logic signed [RS:0] RegimeValue1, RegimeValue2,
+ input logic [ES-1:0] Exponent1, Exponent2,
+ input logic [N-ES+2:0] Mantissa1, Mantissa2,
+ output logic [N-1:0] Add_Mant
+);
+
+// Confirm the operation (s1 xor s2)
+logic Operation = Sign1 ^ Sign2 ;
+
+// Find the greater input
+logic Greater_Than = (InRemain1[N-2:0] > InRemain2[N-2:0])? 1'b1 : 1'b0;
+
+// Assign components to corresponding logic, L - Large S - Small
+logic LS = Greater_Than ? Sign1 : Sign2;
+logic LR = Greater_Than ? RegimeValue1 : RegimeValue2;
+logic LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
+logic LE = Greater_Than ? Exponent1 : Exponent2;
+logic LM = Greater_Than ? Mantissa1 : Mantissa2;
+
+logic SS = Greater_Than ? Sign2 : Sign1;
+logic SR = Greater_Than ? RegimeValue2 : RegimeValue1;
+logic SRC = Greater_Than? InRemain2[N-2] : InRemain1[N-2];
+logic SE = Greater_Than ? Exponent2 : Exponent1;
+logic SM = Greater_Than ? Mantissa2 : Mantissa1;
+
+// Mantissa Addition
+
+logic sign [RS:0] R_diff;
+/*
+find regime difference,
+when both of them are +ve, the difference is RV1 - RV2
+when RV1 +ve but RV2 -ve, the difference is RV1 + RV2
+when RV1 -ve => RV2 also -ve, still RV1 - RV2
+*/
+if (RegimeValue1 >= 0 || RegimeValue2 >= 0)
+ R_diff = RegimeValue1 - RegimeValue2;
+else if (RegimeValue1 >= 0 || RegimeValue2 < 0)
+ R_diff = RegimeValue1 + RegimeValue2;
+else if (RegimeValue1 < 0)
+ R_diff = RegimeValue1 - RegimeValue2;
+
+logic E_diff;
+/*
+after the R_diff found, remember that the regime contributes into the exponent
+as (Useed ^ RegimeValue) where Useed = 2^(2^ES)
+so the E_diff is (R_diff x log2(useed) + LE - SE)
+the reason why it is R_diff x log2(useed) is
+the exponent (2 ^ what)is what we want to find
+for exponent bits, it is the difference
+for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
+*/
+E_diff = (R_diff*log2(2**(2**(ES)))) + (LE - SE);
+
+logic SM_tmp = SM >> E_diff;
+logic Add_Mant = Operation ? LM + SM_tmp : LM - SM_tmp;
+endmodule
\ No newline at end of file
diff --git a/Individual_Project/Core_Arithmetic/Posit_Arithmetic.mpf b/Individual_Project/Core_Arithmetic/Posit_Arithmetic.mpf
new file mode 100644
index 0000000000000000000000000000000000000000..78646e6121cce7af36729455db1fc8d26c537279
--- /dev/null
+++ b/Individual_Project/Core_Arithmetic/Posit_Arithmetic.mpf
@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick =
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick =
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick =
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick =
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick =
+Project_Major_Version = 2020
+Project_Minor_Version = 1
diff --git a/Individual_Project/Core_Arithmetic/work/_info b/Individual_Project/Core_Arithmetic/work/_info
new file mode 100644
index 0000000000000000000000000000000000000000..28766bec8ae8b86d1596ca7dd6911d0674f66819
--- /dev/null
+++ b/Individual_Project/Core_Arithmetic/work/_info
@@ -0,0 +1,10 @@
+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+dH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction
diff --git a/Individual_Project/Data Extraction/Data_Extraction.cr.mti b/Individual_Project/Data Extraction/Data_Extraction.cr.mti
index fc33e3933123397733154082756a0c4970dc1d80..679de352dcc95b979d98b788587d9d4403653b90 100644
--- a/Individual_Project/Data Extraction/Data_Extraction.cr.mti
+++ b/Individual_Project/Data Extraction/Data_Extraction.cr.mti
@@ -1,5 +1,5 @@
-{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv}
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
+{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling package Posit_Extraction_sv_unit
-- Compiling module Data_Extraction
@@ -7,10 +7,18 @@ Top level modules:
Data_Extraction
} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv}
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module Leading_Bit_Detector
Top level modules:
Leading_Bit_Detector
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling package Test_Data_Extraction_sv_unit
+-- Compiling module Test_Data_Extraction
+
+Top level modules:
+ Test_Data_Extraction
+
} {} {}}
diff --git a/Individual_Project/Data Extraction/Data_Extraction.mpf b/Individual_Project/Data Extraction/Data_Extraction.mpf
index 72d42217e05ec76798dd1d9ce6bd5fb78e533c53..e8911392770e466e3425b1b2e9629536ffb0151b 100644
--- a/Individual_Project/Data Extraction/Data_Extraction.mpf
+++ b/Individual_Project/Data Extraction/Data_Extraction.mpf
@@ -2026,7 +2026,7 @@ suppress = 8780 ;an explanation can be had by running: verror 8780
; FlatLibPageDeleteThreshold = 1000
[Project]
-; Warning -- Do not edit the project properties directly.
+** Warning: ; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
@@ -2035,12 +2035,12 @@ Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 3
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1669057534 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1669058108 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1669133479 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1669059504 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1669058862 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1669133480 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -2088,5 +2088,5 @@ DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
-Project_Major_Version = 10
-Project_Minor_Version = 4
+Project_Major_Version = 2020
+Project_Minor_Version = 1
diff --git a/Individual_Project/Data Extraction/Data_Extraction_Testing.jpg b/Individual_Project/Data Extraction/Data_Extraction_Testing.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..c602a4d0ec61a86755de3cdf17bf8902357839f3
Binary files /dev/null and b/Individual_Project/Data Extraction/Data_Extraction_Testing.jpg differ
diff --git a/Individual_Project/Data Extraction/Data_Extraction_Testing_negative_value.jpg b/Individual_Project/Data Extraction/Data_Extraction_Testing_negative_value.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..165339221215c702cebd9a440158e9c7270ea6e3
Binary files /dev/null and b/Individual_Project/Data Extraction/Data_Extraction_Testing_negative_value.jpg differ
diff --git a/Individual_Project/Data Extraction/Posit_Extraction.sv b/Individual_Project/Data Extraction/Posit_Extraction.sv
index f6bf85863c4116dc0c440bfce89d7fcd8a875ca7..a1eb08f4ef8fa6ce5a1e3617f720b24c3a26e902 100644
--- a/Individual_Project/Data Extraction/Posit_Extraction.sv
+++ b/Individual_Project/Data Extraction/Posit_Extraction.sv
@@ -12,7 +12,7 @@
// Author : Xiaoan He (Jasper)
// : xh2g20@ecs.soton.ac.uk
//
-// Revision : Version 1.0 19/11/2022
+// Revision : Version 1.0 22/11/2022
/////////////////////////////////////////////////////////////////////
// `ifndef log_2
@@ -32,7 +32,7 @@ module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2
(
input logic signed [N-1:0] In,
output logic Sign,
- output logic signed [RS-1:0] RegimeValue,
+ output logic signed [RS:0] RegimeValue,
output logic [ES-1:0] Exponent,
output logic [N-ES+2:0] Mantissa
);
@@ -41,6 +41,7 @@ logic signed [N-2:0] InRemain;
logic RegimeCheck;
logic [RS:0] EndPosition;
logic signed [N-2:0] ShiftedRemain;
+logic [(N-ES+2)-1-(N-ES-2)-1:0] ZERO = '0;
int i;
Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
@@ -48,12 +49,14 @@ always_comb
begin
// Sign Bit Extraction
Sign = In[N-1];
- // if sign bit is true, then 2's compliment
- InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0];
+ InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0]; // if sign bit is true, then 2's compliment
// Regime Bits Extraction
-
-
+ /*
+ There is a Leading_Bit_Detector defined before the always_comb block
+ which takes the input without sign bit as module input and outputs
+ EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
+ */
if(RegimeCheck == 1'b1)
RegimeValue = EndPosition - 1;
else if (RegimeCheck == 0)
@@ -64,6 +67,6 @@ begin
Exponent = ShiftedRemain[N-1:((N-1)-ES)];
//Mantissa Bits Extraction
- Mantissa = {1'b1, ShiftedRemain[N-ES-2]};
+ Mantissa = {1'b1, ShiftedRemain[N-ES-2:0], ZERO};
end
endmodule
\ No newline at end of file
diff --git a/Individual_Project/Data Extraction/Test_Data_Extraction.sv b/Individual_Project/Data Extraction/Test_Data_Extraction.sv
index 685d46effd116c00b487db1b0332865c54d60068..73e886c4fb4c176804ee1901abd6d8115be7f696 100644
--- a/Individual_Project/Data Extraction/Test_Data_Extraction.sv
+++ b/Individual_Project/Data Extraction/Test_Data_Extraction.sv
@@ -42,8 +42,19 @@ initial
begin
// initial input is nothing
#10ns In = 8'b0_0000000;
- // sign=0 regime=10 exponent=1001,mant=1
- #50ns In = 8'b1_01_1000_0;
- // 0_10_1000_0
+ #50ns In = 8'b0_01_000_01; // R = -1, E = 100, M = 1.01
+ #50ns In = 8'b0_10_001_10; // R = 0, E = 100, M = 1.1
+ #50ns In = 8'b0_001_010_0; // R = -2, E = 100, M = 1.01
+ #50ns In = 8'b0_110_011_1; // R = 1, E = 100, M = 1.01
+ #50ns In = 8'b0_0001_100; // R = -3, E = 100, M = 1.01
+ #50ns In = 8'b0_1110_101; // R = 2, E = 100, M = 1.01
+ #50ns In = 8'b1_01_000_01; // 101_1111
+ #50ns In = 8'b1_10_001_10; // 011_1010
+ #50ns In = 8'b1_001_010_0; // 110_1100
+ #50ns In = 8'b1_110_011_1; // 001_s1001
+ #50ns In = 8'b1_0001_100; // 111_0100
+ #50ns In = 8'b1_1110_101; // 000_1011
+
+
end
endmodule
\ No newline at end of file
diff --git a/Individual_Project/Data Extraction/vsim.wlf b/Individual_Project/Data Extraction/vsim.wlf
new file mode 100644
index 0000000000000000000000000000000000000000..89eaafd8830116325c89a5120f4ec61182416dd9
Binary files /dev/null and b/Individual_Project/Data Extraction/vsim.wlf differ
diff --git a/Individual_Project/Data Extraction/wave b/Individual_Project/Data Extraction/wave
new file mode 100644
index 0000000000000000000000000000000000000000..547ef03f52e9c040f6177c6301909fb846f21494
--- /dev/null
+++ b/Individual_Project/Data Extraction/wave
@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/In[7]} -radix binary} {{/Test_Data_Extraction/In[6]} -radix binary} {{/Test_Data_Extraction/In[5]} -radix binary} {{/Test_Data_Extraction/In[4]} -radix binary} {{/Test_Data_Extraction/In[3]} -radix binary} {{/Test_Data_Extraction/In[2]} -radix binary} {{/Test_Data_Extraction/In[1]} -radix binary} {{/Test_Data_Extraction/In[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/In[7]} {-height 15 -radix binary} {/Test_Data_Extraction/In[6]} {-height 15 -radix binary} {/Test_Data_Extraction/In[5]} {-height 15 -radix binary} {/Test_Data_Extraction/In[4]} {-height 15 -radix binary} {/Test_Data_Extraction/In[3]} {-height 15 -radix binary} {/Test_Data_Extraction/In[2]} {-height 15 -radix binary} {/Test_Data_Extraction/In[1]} {-height 15 -radix binary} {/Test_Data_Extraction/In[0]} {-height 15 -radix binary}} /Test_Data_Extraction/In
+add wave -noupdate -radix decimal -childformat {{{/Test_Data_Extraction/RegimeValue[3]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[2]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[1]} -radix decimal} {{/Test_Data_Extraction/RegimeValue[0]} -radix decimal}} -expand -subitemconfig {{/Test_Data_Extraction/RegimeValue[3]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[2]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[1]} {-height 15 -radix decimal} {/Test_Data_Extraction/RegimeValue[0]} {-height 15 -radix decimal}} /Test_Data_Extraction/RegimeValue
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/Exponent[2]} -radix binary} {{/Test_Data_Extraction/Exponent[1]} -radix binary} {{/Test_Data_Extraction/Exponent[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/Exponent[2]} {-height 15 -radix binary} {/Test_Data_Extraction/Exponent[1]} {-height 15 -radix binary} {/Test_Data_Extraction/Exponent[0]} {-height 15 -radix binary}} /Test_Data_Extraction/Exponent
+add wave -noupdate -radix binary -childformat {{{/Test_Data_Extraction/Mantissa[7]} -radix binary} {{/Test_Data_Extraction/Mantissa[6]} -radix binary} {{/Test_Data_Extraction/Mantissa[5]} -radix binary} {{/Test_Data_Extraction/Mantissa[4]} -radix binary} {{/Test_Data_Extraction/Mantissa[3]} -radix binary} {{/Test_Data_Extraction/Mantissa[2]} -radix binary} {{/Test_Data_Extraction/Mantissa[1]} -radix binary} {{/Test_Data_Extraction/Mantissa[0]} -radix binary}} -expand -subitemconfig {{/Test_Data_Extraction/Mantissa[7]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[6]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[5]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[4]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[3]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[2]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[1]} {-height 15 -radix binary} {/Test_Data_Extraction/Mantissa[0]} {-height 15 -radix binary}} /Test_Data_Extraction/Mantissa
+add wave -noupdate -radix binary -expand /Test_Data_Extraction/extract1/InRemain
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {9 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 200
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {525 ns}
diff --git a/Individual_Project/Data Extraction/work/_info b/Individual_Project/Data Extraction/work/_info
index 1737cce6f935bf5686d256c3f4d0df9e67288dfa..b5c078d80755fa7daf674b055cbe3163b31b7a5e 100644
--- a/Individual_Project/Data Extraction/work/_info
+++ b/Individual_Project/Data Extraction/work/_info
@@ -1,6 +1,7 @@
m255
K4
z2
+!s11f MIXED_VERSIONS
13
!s112 1.1
!i10d 8192
@@ -9,124 +10,134 @@ z2
cModel Technology
dd:/modelsim/examples
vData_Extraction
-Z0 DXx6 sv_std 3 std 0 22 WmjPaeP=7F5?QFXzJ>D[Q2
-DXx4 work 24 Posit_Extraction_sv_unit 0 22 Ik5d90Sbo;Z_5B[6;nN?c3
-!i10b 1
-Z1 VDg1SIo80bB@j0V0VzS_@n1
+Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
+DXx4 work 24 Posit_Extraction_sv_unit 0 22 nHPXiXQN^`OPbJRiBjLAP0
+Z1 !s110 1669237135
+Z2 VDg1SIo80bB@j0V0VzS_@n1
r1
!s85 0
-31
-!s100 :9jDL8fgjON>>ZZzI=UH]1
-IX?9gdS@<E5GRYXNjTL2OY0
+!i10b 1
+!s100 iLkU_]<WlDhGmB:=]B3Pj0
+IW8FlU70Ik^0U]Vo06bDA_0
!s105 Posit_Extraction_sv_unit
S1
-Z2 dH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction
-Z3 w1669058108
-Z4 8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv
-Z5 FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv
-L0 31
-Z6 OP;L;10.4a;61
-Z7 !s108 1669058622.000000
-Z8 !s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv|
-Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Posit_Extraction.sv|
-!s101 -O0
+Z3 dH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction
+Z4 w1669133479
+Z5 8H:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv
+Z6 FH:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv
+!i122 45
+L0 31 42
+Z7 OV;L;2020.1;71
+31
+Z8 !s108 1669237135.000000
+Z9 !s107 H:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv|
+Z10 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:\INDIVIDUAL PROJECT\Posit\Individual_Project\Data Extraction\Posit_Extraction.sv|
!i113 1
-Z10 o-work work -sv -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
+Z11 o-work work -sv -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
+Z12 tCvgOpt 0
n@data_@extraction
vLeading_Bit_Detector
R0
-!i10b 1
R1
-r1
-!s85 0
-31
-!s100 RGaB4Z:d;NgXmE1MinB4=3
-I6CV7iYKKRNiPVe<:Jd7OZ3
-!s105 Leading_Bit_Detector_sv_unit
-S1
+!i10b 1
+!s100 l2kJkAGiPg>e_:A3_V9GP2
+!s11b Dg1SIo80bB@j0V0VzS_@n1
+IT;<KlXimJY^J7P];WGhFP3
R2
-w1669057534
+S1
+R3
+w1669059504
8H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv
FH:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv
-L0 19
-R6
+!i122 46
+L0 19 42
R7
+r1
+!s85 0
+31
+R8
!s107 H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Leading_Bit_Detector.sv|
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!s85 0
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vTest_Data_Extraction
R0
-DXx4 work 28 Test_Data_Extraction_sv_unit 0 22 eO`G7lR:hj`hW^[elH1aV3
+DXx4 work 28 Test_Data_Extraction_sv_unit 0 22 0d@CAzkJY053^Nzd6l`^n1
R1
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r1
!s85 0
-31
!i10b 1
-!s100 3RPk2ZiH_2bbhhGLnk:DO1
-I63^h:jSFcYooFdfcf]]f60
+!s100 LAOX3S:7DFNS11IQGij=i0
+IOX[^eCI>Y[Kff1d<z=PcL0
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-L0 27
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Z16 !s90 -reportprogress|300|-work|work|-sv|-stats=none|H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Data Extraction/Test_Data_Extraction.sv|
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R0
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diff --git a/Individual_Project/Data Extraction/work/_lib.qdb b/Individual_Project/Data Extraction/work/_lib.qdb
index ccfd7f544ec102bce0cd40551f084b9f18fd5348..d85891648ca55d8f2840cffbc6092e0cd93da21f 100644
Binary files a/Individual_Project/Data Extraction/work/_lib.qdb and b/Individual_Project/Data Extraction/work/_lib.qdb differ
diff --git a/Individual_Project/Data Extraction/work/_lib1_2.qpg b/Individual_Project/Data Extraction/work/_lib1_2.qpg
deleted file mode 100644
index aa5a29235c6cf9d7baef30e99d3fff7e70817671..0000000000000000000000000000000000000000
Binary files a/Individual_Project/Data Extraction/work/_lib1_2.qpg and /dev/null differ
diff --git a/Individual_Project/Data Extraction/work/_lib1_2.qtl b/Individual_Project/Data Extraction/work/_lib1_2.qtl
deleted file mode 100644
index 97c913c8c629a0c63a89a452a45b7cbdf3636e5f..0000000000000000000000000000000000000000
Binary files a/Individual_Project/Data Extraction/work/_lib1_2.qtl and /dev/null differ
diff --git a/Individual_Project/Data Extraction/work/_lib1_2.qdb b/Individual_Project/Data Extraction/work/_lib1_6.qdb
similarity index 94%
rename from Individual_Project/Data Extraction/work/_lib1_2.qdb
rename to Individual_Project/Data Extraction/work/_lib1_6.qdb
index 8accc9680f9e8a77a18e04dce56d174649a861fa..a26132504a8a00dc5abd1529990578f54cf9e68c 100644
Binary files a/Individual_Project/Data Extraction/work/_lib1_2.qdb and b/Individual_Project/Data Extraction/work/_lib1_6.qdb differ
diff --git a/Individual_Project/Data Extraction/work/_lib1_6.qpg b/Individual_Project/Data Extraction/work/_lib1_6.qpg
new file mode 100644
index 0000000000000000000000000000000000000000..99cbd9404c393df77ee7c9596fff28e7aa622f01
Binary files /dev/null and b/Individual_Project/Data Extraction/work/_lib1_6.qpg differ
diff --git a/Individual_Project/Data Extraction/work/_lib1_6.qtl b/Individual_Project/Data Extraction/work/_lib1_6.qtl
new file mode 100644
index 0000000000000000000000000000000000000000..c83e6bb2e30c50d0e0b4445cfd26a2ccf21b6704
Binary files /dev/null and b/Individual_Project/Data Extraction/work/_lib1_6.qtl differ
diff --git a/Individual_Project/Leading_Bit_Detector.sv b/Individual_Project/Leading_Bit_Detector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..807a5d00ff9098afaff5782c6da75da72bf12ca5
--- /dev/null
+++ b/Individual_Project/Leading_Bit_Detector.sv
@@ -0,0 +1,60 @@
+/////////////////////////////////////////////////////////////////////
+// Design unit: Leading Bit Detector
+// :
+// File name : Leading_Bit_Detector.sv
+// :
+// Description: Given the first bit of the regime bit
+// find the first bit different from it
+// :
+// Limitations: None
+// :
+// System : SystemVerilog IEEE 1800-2005
+// :
+// Author : Xiaoan He (Jasper)
+// : xh2g20@ecs.soton.ac.uk
+//
+// Revision : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+
+module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+(
+ input logic signed [N-2:0] InRemain,
+ output logic signed [RS:0] EndPosition,
+ output logic RegimeCheck
+);
+
+function [31:0] log2;
+input reg [31:0] value;
+ begin
+ value = value-1;
+ for (log2=0; value>0; log2=log2+1)
+ value = value>>1;
+ end
+endfunction
+
+//logic RegimeCheck;
+int i;
+
+always_comb
+begin
+ RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
+
+ EndPosition = '0;
+ EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+
+ for(i = 1; i < (N-2); i++)
+ begin
+ /*
+ compareing MSB of InRemain to the follwing bits
+ until the different bit turns up
+ */
+ if (RegimeCheck == InRemain[((N-2)-i)])
+ //begin
+ EndPosition = EndPosition + 1'b1;
+ //end
+ else
+ break;
+ end
+
+end
+endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Extraction.sv b/Individual_Project/Posit_Extraction.sv
index f7f4864316337cc451125085b8c1edc55883b5b6..39e306d8532f00ba87284a4bf2e7b94a031ae6ab 100644
--- a/Individual_Project/Posit_Extraction.sv
+++ b/Individual_Project/Posit_Extraction.sv
@@ -12,7 +12,7 @@
// Author : Xiaoan He (Jasper)
// : xh2g20@ecs.soton.ac.uk
//
-// Revision : Version 1.0 19/11/2022
+// Revision : Version 1.0 22/11/2022
/////////////////////////////////////////////////////////////////////
// `ifndef log_2
@@ -32,50 +32,42 @@ module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2
(
input logic signed [N-1:0] In,
output logic Sign,
- output logic signed [RS-1:0] RegimeValue,
+ output logic signed [RS:0] RegimeValue,
output logic [ES-1:0] Exponent,
output logic [N-ES+2:0] Mantissa
+ output logic signed [N-2:0] InRemain
);
+logic signed [N-2:0] InRemain;
+logic RegimeCheck;
+logic [RS:0] EndPosition;
+logic signed [N-2:0] ShiftedRemain;
+logic [(N-ES+2)-1-(N-ES-2)-1:0] ZERO = '0;
+int i;
+Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
+
always_comb
begin
// Sign Bit Extraction
- logic signed [N-2:0] InRemain;
-
Sign = In[N-1];
- if(Sign = 1) // if sign bit is 1, then 2's compliment
- InRemain = ~In[N-2:0] + 1'b1;
- else
- InRemain = In[N-2:0];
+ InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0]; // if sign bit is true, then 2's compliment
// Regime Bits Extraction
- logic RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
-
- logic [RS-1:0] EndPosition = 1; // initial EP starts from InRemain[1] as InRemain[0] is RC
-
- for(int i = 1; i < N-2; i++)
- begin
- /*
- compareing MSB of InRemain to the follwing bits
- until the different bit turns up
- */
- if(RegimeCheck == InRemain[((N-2)-i)])
- EndPosition = EndPositon + 1;
- else
- break;
- end
-
- if(RegimeCheck == 1)
+ /*
+ There is a Leading_Bit_Detector defined before the always_comb block
+ which takes the input without sign bit as module input and outputs
+ EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
+ */
+ if(RegimeCheck == 1'b1)
RegimeValue = EndPosition - 1;
else if (RegimeCheck == 0)
- RegimeValue = -EndPositon;
+ RegimeValue = -EndPosition;
//Exponent Bits Extraction
- logic signed [N-2:0] ShiftedRemain;
ShiftedRemain = InRemain << (EndPosition + 1 );
Exponent = ShiftedRemain[N-1:((N-1)-ES)];
//Mantissa Bits Extraction
- Mantissa = {1'b1, ShiftedRemain[N-ES-2]};
+ Mantissa = {1'b1, ShiftedRemain[N-ES-2:0], ZERO};
end
endmodule
\ No newline at end of file
diff --git a/Individual_Project/Test_Data_Extraction.sv b/Individual_Project/Test_Data_Extraction.sv
new file mode 100644
index 0000000000000000000000000000000000000000..57c764b04b6eb93d49d7c7ebcd5ecf5f9d27cfe4
--- /dev/null
+++ b/Individual_Project/Test_Data_Extraction.sv
@@ -0,0 +1,61 @@
+/////////////////////////////////////////////////////////////////////
+// Design unit: TestDataExtraction
+// :
+// File name : testExtract.sv
+// :
+// Description: Testbench for extracting posit element
+// from n bits binary number
+// :
+// Limitations: None
+// :
+// System : SystemVerilog IEEE 1800-2005
+// :
+// Author : Xiaoan He (Jasper)
+// : xh2g20@ecs.soton.ac.uk
+//
+// Revision : Version 1.0 21/11/2022
+/////////////////////////////////////////////////////////////////////
+function [31:0] log2;
+input reg [31:0] value;
+ begin
+ value = value-1;
+ for (log2=0; value>0; log2=log2+1)
+ value = value>>1;
+ end
+endfunction
+
+module Test_Data_Extraction;
+parameter N = 8, RS = log2(N), ES = 3;
+
+//input logic
+logic signed [N-1:0]In;
+
+//output logic
+logic Sign;
+logic signed [RS:0] RegimeValue;
+logic [ES-1:0] Exponent;
+logic [N-ES+2:0] Mantissa;
+logic signed [N-2:0] InRemain;
+
+Data_Extraction #(.N(N), .ES(ES)) extract1 (.*);
+
+initial
+ begin
+ // initial input is nothing
+ #10ns In = 8'b0_0000000;
+ #50ns In = 8'b0_01_000_01; // R = -1, E = 100, M = 1.01
+ #50ns In = 8'b0_10_001_10; // R = 0, E = 100, M = 1.1
+ #50ns In = 8'b0_001_010_0; // R = -2, E = 100, M = 1.01
+ #50ns In = 8'b0_110_011_1; // R = 1, E = 100, M = 1.01
+ #50ns In = 8'b0_0001_100; // R = -3, E = 100, M = 1.01
+ #50ns In = 8'b0_1110_101; // R = 2, E = 100, M = 1.01
+ #50ns In = 8'b1_01_000_01; // 101_1111
+ #50ns In = 8'b1_10_001_10; // 011_1010
+ #50ns In = 8'b1_001_010_0; // 110_1100
+ #50ns In = 8'b1_110_011_1; // 001_s1001
+ #50ns In = 8'b1_0001_100; // 111_0100
+ #50ns In = 8'b1_1110_101; // 000_1011
+
+
+ end
+endmodule
\ No newline at end of file
diff --git a/Individual_Project/testExtract.sv b/Individual_Project/testExtract.sv
deleted file mode 100644
index b8a8491ef4526b0b4f34d33f8edd406c821881e2..0000000000000000000000000000000000000000
--- a/Individual_Project/testExtract.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: TestDataExtraction
-// :
-// File name : testExtract.sv
-// :
-// Description: Testbench for extracting posit element
-// from n bits binary number
-// :
-// Limitations: None
-// :
-// System : SystemVerilog IEEE 1800-2005
-// :
-// Author : Xiaoan He (Jasper)
-// : xh2g20@ecs.soton.ac.uk
-//
-// Revision : Version 1.0 14/11/2022
-/////////////////////////////////////////////////////////////////////
-
-module testExtract;
-
-function [31:0] log2;
-input reg [31:0] value;
- begin
- value = value-1;
- for (log2=0; value>0; log2=log2+1)
- value = value>>1;
- end
-endfunction
-
-parameter N = 8, Bs = log2(N), es = 3;
-
-//input logic
-logic signed [N-1:0]In;
-//output logic
-logic Sign;
-logic [ES-1:0]Exponent;
-logic signed [Es-1:0]Regime;
-logic [N-ES+2:0]Mantissa;
-
-Data_Extraction extract1 (.*);
-
-initial
- begin
- // initial input is nothing
- #10ns in = 8'b0_0000000;
- // sign=0 regime=10 exponent=1001,mant=1
- #50ns in = 8'b1_01_1000_0;
- // 0_10_1000_0
- end
-
-endmodule
\ No newline at end of file
diff --git a/Progress_Test_Draft.docx b/Progress_Test_Draft.docx
new file mode 100644
index 0000000000000000000000000000000000000000..fedf91ff25600abaecb4fe09ce029e894c72ce36
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