diff --git a/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv b/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
deleted file mode 100644
index 66c94dac893336b9bfb48e8fc37ead96bd5de7b6..0000000000000000000000000000000000000000
--- a/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
+++ /dev/null
@@ -1,125 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Arithmetic Testbench
-//            :
-// File name  : Arithmetic_tb.sv
-//            :
-// Description: Test Posit Adder Arithmetic
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 23/11/2022
-/////////////////////////////////////////////////////////////////////
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-module Arithmetic_tb;
-parameter N = 8, RS = log2(N), ES = 3;
-
-//input logic
-logic signed [N-2:0] InRemain1, InRemain2;
-logic Sign1, Sign2;
-logic signed [RS:0] RegimeValue1, RegimeValue2;
-logic [ES-1:0] Exponent1, Exponent2;
-logic [N-ES+2:0] Mantissa1, Mantissa2;
-
-//output logic
-logic [N-1:0] E_diff;
-logic [N:0] Add_Mant;
-logic signed [ES+RS:0] LE_O;
-logic [ES-1:0] E_O;
-logic signed [RS:0] R_O;
-logic signed [N-1:0] Result;
-logic signed [N-1:0] out;
-
-Alignment #(.N(N), .ES(ES)) alignment_tb (.*);
-
-initial 
-    begin
-       #10ns 
-       InRemain1 = 7'b0_0000000;
-       InRemain2 = 7'b0_0000000;
-       Sign1 = 0;
-       Sign2 = 0;
-       RegimeValue1 = '0;
-       RegimeValue2 = '0;
-       Exponent1 = '0;
-       Exponent2 = '0;
-       Mantissa1 = '0;
-       Mantissa2 = '0;
-
-       #50ns   // 1+0.625 ~= 1.5
-       InRemain1 = 7'b10_000_00;
-       InRemain2 = 7'b01_111_01;
-       Sign1 = 0;
-       Sign2 = 0;
-       RegimeValue1 = 0;
-       RegimeValue2 = -1;
-       Exponent1 = 3'b000;
-       Exponent2 = 3'b111;
-       Mantissa1 = 8'b10000000;
-       Mantissa2 = 8'b10100000;
-
-       
-
-       #50ns   // 1+ 0.875 ~= 2
-       InRemain1 = 7'b10_000_00;
-       InRemain2 = 7'b01_111_11;
-       Sign1 = 0;
-       Sign2 = 0;
-       RegimeValue1 = 0;
-       RegimeValue2 = -1;
-       Exponent1 = 3'b000;
-       Exponent2 = 3'b111;
-       Mantissa1 = 8'b10000000;
-       Mantissa2 = 8'b11100000;
-
-       #50ns  // 524288 + 12288 ~= 524288
-       InRemain1 = 7'b1110_011;
-       InRemain2 = 7'b110_101_1;
-       Sign1 = 0;
-       Sign2 = 0;
-       RegimeValue1 = 2;
-       RegimeValue2 = 1;
-       Exponent1 = 3'b011;
-       Exponent2 = 3'b101;
-       Mantissa1 = 8'b10000000;
-       Mantissa2 = 8'b11000000;
-
-       #50ns   // 1+(-0.25)
-       InRemain1 = 7'b10_000_00;       
-       InRemain2 = 7'b01_110_00;
-       Sign1 = 0;
-       Sign2 = 1;
-       RegimeValue1 = 0;
-       RegimeValue2 = -1;
-       Exponent1 = 3'b000;
-       Exponent2 = 3'b110;
-       Mantissa1 = 8'b10000000;
-       Mantissa2 = 8'b10000000;
-
-       #50ns   // 32768-24576
-       InRemain1 = 7'b110_111_0;       
-       InRemain2 = 7'b110_110_1;
-       Sign1 = 0;
-       Sign2 = 1;
-       RegimeValue1 = 1;
-       RegimeValue2 = 1;
-       Exponent1 = 3'b111;
-       Exponent2 = 3'b110;
-       Mantissa1 = 8'b10000000;
-       Mantissa2 = 8'b11000000;
-
-
-    end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder.cr.mti b/Individual_Project/Posit_Adder.cr.mti
deleted file mode 100644
index 90416b1a66be9b7882134107efc7c2fa32d66437..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder.cr.mti
+++ /dev/null
@@ -1,39 +0,0 @@
-{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/tbPositAdder.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/tbPositAdder.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling package tbPositAdder_sv_unit
--- Compiling module Test_Posit_Adder
-
-Top level modules:
-	Test_Posit_Adder
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Posit_Adder
-
-Top level modules:
-	Posit_Adder
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Extraction.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling package Posit_Extraction_sv_unit
--- Compiling module Data_Extraction
-
-Top level modules:
-	Data_Extraction
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder_Arithmetic.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder_Arithmetic.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling package Posit_Adder_Arithmetic_sv_unit
--- Compiling module Alignment
-
-Top level modules:
-	Alignment
-
-} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Leading_Bit_Detector.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Leading_Bit_Detector
-
-Top level modules:
-	Leading_Bit_Detector
-
-} {} {}}
diff --git a/Individual_Project/Posit_Adder.sv b/Individual_Project/Posit_Adder.sv
deleted file mode 100644
index e6595f7eae4c32d8d608b78c5641098f5cc907e5..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Posit Adder 
-//            :
-// File name  : Posit_Adder.sv
-//            :
-// Description: Posit Adder Top Level Module
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 07/12/2022
-/////////////////////////////////////////////////////////////////////
-
-module Posit_Adder #(parameter N = 8, parameter RS = log2(N), parameter ES = 3) 
-(
-    input logic signed [N-1:0] In1, In2,
-    output logic signed [ES+RS:0] LE_O,
-    output logic [ES-1:0] E_O,
-    output logic signed [RS:0] R_O
-);
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-// Data Extraction
-logic Sign1, Sign2;
-logic signed [RS:0] RegimeValue1, RegimeValue2;
-logic [ES-1:0] Exponent1, Exponent2;
-logic [N-ES+2:0] Mantissa1, Mantissa2;
-logic signed [N-2:0] InRemain1, InRemain2;
-Data_Extraction #(.N(N), .ES(ES)) DE1(.In(In1), .Sign(Sign1), .RegimeValue(RegimeValue1), .Exponent(Exponent1), .Mantissa(Mantissa1), .InRemain(InRemain1));
-Data_Extraction #(.N(N), .ES(ES)) DE2(.In(Ini2), .Sign(Sign2), .RegimeValue(RegimeValue2), .Exponent(Exponent2), .Mantissa(Mantissa2), .InRemain(InRemain2));
-
-//Arithmetic
-logic [N-1:0] E_diff;
-logic [N:0] Add_Mant;
-Alignment #(.N(N), .ES(ES)) A (.InRemain1(InRemain1), .InRemain2(InRemain2), .Sign1(Sign1), .Sign2(Sign2), .RegimeValue1(RegimeValue1), .RegimeValue2(RegimeValue2), .Exponent1(Exponent1), .Exponent2(Exponent2),.Mantissa1(Mantissa1), .Mantissa2(Mantissa2), .E_diff(E_diff), .Add_Mant(Add_Mant), .LE_O(LE_O), .E_O(E_O), .R_O(R_O));
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Leading_Bit_Detector.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
similarity index 63%
rename from Individual_Project/Leading_Bit_Detector.sv
rename to Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
index 75aee70f69ac2ac3dab8e92424268734956b1000..21ffb5c1b2ed8f00fb5d4ed3f9006bad1c9b6bf6 100644
--- a/Individual_Project/Leading_Bit_Detector.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
@@ -13,34 +13,33 @@
 // Author     : Xiaoan He (Jasper)
 //            : xh2g20@ecs.soton.ac.uk
 //
-// Revision   : Version 1.0 21/11/2022
+// Revision   : Version 1.0 21/2/2023
 /////////////////////////////////////////////////////////////////////
 
-module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = $clog2(N))
+module Leading_Bit_Detector_8B #( parameter N = 8, parameter ES = 3, parameter RS = $clog2(N))
 (
-    input logic signed [N-2:0] InRemain,
-    output logic signed [RS:0] EndPosition,
-    output logic RegimeCheck
+    input logic  [N-1:0] In,
+    output logic signed [RS:0] EndPosition
 );
 
-//logic RegimeCheck; 
+logic Check; 
 int i;
 logic signed [RS:0] EP;
 
 always_comb
 begin
-    RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
+    Check = 1; 
     
-    EP = '0;
-    EndPosition = EP + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+    EndPosition = '0;
+    // EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
 
-    for(i = 1; i < (N-2); i++) 
+    for(i = 1; i < N; i++) 
         begin
             /* 
             compareing MSB of InRemain to the follwing bits
             until the different bit turns up    
             */
-            if (RegimeCheck == InRemain[((N-2)-i)])
+            if (Check != In[(N-i)])
                 //begin
                 EndPosition = EndPosition + 1'b1;
                 //end
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.cr.mti b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.cr.mti
deleted file mode 100644
index 8b137891791fe96927ad78e64b0aad7bded08bdc..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.cr.mti
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Posit_Adder_Alignment.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Posit_Adder_Alignment.sv
deleted file mode 100644
index a5f4e3a79bd506b04992a1479d647ac3ce03b08a..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Posit_Adder_Alignment.sv
+++ /dev/null
@@ -1,104 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Alignment in Posit Adder Arithmetic
-//            :
-// File name  : Posit_Adder_Alignment.sv
-//            :
-// Description: For two Posit Inputs, check which one is greater
-//            : shift the smaller one to the same exponent
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 29/11/2022
-/////////////////////////////////////////////////////////////////////
-
-function [31:0] log2;
-    input reg [31:0] value;
-        begin
-            value = value-1;
-            for (log2=0; value>0; log2=log2+1)
-                value = value>>1;
-        end
-endfunction
-
-module Alignment #(parameter N = 8, parameter ES = 3, parameter RS = log2(N)) 
-(
-    input logic signed [N-2:0] InRemain1, InRemain2,
-    input logic Sign1, Sign2,
-    input logic signed [RS:0] RegimeValue1, RegimeValue2,
-    input logic [ES-1:0] Exponent1, Exponent2,
-    input logic [N-ES+2:0] Mantissa1, Mantissa2,
-    output logic [N-1:0] E_diff,
-    output logic [N-1:0] Add_Mant
-);
-    logic Operation;
-    // components to corresponding logic, L - Large S - Small
-    logic LS, SS;
-    logic [RS:0] LR, SR;
-    logic LRC, SRC;
-    logic [ES-1:0]LE, SE;
-    logic [N-ES+2:0]LM, SM, SM_tmp;
-    // logic SS;
-    // logic [RS:0]SR;
-    // logic SRC;
-    // logic [ES-1:0]SE;
-    // logic [N-ES+2:0]SM, SM_tmp;
-
-    logic Greater_Than;
-    logic signed [RS:0] R_diff;
-
-always_comb
-begin
-    // Confirm the operation (s1 xor s2)
-    Operation = Sign1 ^ Sign2 ;
-
-    // Find the greater input
-    Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
-
-    // Assign components to corresponding logic, L - Large S - Small
-    LS = Greater_Than ? Sign1 : Sign2;
-    LR = Greater_Than ? RegimeValue1 : RegimeValue2;
-    LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
-    LE = Greater_Than ? Exponent1 : Exponent2;
-    LM = Greater_Than ? Mantissa1 : Mantissa2;
-
-    SS = Greater_Than ? Sign2 : Sign1;
-    SR = Greater_Than ? RegimeValue2 : RegimeValue1;
-    SE = Greater_Than ? Exponent2 : Exponent1;
-    SM = Greater_Than ? Mantissa2 : Mantissa1;
-
-    // Mantissa Addition
-    /*
-    find regime difference, 
-    when both of them are +ve, the difference is RV1 - RV2
-    when RV1 +ve but RV2 -ve, the difference is RV1 + RV2
-    when RV1 -ve and RV2 also -ve, still RV1 - RV2
-    */
-
-    // if (RegimeValue1 >= 0 && RegimeValue2 >= 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 >= 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 < 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    R_diff = RegimeValue1 - RegimeValue2;
-
-    /*
-    after the R_diff found, remember that the regime contributes into the exponent
-    as (Useed ^ RegimeValue) where Useed = 2^(2^ES) 
-    so the E_diff is (R_diff x log2(useed) + LE - SE)
-    the reason why it is R_diff x log2(useed) is
-    the exponent (2 ^ what)is what we want to find
-    for exponent bits, it is the difference
-    for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
-    */
-    E_diff = (R_diff*(2**(ES))) + (LE - SE); 
-
-    SM_tmp = SM >> E_diff;
-    Add_Mant = Operation ?  LM - SM_tmp : LM + SM_tmp;
-end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/TB_Alignment.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/TB_Alignment.sv
deleted file mode 100644
index ef98943f33032944510847543e2c9d44f2c0b980..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/TB_Alignment.sv
+++ /dev/null
@@ -1,93 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: TestAlignment
-//            :
-// File name  : TestAlignment.sv
-//            :
-// Description: Testbench for Posit exponent
-//            : alignment during computing
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 29/11/2022
-/////////////////////////////////////////////////////////////////////
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-module Test_Alignment;
-parameter N = 8, RS = log2(N), ES = 3;
-
-//input logic
-logic signed [N-2:0] InRemain1, InRemain2;
-logic Sign1, Sign2;
-logic signed [RS:0] RegimeValue1, RegimeValue2;
-logic [ES-1:0] Exponent1, Exponent2;
-logic [N-ES+2:0] Mantissa1, Mantissa2;
-
-//output logic
-logic [N-1:0] E_diff;
-logic [N-1:0] Add_Mant;
-logic signed [ES+BS:0] LE_O;
-logic [ES-1:0] E_O;
-logic signed [BS-1:0] R_O;
-
-Alignment #(.N(N), .ES(ES)) Alignment (.*);
-
-initial 
-    begin
-         #10ns InRemain1 = 7'b0_0000000;
-               InRemain2 = 7'b0_0000000;
-               Sign1 = 0;
-               Sign2 = 0;
-               RegimeValue1 = '0;
-               RegimeValue2 = '0;
-               Exponent1 = '0;
-               Exponent2 = '0;
-               Mantissa1 = '0;
-               Mantissa2 = '0;
-
-        #50ns  InRemain1 = 7'b1110_011;
-               InRemain2 = 7'b110_101_1;
-               Sign1 = 0;
-               Sign2 = 0;
-               RegimeValue1 = 2;
-               RegimeValue2 = 1;
-               Exponent1 = 3'b011;
-               Exponent2 = 3'b101;
-               Mantissa1 = 8'b10000000;
-               Mantissa2 = 8'b11000000;
-               
-       //  #50ns  InRemain1 = 7'b1110_011;
-       //         InRemain2 = 7'b001_101_1;
-       //         Sign1 = 0;
-       //         Sign2 = 0;
-       //         RegimeValue1 = 2;
-       //         RegimeValue2 = -2;
-       //         Exponent1 = 3'b011;
-       //         Exponent2 = 3'b101;
-       //         Mantissa1 = '0;
-       //         Mantissa2 = '0;
-
-        #50ns  InRemain1 = 7'b01_011_10;
-               InRemain2 = 7'b001_101_1;
-               Sign1 = 0;
-               Sign2 = 0;
-               RegimeValue1 = -1;
-               RegimeValue2 = -2;
-               Exponent1 = 3'b011;
-               Exponent2 = 3'b101;
-               Mantissa1 = 8'b11000000;
-               Mantissa2 = 8'b11000000;
-    end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/wave.do b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/wave.do
deleted file mode 100644
index bdcb3a0879c440f55f15bf766c0f1f25a2913bd2..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/wave.do
+++ /dev/null
@@ -1,28 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -radix binary -childformat {{{/Test_Alignment/InRemain1[6]} -radix binary} {{/Test_Alignment/InRemain1[5]} -radix binary} {{/Test_Alignment/InRemain1[4]} -radix binary} {{/Test_Alignment/InRemain1[3]} -radix binary} {{/Test_Alignment/InRemain1[2]} -radix binary} {{/Test_Alignment/InRemain1[1]} -radix binary} {{/Test_Alignment/InRemain1[0]} -radix binary}} -expand -subitemconfig {{/Test_Alignment/InRemain1[6]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[5]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[4]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[3]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[2]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[1]} {-height 15 -radix binary} {/Test_Alignment/InRemain1[0]} {-height 15 -radix binary}} /Test_Alignment/InRemain1
-add wave -noupdate -radix binary -childformat {{{/Test_Alignment/InRemain2[6]} -radix binary} {{/Test_Alignment/InRemain2[5]} -radix binary} {{/Test_Alignment/InRemain2[4]} -radix binary} {{/Test_Alignment/InRemain2[3]} -radix binary} {{/Test_Alignment/InRemain2[2]} -radix binary} {{/Test_Alignment/InRemain2[1]} -radix binary} {{/Test_Alignment/InRemain2[0]} -radix binary}} -expand -subitemconfig {{/Test_Alignment/InRemain2[6]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[5]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[4]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[3]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[2]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[1]} {-height 15 -radix binary} {/Test_Alignment/InRemain2[0]} {-height 15 -radix binary}} /Test_Alignment/InRemain2
-add wave -noupdate -radix decimal /Test_Alignment/RegimeValue1
-add wave -noupdate -radix decimal /Test_Alignment/RegimeValue2
-add wave -noupdate -radix binary /Test_Alignment/Exponent1
-add wave -noupdate -radix binary /Test_Alignment/Exponent2
-add wave -noupdate -radix decimal /Test_Alignment/E_diff
-add wave -noupdate /Test_Alignment/Alignment1/R_diff
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {79018 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 206
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {420 ns}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_info b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_info
deleted file mode 100644
index dba4021993f601e7f086dcf20c651c02b593653a..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_info
+++ /dev/null
@@ -1,117 +0,0 @@
-m255
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qpg b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qpg
deleted file mode 100644
index cde51e3860c99d7ca099fe7ade98cdd7805d2311..0000000000000000000000000000000000000000
Binary files a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qpg and /dev/null differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qtl b/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qtl
deleted file mode 100644
index 217f97e744241429d1e0609b800fbd5931a9f655..0000000000000000000000000000000000000000
Binary files a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qtl and /dev/null differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.cr.mti b/Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.cr.mti
deleted file mode 100644
index 66e47d093900e7dfa0c08b96d6aba18148ef314b..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.cr.mti
+++ /dev/null
@@ -1,8 +0,0 @@
-{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Leading_Bit_Detector_8b.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Leading_Bit_Detector_8b.sv}
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module Leading_Bit_Detector_8b
-
-Top level modules:
-	Leading_Bit_Detector_8b
-
-} {} {}}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
index 807a5d00ff9098afaff5782c6da75da72bf12ca5..75aee70f69ac2ac3dab8e92424268734956b1000 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
@@ -16,31 +16,23 @@
 // Revision   : Version 1.0 21/11/2022
 /////////////////////////////////////////////////////////////////////
 
-module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = $clog2(N))
 (
     input logic signed [N-2:0] InRemain,
     output logic signed [RS:0] EndPosition,
     output logic RegimeCheck
 );
 
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
 //logic RegimeCheck; 
 int i;
+logic signed [RS:0] EP;
 
 always_comb
 begin
     RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
     
-    EndPosition = '0;
-    EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+    EP = '0;
+    EndPosition = EP + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
 
     for(i = 1; i < (N-2); i++) 
         begin
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector_8b.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector_8b.sv
deleted file mode 100644
index 71e330c9ce112562c9014bdb379e70036e092b59..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector_8b.sv
+++ /dev/null
@@ -1,60 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: 8 bits Leading Bit Detector
-//            :
-// File name  : 8b_Leading_Bit_Detector.sv
-//            :
-// Description: Given the first bit of the regime bit
-//              find the first bit different from it
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan(Jasper) He 
-//            : xh2g20@soton.ac.uk
-//
-// Revision   : Version 1.0 01/12/2022
-/////////////////////////////////////////////////////////////////////
-
-module Leading_Bit_Detector_8b #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
-(
-    input logic signed [N-1:0] Add_Mant,
-    output logic signed [RS:0] shift
-    //output logic shift
-);
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-logic shft; 
-int i;
-
-always_comb
-begin
-    shft = Add_Mant[N-1]; //the MSB of InRemain (In[6])is the number to be shifted
-    
-    shift = '0;
-    shift = shift + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
-
-    for(i = 1; i < (N-1); i++) 
-        begin
-            /* 
-            compareing MSB of Add_Mant to the follwing bits
-            until the different bit turns up    
-            */
-            if (shft == Add_Mant[((N-1)-i)])
-                //begin
-                shift = shift + 1'b1;
-                //end
-            else 
-                break;
-        end
-
-end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Pin1_8bit.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/Pin1_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e213ed0152dce071932030466d6a867562cd20ac
--- /dev/null
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Pin2_8bit.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/Pin2_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..40f3a8bba6d54ea3a7e532a318b662c1b014efcc
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Pin2_8bit.txt
@@ -0,0 +1,65536 @@
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..c73f8d5e9ef6a7b4a3cdc05bcafab2e5d61b87b4
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.cr.mti
@@ -0,0 +1,36 @@
+{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Posit_Adder_tb
+
+Top level modules:
+	Posit_Adder_tb
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Leading_Bit_Detector
+
+Top level modules:
+	Leading_Bit_Detector
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Data_Extraction
+
+Top level modules:
+	Data_Extraction
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Leading_Bit_Detector_8B
+
+Top level modules:
+	Leading_Bit_Detector_8B
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Posit_Adder
+
+Top level modules:
+	Posit_Adder
+
+} {} {}}
diff --git a/Individual_Project/Posit_Adder.mpf b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
similarity index 93%
rename from Individual_Project/Posit_Adder.mpf
rename to Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
index e4cba0e36d4dfa190021d499f76f6b4bc4867242..9a8724888ba5d35da54e8176cc63ab66dd3598f7 100644
--- a/Individual_Project/Posit_Adder.mpf
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.mpf
@@ -220,10 +220,10 @@ Resolution = ps
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 300 ns
+RunLength = 1600 ps
 
 ; Maximum iterations that can be run without advancing simulation time
-IterationLimit = 5000
+IterationLimit = 10000000
 
 ; Directive to license manager:
 ; vhdl          Immediately reserve a VHDL license
@@ -411,16 +411,16 @@ Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 5
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/tbPositAdder.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1670427142 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1670428143 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Extraction.sv
-Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1670345718 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder_Arithmetic.sv
-Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1670425187 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Leading_Bit_Detector.sv
-Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1670345624 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1676404420 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677028231 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677036594 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/8B_LBD.sv
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677030944 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
+Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677036563 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qpf b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..d33a42f1c14b0d0920f0f28129328962383fd180
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 19:55:47  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "19:55:47  February 14, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "Posit_Adder"
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qsf b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..a492da41b4f549b07b924caf11026e0c85a784ea
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qsf
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 19:55:47  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Posit_Adder_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY Posit_Adder
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:55:47  FEBRUARY 14, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name SYSTEMVERILOG_FILE Posit_Adder_Arithmetic.sv
+set_global_assignment -name SYSTEMVERILOG_FILE Leading_Bit_Detector.sv
+set_global_assignment -name SYSTEMVERILOG_FILE Posit_Extraction.sv
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qws b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qws
new file mode 100644
index 0000000000000000000000000000000000000000..bf1e54df58bd9f1aa6a3ade70cee4e5a4b948a1e
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.qws differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
new file mode 100644
index 0000000000000000000000000000000000000000..09c4f7ae9cea55266e3a2fff372ce5a618a46b4d
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder.sv
@@ -0,0 +1,167 @@
+/////////////////////////////////////////////////////////////////////
+// Design unit: Posit Adder Arithmetic
+//            :
+// File name  : Posit_Adder_Arithmetic.sv
+//            :
+// Description: Mantissa addition and subtraction
+//            : exponent and regime computation
+//            :
+// Limitations: None
+//            : 
+// System     : SystemVerilog IEEE 1800-2005
+//            :
+// Author     : Xiaoan(Jasper) He 
+//            : xh2g20@soton.ac.uk
+//
+// Revision   : Version 2 21/02/2023
+/////////////////////////////////////////////////////////////////////
+timeunit 1ns; timeprecision 1ps;
+module Posit_Adder #(parameter N = 8, parameter ES = 3, parameter RS = $clog2(N)) 
+(
+    input logic[N-1:0] IN1, IN2,
+    output logic [N-1:0] OUT
+);
+
+logic Sign1, Sign2;
+logic signed [N-2:0] InRemain1, InRemain2;
+logic signed [RS:0] RegimeValue1,RegimeValue2;
+logic [ES-1:0] Exponent1, Exponent2;
+logic [N-ES+2:0] Mantissa1, Mantissa2;
+
+Data_Extraction #(.N(N), .ES(ES)) Extract_IN1 (.In(IN1), .Sign(Sign1), .RegimeValue(RegimeValue1), .Exponent(Exponent1), .Mantissa(Mantissa1), .InRemain(InRemain1), .inf(inf1), .zero(zero1));
+Data_Extraction #(.N(N), .ES(ES)) Extract_IN2 (.In(IN2), .Sign(Sign2), .RegimeValue(RegimeValue2), .Exponent(Exponent2), .Mantissa(Mantissa2), .InRemain(InRemain2), .inf(inf2), .zero(zero2));
+
+logic inf, zero;
+logic Operation;
+// components to corresponding logic, L - Large S - Small
+logic signed [N-2:0] LIn, SIn;
+logic LS, SS;
+logic [RS:0] LR, SR;
+logic LRC, SRC;
+logic [ES-1:0]LE, SE;
+logic [N-1:0]LM, SM, SM_tmp;
+
+logic [N-1:0] E_diff;
+logic [N:0] Add_Mant;
+logic [N-1:0] Add_Mant_sft, Add_Mant_N;
+logic [N-1:0] LBD_in;
+logic signed [ES+RS:0] LE_O;
+logic [ES-1:0] E_O;
+logic signed [RS:0] R_O;
+logic Greater_Than;
+logic signed [RS:0] R_diff;
+logic Mant_Ovf;
+logic signed [RS:0] shift;
+logic [ES+RS:0] LE_ON;
+logic [N-1:0] RegimeBits;
+
+logic [(2*N-1)+3:0] tmp_o;
+logic [(3*N-1)+3:0] sft_tmp_o;
+logic L,G,R,S,ulp;
+logic [N-1:0] rnd_ulp; 
+logic [N:0] sft_tmp_o_rnd_ulp;
+logic [N-1:0] sft_tmp_o_rnd;
+logic [N-1:0] sft_tmp_oN;
+
+Leading_Bit_Detector_8B #(.N(N), .ES(ES)) LBD_8B (.In(LBD_in), .EndPosition(shift));
+
+always_comb
+begin
+    // check infinity and zero
+    inf = inf1 | inf2;
+	zero = zero1 & zero2;
+
+    // Confirm the operation (s1 XNOR s2)
+    Operation = Sign1 ~^ Sign2 ;
+
+    // Find the greater InRemain
+    Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
+
+    // Assign components to corresponding logic, L - Large S - Small
+    LIn = Greater_Than ? InRemain1 : InRemain2;
+    LS = Greater_Than ? Sign1 : Sign2;
+    LR = Greater_Than ? RegimeValue1 : RegimeValue2;
+    LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
+    LE = Greater_Than ? Exponent1 : Exponent2;
+    LM = Greater_Than ? Mantissa1 : Mantissa2; // the first bit (0) is reserved for overflow detection
+    
+    SIn = Greater_Than ? InRemain2 : InRemain1;
+    SS = Greater_Than ? Sign2 : Sign1;
+    SR = Greater_Than ? RegimeValue2 : RegimeValue1;
+    LRC = Greater_Than? InRemain2[N-2] : InRemain1[N-2];
+    SE = Greater_Than ? Exponent2 : Exponent1;
+    SM = Greater_Than ? Mantissa2 : Mantissa1;
+
+
+    // Mantissa Addition
+    R_diff = LR - SR;
+
+    /*
+    after the R_diff found, remember that the regime contributes into the exponent
+    as (Useed ^ RegimeValue) where Useed = 2^(2^ES) 
+    so the E_diff is (R_diff x log2(useed) + LE - SE)
+    the reason why it is R_diff x log2(useed) is
+    the exponent (2 ^ what)is what we want to find
+    for exponent bits, it is the difference
+    for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
+    */
+    E_diff = (R_diff*(2**(ES))) + (LE - SE); 
+
+    SM_tmp = SM >> E_diff;
+    Add_Mant = Operation ?  LM + SM_tmp : LM - SM_tmp;
+    
+    // check for Mantissa Overflow
+    Mant_Ovf = Add_Mant[N];
+    //Add_Mant = Mant_Ovf ? Add_Mant : (Add_Mant << 1);
+
+    /*
+     In the case of subtraction between two close numbers
+     some MSBs may lost, it is useful to detect the 
+     Leading ONE and left shift accordingly
+    */
+    
+        LBD_in = {{(Add_Mant[N] | Add_Mant[N-1]), Add_Mant[N-2:0]}};
+        Add_Mant_sft = Add_Mant[N:1] << shift;
+        Add_Mant_N = Add_Mant_sft[N-1] ? Add_Mant_sft[N-1:0] : {Add_Mant_sft[N-2:0],1'b0};
+
+    // Compute regime and exponent of final result
+    
+    /* 
+    The exponent is mainly based on the larger input
+    taking overflow and left shift into account
+    */
+    LE_O = {LR, LE} + Mant_Ovf - shift;
+    //LE_O = {LR, LE} + Mant_Ovf;
+    LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
+
+    E_O = LE_O[ES-1:0];
+
+    R_O = (~LE_O[ES+RS] || |(LE_ON[ES-1:0])) ? LE_ON[ES+RS-1:ES] + 1'b1 : LE_ON[ES+RS-1:ES];
+
+ 
+    tmp_o = { {N{~LE_O[ES+RS]}}, LE_O[ES+RS], E_O, Add_Mant_N[N-2:ES], 3'b0 };
+    sft_tmp_o = {tmp_o, {N{1'b0}}} ;
+    sft_tmp_o = sft_tmp_o >> R_O;
+
+    L = sft_tmp_o[N+4]; 
+    G = sft_tmp_o[N+3]; 
+    R = sft_tmp_o[N+2]; 
+    S = |sft_tmp_o[N+1:0];
+    ulp = ((G & (R | S)) | (L & G & ~(R | S)));
+    
+    rnd_ulp= {{N-1{1'b0}},ulp};
+
+    
+    sft_tmp_o_rnd_ulp = sft_tmp_o[2*N-1+3:N+3] + rnd_ulp;
+
+    
+    sft_tmp_o_rnd = (R_O < N-ES-2) ? sft_tmp_o_rnd_ulp[N-1:0] : sft_tmp_o[2*N-1+3:N+3];
+
+
+    //Final Output
+    
+    sft_tmp_oN = LS ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
+    OUT = {LS, sft_tmp_oN[N-1:1]};
+
+end
+endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv
deleted file mode 100644
index c302ad7474f891b0bb7db3e4721f7abd97bc9c8f..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv
+++ /dev/null
@@ -1,220 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Posit Adder Arithmetic
-//            :
-// File name  : Posit_Adder_Arithmetic.sv
-//            :
-// Description: Mantissa addition and subtraction
-//            : exponent and regime computation
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan(Jasper) He 
-//            : xh2g20@soton.ac.uk
-//
-// Revision   : Version 1.0 02/02/2023
-/////////////////////////////////////////////////////////////////////
-
-function [31:0] log2;
-    input reg [31:0] value;
-        begin
-            value = value-1;
-            for (log2=0; value>0; log2=log2+1)
-                value = value>>1;
-        end
-endfunction
-
-module Alignment #(parameter N = 8, parameter ES = 3, parameter RS = log2(N)) 
-(
-    input logic signed [N-2:0] InRemain1, InRemain2,
-    input logic Sign1, Sign2,
-    input logic signed [RS:0] RegimeValue1, RegimeValue2,
-    input logic [ES-1:0] Exponent1, Exponent2,
-    input logic [N-ES+2:0] Mantissa1, Mantissa2,
-    output logic [N-1:0] E_diff,
-    output logic [N:0] Add_Mant,
-    output logic signed [ES+RS:0] LE_O,
-    output logic [ES-1:0] E_O,
-    output logic signed [RS:0] R_O,
-    output logic signed [N-1:0] Result,
-    output logic signed [N-1:0] out
-);
-    logic Operation;
-    // components to corresponding logic, L - Large S - Small
-    logic signed [N-2:0] LIn, SIn;
-    logic LS, SS;
-    logic [RS:0] LR, SR;
-    logic LRC, SRC;
-    logic [ES-1:0]LE, SE;
-    logic [N-1:0]LM, SM, SM_tmp;
-    // logic SS;
-    // logic [RS:0]SR;
-    // logic SRC;
-    // logic [ES-1:0]SE;
-    // logic [N-ES+2:0]SM, SM_tmp;
-
-    logic Greater_Than;
-    logic signed [RS:0] R_diff;
-    logic Mant_Ovf;
-    logic signed [RS:0] shift;
-    logic [ES+RS:0] LE_ON;
-    logic [N-1:0] RegimeBits;
-    //Leading_Bit_Detector_8b #(.N(N), .ES(ES)) LBD_Mant (.*);
-    //logic [N-1:0] ONEs;
-    logic [(2*N-1)+3:0] tmp_o;
-    logic [(3*N-1)+3:0] sft_tmp_o;
-
-    logic L,G,R,S,ulp;
-    logic [N-1:0] rnd_ulp; 
-    logic [N:0] sft_tmp_o_rnd_ulp;
-    logic [N-1:0] sft_tmp_o_rnd;
-    logic [N-1:0] sft_tmp_oN;
-
-always_comb
-begin
-    // Confirm the operation (s1 XNOR s2)
-    Operation = Sign1 ~^ Sign2 ;
-
-
-    // Find the greater input
-    Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
-    // Assign components to corresponding logic, L - Large S - Small
-    LIn = Greater_Than ? InRemain1 : InRemain2;
-    LS = Greater_Than ? Sign1 : Sign2;
-    LR = Greater_Than ? RegimeValue1 : RegimeValue2;
-    LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
-    LE = Greater_Than ? Exponent1 : Exponent2;
-    LM = Greater_Than ? Mantissa1 : Mantissa2; // the first bit (0) is reserved for overflow detection
-    
-    SIn = Greater_Than ? InRemain2 : InRemain1;
-    SS = Greater_Than ? Sign2 : Sign1;
-    SR = Greater_Than ? RegimeValue2 : RegimeValue1;
-    LRC = Greater_Than? InRemain2[N-2] : InRemain1[N-2];
-    SE = Greater_Than ? Exponent2 : Exponent1;
-    SM = Greater_Than ? Mantissa2 : Mantissa1;
-
-
-    // Mantissa Addition
-    /*
-    find regime difference, 
-    when both of them are +ve, the difference is RV1 - RV2
-    when RV1 +ve but RV2 -ve, the difference is RV1 + RV2
-    when RV1 -ve and RV2 also -ve, still RV1 - RV2
-    */
-
-    // if (RegimeValue1 >= 0 && RegimeValue2 >= 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 >= 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 < 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    R_diff = LR - SR;
-
-    /*
-    after the R_diff found, remember that the regime contributes into the exponent
-    as (Useed ^ RegimeValue) where Useed = 2^(2^ES) 
-    so the E_diff is (R_diff x log2(useed) + LE - SE)
-    the reason why it is R_diff x log2(useed) is
-    the exponent (2 ^ what)is what we want to find
-    for exponent bits, it is the difference
-    for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
-    */
-    E_diff = (R_diff*(2**(ES))) + (LE - SE); 
-
-    SM_tmp = SM >> E_diff;
-    Add_Mant = Operation ?  LM + SM_tmp : LM - SM_tmp;
-
-    // check for Mantissa Overflow
-    Mant_Ovf = Add_Mant[N];
-    Add_Mant = Mant_Ovf ? Add_Mant : (Add_Mant << 1);
-
-    /*
-     In the case of subtraction between two close numbers
-     some MSBs may lost, it is useful to detect the 
-     Leading ONE and left shift accordingly
-    */
-    
-    //Add_Mant = Add_Mant << shift;
-
-    
-    // Compute regime and exponent of final result
-    
-    /* 
-    The exponent is mainly based on the larger input
-    taking overflow and left shift into account
-    */
-    // LE_O = {LR, LE} + Mant_Ovf; //- shift;
-    // LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
-    
-    LE_O = {LR, LE} + Mant_Ovf; //- shift;
-    LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
-
-    E_O = LE_O[ES-1:0];
-
-    R_O = (~LE_O[ES+RS] || |(LE_ON[ES-1:0])) ? LE_ON[ES+RS-1:ES] + 1 : LE_ON[ES+RS-1:ES];
-
-    // if(!LE_O[ES+RS])
-    //     begin
-    //     E_O = LE_O[ES-1:0];
-    //     R_O = LE_O[ES+RS:ES];
-    //     end
-    // else 
-    //     begin 
-    //     LE_ON = -LE_O;
-    //     if(|LE_ON[ES-1:0])
-    //         begin
-    //         E_O = LE_O[ES-1:0];
-    //         R_O = LE_ON[ES+RS:ES]+1;
-    //         end
-    //     else   
-    //         begin
-    //         E_O = LE_O[ES-1:0];
-    //         R_O = LE_ON[ES+RS:ES];
-    //         end
-    //     end
-
-    
-    tmp_o = { {N{~LE_O[ES+RS]}}, LE_O[ES+RS], E_O, Add_Mant[(N-1):(N-(2*N-N-1-ES))], 3'b0 };
-    sft_tmp_o = {tmp_o, 8'b0} ;
-    sft_tmp_o = sft_tmp_o>> R_O;
-
-    L = sft_tmp_o[N+4]; 
-    G = sft_tmp_o[N+3]; 
-    R = sft_tmp_o[N+2]; 
-    S = |sft_tmp_o[N+1:0];
-    ulp = ((G & (R | S)) | (L & G & ~(R | S)));
-    
-    rnd_ulp= {{N-1{1'b0}},ulp};
-
-    
-    sft_tmp_o_rnd_ulp = sft_tmp_o[2*N-1+3:N+3] + rnd_ulp;
-
-    
-    sft_tmp_o_rnd = (R_O < N-ES-2) ? sft_tmp_o_rnd_ulp[N-1:0] : sft_tmp_o[2*N-1+3:N+3];
-
-
-    //Final Output
-    
-    sft_tmp_oN = LS ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
-    out = {LS, sft_tmp_oN[N-1:1]};
-    //out = inf|zero|(~DSR_left_out[N-1]) ? {inf,{N-1{1'b0}}} : {ls, sft_tmp_oN[N-1:1]};
-
-    // /*
-    //     if LE_O is -ve and Least Significant ES bits of LE_ON is non zero
-    //     E_O is 2's complement of Least Significant ES bits of LE_ON
-    //     if LE_O is positive, E_O = LSB ES bits of LE_O    
-    // */
-   
-    // /*  
-    //     if LE_O is +ve OR LE_O is -ve and LSB ES bits of LE_ON is non zero
-    //     R_O = 
-    // */
-    // //R_O = LE_O[ES+RS:ES];
-    // if (!LE_O[ES+RS])
-    //     R_O = LE_ON[ES+RS-1 : ES];
-    // else if ((LE_O[ES+RS]&(|LE_ON[ES-1 : 0])))
-    //     R_O =  (LE_ON[ES+RS-1 : ES] +1'b1);
-
-end
-endmodule
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
index ad75df2d906acba1b8da0eb3875225dc633603ec..ca398b879d5e36304870b02b06912667486bcb21 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_tb.sv
@@ -14,17 +14,10 @@
 //
 // Revision   : Version 1.0 08/02/2023
 /////////////////////////////////////////////////////////////////////
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
+timeunit 1ns; timeprecision 1ps;
 
 module Posit_Adder_tb;
-parameter N = 8, RS = log2(N), ES = 3;
+parameter N = 8, RS = $clog2(N), ES = 3;
 
 //input logic
 logic signed [N-1:0] IN1, IN2;
@@ -32,40 +25,115 @@ logic signed [N-1:0] IN1, IN2;
 //output logic
 logic signed [N-1:0] OUT;
 
-Posit_Adder #(.N(N), .ES(ES)) Posit_Adder_testing (.*);
+Posit_Adder #(.N(N), .ES(ES)) PA_tb (.*);
 
-initial 
-    begin
-        #10ns 
-        IN1 = 8'b0_0000000;
-        IN2 = 8'b0_0000000;
-        OUT = 8'b0_0000000;
+reg clk;
+integer outfile;
 
-        #50ns   //  65536+112
-        IN1 = 8'b0_1110_000;
-        IN2 = 8'b0_10_110_11;
+reg start;
+reg [N-1:0] data1 [1:65536];
+reg [N-1:0] data2 [1:65536];
+initial $readmemb("Pin1_8bit.txt",data1);
+initial $readmemb("Pin2_8bit.txt",data2);
 
-        #50ns   // 524288+1024
-        IN1 = 8'b0_1110_011;
-        IN2 = 8'b0_110_010_0;
+reg [15:0] i;
+	
+	initial begin
+		// Initialize Inputs
+		IN1 = 0;
+		IN2 = 0;
+		clk = 0;
+		start = 0;
+	
+		
+		// Wait 100 ns for global reset to finish
+		#100 i=0;
+		#20 start = 1;
+                #655500 start = 0;
+		#100;
+		
+		$fclose(outfile);
+		$finish;
+	end
 
-        #50ns   // 10+12
-        IN1 = 8'b0_10_011_01;
-        IN2 = 8'b0_10_011_10;
+ always #5 clk=~clk;
+
+  always @(posedge clk) begin			
+ 	IN1=data1[i];	
+	IN2=data2[i];
+	if(i==16'hffff)
+  	      $finish;
+	else i = i + 1;
+ end
+
+initial outfile = $fopen("error_8bit.txt", "wb");
+
+reg [N-1:0] result [1:65536];
+reg [N-1:0] show_result;
+initial $readmemb("Pout_8bit_ES4.txt",result);
+reg [N-1:0] diff;
+always @(negedge clk) begin
+	if(start)begin
+        show_result = result[i-1];
+     	diff = (result[i-1] > OUT) ? result[i-1]-OUT : OUT-result[i-1];
+     	//$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\n",in1, in2, out,result[i-1],diff);
+     	$fwrite(outfile, "%d\n",diff);
+     	end
+end
+
+
+// initial 
+//     begin
+//         #10ns 
+        // IN1 = 8'b0_0000000;
+        // IN2 = 8'b0_0000000;
+
+        // IN1 = 8'b0_0000011;
+        // IN2 = 8'b0_0000000;
+//         #50ns   //  56-10
+//         IN1 = 8'b01010111;
+//         IN2 = 8'b10110011;
+
+//         #50ns   //  1-0.875
+//         IN1 = 8'b01000000 ;
+//         IN2 = 8'b11000001;
+
+//         #50ns   //  -0.5+1.75
+//         IN1 = 8'b11000100;
+//         IN2 = 8'b01000011;
+
+//         #50ns   //  56-10
+//         IN1 = 8'b01000110;
+//         IN2 = 8'b11000000;
+
+//         // #50ns   //  56-10
+//         // IN1 = 8'b01010111;
+//         // IN2 = 8'b10110011;
+
+//         #50ns   //  65536+112
+//         IN1 = 8'b0_1110_000;
+//         IN2 = 8'b0_10_110_11;
+
+//         #50ns   // 524288+1024
+//         IN1 = 8'b0_1110_011;
+//         IN2 = 8'b0_110_010_0;
+
+//         #50ns   // 10+12
+//         IN1 = 8'b0_10_011_01;
+//         IN2 = 8'b0_10_011_10;
         
-        #50ns   // 40+24
-        IN1 = 8'b0_10_101_01;
-        IN2 = 8'b0_10_100_10;
-
-         #50ns   // 0.0234375+0.01953125
-        IN1 = 8'b0_01_010_10;
-        IN2 = 8'b0_01_010_01;
-
-         #50ns   // 0.125+0.15625
-        IN1 = 8'b0_01_101_00;
-        IN2 = 8'b0_01_101_01;
-       
-    end
+//         #50ns   // 40+24
+//         IN1 = 8'b0_10_101_01;
+//         IN2 = 8'b0_10_100_10;
+
+//          #50ns   // 0.0234375+0.01953125
+//         IN1 = 8'b0_01_010_10;
+//         IN2 = 8'b0_01_010_01;
+
+//          #50ns   // 0.125+0.15625
+//         IN1 = 8'b0_01_101_00;
+//         IN2 = 8'b0_01_101_01;
+    // end
 
 
 
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
index 1d9f4049082ca9f8dcb1d4e3dd0765dc04f9be61..6167a1c092fec0569e0f7ed51e4de661e3a8258b 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv
@@ -9,38 +9,27 @@
 //            : 
 // System     : SystemVerilog IEEE 1800-2005
 //            :
-// Author     : Xiaoan(Jasper) He 
+// Author     : Xiaoan He (Jasper)
 //            : xh2g20@ecs.soton.ac.uk
 //
-// Revision   : Version 1.1 30/11/2022
+// Revision   : Version 1.0 22/11/2022
 /////////////////////////////////////////////////////////////////////
 
-// `ifndef log_2
-// `define log_2
-// `include "log_2.sv"
-
-function [31:0] log2;
-    input reg [31:0] value;
-        begin
-            value = value-1;
-            for (log2=0; value>0; log2=log2+1)
-                value = value>>1;
-        end
-endfunction
-
-module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = $clog2(N))
 (
     input logic signed [N-1:0] In,
-    output logic Sign,
+    output logic signed Sign,
     output logic signed [RS:0] RegimeValue,
     output logic [ES-1:0] Exponent,
     output logic [N-ES+2:0] Mantissa,
-    output logic signed [N-2:0] InRemain
+    output logic signed [N-2:0] InRemain,
+    output logic inf,
+    output logic zero
 );
 
-//logic signed [N-2:0] InRemain;
+logic zero_check;
 logic RegimeCheck; 
-logic [RS:0] EndPosition;
+logic signed [RS:0] EndPosition;
 logic signed [N-2:0] ShiftedRemain;
 logic [(N-ES+2)-1-(N-ES-2)-1:0] ZERO = '0;
 int i;
@@ -48,24 +37,36 @@ Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
 
 always_comb
 begin
+    //infinity & zero check;
+    zero_check = |In[N-2:0];
+    inf = In[N-1] & (~zero_check);
+    zero = ~(In[N-1] | zero_check);
+
     // Sign Bit Extraction
     Sign = In[N-1];
-    InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0]; // if sign bit is true, then 2's compliment
+
+    // if sign bit is 1, then 2's compliment
+    if (Sign)
+        InRemain = -In[N-2:0];
+    else   
+        InRemain = In[N-2:0];
+
 
     // Regime Bits Extraction
     /*
-     There is a Leading_Bit_Detector defined before the always_comb block 
-     which takes the input without sign bit as module input and outputs 
+     the Leading_Bit_Detector defined before the always_comb block 
+     takes the input without sign bit as module input and outputs 
      EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
     */
-    if(RegimeCheck == 1'b1)
-        RegimeValue = EndPosition - 1;
-    else if (RegimeCheck == 0)
+    if(zero)
+        RegimeValue = 0;
+    else if (RegimeCheck)
+        RegimeValue = EndPosition - 1'b1;
+        else 
         RegimeValue = -EndPosition;
-
     //Exponent Bits Extraction
-    ShiftedRemain = InRemain << (EndPosition + 1 );
-    Exponent = ShiftedRemain[N-1:((N-1)-ES)];
+    ShiftedRemain = InRemain << (EndPosition + 1'b1 );
+    Exponent = ShiftedRemain[N-2:((N-1)-ES)];
 
     //Mantissa Bits Extraction
     Mantissa = {1'b1, ShiftedRemain[N-ES-2:0], ZERO};
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Post_Processing.sv b/Individual_Project/Posit_Adder/Core_Arithmetic/Post_Processing.sv
deleted file mode 100644
index 68ee3e56e1bdf1fe582a3e0bd88ff2abe92e363d..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Post_Processing.sv
+++ /dev/null
@@ -1,43 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Post Processing
-//            :
-// File name  : Post_Processing.sv
-//            :
-// Description: 
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 12/12/2022
-/////////////////////////////////////////////////////////////////////
-
-module Post_Processing #(parameter N = 8, parameter ES = 3, parameter RS = log2(N)) 
-(
-    input logic [ES-1:0] E_O,
-    input logic signed [RS:0] R_O,
-    output logic [N-1:0]RegimeBits,
-    output logic [ES-1:0]ExponentBits,
-);
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-int i;
-logic [N-1:0] ONEs;
-
-always_comb
-begin
-ONEs = '1;
-RegimeBits = R_O[RS]? ONEs << (R_O-1'b1) : ONEs >> R_O
-end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Pout_8bit_ES4.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/Pout_8bit_ES4.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5b6e4f1d3956b8b527ab2d7959e87ab11b991c6c
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/Pout_8bit_ES4.txt
@@ -0,0 +1,65536 @@
+00000000
+00000001
+00000010
+00000011
+00000100
+00000101
+00000110
+00000111
+00001000
+00001001
+00001010
+00001011
+00001100
+00001101
+00001110
+00001111
+00010000
+00010001
+00010010
+00010011
+00010100
+00010101
+00010110
+00010111
+00011000
+00011001
+00011010
+00011011
+00011100
+00011101
+00011110
+00011111
+00100000
+00100001
+00100010
+00100011
+00100100
+00100101
+00100110
+00100111
+00101000
+00101001
+00101010
+00101011
+00101100
+00101101
+00101110
+00101111
+00110000
+00110001
+00110010
+00110011
+00110100
+00110101
+00110110
+00110111
+00111000
+00111001
+00111010
+00111011
+00111100
+00111101
+00111110
+00111111
+01000000
+01000001
+01000010
+01000011
+01000100
+01000101
+01000110
+01000111
+01001000
+01001001
+01001010
+01001011
+01001100
+01001101
+01001110
+01001111
+01010000
+01010001
+01010010
+01010011
+01010100
+01010101
+01010110
+01010111
+01011000
+01011001
+01011010
+01011011
+01011100
+01011101
+01011110
+01011111
+01100000
+01100001
+01100010
+01100011
+01100100
+01100101
+01100110
+01100111
+01101000
+01101001
+01101010
+01101011
+01101100
+01101101
+01101110
+01101111
+01110000
+01110001
+01110010
+01110011
+01110100
+01110101
+01110110
+01110111
+01111000
+01111001
+01111010
+01111011
+01111100
+01111101
+01111110
+01111111
+10000000
+10000001
+10000010
+10000011
+10000100
+10000101
+10000110
+10000111
+10001000
+10001001
+10001010
+10001011
+10001100
+10001101
+10001110
+10001111
+10010000
+10010001
+10010010
+10010011
+10010100
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/c5_pin_model_dump.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/c5_pin_model_dump.txt
new file mode 100644
index 0000000000000000000000000000000000000000..31bb72c180c644b5936c76019879f6dabecae944
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/.cmp.kpt b/Individual_Project/Posit_Adder/Core_Arithmetic/db/.cmp.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..a8078699711bccbafc68026fbb762443827fca3a
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/.cmp.kpt differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..3385c491f8d4c848384bab5aa5dd305045a52c6a
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..9f83429b70337e1d9af886b7b6ac579222c103cc
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(0).cnf.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..c55088f446a7e239a39afb7354c52b94ee77be3d
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..351c368aee31f3e58da10e542d18d97300ddbe53
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(1).cnf.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..da5115fa53012631c5d2772ec6a1db5113ef18d4
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..c9fc137e9e4ef678fc47408ca1d18479ca62b0a7
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.(2).cnf.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..99f237421231d6e3592f830d823195d7547cd5d8
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676404756944 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676404756944 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:59:16 2023 " "Processing started: Tue Feb 14 19:59:16 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676404756944 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1676404756944 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1676404756944 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1676404757667 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1676404761820 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4892 " "Peak virtual memory: 4892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676404762184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:59:22 2023 " "Processing ended: Tue Feb 14 19:59:22 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676404762184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676404762184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676404762184 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1676404762184 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..35d978a6cae875990a8f9de6d105b723bcec3eee
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.asm.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cbx.xml b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cbx.xml
new file mode 100644
index 0000000000000000000000000000000000000000..d23837fb371589595fa50c652e81d25258ecbff6
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="Posit_Adder">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.idb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.idb
new file mode 100644
index 0000000000000000000000000000000000000000..9fa34e045218332d7a003b7e014be7b476403fd7
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.idb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..189833529cc4a891ba8f66dbb7437dfdbaf11efc
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp_merge.kpt b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp_merge.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..d7af8c7027a4cb3e9b57215774f88bd6cff47316
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cmp_merge.kpt differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..e0d06c5b2ad7415a435efa5bcb59e2f358e3bd53
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_0c_fast.hsd differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..3651200a0bf065de37c8578bdb32954144c933d1
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.ff_85c_fast.hsd differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_0c_slow.hsd b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..6ff63fe34500be6b7f11c866a65d5a8b1abbe12e
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_0c_slow.hsd differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_85c_slow.hsd b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..d3df58bc8c9a04b26dfefc7ae758dcf011076d96
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.cyclonev_io_sim_cache.tt_85c_slow.hsd differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.db_info b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..446454f7d3c6375c16b0618477ce9b50a86f0b58
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 21 16:35:12 2023
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.eda.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.eda.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..7a9821f126aa6af26c8d954b223e3eea09527447
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.eda.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676404768421 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676404768421 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:59:28 2023 " "Processing started: Tue Feb 14 19:59:28 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676404768421 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676404768421 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676404768421 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1676404769378 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Posit_Adder.vo H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/ simulation " "Generated file Posit_Adder.vo in folder \"H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1676404769441 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4730 " "Peak virtual memory: 4730 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676404769490 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:59:29 2023 " "Processing ended: Tue Feb 14 19:59:29 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676404769490 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676404769490 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676404769490 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1676404769490 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.fit.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.fit.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..ac594f606ea089283b8b2f4fb401e30eebf1cc6e
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1676404717916 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1676404717916 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "Posit_Adder 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"Posit_Adder\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1676404717927 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676404717966 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676404717966 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1676404718258 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1676404718281 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1676404718481 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "24 24 " "No exact pin location assignment(s) for 24 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1676404718696 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1676404726558 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404726619 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1676404726622 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676404726622 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676404726622 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1676404726622 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1676404726623 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1676404726623 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1676404726623 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1676404726623 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1676404726623 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404726636 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Posit_Adder.sdc " "Synopsys Design Constraints File file not found: 'Posit_Adder.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1676404731305 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1676404731305 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1676404731306 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1676404731306 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1676404731307 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1676404731307 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1676404731308 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1676404731312 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1676404731361 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:11 " "Fitter placement preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404742638 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1676404747075 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1676404747547 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404747547 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1676404748376 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" {  } { { "loc" "" { Generic "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1676404751640 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1676404751640 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1676404751836 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1676404751836 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1676404751836 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404751840 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1676404752916 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676404752946 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676404753215 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676404753215 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676404753462 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676404755148 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg " "Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1676404755449 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6736 " "Peak virtual memory: 6736 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676404755871 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:59:15 2023 " "Processing ended: Tue Feb 14 19:59:15 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676404755871 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676404755871 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676404755871 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1676404755871 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hier_info b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hier_info
new file mode 100644
index 0000000000000000000000000000000000000000..fffc453610d82ad55c9c6fffed5edc89a59056e8
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hier_info
@@ -0,0 +1,165 @@
+|Posit_Adder
+IN1[0] => IN1[0].IN1
+IN1[1] => IN1[1].IN1
+IN1[2] => IN1[2].IN1
+IN1[3] => IN1[3].IN1
+IN1[4] => IN1[4].IN1
+IN1[5] => IN1[5].IN1
+IN1[6] => IN1[6].IN1
+IN1[7] => IN1[7].IN1
+IN2[0] => IN2[0].IN1
+IN2[1] => IN2[1].IN1
+IN2[2] => IN2[2].IN1
+IN2[3] => IN2[3].IN1
+IN2[4] => IN2[4].IN1
+IN2[5] => IN2[5].IN1
+IN2[6] => IN2[6].IN1
+IN2[7] => IN2[7].IN1
+OUT[0] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[1] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[2] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[3] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[4] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[5] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[6] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[7] << LS.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Adder|Data_Extraction:Extract_IN1
+In[0] => InRemain.DATAA
+In[0] => Add0.IN8
+In[1] => InRemain.DATAA
+In[1] => Add0.IN7
+In[2] => InRemain.DATAA
+In[2] => Add0.IN6
+In[3] => InRemain.DATAA
+In[3] => Add0.IN5
+In[4] => InRemain.DATAA
+In[4] => Add0.IN4
+In[5] => InRemain.DATAA
+In[5] => Add0.IN3
+In[6] => InRemain.DATAA
+In[6] => Add0.IN2
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => Sign.DATAIN
+Sign <= In[7].DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[0] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[1] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[2] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[3] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[4] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[0] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[1] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[2] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[0] <= <GND>
+Mantissa[1] <= <GND>
+Mantissa[2] <= <GND>
+Mantissa[3] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[4] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[5] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[6] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[7] <= <VCC>
+InRemain[0] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[1] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[2] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[3] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[4] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[5] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[6] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Adder|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1
+InRemain[0] => ~NO_FANOUT~
+InRemain[1] => always0.IN0
+InRemain[2] => always0.IN0
+InRemain[3] => always0.IN0
+InRemain[4] => always0.IN0
+InRemain[5] => always0.IN0
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => RegimeCheck.DATAIN
+EndPosition[0] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[1] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[2] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[3] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+RegimeCheck <= InRemain[6].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Adder|Data_Extraction:Extract_IN2
+In[0] => InRemain.DATAA
+In[0] => Add0.IN8
+In[1] => InRemain.DATAA
+In[1] => Add0.IN7
+In[2] => InRemain.DATAA
+In[2] => Add0.IN6
+In[3] => InRemain.DATAA
+In[3] => Add0.IN5
+In[4] => InRemain.DATAA
+In[4] => Add0.IN4
+In[5] => InRemain.DATAA
+In[5] => Add0.IN3
+In[6] => InRemain.DATAA
+In[6] => Add0.IN2
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => Sign.DATAIN
+Sign <= In[7].DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[0] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[1] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[2] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[3] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[4] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[0] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[1] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[2] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[0] <= <GND>
+Mantissa[1] <= <GND>
+Mantissa[2] <= <GND>
+Mantissa[3] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[4] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[5] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[6] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[7] <= <VCC>
+InRemain[0] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[1] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[2] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[3] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[4] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[5] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[6] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Adder|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1
+InRemain[0] => ~NO_FANOUT~
+InRemain[1] => always0.IN0
+InRemain[2] => always0.IN0
+InRemain[3] => always0.IN0
+InRemain[4] => always0.IN0
+InRemain[5] => always0.IN0
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => RegimeCheck.DATAIN
+EndPosition[0] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[1] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[2] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[3] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+RegimeCheck <= InRemain[6].DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hif b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hif
new file mode 100644
index 0000000000000000000000000000000000000000..19e08174f96fed099c9cc30722c44ff17a74472f
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.hif differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.html b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.html
new file mode 100644
index 0000000000000000000000000000000000000000..de5c60eff702bd3287dbc38704f700417a14495e
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.html
@@ -0,0 +1,82 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >Extract_IN2|LBD1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN2</TD>
+<TD >8</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >24</TD>
+<TD >5</TD>
+<TD >5</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN1|LBD1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN1</TD>
+<TD >8</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >24</TD>
+<TD >5</TD>
+<TD >5</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..a300d4a64ae72be6b9eb2180b8ecde1970d51e6a
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.txt
new file mode 100644
index 0000000000000000000000000000000000000000..057a4862172fec0f9b5354fce8575a75dd885073
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.lpc.txt
@@ -0,0 +1,10 @@
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                            ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy        ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Extract_IN2|LBD1 ; 7     ; 0              ; 1            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN2      ; 8     ; 5              ; 0            ; 5              ; 24     ; 5               ; 5             ; 5               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN1|LBD1 ; 7     ; 0              ; 1            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN1      ; 8     ; 5              ; 0            ; 5              ; 24     ; 5               ; 5             ; 5               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.ammdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..abcb3fcadbb7dc2eda53aadaab31a267a693fbe4
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.ammdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.bpm b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..48105f3c6175610cea68aebfb341a0f154054245
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.bpm differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..b52bb846c8584c3528506932834e5165c2fff29d
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..fca443a5ae2914941746581962e8c3bdca353120
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.kpt b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..2e31b791873b0b84d263238181519bea624df5ef
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.kpt differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.logdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..622d606163712185db2a2472fd0c6619ab31c4e0
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.qmsg
@@ -0,0 +1,22 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676997321929 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676997321930 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 21 16:35:21 2023 " "Processing started: Tue Feb 21 16:35:21 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676997321930 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997321930 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997321930 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676997322534 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676997322535 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_adder_arithmetic.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_adder_arithmetic.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Posit_Adder " "Found entity 1: Posit_Adder" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676997329570 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997329570 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "leading_bit_detector.sv 1 1 " "Found 1 design units, including 1 entities, in source file leading_bit_detector.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Leading_Bit_Detector " "Found entity 1: Leading_Bit_Detector" {  } { { "Leading_Bit_Detector.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676997329573 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997329573 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_extraction.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_extraction.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Extraction " "Found entity 1: Data_Extraction" {  } { { "Posit_Extraction.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676997329580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997329580 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Posit_Adder " "Elaborating entity \"Posit_Adder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676997329636 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LIn Posit_Adder_Arithmetic.sv(46) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object \"LIn\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SIn Posit_Adder_Arithmetic.sv(46) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object \"SIn\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SS Posit_Adder_Arithmetic.sv(47) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(47): object \"SS\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LRC Posit_Adder_Arithmetic.sv(49) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(49): object \"LRC\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 Posit_Adder_Arithmetic.sv(122) " "Verilog HDL assignment warning at Posit_Adder_Arithmetic.sv(122): truncated value with size 32 to match size of target (8)" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Warning" "WVRFX_VERI_2086_UNCONVERTED" "Posit_Adder_Arithmetic.sv(179) " "Verilog HDL warning at Posit_Adder_Arithmetic.sv(179): converting signed shift amount to unsigned" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 179 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Analysis & Synthesis" 0 -1 1676997329658 "|Posit_Adder"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Data_Extraction Data_Extraction:Extract_IN1 " "Elaborating entity \"Data_Extraction\" for hierarchy \"Data_Extraction:Extract_IN1\"" {  } { { "Posit_Adder_Arithmetic.sv" "Extract_IN1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676997329661 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Leading_Bit_Detector Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1 " "Elaborating entity \"Leading_Bit_Detector\" for hierarchy \"Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1\"" {  } { { "Posit_Extraction.sv" "LBD1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676997329670 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1676997330178 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676997330722 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676997331437 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676997331437 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "200 " "Implemented 200 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676997331526 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676997331526 ""} { "Info" "ICUT_CUT_TM_LCELLS" "176 " "Implemented 176 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676997331526 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676997331526 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4837 " "Peak virtual memory: 4837 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676997331543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 21 16:35:31 2023 " "Processing ended: Tue Feb 21 16:35:31 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676997331543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676997331543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676997331543 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676997331543 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.rdb
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index 0000000000000000000000000000000000000000..4e0250cb6816899f316ee6d526b99d396407523d
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.cdb
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index 0000000000000000000000000000000000000000..c6cb782399c0570c2e87ff2b2aefba1a7ce8df7e
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..e62312b24e80c006bae32b52c10512ae194e39bb
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.logdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.pre_map.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.pre_map.hdb
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index 0000000000000000000000000000000000000000..b479bddd110d9da3cd702abbf6a410239a46d9c0
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.pre_map.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.root_partition.map.reg_db.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.root_partition.map.reg_db.cdb
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index 0000000000000000000000000000000000000000..3cb2b933646b8c4ac4532ff2a41378e28bcaf6e7
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.root_partition.map.reg_db.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.routing.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.routing.rdb
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index 0000000000000000000000000000000000000000..0d84b946532ae7b35e4b82dc5a28b1ef79285886
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.routing.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv.hdb
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index 0000000000000000000000000000000000000000..bf5f1c5d63dd13b54c60ed111a8bfc89ec757b6d
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv.hdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg.cdb
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Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg_swap.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg_swap.cdb
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Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.rtlv_sg_swap.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry.sci b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry.sci
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index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry.sci differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry_dsc.sci b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry_dsc.sci
new file mode 100644
index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sld_design_entry_dsc.sci differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.smart_action.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.smart_action.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e04bbcfecfa47784a5fc67ffb30a5d652da87a98
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..e1ef9dd63a8aa80770e4f90f30a481d93486e68f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676404763445 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676404763446 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:59:23 2023 " "Processing started: Tue Feb 14 19:59:23 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676404763446 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1676404763446 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Posit_Adder -c Posit_Adder " "Command: quartus_sta Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1676404763446 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1676404763601 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1676404764222 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1676404764222 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404764259 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404764259 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Posit_Adder.sdc " "Synopsys Design Constraints File file not found: 'Posit_Adder.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1676404764673 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404764673 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676404764674 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676404764674 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1676404764675 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676404764675 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1676404764675 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1676404764683 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676404764685 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764688 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764697 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764700 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764703 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764705 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404764708 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676404764712 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676404764738 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676404765374 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404765433 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676404765434 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676404765434 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676404765434 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765436 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765440 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765443 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765446 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765449 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404765451 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676404765454 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676404765592 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676404766100 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404766148 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676404766149 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676404766149 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676404766149 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766153 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766155 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766159 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766162 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766163 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676404766167 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676404766301 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676404766302 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676404766302 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676404766303 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766306 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766310 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766312 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766315 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676404766317 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676404767340 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676404767343 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5169 " "Peak virtual memory: 5169 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676404767391 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:59:27 2023 " "Processing ended: Tue Feb 14 19:59:27 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676404767391 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676404767391 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676404767391 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1676404767391 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.rdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..399b2235ab266d5490abbc9418db170e89133589
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.sta.rdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tis_db_list.ddb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tis_db_list.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..99d83cf5d962a594b666f6ccc4b2389ada79d756
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tis_db_list.ddb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_0c.ddb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_0c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..73869baa1e2ad89d98c7933ded0e3cad37d69748
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_0c.ddb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_85c.ddb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_85c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..a04f61132f9bb5e32dfb2217627e6033e8b55af2
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.fast_1100mv_85c.ddb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_0c.ddb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_0c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..66b34db0670f0094ed35c6c2ae9a26d7e6064d8f
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_0c.ddb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_85c.ddb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_85c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..8fbd3f0e7ec0c1a0731b24a765b2f824f0d96520
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tiscmp.slow_1100mv_85c.ddb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tmw_info b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tmw_info
new file mode 100644
index 0000000000000000000000000000000000000000..b00d4d56e2c34ad87472da5619c94050a5728e8b
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.tmw_info
@@ -0,0 +1,2 @@
+start_analysis_synthesis:s:00:00:11
+start_analysis_elaboration:s
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.vpr.ammdb b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.vpr.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..20a8a63a59f5708a581420f54f4f67eccea32ca6
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder.vpr.ammdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder_partition_pins.json b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder_partition_pins.json
new file mode 100644
index 0000000000000000000000000000000000000000..0fe50df08e41e6cb972f1585031e6f8663efcc82
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/Posit_Adder_partition_pins.json
@@ -0,0 +1,105 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "OUT[0]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[1]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[2]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[3]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[4]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[5]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[6]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[0]",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
\ No newline at end of file
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/db/prev_cmp_Posit_Adder.qmsg b/Individual_Project/Posit_Adder/Core_Arithmetic/db/prev_cmp_Posit_Adder.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..208e254fd502b5a0f55fd13b9b18f8c11b50ba35
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/db/prev_cmp_Posit_Adder.qmsg
@@ -0,0 +1,23 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676404567598 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676404567599 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:56:07 2023 " "Processing started: Tue Feb 14 19:56:07 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676404567599 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404567599 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404567599 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676404568151 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676404568151 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_adder_arithmetic.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_adder_arithmetic.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Posit_Adder " "Found entity 1: Posit_Adder" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676404575046 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404575046 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "leading_bit_detector.sv 1 1 " "Found 1 design units, including 1 entities, in source file leading_bit_detector.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Leading_Bit_Detector " "Found entity 1: Leading_Bit_Detector" {  } { { "Leading_Bit_Detector.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676404575049 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404575049 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_extraction.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_extraction.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Extraction " "Found entity 1: Data_Extraction" {  } { { "Posit_Extraction.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676404575051 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404575051 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Posit_Adder " "Elaborating entity \"Posit_Adder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676404575074 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LIn Posit_Adder_Arithmetic.sv(46) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object \"LIn\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676404575079 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SIn Posit_Adder_Arithmetic.sv(46) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object \"SIn\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676404575080 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SS Posit_Adder_Arithmetic.sv(47) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(47): object \"SS\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676404575080 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LRC Posit_Adder_Arithmetic.sv(49) " "Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(49): object \"LRC\" assigned a value but never read" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1676404575080 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 Posit_Adder_Arithmetic.sv(122) " "Verilog HDL assignment warning at Posit_Adder_Arithmetic.sv(122): truncated value with size 32 to match size of target (8)" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676404575082 "|Posit_Adder"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Posit_Adder_Arithmetic.sv(154) " "Verilog HDL assignment warning at Posit_Adder_Arithmetic.sv(154): truncated value with size 32 to match size of target (4)" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676404575082 "|Posit_Adder"}
+{ "Warning" "WVRFX_VERI_2086_UNCONVERTED" "Posit_Adder_Arithmetic.sv(179) " "Verilog HDL warning at Posit_Adder_Arithmetic.sv(179): converting signed shift amount to unsigned" {  } { { "Posit_Adder_Arithmetic.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 179 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Analysis & Synthesis" 0 -1 1676404575083 "|Posit_Adder"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Data_Extraction Data_Extraction:Extract_IN1 " "Elaborating entity \"Data_Extraction\" for hierarchy \"Data_Extraction:Extract_IN1\"" {  } { { "Posit_Adder_Arithmetic.sv" "Extract_IN1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676404575094 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Leading_Bit_Detector Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1 " "Elaborating entity \"Leading_Bit_Detector\" for hierarchy \"Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1\"" {  } { { "Posit_Extraction.sv" "LBD1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676404575102 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1676404575590 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676404576135 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676404576743 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676404576743 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "200 " "Implemented 200 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676404576785 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676404576785 ""} { "Info" "ICUT_CUT_TM_LCELLS" "176 " "Implemented 176 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676404576785 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676404576785 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676404576802 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:56:16 2023 " "Processing ended: Tue Feb 14 19:56:16 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676404576802 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676404576802 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676404576802 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676404576802 ""}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt b/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..658be9c7743cc4f76e73bd7508b0736140c303b7
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/error_8bit.txt
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/README b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/README
new file mode 100644
index 0000000000000000000000000000000000000000..9f62dcda0512fec7b5b55c11a13d70f91548996f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.db_info b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..3b22d53ca1017f4a2a0bbba55b0fc7d14de7b585
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 14 19:56:15 2023
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.ammdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.ammdb
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.dfp b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.dfp
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.cdb
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.hdb
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.sig b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
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+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.hdb
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.logdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.rcfdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.cmp.rcfdb
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.sig b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.sig
new file mode 100644
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.rrs.cdb b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.rrs.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..32922531165ab79bf84f7ef699f7d626646ee4f9
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/incremental_db/compiled_partitions/Posit_Adder.rrs.cdb differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.asm.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.asm.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..60811c64a1b099c565b927d7bcc7723448656e15
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.asm.rpt
@@ -0,0 +1,91 @@
+Assembler report for Posit_Adder
+Tue Feb 14 19:59:22 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Feb 14 19:59:22 2023 ;
+; Revision Name         ; Posit_Adder                           ;
+; Top-level Entity Name ; Posit_Adder                           ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                               ;
++---------------------------------------------------------------------------------------------------------+
+; File Name                                                                                               ;
++---------------------------------------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof ;
++---------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof ;
++----------------+------------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                          ;
++----------------+------------------------------------------------------------------------------------------------------------------+
+; JTAG usercode  ; 0x00B27A04                                                                                                       ;
+; Checksum       ; 0x00B27A04                                                                                                       ;
++----------------+------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:59:16 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4892 megabytes
+    Info: Processing ended: Tue Feb 14 19:59:22 2023
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.done b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.done
new file mode 100644
index 0000000000000000000000000000000000000000..48a18cd949e034250dc63e035986fbd7cb5d00f8
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.done
@@ -0,0 +1 @@
+Tue Feb 21 16:35:32 2023
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.eda.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.eda.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..9fa3d2aeb9db2aff9044e040444a4f23122cb797
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.eda.rpt
@@ -0,0 +1,94 @@
+EDA Netlist Writer report for Posit_Adder
+Tue Feb 14 19:59:29 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Tue Feb 14 19:59:29 2023 ;
+; Revision Name             ; Posit_Adder                           ;
+; Top-level Entity Name     ; Posit_Adder                           ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                             ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Option                                                                                            ; Setting                     ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Tool Name                                                                                         ; Questa Intel FPGA (Verilog) ;
+; Generate functional simulation netlist                                                            ; On                          ;
+; Truncate long hierarchy paths                                                                     ; Off                         ;
+; Map illegal HDL characters                                                                        ; Off                         ;
+; Flatten buses into individual nodes                                                               ; Off                         ;
+; Maintain hierarchy                                                                                ; Off                         ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                         ;
+; Enable glitch filtering                                                                           ; Off                         ;
+; Do not write top level VHDL entity                                                                ; Off                         ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                         ;
+; Architecture name in VHDL output netlist                                                          ; structure                   ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                         ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                         ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                  ;
++-------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                             ;
++-------------------------------------------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.vo ;
++-------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:59:28 2023
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Posit_Adder -c Posit_Adder
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (204019): Generated file Posit_Adder.vo in folder "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4730 megabytes
+    Info: Processing ended: Tue Feb 14 19:59:29 2023
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5217ab32fb99d89eee106e793f8d437e57c3f09c
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.rpt
@@ -0,0 +1,1790 @@
+Fitter report for Posit_Adder
+Tue Feb 14 19:59:15 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Incremental Compilation Preservation Summary
+  6. Incremental Compilation Partition Settings
+  7. Incremental Compilation Placement Preservation
+  8. Pin-Out File
+  9. Fitter Resource Usage Summary
+ 10. Fitter Partition Statistics
+ 11. Input Pins
+ 12. Output Pins
+ 13. I/O Bank Usage
+ 14. All Package Pins
+ 15. I/O Assignment Warnings
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Routing Usage Summary
+ 20. I/O Rules Summary
+ 21. I/O Rules Details
+ 22. I/O Rules Matrix
+ 23. Fitter Device Options
+ 24. Operating Settings and Conditions
+ 25. Fitter Messages
+ 26. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++---------------------------------+------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Feb 14 19:59:15 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Adder                                    ;
+; Top-level Entity Name           ; Posit_Adder                                    ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; 109 / 32,070 ( < 1 % )                         ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24 / 457 ( 5 % )                               ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                          ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                 ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                  ;
++---------------------------------+------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                             ; Setting                               ; Default Value                         ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                             ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                  ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                  ; 85                                    ;                                       ;
+; Use smart compilation                                              ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                                    ; On                                    ;
+; Enable compact report table                                        ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                   ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                  ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                        ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                 ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                               ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                       ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                        ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                   ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                                  ; Care                                  ;
+; Power Optimization During Fitting                                  ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                   ; Off                                   ; Off                                   ;
+; Optimize Timing                                                    ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                           ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                         ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                      ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                      ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization               ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                              ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                          ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                              ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                  ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                              ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                       ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                          ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                             ; Off                                   ; Off                                   ;
+; Fitter Effort                                                      ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                    ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                          ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                  ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                               ; On                                    ; On                                    ;
+; Reserve all unused pins                                            ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                        ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                  ; On                                    ; On                                    ;
+; Active Serial clock source                                         ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
+; Clamping Diode                                                     ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode   ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                     ; On                                    ; On                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.2%      ;
+;     Processor 3            ;   0.2%      ;
+;     Processor 4            ;   0.2%      ;
+;     Processor 5            ;   0.2%      ;
+;     Processor 6            ;   0.2%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 225 ) ; 0.00 % ( 0 / 225 )         ; 0.00 % ( 0 / 225 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 225 ) ; 0.00 % ( 0 / 225 )         ; 0.00 % ( 0 / 225 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 225 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 109 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 109                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 109 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 0                  ;       ;
+;         [b] ALMs used for LUT logic                         ; 109                ;       ;
+;         [c] ALMs used for registers                         ; 0                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32,070         ; 0 %   ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 13 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 13                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 177                ;       ;
+;     -- 7 input functions                                    ; 3                  ;       ;
+;     -- 6 input functions                                    ; 41                 ;       ;
+;     -- 5 input functions                                    ; 41                 ;       ;
+;     -- 4 input functions                                    ; 41                 ;       ;
+;     -- <=3 input functions                                  ; 51                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Dedicated logic registers                                   ; 0                  ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 0 / 64,140         ; 0 %   ;
+;         -- Secondary logic registers                        ; 0 / 64,140         ; 0 %   ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 0                  ;       ;
+;         -- Routing optimization registers                   ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 24 / 457           ; 5 %   ;
+;     -- Clock pins                                           ; 0 / 8              ; 0 %   ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global signals                                              ; 0                  ;       ;
+;     -- Global clocks                                        ; 0 / 16             ; 0 %   ;
+;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
+;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 1.0% / 1.0% / 1.1% ;       ;
+; Maximum fan-out                                             ; 29                 ;       ;
+; Highest non-global fan-out                                  ; 29                 ;       ;
+; Total fan-out                                               ; 820                ;       ;
+; Average fan-out                                             ; 3.64               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 109 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 109                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 109 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 0                     ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 109                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 0                     ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 13 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 13                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 177                   ; 0                              ;
+;     -- 7 input functions                                    ; 3                     ; 0                              ;
+;     -- 6 input functions                                    ; 41                    ; 0                              ;
+;     -- 5 input functions                                    ; 41                    ; 0                              ;
+;     -- 4 input functions                                    ; 41                    ; 0                              ;
+;     -- <=3 input functions                                  ; 51                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 0                     ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 0 / 64140 ( 0 % )     ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 0 / 64140 ( 0 % )     ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 0                     ; 0                              ;
+;         -- Routing optimization registers                   ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 24                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 0                     ; 0                              ;
+; Total block memory implementation bits                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 823                   ; 0                              ;
+;     -- Registered Connections                               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 16                    ; 0                              ;
+;     -- Output Ports                                         ; 8                     ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                            ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; IN1[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[1] ; W22   ; 5A       ; 89           ; 8            ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[2] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[3] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[4] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[5] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[6] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[7] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; 12                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[0] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[1] ; W21   ; 5A       ; 89           ; 8            ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[2] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[3] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[4] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[6] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[7] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; 12                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; OUT[0] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[2] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[3] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[6] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[7] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 4A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 5A       ; 24 / 32 ( 75 % ) ; 2.5V          ; --           ; 2.5V          ;
+; 5B       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; IN1[4]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; IN2[0]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; IN1[2]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; IN1[5]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; IN2[7]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; IN1[6]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; OUT[1]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC29     ; 247        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC30     ; 259        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; OUT[2]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; IN2[4]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD30     ; 257        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; IN1[0]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; IN1[7]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; IN2[3]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; OUT[6]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AF30     ; 239        ; 5A             ; OUT[5]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AG28     ; 233        ; 5A             ; IN2[5]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; OUT[0]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AH29     ; 218        ; 5A             ; IN2[2]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; OUT[3]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; OUT[7]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; IN2[1]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; IN1[1]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; OUT[4]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; IN2[6]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; IN1[3]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; OUT[0]   ; Incomplete set of assignments ;
+; OUT[1]   ; Incomplete set of assignments ;
+; OUT[2]   ; Incomplete set of assignments ;
+; OUT[3]   ; Incomplete set of assignments ;
+; OUT[4]   ; Incomplete set of assignments ;
+; OUT[5]   ; Incomplete set of assignments ;
+; OUT[6]   ; Incomplete set of assignments ;
+; OUT[7]   ; Incomplete set of assignments ;
+; IN2[7]   ; Incomplete set of assignments ;
+; IN1[7]   ; Incomplete set of assignments ;
+; IN2[6]   ; Incomplete set of assignments ;
+; IN1[6]   ; Incomplete set of assignments ;
+; IN2[5]   ; Incomplete set of assignments ;
+; IN1[5]   ; Incomplete set of assignments ;
+; IN2[4]   ; Incomplete set of assignments ;
+; IN1[4]   ; Incomplete set of assignments ;
+; IN2[3]   ; Incomplete set of assignments ;
+; IN1[3]   ; Incomplete set of assignments ;
+; IN2[2]   ; Incomplete set of assignments ;
+; IN1[2]   ; Incomplete set of assignments ;
+; IN2[1]   ; Incomplete set of assignments ;
+; IN1[1]   ; Incomplete set of assignments ;
+; IN2[0]   ; Incomplete set of assignments ;
+; IN1[0]   ; Incomplete set of assignments ;
+; OUT[0]   ; Missing location assignment   ;
+; OUT[1]   ; Missing location assignment   ;
+; OUT[2]   ; Missing location assignment   ;
+; OUT[3]   ; Missing location assignment   ;
+; OUT[4]   ; Missing location assignment   ;
+; OUT[5]   ; Missing location assignment   ;
+; OUT[6]   ; Missing location assignment   ;
+; OUT[7]   ; Missing location assignment   ;
+; IN2[7]   ; Missing location assignment   ;
+; IN1[7]   ; Missing location assignment   ;
+; IN2[6]   ; Missing location assignment   ;
+; IN1[6]   ; Missing location assignment   ;
+; IN2[5]   ; Missing location assignment   ;
+; IN1[5]   ; Missing location assignment   ;
+; IN2[4]   ; Missing location assignment   ;
+; IN1[4]   ; Missing location assignment   ;
+; IN2[3]   ; Missing location assignment   ;
+; IN1[3]   ; Missing location assignment   ;
+; IN2[2]   ; Missing location assignment   ;
+; IN1[2]   ; Missing location assignment   ;
+; IN2[1]   ; Missing location assignment   ;
+; IN1[1]   ; Missing location assignment   ;
+; IN2[0]   ; Missing location assignment   ;
+; IN1[0]   ; Missing location assignment   ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+; Compilation Hierarchy Node        ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                ; Entity Name          ; Library Name ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+; |Posit_Adder                      ; 108.5 (77.0)         ; 108.5 (77.5)                     ; 0.0 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 177 (128)           ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 24   ; 0            ; |Posit_Adder                                                       ; Posit_Adder          ; work         ;
+;    |Data_Extraction:Extract_IN1|  ; 16.5 (14.5)          ; 16.5 (14.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 26 (24)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN1                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (2)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
+;    |Data_Extraction:Extract_IN2|  ; 14.5 (12.5)          ; 14.5 (12.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 23 (21)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN2                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (2)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                   ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name   ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; OUT[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; IN2[7] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[7] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[6] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[6] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[5] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[5] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[4] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[4] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[3] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[3] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[2] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[2] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[1] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[1] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[0] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[0] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                           ;
++--------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                        ; Pad To Core Index ; Setting ;
++--------------------------------------------+-------------------+---------+
+; IN2[7]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~25 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~21 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~17 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~13 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~9  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~5  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~1  ; 0                 ; 0       ;
+;      - Add3~38                             ; 0                 ; 0       ;
+;      - Add3~13                             ; 0                 ; 0       ;
+;      - Add3~17                             ; 0                 ; 0       ;
+;      - LS~0                                ; 0                 ; 0       ;
+;      - Operation                           ; 0                 ; 0       ;
+; IN1[7]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~25 ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~21 ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~17 ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~13 ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~9  ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~5  ; 1                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~1  ; 1                 ; 0       ;
+;      - Add3~38                             ; 1                 ; 0       ;
+;      - Add3~13                             ; 1                 ; 0       ;
+;      - Add3~17                             ; 1                 ; 0       ;
+;      - LS~0                                ; 1                 ; 0       ;
+;      - Operation                           ; 1                 ; 0       ;
+; IN2[6]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~1  ; 1                 ; 0       ;
+; IN1[6]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~1  ; 1                 ; 0       ;
+; IN2[5]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~5  ; 1                 ; 0       ;
+; IN1[5]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~5  ; 0                 ; 0       ;
+; IN2[4]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~9  ; 1                 ; 0       ;
+; IN1[4]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~9  ; 1                 ; 0       ;
+; IN2[3]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~13 ; 1                 ; 0       ;
+; IN1[3]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~13 ; 0                 ; 0       ;
+; IN2[2]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~17 ; 1                 ; 0       ;
+; IN1[2]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~17 ; 0                 ; 0       ;
+; IN2[1]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~21 ; 1                 ; 0       ;
+; IN1[1]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~21 ; 0                 ; 0       ;
+; IN2[0]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~25 ; 1                 ; 0       ;
+; IN1[0]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~25 ; 1                 ; 0       ;
++--------------------------------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 238 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 0 / 13,420 ( 0 % )      ;
+; C2 interconnects                            ; 59 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 17 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 52 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 0 / 16 ( 0 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 65 / 84,580 ( < 1 % )   ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 8 / 12,676 ( < 1 % )    ;
+; R14/C12 interconnect drivers                ; 0 / 20,720 ( 0 % )      ;
+; R3 interconnects                            ; 79 / 130,992 ( < 1 % )  ;
+; R6 interconnects                            ; 83 / 266,960 ( < 1 % )  ;
+; Spine clocks                                ; 0 / 360 ( 0 % )         ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                 ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 24        ; 0            ; 0            ; 24        ; 24        ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 24           ; 24           ; 24           ; 24           ; 24           ; 0         ; 24           ; 24           ; 0         ; 0         ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 24           ; 24           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; OUT[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "Posit_Adder"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 24 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Posit_Adder.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:11
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Info (144001): Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 6736 megabytes
+    Info: Processing ended: Tue Feb 14 19:59:15 2023
+    Info: Elapsed time: 00:00:38
+    Info: Total CPU time (on all processors): 00:00:43
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg.
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg
new file mode 100644
index 0000000000000000000000000000000000000000..930291945870c27fa8ede0009c58b1d66c8d95a3
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.summary b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.summary
new file mode 100644
index 0000000000000000000000000000000000000000..6f91bfe613e212f1f8c37a8ceaa1435f6fcdbc06
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Feb 14 19:59:15 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : Posit_Adder
+Top-level Entity Name : Posit_Adder
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 109 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 24 / 457 ( 5 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.flow.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.flow.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..2ee14695d678e5400b86b1d43192698c3dea216a
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.flow.rpt
@@ -0,0 +1,124 @@
+Flow report for Posit_Adder
+Tue Feb 21 16:35:31 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++---------------------------------+------------------------------------------------+
+; Flow Status                     ; Successful - Tue Feb 21 16:35:31 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Adder                                    ;
+; Top-level Entity Name           ; Posit_Adder                                    ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 0                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/21/2023 16:35:22 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; Posit_Adder         ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                               ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID               ; 1099276844422.167699732226500          ; --            ; --          ; --                                ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
+; EDA_SIMULATION_TOOL                 ; Questa Intel FPGA (Verilog)            ; <None>        ; --          ; --                                ;
+; EDA_TIME_SCALE                      ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --                                ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --                                ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --                                ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10     ; 1.0                     ; 4837 MB             ; 00:00:10                           ;
+; Total                ; 00:00:10     ; --                      ; --                  ; 00:00:10                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder
+
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.jdi b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.jdi
new file mode 100644
index 0000000000000000000000000000000000000000..def11aa79754d9a2db754612e0dd23cfe34dbd9f
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="8fdcb4b79367c4914215"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="Posit_Adder.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..17baaea38a5b2767d66201f203d7d88412449294
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.rpt
@@ -0,0 +1,419 @@
+Analysis & Synthesis report for Posit_Adder
+Tue Feb 21 16:35:31 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 10. Parameter Settings for User Entity Instance: Top-level Entity: |Posit_Adder
+ 11. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1
+ 12. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1
+ 13. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2
+ 14. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1
+ 15. Port Connectivity Checks: "Data_Extraction:Extract_IN2"
+ 16. Port Connectivity Checks: "Data_Extraction:Extract_IN1"
+ 17. Post-Synthesis Netlist Statistics for Top Partition
+ 18. Elapsed Time Per Partition
+ 19. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++---------------------------------+------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Feb 21 16:35:31 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Adder                                    ;
+; Top-level Entity Name           ; Posit_Adder                                    ;
+; Family                          ; Cyclone V                                      ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 0                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; Posit_Adder        ; Posit_Adder        ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                             ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                         ; Library ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------+---------+
+; Posit_Adder_Arithmetic.sv        ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv ;         ;
+; Leading_Bit_Detector.sv          ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv   ;         ;
+; Posit_Extraction.sv              ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv       ;         ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary          ;
++---------------------------------------------+--------+
+; Resource                                    ; Usage  ;
++---------------------------------------------+--------+
+; Estimate of Logic utilization (ALMs needed) ; 110    ;
+;                                             ;        ;
+; Combinational ALUT usage for logic          ; 176    ;
+;     -- 7 input functions                    ; 3      ;
+;     -- 6 input functions                    ; 41     ;
+;     -- 5 input functions                    ; 41     ;
+;     -- 4 input functions                    ; 41     ;
+;     -- <=3 input functions                  ; 50     ;
+;                                             ;        ;
+; Dedicated logic registers                   ; 0      ;
+;                                             ;        ;
+; I/O pins                                    ; 24     ;
+;                                             ;        ;
+; Total DSP Blocks                            ; 0      ;
+;                                             ;        ;
+; Maximum fan-out node                        ; Add5~1 ;
+; Maximum fan-out                             ; 29     ;
+; Total fan-out                               ; 820    ;
+; Average fan-out                             ; 3.66   ;
++---------------------------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                   ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+; Compilation Hierarchy Node        ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                ; Entity Name          ; Library Name ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+; |Posit_Adder                      ; 176 (127)           ; 0 (0)                     ; 0                 ; 0          ; 24   ; 0            ; |Posit_Adder                                                       ; Posit_Adder          ; work         ;
+;    |Data_Extraction:Extract_IN1|  ; 26 (24)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN1                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
+;    |Data_Extraction:Extract_IN2|  ; 23 (21)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN2                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Adder|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------------------------------------------+----------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                  ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                        ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN1|ShiftLeft0                               ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN2|ShiftLeft0                               ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight0                                                          ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight1                                                          ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight1                                                          ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight1                                                          ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight1                                                          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |Posit_Adder|ShiftRight1                                                          ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1|EndPosition[0] ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN1|ShiftLeft0                               ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1|EndPosition[0] ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Posit_Adder|Data_Extraction:Extract_IN2|ShiftLeft0                               ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Adder|Add3                                                                 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |Posit_Adder ;
++----------------+----------------------------------+-------------------------+
+; Parameter Name ; Value                            ; Type                    ;
++----------------+----------------------------------+-------------------------+
+; N              ; 8                                ; Signed Integer          ;
+; ES             ; 3                                ; Signed Integer          ;
+; RS             ; 00000000000000000000000000000011 ; Unsigned Binary         ;
++----------------+----------------------------------+-------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; N              ; 8     ; Signed Integer                                  ;
+; ES             ; 3     ; Signed Integer                                  ;
+; RS             ; 3     ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ;
++----------------+-------+---------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                      ;
++----------------+-------+---------------------------------------------------------------------------+
+; N              ; 8     ; Signed Integer                                                            ;
+; ES             ; 3     ; Signed Integer                                                            ;
+; RS             ; 3     ; Signed Integer                                                            ;
++----------------+-------+---------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; N              ; 8     ; Signed Integer                                  ;
+; ES             ; 3     ; Signed Integer                                  ;
+; RS             ; 3     ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ;
++----------------+-------+---------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                      ;
++----------------+-------+---------------------------------------------------------------------------+
+; N              ; 8     ; Signed Integer                                                            ;
+; ES             ; 3     ; Signed Integer                                                            ;
+; RS             ; 3     ; Signed Integer                                                            ;
++----------------+-------+---------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "Data_Extraction:Extract_IN2"                                                                                                          ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+; Port        ; Type   ; Severity ; Details                                                                                                                        ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+; RegimeValue ; Output ; Warning  ; Output or bidir port (5 bits) is wider than the port expression (4 bits) it drives; bit(s) "RegimeValue[4..4]" have no fanouts ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "Data_Extraction:Extract_IN1"                                                                                                          ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+; Port        ; Type   ; Severity ; Details                                                                                                                        ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+; RegimeValue ; Output ; Warning  ; Output or bidir port (5 bits) is wider than the port expression (4 bits) it drives; bit(s) "RegimeValue[4..4]" have no fanouts ;
++-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb     ; 176                         ;
+;     arith             ; 49                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 2                           ;
+;         2 data inputs ; 16                          ;
+;         3 data inputs ; 3                           ;
+;         4 data inputs ; 20                          ;
+;         5 data inputs ; 7                           ;
+;     extend            ; 3                           ;
+;         7 data inputs ; 3                           ;
+;     normal            ; 124                         ;
+;         2 data inputs ; 14                          ;
+;         3 data inputs ; 14                          ;
+;         4 data inputs ; 21                          ;
+;         5 data inputs ; 34                          ;
+;         6 data inputs ; 41                          ;
+; boundary_port         ; 24                          ;
+;                       ;                             ;
+; Max LUT depth         ; 19.50                       ;
+; Average LUT depth     ; 18.66                       ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 21 16:35:21 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file posit_adder_arithmetic.sv
+    Info (12023): Found entity 1: Posit_Adder File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 28
+Info (12021): Found 1 design units, including 1 entities, in source file leading_bit_detector.sv
+    Info (12023): Found entity 1: Leading_Bit_Detector File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Leading_Bit_Detector.sv Line: 19
+Info (12021): Found 1 design units, including 1 entities, in source file posit_extraction.sv
+    Info (12023): Found entity 1: Data_Extraction File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv Line: 22
+Info (12127): Elaborating entity "Posit_Adder" for the top level hierarchy
+Warning (10036): Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object "LIn" assigned a value but never read File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 46
+Warning (10036): Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(46): object "SIn" assigned a value but never read File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 46
+Warning (10036): Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(47): object "SS" assigned a value but never read File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 47
+Warning (10036): Verilog HDL or VHDL warning at Posit_Adder_Arithmetic.sv(49): object "LRC" assigned a value but never read File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 49
+Warning (10230): Verilog HDL assignment warning at Posit_Adder_Arithmetic.sv(122): truncated value with size 32 to match size of target (8) File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 122
+Warning (10764): Verilog HDL warning at Posit_Adder_Arithmetic.sv(179): converting signed shift amount to unsigned File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 179
+Info (12128): Elaborating entity "Data_Extraction" for hierarchy "Data_Extraction:Extract_IN1" File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Adder_Arithmetic.sv Line: 40
+Info (12128): Elaborating entity "Leading_Bit_Detector" for hierarchy "Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1" File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Adder/Core_Arithmetic/Posit_Extraction.sv Line: 38
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 200 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 8 output pins
+    Info (21061): Implemented 176 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
+    Info: Peak virtual memory: 4837 megabytes
+    Info: Processing ended: Tue Feb 21 16:35:31 2023
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:10
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.summary b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.summary
new file mode 100644
index 0000000000000000000000000000000000000000..dccc4860711c603b0bab573cbdcfa9763491f19d
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Feb 21 16:35:31 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : Posit_Adder
+Top-level Entity Name : Posit_Adder
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 24
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.pin b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.pin
new file mode 100644
index 0000000000000000000000000000000000000000..7e57774b74ac6866dd607f682220e199d4a2b461
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.pin
@@ -0,0 +1,977 @@
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       2.5V
+ --                  Bank 4A:       2.5V
+ --                  Bank 5A:       2.5V
+ --                  Bank 5B:       2.5V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+CHIP  "Posit_Adder"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+IN1[4]                       : AA24      : input  : 2.5 V             :         : 5A        : N              
+IN2[0]                       : AA25      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 2.5V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+IN1[2]                       : AB22      : input  : 2.5 V             :         : 5A        : N              
+IN1[5]                       : AB23      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AB24      : power  :                   : 2.5V    : 5A        :                
+IN2[7]                       : AB25      : input  : 2.5 V             :         : 5A        : N              
+IN1[6]                       : AB26      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+OUT[1]                       : AC27      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30      :        :                   :         : 5B        :                
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+OUT[2]                       : AD26      : output : 2.5 V             :         : 5A        : N              
+IN2[4]                       : AD27      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AD28      : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30      :        :                   :         : 5B        :                
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 2.5V    : 4A        :                
+IN1[0]                       : AE26      : input  : 2.5 V             :         : 5A        : N              
+IN1[7]                       : AE27      : input  : 2.5 V             :         : 5A        : N              
+IN2[3]                       : AE28      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29      :        :                   :         : 5B        :                
+VCCIO5B                      : AE30      : power  :                   : 2.5V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+OUT[6]                       : AF28      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF29      :        :                   :         : 5A        :                
+OUT[5]                       : AF30      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG27      :        :                   :         : 5A        :                
+IN2[5]                       : AG28      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AG29      : power  :                   : 2.5V    : 5A        :                
+OUT[0]                       : AG30      : output : 2.5 V             :         : 5A        : N              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH28      :        :                   :         : 5A        :                
+IN2[2]                       : AH29      : input  : 2.5 V             :         : 5A        : N              
+OUT[3]                       : AH30      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29      :        :                   :         : 5A        :                
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 2.5V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 2.5V    : 5A        :                
+OUT[7]                       : V23       : output : 2.5 V             :         : 5A        : N              
+VCCPD5A                      : V24       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+IN2[1]                       : W21       : input  : 2.5 V             :         : 5A        : N              
+IN1[1]                       : W22       : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : W23       : power  :                   : 2.5V    : 5A        :                
+OUT[4]                       : W24       : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+IN2[6]                       : Y23       : input  : 2.5 V             :         : 5A        : N              
+IN1[3]                       : Y24       : input  : 2.5 V             :         : 5A        : N              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sld b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sld
new file mode 100644
index 0000000000000000000000000000000000000000..f7d3ed7cc6abd95c50005b31855c0eec845cbeed
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof
new file mode 100644
index 0000000000000000000000000000000000000000..127f875a95e8a7a3518d5f9644cb816c359811be
Binary files /dev/null and b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sof differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.rpt b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..8e92ff818205582e6f4b364d45a3f1dfdd467923
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.rpt
@@ -0,0 +1,579 @@
+Timing Analyzer report for Posit_Adder
+Tue Feb 14 19:59:27 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++--------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                        ;
++-----------------------+--------------------------------------------------------+
+; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                                 ;
+; Revision Name         ; Posit_Adder                                            ;
+; Device Family         ; Cyclone V                                              ;
+; Device Name           ; 5CSEMA5F31C6                                           ;
+; Timing Models         ; Final                                                  ;
+; Delay Model           ; Combined                                               ;
+; Rise/Fall Delays      ; Enabled                                                ;
++-----------------------+--------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.15        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.1%      ;
+;     Processor 3            ;   3.1%      ;
+;     Processor 4            ;   3.0%      ;
+;     Processor 5            ;   3.0%      ;
+;     Processor 6            ;   3.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                             ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin    ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; OUT[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[4] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[5] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[6] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[7] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-----------------------------------------------------------+
+; Input Transition Times                                    ;
++--------+--------------+-----------------+-----------------+
+; Pin    ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++--------+--------------+-----------------+-----------------+
+; IN2[7] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[7] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[6] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[6] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[5] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[5] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[4] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[4] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[3] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[3] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[2] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[2] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[1] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[1] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[0] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[0] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++--------+--------------+-----------------+-----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0568 V           ; 0.173 V                              ; 0.113 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0568 V          ; 0.173 V                             ; 0.113 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.0374 V           ; 0.189 V                              ; 0.158 V                              ; 4.66e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.0374 V          ; 0.189 V                             ; 0.158 V                             ; 4.66e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 16    ; 16   ;
+; Unconstrained Input Port Paths  ; 128   ; 128  ;
+; Unconstrained Output Ports      ; 8     ; 8    ;
+; Unconstrained Output Port Paths ; 128   ; 128  ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; IN1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; OUT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; IN1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; OUT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:59:23 2023
+Info: Command: quartus_sta Posit_Adder -c Posit_Adder
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Posit_Adder.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 5169 megabytes
+    Info: Processing ended: Tue Feb 14 19:59:27 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.summary b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.summary
new file mode 100644
index 0000000000000000000000000000000000000000..aa5b327ca51ad51bc2474f1a8c822d1c6b0b3acf
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/output_files/Posit_Adder.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.sft b/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.sft
new file mode 100644
index 0000000000000000000000000000000000000000..9a92a1ec74c2e6108c1769581ffc131af7afc4e6
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.sft
@@ -0,0 +1 @@
+set tool_name "Questa Intel FPGA (Verilog)"
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.vo b/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.vo
new file mode 100644
index 0000000000000000000000000000000000000000..5ebe910cc48bafb6f951cc6d7daecd74d5f0f1d2
--- /dev/null
+++ b/Individual_Project/Posit_Adder/Core_Arithmetic/simulation/questa/Posit_Adder.vo
@@ -0,0 +1,5084 @@
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition"
+
+// DATE "02/14/2023 19:59:29"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for Questa Intel FPGA (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module Posit_Adder (
+	IN1,
+	IN2,
+	OUT);
+input 	[7:0] IN1;
+input 	[7:0] IN2;
+output 	[7:0] OUT;
+
+// Design Ports Information
+// OUT[0]	=>  Location: PIN_AG30,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[1]	=>  Location: PIN_AC27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[2]	=>  Location: PIN_AD26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[3]	=>  Location: PIN_AH30,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[4]	=>  Location: PIN_W24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[5]	=>  Location: PIN_AF30,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[6]	=>  Location: PIN_AF28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[7]	=>  Location: PIN_V23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[7]	=>  Location: PIN_AB25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[7]	=>  Location: PIN_AE27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[6]	=>  Location: PIN_Y23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[6]	=>  Location: PIN_AB26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[5]	=>  Location: PIN_AG28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[5]	=>  Location: PIN_AB23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[4]	=>  Location: PIN_AD27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[4]	=>  Location: PIN_AA24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[3]	=>  Location: PIN_AE28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[3]	=>  Location: PIN_Y24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[2]	=>  Location: PIN_AH29,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[2]	=>  Location: PIN_AB22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[1]	=>  Location: PIN_W21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[1]	=>  Location: PIN_W22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[0]	=>  Location: PIN_AA25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[0]	=>  Location: PIN_AE26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \IN2[7]~input_o ;
+wire \IN2[6]~input_o ;
+wire \IN2[5]~input_o ;
+wire \IN2[4]~input_o ;
+wire \IN2[3]~input_o ;
+wire \IN2[2]~input_o ;
+wire \IN2[1]~input_o ;
+wire \IN2[0]~input_o ;
+wire \Extract_IN2|Add0~26 ;
+wire \Extract_IN2|Add0~22 ;
+wire \Extract_IN2|Add0~18 ;
+wire \Extract_IN2|Add0~14 ;
+wire \Extract_IN2|Add0~10 ;
+wire \Extract_IN2|Add0~6 ;
+wire \Extract_IN2|Add0~1_sumout ;
+wire \IN1[6]~input_o ;
+wire \IN1[7]~input_o ;
+wire \IN1[5]~input_o ;
+wire \IN1[4]~input_o ;
+wire \IN1[3]~input_o ;
+wire \IN1[2]~input_o ;
+wire \IN1[1]~input_o ;
+wire \IN1[0]~input_o ;
+wire \Extract_IN1|Add0~26 ;
+wire \Extract_IN1|Add0~22 ;
+wire \Extract_IN1|Add0~18 ;
+wire \Extract_IN1|Add0~14 ;
+wire \Extract_IN1|Add0~10 ;
+wire \Extract_IN1|Add0~6 ;
+wire \Extract_IN1|Add0~1_sumout ;
+wire \Extract_IN2|Add0~5_sumout ;
+wire \Extract_IN2|Add0~25_sumout ;
+wire \Extract_IN1|Add0~25_sumout ;
+wire \Extract_IN1|Add0~21_sumout ;
+wire \Extract_IN2|Add0~17_sumout ;
+wire \Extract_IN2|Add0~21_sumout ;
+wire \Extract_IN1|Add0~17_sumout ;
+wire \LessThan0~0_combout ;
+wire \Extract_IN1|Add0~13_sumout ;
+wire \Extract_IN2|Add0~13_sumout ;
+wire \Extract_IN2|Add0~9_sumout ;
+wire \Extract_IN1|Add0~9_sumout ;
+wire \LessThan0~1_combout ;
+wire \LessThan0~2_combout ;
+wire \Extract_IN1|Add0~5_sumout ;
+wire \LessThan0~3_combout ;
+wire \LessThan0~4_combout ;
+wire \LessThan0~6_combout ;
+wire \LessThan0~7_combout ;
+wire \LessThan0~5_combout ;
+wire \LessThan0~8_combout ;
+wire \Extract_IN2|RegimeValue[2]~0_combout ;
+wire \Extract_IN1|RegimeValue[2]~0_combout ;
+wire \Extract_IN2|RegimeValue[1]~2_combout ;
+wire \Extract_IN1|RegimeValue[1]~2_combout ;
+wire \Extract_IN1|RegimeValue[1]~1_combout ;
+wire \Extract_IN2|LBD1|EndPosition[0]~0_combout ;
+wire \Extract_IN2|RegimeValue[1]~1_combout ;
+wire \Extract_IN1|Add3~0_combout ;
+wire \Extract_IN1|LBD1|EndPosition[1]~0_combout ;
+wire \Extract_IN1|ShiftLeft0~1_combout ;
+wire \Extract_IN1|LBD1|EndPosition[0]~1_combout ;
+wire \Extract_IN1|ShiftLeft0~0_combout ;
+wire \Extract_IN1|ShiftLeft0~2_combout ;
+wire \Extract_IN2|ShiftLeft0~1_combout ;
+wire \Extract_IN2|ShiftLeft0~2_combout ;
+wire \Extract_IN2|ShiftLeft0~0_combout ;
+wire \Extract_IN2|LBD1|EndPosition[1]~1_combout ;
+wire \Extract_IN2|ShiftLeft0~3_combout ;
+wire \Extract_IN1|ShiftLeft0~5_combout ;
+wire \Extract_IN1|ShiftLeft0~6_combout ;
+wire \Extract_IN2|ShiftLeft0~6_combout ;
+wire \Extract_IN2|ShiftLeft0~7_combout ;
+wire \Extract_IN1|ShiftLeft0~3_combout ;
+wire \Extract_IN1|ShiftLeft0~4_combout ;
+wire \Extract_IN2|ShiftLeft0~4_combout ;
+wire \Extract_IN2|ShiftLeft0~5_combout ;
+wire \ShiftRight0~6_combout ;
+wire \Add0~18_cout ;
+wire \Add0~14 ;
+wire \Add0~10 ;
+wire \Add0~5_sumout ;
+wire \Add0~6 ;
+wire \Add0~1_sumout ;
+wire \LessThan0~10_combout ;
+wire \LessThan0~12_combout ;
+wire \LessThan0~11_combout ;
+wire \LessThan0~13_combout ;
+wire \LessThan0~9_combout ;
+wire \Add1~0_combout ;
+wire \Add1~1_combout ;
+wire \SE[2]~0_combout ;
+wire \Add0~13_sumout ;
+wire \LE[2]~0_combout ;
+wire \Add1~2_combout ;
+wire \ShiftRight0~7_combout ;
+wire \Add0~9_sumout ;
+wire \Add3~26_combout ;
+wire \Extract_IN2|ShiftLeft0~8_combout ;
+wire \Extract_IN1|ShiftLeft0~8_combout ;
+wire \LM[6]~0_combout ;
+wire \Operation~combout ;
+wire \Extract_IN2|ShiftLeft0~9_combout ;
+wire \Extract_IN1|ShiftLeft0~9_combout ;
+wire \Add3~42_combout ;
+wire \ShiftRight0~0_combout ;
+wire \Add3~25_combout ;
+wire \Extract_IN2|ShiftLeft0~10_combout ;
+wire \Extract_IN1|ShiftLeft0~10_combout ;
+wire \Add1~4_combout ;
+wire \Extract_IN1|ShiftLeft0~12_combout ;
+wire \ShiftRight0~5_combout ;
+wire \ShiftRight0~4_combout ;
+wire \Add1~3_combout ;
+wire \Add3~46_combout ;
+wire \ShiftRight0~2_combout ;
+wire \ShiftRight0~1_combout ;
+wire \ShiftRight0~3_combout ;
+wire \Add3~20_combout ;
+wire \Extract_IN1|ShiftLeft0~7_combout ;
+wire \Extract_IN1|ShiftLeft0~11_combout ;
+wire \ShiftRight0~8_combout ;
+wire \Add3~27_combout ;
+wire \Add3~28_combout ;
+wire \Add3~33_combout ;
+wire \Add3~34_combout ;
+wire \Add3~35_combout ;
+wire \ShiftRight0~9_combout ;
+wire \ShiftRight0~10_combout ;
+wire \Add3~40_combout ;
+wire \Add3~41_combout ;
+wire \Add3~38_cout ;
+wire \Add3~31_cout ;
+wire \Add3~23 ;
+wire \Add3~2 ;
+wire \Add3~6 ;
+wire \Add3~10 ;
+wire \Add3~14 ;
+wire \Add3~17_sumout ;
+wire \Add5~18 ;
+wire \Add5~22 ;
+wire \Add5~14 ;
+wire \Add5~10 ;
+wire \Add5~26 ;
+wire \Add5~6 ;
+wire \Add5~1_sumout ;
+wire \Add5~9_sumout ;
+wire \Add5~5_sumout ;
+wire \Add5~25_sumout ;
+wire \LessThan1~0_combout ;
+wire \LS~0_combout ;
+wire \Add5~13_sumout ;
+wire \Add5~21_sumout ;
+wire \Add5~17_sumout ;
+wire \Add6~0_combout ;
+wire \R_O[3]~0_combout ;
+wire \R_O[2]~1_combout ;
+wire \R_O[0]~2_combout ;
+wire \ShiftRight1~0_combout ;
+wire \Add3~5_sumout ;
+wire \Add3~9_sumout ;
+wire \Add_Mant[6]~0_combout ;
+wire \ShiftRight1~2_combout ;
+wire \Add3~13_sumout ;
+wire \Add3~1_sumout ;
+wire \R_O[1]~3_combout ;
+wire \ShiftRight1~1_combout ;
+wire \ShiftRight1~3_combout ;
+wire \ShiftRight1~4_combout ;
+wire \Add3~22_sumout ;
+wire \Add_Mant[4]~2_combout ;
+wire \ShiftRight1~15_combout ;
+wire \ShiftRight1~11_combout ;
+wire \ShiftRight1~16_combout ;
+wire \ulp~3_combout ;
+wire \ulp~2_combout ;
+wire \ulp~4_combout ;
+wire \ulp~7_combout ;
+wire \ulp~0_combout ;
+wire \ulp~5_combout ;
+wire \Add_Mant[7]~1_combout ;
+wire \ShiftRight1~8_combout ;
+wire \ShiftRight1~5_combout ;
+wire \ulp~1_combout ;
+wire \ulp~6_combout ;
+wire \Add8~30 ;
+wire \Add8~1_sumout ;
+wire \Add8~29_sumout ;
+wire \sft_tmp_o_rnd[0]~0_combout ;
+wire \Add9~1_sumout ;
+wire \sft_tmp_oN~0_combout ;
+wire \ShiftRight1~6_combout ;
+wire \ShiftRight1~7_combout ;
+wire \Add8~2 ;
+wire \Add8~5_sumout ;
+wire \Add9~2 ;
+wire \Add9~5_sumout ;
+wire \sft_tmp_oN~1_combout ;
+wire \ShiftRight1~9_combout ;
+wire \ShiftRight1~10_combout ;
+wire \ShiftRight1~17_combout ;
+wire \ShiftRight1~18_combout ;
+wire \Add8~6 ;
+wire \Add8~9_sumout ;
+wire \Add9~6 ;
+wire \Add9~9_sumout ;
+wire \sft_tmp_oN~2_combout ;
+wire \Add8~10 ;
+wire \Add8~13_sumout ;
+wire \ShiftRight1~19_combout ;
+wire \Add9~10 ;
+wire \Add9~13_sumout ;
+wire \sft_tmp_oN~3_combout ;
+wire \ShiftRight1~12_combout ;
+wire \Add8~14 ;
+wire \Add8~17_sumout ;
+wire \Add9~14 ;
+wire \Add9~17_sumout ;
+wire \sft_tmp_oN~4_combout ;
+wire \Add8~18 ;
+wire \Add8~21_sumout ;
+wire \ShiftRight1~13_combout ;
+wire \Add9~18 ;
+wire \Add9~21_sumout ;
+wire \sft_tmp_oN~5_combout ;
+wire \ShiftRight1~14_combout ;
+wire \Add8~22 ;
+wire \Add8~25_sumout ;
+wire \Add9~22 ;
+wire \Add9~25_sumout ;
+wire \sft_tmp_oN~6_combout ;
+
+
+// Location: IOOBUF_X89_Y16_N56
+cyclonev_io_obuf \OUT[0]~output (
+	.i(\sft_tmp_oN~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[0]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[0]~output .bus_hold = "false";
+defparam \OUT[0]~output .open_drain_output = "false";
+defparam \OUT[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N22
+cyclonev_io_obuf \OUT[1]~output (
+	.i(\sft_tmp_oN~1_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[1]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[1]~output .bus_hold = "false";
+defparam \OUT[1]~output .open_drain_output = "false";
+defparam \OUT[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N5
+cyclonev_io_obuf \OUT[2]~output (
+	.i(\sft_tmp_oN~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[2]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[2]~output .bus_hold = "false";
+defparam \OUT[2]~output .open_drain_output = "false";
+defparam \OUT[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N39
+cyclonev_io_obuf \OUT[3]~output (
+	.i(\sft_tmp_oN~3_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[3]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[3]~output .bus_hold = "false";
+defparam \OUT[3]~output .open_drain_output = "false";
+defparam \OUT[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N22
+cyclonev_io_obuf \OUT[4]~output (
+	.i(\sft_tmp_oN~4_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[4]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[4]~output .bus_hold = "false";
+defparam \OUT[4]~output .open_drain_output = "false";
+defparam \OUT[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N56
+cyclonev_io_obuf \OUT[5]~output (
+	.i(\sft_tmp_oN~5_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[5]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[5]~output .bus_hold = "false";
+defparam \OUT[5]~output .open_drain_output = "false";
+defparam \OUT[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N56
+cyclonev_io_obuf \OUT[6]~output (
+	.i(\sft_tmp_oN~6_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[6]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[6]~output .bus_hold = "false";
+defparam \OUT[6]~output .open_drain_output = "false";
+defparam \OUT[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N5
+cyclonev_io_obuf \OUT[7]~output (
+	.i(\LS~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[7]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[7]~output .bus_hold = "false";
+defparam \OUT[7]~output .open_drain_output = "false";
+defparam \OUT[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y11_N61
+cyclonev_io_ibuf \IN2[7]~input (
+	.i(IN2[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[7]~input_o ));
+// synopsys translate_off
+defparam \IN2[7]~input .bus_hold = "false";
+defparam \IN2[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N4
+cyclonev_io_ibuf \IN2[6]~input (
+	.i(IN2[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[6]~input_o ));
+// synopsys translate_off
+defparam \IN2[6]~input .bus_hold = "false";
+defparam \IN2[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N38
+cyclonev_io_ibuf \IN2[5]~input (
+	.i(IN2[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[5]~input_o ));
+// synopsys translate_off
+defparam \IN2[5]~input .bus_hold = "false";
+defparam \IN2[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N55
+cyclonev_io_ibuf \IN2[4]~input (
+	.i(IN2[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[4]~input_o ));
+// synopsys translate_off
+defparam \IN2[4]~input .bus_hold = "false";
+defparam \IN2[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y11_N95
+cyclonev_io_ibuf \IN2[3]~input (
+	.i(IN2[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[3]~input_o ));
+// synopsys translate_off
+defparam \IN2[3]~input .bus_hold = "false";
+defparam \IN2[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y6_N55
+cyclonev_io_ibuf \IN2[2]~input (
+	.i(IN2[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[2]~input_o ));
+// synopsys translate_off
+defparam \IN2[2]~input .bus_hold = "false";
+defparam \IN2[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N4
+cyclonev_io_ibuf \IN2[1]~input (
+	.i(IN2[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[1]~input_o ));
+// synopsys translate_off
+defparam \IN2[1]~input .bus_hold = "false";
+defparam \IN2[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N38
+cyclonev_io_ibuf \IN2[0]~input (
+	.i(IN2[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[0]~input_o ));
+// synopsys translate_off
+defparam \IN2[0]~input .bus_hold = "false";
+defparam \IN2[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N0
+cyclonev_lcell_comb \Extract_IN2|Add0~25 (
+// Equation(s):
+// \Extract_IN2|Add0~25_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[0]~input_o ) ) + ( \IN2[7]~input_o  ) + ( !VCC ))
+// \Extract_IN2|Add0~26  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[0]~input_o ) ) + ( \IN2[7]~input_o  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(gnd),
+	.datad(!\IN2[0]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~25_sumout ),
+	.cout(\Extract_IN2|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~25 .extended_lut = "off";
+defparam \Extract_IN2|Add0~25 .lut_mask = 64'h0000CCCC000033CC;
+defparam \Extract_IN2|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N3
+cyclonev_lcell_comb \Extract_IN2|Add0~21 (
+// Equation(s):
+// \Extract_IN2|Add0~21_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[1]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~26  ))
+// \Extract_IN2|Add0~22  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[1]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(!\IN2[1]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~21_sumout ),
+	.cout(\Extract_IN2|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~21 .extended_lut = "off";
+defparam \Extract_IN2|Add0~21 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Extract_IN2|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N6
+cyclonev_lcell_comb \Extract_IN2|Add0~17 (
+// Equation(s):
+// \Extract_IN2|Add0~17_sumout  = SUM(( GND ) + ( !\IN2[7]~input_o  $ (!\IN2[2]~input_o ) ) + ( \Extract_IN2|Add0~22  ))
+// \Extract_IN2|Add0~18  = CARRY(( GND ) + ( !\IN2[7]~input_o  $ (!\IN2[2]~input_o ) ) + ( \Extract_IN2|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN2[2]~input_o ),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~17_sumout ),
+	.cout(\Extract_IN2|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~17 .extended_lut = "off";
+defparam \Extract_IN2|Add0~17 .lut_mask = 64'h0000CC3300000000;
+defparam \Extract_IN2|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N9
+cyclonev_lcell_comb \Extract_IN2|Add0~13 (
+// Equation(s):
+// \Extract_IN2|Add0~13_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[3]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~18  ))
+// \Extract_IN2|Add0~14  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[3]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(gnd),
+	.datad(!\IN2[3]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~13_sumout ),
+	.cout(\Extract_IN2|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~13 .extended_lut = "off";
+defparam \Extract_IN2|Add0~13 .lut_mask = 64'h0000FFFF000033CC;
+defparam \Extract_IN2|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N12
+cyclonev_lcell_comb \Extract_IN2|Add0~9 (
+// Equation(s):
+// \Extract_IN2|Add0~9_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[4]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~14  ))
+// \Extract_IN2|Add0~10  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[4]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(gnd),
+	.datad(!\IN2[4]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~9_sumout ),
+	.cout(\Extract_IN2|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~9 .extended_lut = "off";
+defparam \Extract_IN2|Add0~9 .lut_mask = 64'h0000FFFF000033CC;
+defparam \Extract_IN2|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N15
+cyclonev_lcell_comb \Extract_IN2|Add0~5 (
+// Equation(s):
+// \Extract_IN2|Add0~5_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[5]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~10  ))
+// \Extract_IN2|Add0~6  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[5]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(!\IN2[5]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~5_sumout ),
+	.cout(\Extract_IN2|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~5 .extended_lut = "off";
+defparam \Extract_IN2|Add0~5 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Extract_IN2|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N18
+cyclonev_lcell_comb \Extract_IN2|Add0~1 (
+// Equation(s):
+// \Extract_IN2|Add0~1_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[6]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(!\IN2[7]~input_o ),
+	.datac(!\IN2[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~1 .extended_lut = "off";
+defparam \Extract_IN2|Add0~1 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Extract_IN2|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N55
+cyclonev_io_ibuf \IN1[6]~input (
+	.i(IN1[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[6]~input_o ));
+// synopsys translate_off
+defparam \IN1[6]~input .bus_hold = "false";
+defparam \IN1[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y11_N78
+cyclonev_io_ibuf \IN1[7]~input (
+	.i(IN1[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[7]~input_o ));
+// synopsys translate_off
+defparam \IN1[7]~input .bus_hold = "false";
+defparam \IN1[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N21
+cyclonev_io_ibuf \IN1[5]~input (
+	.i(IN1[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[5]~input_o ));
+// synopsys translate_off
+defparam \IN1[5]~input .bus_hold = "false";
+defparam \IN1[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y11_N44
+cyclonev_io_ibuf \IN1[4]~input (
+	.i(IN1[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[4]~input_o ));
+// synopsys translate_off
+defparam \IN1[4]~input .bus_hold = "false";
+defparam \IN1[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N21
+cyclonev_io_ibuf \IN1[3]~input (
+	.i(IN1[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[3]~input_o ));
+// synopsys translate_off
+defparam \IN1[3]~input .bus_hold = "false";
+defparam \IN1[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N4
+cyclonev_io_ibuf \IN1[2]~input (
+	.i(IN1[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[2]~input_o ));
+// synopsys translate_off
+defparam \IN1[2]~input .bus_hold = "false";
+defparam \IN1[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N21
+cyclonev_io_ibuf \IN1[1]~input (
+	.i(IN1[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[1]~input_o ));
+// synopsys translate_off
+defparam \IN1[1]~input .bus_hold = "false";
+defparam \IN1[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N38
+cyclonev_io_ibuf \IN1[0]~input (
+	.i(IN1[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[0]~input_o ));
+// synopsys translate_off
+defparam \IN1[0]~input .bus_hold = "false";
+defparam \IN1[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N30
+cyclonev_lcell_comb \Extract_IN1|Add0~25 (
+// Equation(s):
+// \Extract_IN1|Add0~25_sumout  = SUM(( \IN1[7]~input_o  ) + ( !\IN1[7]~input_o  $ (!\IN1[0]~input_o ) ) + ( !VCC ))
+// \Extract_IN1|Add0~26  = CARRY(( \IN1[7]~input_o  ) + ( !\IN1[7]~input_o  $ (!\IN1[0]~input_o ) ) + ( !VCC ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[0]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~25_sumout ),
+	.cout(\Extract_IN1|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~25 .extended_lut = "off";
+defparam \Extract_IN1|Add0~25 .lut_mask = 64'h0000AA5500005555;
+defparam \Extract_IN1|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N33
+cyclonev_lcell_comb \Extract_IN1|Add0~21 (
+// Equation(s):
+// \Extract_IN1|Add0~21_sumout  = SUM(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[1]~input_o ) ) + ( \Extract_IN1|Add0~26  ))
+// \Extract_IN1|Add0~22  = CARRY(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[1]~input_o ) ) + ( \Extract_IN1|Add0~26  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[1]~input_o ),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~21_sumout ),
+	.cout(\Extract_IN1|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~21 .extended_lut = "off";
+defparam \Extract_IN1|Add0~21 .lut_mask = 64'h0000AA5500000000;
+defparam \Extract_IN1|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N36
+cyclonev_lcell_comb \Extract_IN1|Add0~17 (
+// Equation(s):
+// \Extract_IN1|Add0~17_sumout  = SUM(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[2]~input_o ) ) + ( \Extract_IN1|Add0~22  ))
+// \Extract_IN1|Add0~18  = CARRY(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[2]~input_o ) ) + ( \Extract_IN1|Add0~22  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[2]~input_o ),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~17_sumout ),
+	.cout(\Extract_IN1|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~17 .extended_lut = "off";
+defparam \Extract_IN1|Add0~17 .lut_mask = 64'h0000AA5500000000;
+defparam \Extract_IN1|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N39
+cyclonev_lcell_comb \Extract_IN1|Add0~13 (
+// Equation(s):
+// \Extract_IN1|Add0~13_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[3]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~18  ))
+// \Extract_IN1|Add0~14  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[3]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~18  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN1[3]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~13_sumout ),
+	.cout(\Extract_IN1|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~13 .extended_lut = "off";
+defparam \Extract_IN1|Add0~13 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Extract_IN1|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N42
+cyclonev_lcell_comb \Extract_IN1|Add0~9 (
+// Equation(s):
+// \Extract_IN1|Add0~9_sumout  = SUM(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[4]~input_o ) ) + ( \Extract_IN1|Add0~14  ))
+// \Extract_IN1|Add0~10  = CARRY(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[4]~input_o ) ) + ( \Extract_IN1|Add0~14  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[4]~input_o ),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~9_sumout ),
+	.cout(\Extract_IN1|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~9 .extended_lut = "off";
+defparam \Extract_IN1|Add0~9 .lut_mask = 64'h0000AA5500000000;
+defparam \Extract_IN1|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N45
+cyclonev_lcell_comb \Extract_IN1|Add0~5 (
+// Equation(s):
+// \Extract_IN1|Add0~5_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[5]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~10  ))
+// \Extract_IN1|Add0~6  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[5]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~10  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN1[5]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~5_sumout ),
+	.cout(\Extract_IN1|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~5 .extended_lut = "off";
+defparam \Extract_IN1|Add0~5 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN1|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N48
+cyclonev_lcell_comb \Extract_IN1|Add0~1 (
+// Equation(s):
+// \Extract_IN1|Add0~1_sumout  = SUM(( !\IN1[6]~input_o  $ (!\IN1[7]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(!\IN1[6]~input_o ),
+	.datac(!\IN1[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~1 .extended_lut = "off";
+defparam \Extract_IN1|Add0~1 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Extract_IN1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N0
+cyclonev_lcell_comb \LessThan0~0 (
+// Equation(s):
+// \LessThan0~0_combout  = ( \Extract_IN2|Add0~21_sumout  & ( \Extract_IN1|Add0~17_sumout  & ( (!\Extract_IN2|Add0~25_sumout  & (\Extract_IN1|Add0~25_sumout  & \Extract_IN1|Add0~21_sumout )) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( 
+// \Extract_IN1|Add0~17_sumout  & ( ((!\Extract_IN2|Add0~25_sumout  & \Extract_IN1|Add0~25_sumout )) # (\Extract_IN1|Add0~21_sumout ) ) ) ) # ( \Extract_IN2|Add0~21_sumout  & ( !\Extract_IN1|Add0~17_sumout  & ( (!\Extract_IN2|Add0~25_sumout  & 
+// (\Extract_IN1|Add0~25_sumout  & (\Extract_IN1|Add0~21_sumout  & !\Extract_IN2|Add0~17_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( !\Extract_IN1|Add0~17_sumout  & ( (!\Extract_IN2|Add0~17_sumout  & (((!\Extract_IN2|Add0~25_sumout  & 
+// \Extract_IN1|Add0~25_sumout )) # (\Extract_IN1|Add0~21_sumout ))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~25_sumout ),
+	.datab(!\Extract_IN1|Add0~25_sumout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(!\Extract_IN2|Add0~17_sumout ),
+	.datae(!\Extract_IN2|Add0~21_sumout ),
+	.dataf(!\Extract_IN1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~0 .extended_lut = "off";
+defparam \LessThan0~0 .lut_mask = 64'h2F0002002F2F0202;
+defparam \LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N39
+cyclonev_lcell_comb \LessThan0~1 (
+// Equation(s):
+// \LessThan0~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN2|Add0~17_sumout  ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~1 .extended_lut = "off";
+defparam \LessThan0~1 .lut_mask = 64'h00000000AAAAAAAA;
+defparam \LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N12
+cyclonev_lcell_comb \LessThan0~2 (
+// Equation(s):
+// \LessThan0~2_combout  = ( \Extract_IN1|Add0~9_sumout  & ( \LessThan0~1_combout  & ( (!\Extract_IN1|Add0~13_sumout  & (\Extract_IN2|Add0~13_sumout  & \Extract_IN2|Add0~9_sumout )) ) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( \LessThan0~1_combout  & ( 
+// ((!\Extract_IN1|Add0~13_sumout  & \Extract_IN2|Add0~13_sumout )) # (\Extract_IN2|Add0~9_sumout ) ) ) ) # ( \Extract_IN1|Add0~9_sumout  & ( !\LessThan0~1_combout  & ( (\Extract_IN2|Add0~9_sumout  & ((!\LessThan0~0_combout  & ((!\Extract_IN1|Add0~13_sumout 
+// ) # (\Extract_IN2|Add0~13_sumout ))) # (\LessThan0~0_combout  & (!\Extract_IN1|Add0~13_sumout  & \Extract_IN2|Add0~13_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( !\LessThan0~1_combout  & ( ((!\LessThan0~0_combout  & 
+// ((!\Extract_IN1|Add0~13_sumout ) # (\Extract_IN2|Add0~13_sumout ))) # (\LessThan0~0_combout  & (!\Extract_IN1|Add0~13_sumout  & \Extract_IN2|Add0~13_sumout ))) # (\Extract_IN2|Add0~9_sumout ) ) ) )
+
+	.dataa(!\LessThan0~0_combout ),
+	.datab(!\Extract_IN1|Add0~13_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(!\Extract_IN2|Add0~9_sumout ),
+	.datae(!\Extract_IN1|Add0~9_sumout ),
+	.dataf(!\LessThan0~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~2 .extended_lut = "off";
+defparam \LessThan0~2 .lut_mask = 64'h8EFF008E0CFF000C;
+defparam \LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N21
+cyclonev_lcell_comb \LessThan0~3 (
+// Equation(s):
+// \LessThan0~3_combout  = ( \Extract_IN1|Add0~1_sumout  & ( (!\Extract_IN2|Add0~1_sumout ) # ((!\Extract_IN2|Add0~5_sumout  & ((!\LessThan0~2_combout ) # (\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN2|Add0~5_sumout  & (!\LessThan0~2_combout  & 
+// \Extract_IN1|Add0~5_sumout ))) ) ) # ( !\Extract_IN1|Add0~1_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~5_sumout  & ((!\LessThan0~2_combout ) # (\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN2|Add0~5_sumout  & (!\LessThan0~2_combout  & 
+// \Extract_IN1|Add0~5_sumout )))) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\LessThan0~2_combout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~3 .extended_lut = "off";
+defparam \LessThan0~3 .lut_mask = 64'h80C880C8ECFEECFE;
+defparam \LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N3
+cyclonev_lcell_comb \LessThan0~4 (
+// Equation(s):
+// \LessThan0~4_combout  = (\Extract_IN1|Add0~1_sumout  & !\Extract_IN2|Add0~1_sumout )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~4 .extended_lut = "off";
+defparam \LessThan0~4 .lut_mask = 64'h5050505050505050;
+defparam \LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N30
+cyclonev_lcell_comb \LessThan0~6 (
+// Equation(s):
+// \LessThan0~6_combout  = ( \Extract_IN1|Add0~21_sumout  & ( (!\Extract_IN2|Add0~21_sumout ) # ((\Extract_IN1|Add0~25_sumout  & !\Extract_IN2|Add0~25_sumout )) ) ) # ( !\Extract_IN1|Add0~21_sumout  & ( (\Extract_IN1|Add0~25_sumout  & 
+// (!\Extract_IN2|Add0~21_sumout  & !\Extract_IN2|Add0~25_sumout )) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add0~25_sumout ),
+	.datac(!\Extract_IN2|Add0~21_sumout ),
+	.datad(!\Extract_IN2|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~6 .extended_lut = "off";
+defparam \LessThan0~6 .lut_mask = 64'h30003000F3F0F3F0;
+defparam \LessThan0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N6
+cyclonev_lcell_comb \LessThan0~7 (
+// Equation(s):
+// \LessThan0~7_combout  = ( \LessThan0~6_combout  & ( (!\Extract_IN2|Add0~13_sumout  & (((!\Extract_IN2|Add0~17_sumout ) # (\Extract_IN1|Add0~17_sumout )) # (\Extract_IN1|Add0~13_sumout ))) # (\Extract_IN2|Add0~13_sumout  & (\Extract_IN1|Add0~13_sumout  & 
+// ((!\Extract_IN2|Add0~17_sumout ) # (\Extract_IN1|Add0~17_sumout )))) ) ) # ( !\LessThan0~6_combout  & ( (!\Extract_IN2|Add0~13_sumout  & (((\Extract_IN1|Add0~17_sumout  & !\Extract_IN2|Add0~17_sumout )) # (\Extract_IN1|Add0~13_sumout ))) # 
+// (\Extract_IN2|Add0~13_sumout  & (\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~17_sumout  & !\Extract_IN2|Add0~17_sumout ))) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN1|Add0~13_sumout ),
+	.datac(!\Extract_IN1|Add0~17_sumout ),
+	.datad(!\Extract_IN2|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~7 .extended_lut = "off";
+defparam \LessThan0~7 .lut_mask = 64'h2B222B22BB2BBB2B;
+defparam \LessThan0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N27
+cyclonev_lcell_comb \LessThan0~5 (
+// Equation(s):
+// \LessThan0~5_combout  = ( \Extract_IN1|Add0~1_sumout  & ( !\Extract_IN2|Add0~1_sumout  ) ) # ( !\Extract_IN1|Add0~1_sumout  & ( \Extract_IN2|Add0~1_sumout  ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~5 .extended_lut = "off";
+defparam \LessThan0~5 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N42
+cyclonev_lcell_comb \LessThan0~8 (
+// Equation(s):
+// \LessThan0~8_combout  = ( \Extract_IN1|Add0~5_sumout  & ( !\LessThan0~5_combout  & ( (!\Extract_IN2|Add0~5_sumout ) # ((!\Extract_IN2|Add0~9_sumout  & ((\Extract_IN1|Add0~9_sumout ) # (\LessThan0~7_combout ))) # (\Extract_IN2|Add0~9_sumout  & 
+// (\LessThan0~7_combout  & \Extract_IN1|Add0~9_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~5_sumout  & ( !\LessThan0~5_combout  & ( (!\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~9_sumout  & ((\Extract_IN1|Add0~9_sumout ) # (\LessThan0~7_combout ))) # 
+// (\Extract_IN2|Add0~9_sumout  & (\LessThan0~7_combout  & \Extract_IN1|Add0~9_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\LessThan0~7_combout ),
+	.datad(!\Extract_IN1|Add0~9_sumout ),
+	.datae(!\Extract_IN1|Add0~5_sumout ),
+	.dataf(!\LessThan0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~8 .extended_lut = "off";
+defparam \LessThan0~8 .lut_mask = 64'h088AAEEF00000000;
+defparam \LessThan0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N51
+cyclonev_lcell_comb \Extract_IN2|RegimeValue[2]~0 (
+// Equation(s):
+// \Extract_IN2|RegimeValue[2]~0_combout  = ( \Extract_IN2|Add0~1_sumout  & ( (\Extract_IN2|Add0~17_sumout  & (\Extract_IN2|Add0~9_sumout  & (\Extract_IN2|Add0~13_sumout  & \Extract_IN2|Add0~5_sumout ))) ) ) # ( !\Extract_IN2|Add0~1_sumout  & ( 
+// (((\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~13_sumout )) # (\Extract_IN2|Add0~9_sumout )) # (\Extract_IN2|Add0~17_sumout ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(!\Extract_IN2|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|RegimeValue[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|RegimeValue[2]~0 .extended_lut = "off";
+defparam \Extract_IN2|RegimeValue[2]~0 .lut_mask = 64'h7FFF7FFF00010001;
+defparam \Extract_IN2|RegimeValue[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N3
+cyclonev_lcell_comb \Extract_IN1|RegimeValue[2]~0 (
+// Equation(s):
+// \Extract_IN1|RegimeValue[2]~0_combout  = ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout ) # ((\Extract_IN1|Add0~5_sumout  & (\Extract_IN1|Add0~17_sumout  & \Extract_IN1|Add0~9_sumout ))) ) ) # ( !\Extract_IN1|Add0~13_sumout  & ( 
+// (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~9_sumout ) # (\Extract_IN1|Add0~17_sumout )) # (\Extract_IN1|Add0~5_sumout ))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(!\Extract_IN1|Add0~17_sumout ),
+	.datad(!\Extract_IN1|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|RegimeValue[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|RegimeValue[2]~0 .extended_lut = "off";
+defparam \Extract_IN1|RegimeValue[2]~0 .lut_mask = 64'h2AAA2AAAAAABAAAB;
+defparam \Extract_IN1|RegimeValue[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N48
+cyclonev_lcell_comb \Extract_IN2|RegimeValue[1]~2 (
+// Equation(s):
+// \Extract_IN2|RegimeValue[1]~2_combout  = ( \Extract_IN2|Add0~1_sumout  & ( (\Extract_IN2|Add0~9_sumout  & (\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~17_sumout ) # (!\Extract_IN2|Add0~13_sumout )))) ) ) # ( !\Extract_IN2|Add0~1_sumout  & ( 
+// (((!\Extract_IN2|Add0~17_sumout  & !\Extract_IN2|Add0~13_sumout )) # (\Extract_IN2|Add0~5_sumout )) # (\Extract_IN2|Add0~9_sumout ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(!\Extract_IN2|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|RegimeValue[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|RegimeValue[1]~2 .extended_lut = "off";
+defparam \Extract_IN2|RegimeValue[1]~2 .lut_mask = 64'hB3FFB3FF00320032;
+defparam \Extract_IN2|RegimeValue[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N18
+cyclonev_lcell_comb \Extract_IN1|RegimeValue[1]~2 (
+// Equation(s):
+// \Extract_IN1|RegimeValue[1]~2_combout  = ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~9_sumout )) # (\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~5_sumout  & 
+// (!\Extract_IN1|Add0~17_sumout  & \Extract_IN1|Add0~9_sumout ))) ) ) # ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((!\Extract_IN1|Add0~17_sumout ) # (\Extract_IN1|Add0~9_sumout )) # (\Extract_IN1|Add0~5_sumout ))) # 
+// (\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~5_sumout  & ((\Extract_IN1|Add0~9_sumout )))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(!\Extract_IN1|Add0~17_sumout ),
+	.datad(!\Extract_IN1|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|RegimeValue[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|RegimeValue[1]~2 .extended_lut = "off";
+defparam \Extract_IN1|RegimeValue[1]~2 .lut_mask = 64'hA2BBA2BB22BA22BA;
+defparam \Extract_IN1|RegimeValue[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N6
+cyclonev_lcell_comb \Extract_IN1|RegimeValue[1]~1 (
+// Equation(s):
+// \Extract_IN1|RegimeValue[1]~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~9_sumout  & (((!\Extract_IN1|Add0~1_sumout ) # (\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~9_sumout  & 
+// (\Extract_IN1|Add0~5_sumout  & ((!\Extract_IN1|Add0~1_sumout ) # (\Extract_IN1|Add0~21_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( ((!\Extract_IN1|Add0~9_sumout  & !\Extract_IN1|Add0~1_sumout )) # 
+// (\Extract_IN1|Add0~5_sumout ) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (\Extract_IN1|Add0~5_sumout  & ((!\Extract_IN1|Add0~9_sumout ) # (!\Extract_IN1|Add0~1_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( 
+// !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~9_sumout  & (((\Extract_IN1|Add0~21_sumout  & !\Extract_IN1|Add0~1_sumout )) # (\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~9_sumout  & (((!\Extract_IN1|Add0~1_sumout  & 
+// \Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|RegimeValue[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|RegimeValue[1]~1 .extended_lut = "off";
+defparam \Extract_IN1|RegimeValue[1]~1 .lut_mask = 64'h40FC00FCC0FFC0FD;
+defparam \Extract_IN1|RegimeValue[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N54
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[0]~0 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[0]~0_combout  = ( \Extract_IN2|Add0~21_sumout  & ( \Extract_IN2|Add0~5_sumout  & ( (!\Extract_IN2|Add0~1_sumout ) # ((!\Extract_IN2|Add0~13_sumout  & \Extract_IN2|Add0~9_sumout )) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( 
+// \Extract_IN2|Add0~5_sumout  & ( (!\Extract_IN2|Add0~1_sumout ) # ((\Extract_IN2|Add0~9_sumout  & ((!\Extract_IN2|Add0~13_sumout ) # (\Extract_IN2|Add0~17_sumout )))) ) ) ) # ( \Extract_IN2|Add0~21_sumout  & ( !\Extract_IN2|Add0~5_sumout  & ( 
+// ((!\Extract_IN2|Add0~9_sumout  & ((!\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~13_sumout )))) # (\Extract_IN2|Add0~1_sumout ) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( !\Extract_IN2|Add0~5_sumout  & ( ((\Extract_IN2|Add0~13_sumout  & 
+// !\Extract_IN2|Add0~9_sumout )) # (\Extract_IN2|Add0~1_sumout ) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~13_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(!\Extract_IN2|Add0~9_sumout ),
+	.datae(!\Extract_IN2|Add0~21_sumout ),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[0]~0 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[0]~0 .lut_mask = 64'h3F0FBF0FF0FDF0FC;
+defparam \Extract_IN2|LBD1|EndPosition[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N15
+cyclonev_lcell_comb \Extract_IN2|RegimeValue[1]~1 (
+// Equation(s):
+// \Extract_IN2|RegimeValue[1]~1_combout  = ( \Extract_IN2|LBD1|EndPosition[0]~0_combout  & ( !\Extract_IN2|Add0~1_sumout  ) ) # ( !\Extract_IN2|LBD1|EndPosition[0]~0_combout  & ( \Extract_IN2|Add0~1_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|RegimeValue[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|RegimeValue[1]~1 .extended_lut = "off";
+defparam \Extract_IN2|RegimeValue[1]~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \Extract_IN2|RegimeValue[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N0
+cyclonev_lcell_comb \Extract_IN1|Add3~0 (
+// Equation(s):
+// \Extract_IN1|Add3~0_combout  = ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~1_sumout ) # (!\Extract_IN1|Add0~5_sumout ) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( (\Extract_IN1|Add0~5_sumout ) # (\Extract_IN1|Add0~1_sumout ) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|Add3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add3~0 .extended_lut = "off";
+defparam \Extract_IN1|Add3~0 .lut_mask = 64'h55FF55FFFFAAFFAA;
+defparam \Extract_IN1|Add3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N6
+cyclonev_lcell_comb \Extract_IN1|LBD1|EndPosition[1]~0 (
+// Equation(s):
+// \Extract_IN1|LBD1|EndPosition[1]~0_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((!\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~5_sumout  & 
+// ((!\Extract_IN1|Add0~9_sumout ) # (\Extract_IN1|Add0~21_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~1_sumout  & 
+// (!\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~5_sumout )) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~9_sumout  & !\Extract_IN1|Add0~5_sumout )) # 
+// (\Extract_IN1|Add0~1_sumout  & ((\Extract_IN1|Add0~5_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (!\Extract_IN1|Add0~5_sumout  & ((!\Extract_IN1|Add0~21_sumout ) # 
+// (\Extract_IN1|Add0~9_sumout )))) # (\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .lut_mask = 64'hB00F300FF00CF00D;
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N18
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~1 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~9_sumout  & (!\Extract_IN1|Add0~1_sumout  & !\Extract_IN1|Add0~5_sumout )) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( 
+// \Extract_IN1|Add0~13_sumout  & ( (\Extract_IN1|Add0~21_sumout  & (\Extract_IN1|Add0~9_sumout  & (\Extract_IN1|Add0~1_sumout  & \Extract_IN1|Add0~5_sumout ))) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( 
+// (!\Extract_IN1|Add0~9_sumout  & (\Extract_IN1|Add0~21_sumout  & (!\Extract_IN1|Add0~1_sumout  & !\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~9_sumout  & (((\Extract_IN1|Add0~1_sumout  & \Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~1 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~1 .lut_mask = 64'h000040030001C000;
+defparam \Extract_IN1|ShiftLeft0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N42
+cyclonev_lcell_comb \Extract_IN1|LBD1|EndPosition[0]~1 (
+// Equation(s):
+// \Extract_IN1|LBD1|EndPosition[0]~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~9_sumout  & !\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~1_sumout  & 
+// (\Extract_IN1|Add0~5_sumout  & ((!\Extract_IN1|Add0~9_sumout ) # (\Extract_IN1|Add0~21_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~9_sumout  & 
+// !\Extract_IN1|Add0~5_sumout )) # (\Extract_IN1|Add0~1_sumout  & ((\Extract_IN1|Add0~5_sumout ))) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~5_sumout ))) # 
+// (\Extract_IN1|Add0~1_sumout  & (!\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~5_sumout )) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (!\Extract_IN1|Add0~5_sumout  & 
+// ((!\Extract_IN1|Add0~21_sumout ) # (\Extract_IN1|Add0~9_sumout )))) # (\Extract_IN1|Add0~1_sumout  & (((!\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .lut_mask = 64'hB00CF00C300F300D;
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N0
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~0 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~0_combout  = ( \Extract_IN1|Add0~13_sumout  & ( ((\Extract_IN1|Add0~1_sumout  & \Extract_IN1|Add0~5_sumout )) # (\Extract_IN1|Add0~9_sumout ) ) ) # ( !\Extract_IN1|Add0~13_sumout  & ( (\Extract_IN1|Add0~9_sumout  & 
+// ((\Extract_IN1|Add0~5_sumout ) # (\Extract_IN1|Add0~1_sumout ))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(gnd),
+	.datad(!\Extract_IN1|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~0 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~0 .lut_mask = 64'h0077007711FF11FF;
+defparam \Extract_IN1|ShiftLeft0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N24
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~2 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~2_combout  = ( \Extract_IN1|ShiftLeft0~0_combout  & ( \Extract_IN1|Add0~25_sumout  & ( ((!\Extract_IN1|LBD1|EndPosition[0]~1_combout  & ((!\Extract_IN1|LBD1|EndPosition[1]~0_combout ))) # (\Extract_IN1|LBD1|EndPosition[0]~1_combout 
+//  & (\Extract_IN1|Add3~0_combout ))) # (\Extract_IN1|ShiftLeft0~1_combout ) ) ) ) # ( !\Extract_IN1|ShiftLeft0~0_combout  & ( \Extract_IN1|Add0~25_sumout  & ( (!\Extract_IN1|LBD1|EndPosition[0]~1_combout  & ((!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & 
+// (!\Extract_IN1|Add3~0_combout )) # (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ((\Extract_IN1|ShiftLeft0~1_combout ))))) # (\Extract_IN1|LBD1|EndPosition[0]~1_combout  & (!\Extract_IN1|Add3~0_combout  & ((\Extract_IN1|ShiftLeft0~1_combout )))) ) ) ) # 
+// ( \Extract_IN1|ShiftLeft0~0_combout  & ( !\Extract_IN1|Add0~25_sumout  & ( ((\Extract_IN1|Add3~0_combout  & ((!\Extract_IN1|LBD1|EndPosition[1]~0_combout ) # (\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) # (\Extract_IN1|ShiftLeft0~1_combout ) ) ) ) # ( 
+// !\Extract_IN1|ShiftLeft0~0_combout  & ( !\Extract_IN1|Add0~25_sumout  & ( (\Extract_IN1|ShiftLeft0~1_combout  & ((!\Extract_IN1|Add3~0_combout ) # ((\Extract_IN1|LBD1|EndPosition[1]~0_combout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add3~0_combout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~1_combout ),
+	.datad(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~0_combout ),
+	.dataf(!\Extract_IN1|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~2 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~2 .lut_mask = 64'h0B0A4F5F8B0ACF5F;
+defparam \Extract_IN1|ShiftLeft0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N18
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~1 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~1_combout  = ( \Extract_IN2|Add0~9_sumout  & ( ((\Extract_IN2|Add0~13_sumout ) # (\Extract_IN2|Add0~1_sumout )) # (\Extract_IN2|Add0~5_sumout ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( (\Extract_IN2|Add0~5_sumout  & 
+// (\Extract_IN2|Add0~1_sumout  & \Extract_IN2|Add0~13_sumout )) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~1 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~1 .lut_mask = 64'h010101017F7F7F7F;
+defparam \Extract_IN2|ShiftLeft0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N36
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~2 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~2_combout  = ( \Extract_IN2|Add0~21_sumout  & ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~1_sumout  & (\Extract_IN2|Add0~9_sumout  & (!\Extract_IN2|Add0~17_sumout  $ (!\Extract_IN2|Add0~13_sumout )))) ) ) ) # ( 
+// !\Extract_IN2|Add0~21_sumout  & ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~17_sumout  & (!\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & \Extract_IN2|Add0~9_sumout ))) ) ) ) # ( \Extract_IN2|Add0~21_sumout  & ( 
+// !\Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~17_sumout  & (!\Extract_IN2|Add0~1_sumout  & !\Extract_IN2|Add0~9_sumout )) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( !\Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~17_sumout  & 
+// (\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & !\Extract_IN2|Add0~9_sumout ))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~13_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(!\Extract_IN2|Add0~9_sumout ),
+	.datae(!\Extract_IN2|Add0~21_sumout ),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~2 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~2 .lut_mask = 64'h1000500000040006;
+defparam \Extract_IN2|ShiftLeft0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N21
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~0 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~0_combout  = ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~1_sumout  & \Extract_IN2|Add0~9_sumout ) ) ) # ( !\Extract_IN2|Add0~5_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & !\Extract_IN2|Add0~9_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(!\Extract_IN2|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~0 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~0 .lut_mask = 64'hF000F000000F000F;
+defparam \Extract_IN2|ShiftLeft0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N30
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[1]~1 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[1]~1_combout  = ( \Extract_IN2|Add0~21_sumout  & ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~1_sumout  & (((!\Extract_IN2|Add0~13_sumout ) # (!\Extract_IN2|Add0~9_sumout )) # (\Extract_IN2|Add0~17_sumout ))) ) ) ) # 
+// ( !\Extract_IN2|Add0~21_sumout  & ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~13_sumout ) # (!\Extract_IN2|Add0~9_sumout ))) ) ) ) # ( \Extract_IN2|Add0~21_sumout  & ( !\Extract_IN2|Add0~5_sumout  & ( 
+// (!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~9_sumout ) # (\Extract_IN2|Add0~13_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( !\Extract_IN2|Add0~5_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~17_sumout ) # 
+// ((\Extract_IN2|Add0~9_sumout ) # (\Extract_IN2|Add0~13_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~13_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(!\Extract_IN2|Add0~9_sumout ),
+	.datae(!\Extract_IN2|Add0~21_sumout ),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .lut_mask = 64'hB0F030F00F0C0F0D;
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N24
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~3 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~3_combout  = ( \Extract_IN2|Add0~25_sumout  & ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (!\Extract_IN2|ShiftLeft0~0_combout  & (\Extract_IN2|ShiftLeft0~1_combout )) # (\Extract_IN2|ShiftLeft0~0_combout  & 
+// ((\Extract_IN2|ShiftLeft0~2_combout ))) ) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (!\Extract_IN2|ShiftLeft0~0_combout  & (\Extract_IN2|ShiftLeft0~1_combout )) # (\Extract_IN2|ShiftLeft0~0_combout  & 
+// ((\Extract_IN2|ShiftLeft0~2_combout ))) ) ) ) # ( \Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (!\Extract_IN2|ShiftLeft0~0_combout  & (((\Extract_IN2|ShiftLeft0~1_combout )))) # (\Extract_IN2|ShiftLeft0~0_combout  & 
+// (((\Extract_IN2|ShiftLeft0~2_combout )) # (\Extract_IN2|LBD1|EndPosition[0]~0_combout ))) ) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (!\Extract_IN2|ShiftLeft0~0_combout  & 
+// (\Extract_IN2|ShiftLeft0~1_combout )) # (\Extract_IN2|ShiftLeft0~0_combout  & ((\Extract_IN2|ShiftLeft0~2_combout ))) ) ) )
+
+	.dataa(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~1_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~2_combout ),
+	.datad(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datae(!\Extract_IN2|Add0~25_sumout ),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~3 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~3 .lut_mask = 64'h330F335F330F330F;
+defparam \Extract_IN2|ShiftLeft0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N30
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~5 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~5_combout  = ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~17_sumout )) # (\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~1_sumout  & 
+// ((!\Extract_IN1|Add0~5_sumout ) # ((!\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~17_sumout )))) ) ) # ( !\Extract_IN1|Add0~13_sumout  & ( (\Extract_IN1|Add0~17_sumout  & ((!\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~9_sumout  & 
+// !\Extract_IN1|Add0~5_sumout )) # (\Extract_IN1|Add0~1_sumout  & (!\Extract_IN1|Add0~9_sumout  & \Extract_IN1|Add0~5_sumout )))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~5_sumout ),
+	.datad(!\Extract_IN1|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~5 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~5 .lut_mask = 64'h002400245A7E5A7E;
+defparam \Extract_IN1|ShiftLeft0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N12
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~6 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~6_combout  = ( \Extract_IN1|Add3~0_combout  & ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( ((!\Extract_IN1|LBD1|EndPosition[0]~1_combout  & \Extract_IN1|Add0~21_sumout )) # (\Extract_IN1|ShiftLeft0~5_combout ) ) ) ) # ( 
+// !\Extract_IN1|Add3~0_combout  & ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( ((!\Extract_IN1|LBD1|EndPosition[0]~1_combout  & \Extract_IN1|Add0~21_sumout )) # (\Extract_IN1|ShiftLeft0~5_combout ) ) ) ) # ( \Extract_IN1|Add3~0_combout  & ( 
+// !\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( \Extract_IN1|ShiftLeft0~5_combout  ) ) ) # ( !\Extract_IN1|Add3~0_combout  & ( !\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( ((\Extract_IN1|Add0~25_sumout  & \Extract_IN1|LBD1|EndPosition[0]~1_combout )) 
+// # (\Extract_IN1|ShiftLeft0~5_combout ) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(!\Extract_IN1|ShiftLeft0~5_combout ),
+	.datae(!\Extract_IN1|Add3~0_combout ),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~6 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~6 .lut_mask = 64'h11FF00FF0CFF0CFF;
+defparam \Extract_IN1|ShiftLeft0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N42
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~6 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~6_combout  = ( \Extract_IN2|Add0~13_sumout  & ( (!\Extract_IN2|Add0~5_sumout  & (((\Extract_IN2|Add0~17_sumout  & \Extract_IN2|Add0~9_sumout )) # (\Extract_IN2|Add0~1_sumout ))) # (\Extract_IN2|Add0~5_sumout  & 
+// ((!\Extract_IN2|Add0~1_sumout ) # ((\Extract_IN2|Add0~17_sumout  & !\Extract_IN2|Add0~9_sumout )))) ) ) # ( !\Extract_IN2|Add0~13_sumout  & ( (\Extract_IN2|Add0~17_sumout  & ((!\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~9_sumout  & 
+// !\Extract_IN2|Add0~1_sumout )) # (\Extract_IN2|Add0~5_sumout  & (!\Extract_IN2|Add0~9_sumout  & \Extract_IN2|Add0~1_sumout )))) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~5_sumout ),
+	.datac(!\Extract_IN2|Add0~9_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~6 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~6 .lut_mask = 64'h0410041037DC37DC;
+defparam \Extract_IN2|ShiftLeft0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N48
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~7 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~7_combout  = ( \Extract_IN2|Add0~25_sumout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( ((!\Extract_IN2|LBD1|EndPosition[0]~0_combout  & ((!\Extract_IN2|LBD1|EndPosition[1]~1_combout ))) # (\Extract_IN2|LBD1|EndPosition[0]~0_combout 
+//  & (\Extract_IN2|Add0~21_sumout  & \Extract_IN2|LBD1|EndPosition[1]~1_combout ))) # (\Extract_IN2|ShiftLeft0~6_combout ) ) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( ((\Extract_IN2|LBD1|EndPosition[0]~0_combout  & 
+// (\Extract_IN2|Add0~21_sumout  & \Extract_IN2|LBD1|EndPosition[1]~1_combout ))) # (\Extract_IN2|ShiftLeft0~6_combout ) ) ) ) # ( \Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~6_combout  ) ) ) # ( 
+// !\Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~6_combout  ) ) )
+
+	.dataa(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~6_combout ),
+	.datac(!\Extract_IN2|Add0~21_sumout ),
+	.datad(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datae(!\Extract_IN2|Add0~25_sumout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~7 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~7 .lut_mask = 64'h333333333337BB37;
+defparam \Extract_IN2|ShiftLeft0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N33
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~3 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~3_combout  = ( \Extract_IN1|Add0~5_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~17_sumout )))) # (\Extract_IN1|Add0~1_sumout  & (!\Extract_IN1|Add0~9_sumout  & (\Extract_IN1|Add0~21_sumout ))) ) ) # ( 
+// !\Extract_IN1|Add0~5_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~9_sumout  & (\Extract_IN1|Add0~21_sumout ))) # (\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~17_sumout )))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~9_sumout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(!\Extract_IN1|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~3 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~3 .lut_mask = 64'h0257025704AE04AE;
+defparam \Extract_IN1|ShiftLeft0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N36
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~4 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~4_combout  = ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( ((\Extract_IN1|Add0~25_sumout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout )) # (\Extract_IN1|ShiftLeft0~3_combout ) ) ) # ( 
+// !\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( \Extract_IN1|ShiftLeft0~3_combout  ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~4 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~4 .lut_mask = 64'h0F0F0F0F4F4F4F4F;
+defparam \Extract_IN1|ShiftLeft0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N45
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~4 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~4_combout  = ( \Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~17_sumout )) # (\Extract_IN2|Add0~5_sumout  & (((!\Extract_IN2|Add0~9_sumout  & \Extract_IN2|Add0~21_sumout )))) ) ) # ( 
+// !\Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~5_sumout  & (((\Extract_IN2|Add0~9_sumout  & \Extract_IN2|Add0~21_sumout )))) # (\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~17_sumout )) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(!\Extract_IN2|Add0~5_sumout ),
+	.datac(!\Extract_IN2|Add0~9_sumout ),
+	.datad(!\Extract_IN2|Add0~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~4 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~4 .lut_mask = 64'h111D111D44744474;
+defparam \Extract_IN2|ShiftLeft0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N57
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~5 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~5_combout  = ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( ((\Extract_IN2|LBD1|EndPosition[0]~0_combout  & (\Extract_IN2|ShiftLeft0~0_combout  & \Extract_IN2|Add0~25_sumout ))) # (\Extract_IN2|ShiftLeft0~4_combout ) ) ) # ( 
+// !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( \Extract_IN2|ShiftLeft0~4_combout  ) )
+
+	.dataa(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~4_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datad(!\Extract_IN2|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~5 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~5 .lut_mask = 64'h3333333333373337;
+defparam \Extract_IN2|ShiftLeft0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N30
+cyclonev_lcell_comb \ShiftRight0~6 (
+// Equation(s):
+// \ShiftRight0~6_combout  = ( \Extract_IN2|ShiftLeft0~5_combout  & ( (!\Extract_IN1|ShiftLeft0~4_combout ) # (!\Extract_IN2|ShiftLeft0~7_combout  $ (!\Extract_IN1|ShiftLeft0~6_combout )) ) ) # ( !\Extract_IN2|ShiftLeft0~5_combout  & ( 
+// (!\Extract_IN2|ShiftLeft0~7_combout  $ (!\Extract_IN1|ShiftLeft0~6_combout )) # (\Extract_IN1|ShiftLeft0~4_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~6 .extended_lut = "off";
+defparam \ShiftRight0~6 .lut_mask = 64'h3CFF3CFFFF3CFF3C;
+defparam \ShiftRight0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N36
+cyclonev_lcell_comb \Add0~18 (
+// Equation(s):
+// \Add0~18_cout  = CARRY(( VCC ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\Add0~18_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~18 .extended_lut = "off";
+defparam \Add0~18 .lut_mask = 64'h000000000000FFFF;
+defparam \Add0~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N39
+cyclonev_lcell_comb \Add0~13 (
+// Equation(s):
+// \Add0~13_sumout  = SUM(( (!\LessThan0~3_combout  & (((!\Extract_IN1|RegimeValue[1]~1_combout )))) # (\LessThan0~3_combout  & (!\Extract_IN2|Add0~1_sumout  $ (((\Extract_IN2|LBD1|EndPosition[0]~0_combout ))))) ) + ( (!\LessThan0~3_combout  & 
+// (!\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition[0]~0_combout ))))) # (\LessThan0~3_combout  & (((\Extract_IN1|RegimeValue[1]~1_combout )))) ) + ( \Add0~18_cout  ))
+// \Add0~14  = CARRY(( (!\LessThan0~3_combout  & (((!\Extract_IN1|RegimeValue[1]~1_combout )))) # (\LessThan0~3_combout  & (!\Extract_IN2|Add0~1_sumout  $ (((\Extract_IN2|LBD1|EndPosition[0]~0_combout ))))) ) + ( (!\LessThan0~3_combout  & 
+// (!\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition[0]~0_combout ))))) # (\LessThan0~3_combout  & (((\Extract_IN1|RegimeValue[1]~1_combout )))) ) + ( \Add0~18_cout  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\LessThan0~3_combout ),
+	.datac(!\Extract_IN1|RegimeValue[1]~1_combout ),
+	.datad(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datag(gnd),
+	.cin(\Add0~18_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~13_sumout ),
+	.cout(\Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~13 .extended_lut = "off";
+defparam \Add0~13 .lut_mask = 64'h0000B8740000E2D1;
+defparam \Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N42
+cyclonev_lcell_comb \Add0~9 (
+// Equation(s):
+// \Add0~9_sumout  = SUM(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (!\Extract_IN1|RegimeValue[1]~2_combout )) # (\LessThan0~8_combout  & ((!\Extract_IN2|RegimeValue[1]~2_combout ))))) # (\LessThan0~4_combout  & 
+// (((!\Extract_IN2|RegimeValue[1]~2_combout )))) ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[1]~2_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[1]~2_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[1]~2_combout )))) ) + ( \Add0~14  ))
+// \Add0~10  = CARRY(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (!\Extract_IN1|RegimeValue[1]~2_combout )) # (\LessThan0~8_combout  & ((!\Extract_IN2|RegimeValue[1]~2_combout ))))) # (\LessThan0~4_combout  & 
+// (((!\Extract_IN2|RegimeValue[1]~2_combout )))) ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[1]~2_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[1]~2_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[1]~2_combout )))) ) + ( \Add0~14  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|RegimeValue[1]~2_combout ),
+	.datad(!\Extract_IN2|RegimeValue[1]~2_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|RegimeValue[1]~2_combout ),
+	.datag(gnd),
+	.cin(\Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~9_sumout ),
+	.cout(\Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~9 .extended_lut = "off";
+defparam \Add0~9 .lut_mask = 64'h0000F8700000F780;
+defparam \Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N45
+cyclonev_lcell_comb \Add0~5 (
+// Equation(s):
+// \Add0~5_sumout  = SUM(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (!\Extract_IN1|RegimeValue[2]~0_combout )) # (\LessThan0~8_combout  & ((!\Extract_IN2|RegimeValue[2]~0_combout ))))) # (\LessThan0~4_combout  & 
+// (((!\Extract_IN2|RegimeValue[2]~0_combout )))) ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[2]~0_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[2]~0_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[2]~0_combout )))) ) + ( \Add0~10  ))
+// \Add0~6  = CARRY(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (!\Extract_IN1|RegimeValue[2]~0_combout )) # (\LessThan0~8_combout  & ((!\Extract_IN2|RegimeValue[2]~0_combout ))))) # (\LessThan0~4_combout  & 
+// (((!\Extract_IN2|RegimeValue[2]~0_combout )))) ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[2]~0_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[2]~0_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[2]~0_combout )))) ) + ( \Add0~10  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|RegimeValue[2]~0_combout ),
+	.datad(!\Extract_IN2|RegimeValue[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|RegimeValue[2]~0_combout ),
+	.datag(gnd),
+	.cin(\Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~5_sumout ),
+	.cout(\Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~5 .extended_lut = "off";
+defparam \Add0~5 .lut_mask = 64'h0000F8700000F780;
+defparam \Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N48
+cyclonev_lcell_comb \Add0~1 (
+// Equation(s):
+// \Add0~1_sumout  = SUM(( (!\LessThan0~3_combout  & ((\Extract_IN1|Add0~1_sumout ))) # (\LessThan0~3_combout  & (\Extract_IN2|Add0~1_sumout )) ) + ( (!\LessThan0~3_combout  & (!\Extract_IN2|Add0~1_sumout )) # (\LessThan0~3_combout  & 
+// ((!\Extract_IN1|Add0~1_sumout ))) ) + ( \Add0~6  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~1 .extended_lut = "off";
+defparam \Add0~1 .lut_mask = 64'h0000535300003535;
+defparam \Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N36
+cyclonev_lcell_comb \LessThan0~10 (
+// Equation(s):
+// \LessThan0~10_combout  = !\Extract_IN2|Add0~5_sumout  $ (!\Extract_IN1|Add0~5_sumout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~10 .extended_lut = "off";
+defparam \LessThan0~10 .lut_mask = 64'h0FF00FF00FF00FF0;
+defparam \LessThan0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N33
+cyclonev_lcell_comb \LessThan0~12 (
+// Equation(s):
+// \LessThan0~12_combout  = ( \Extract_IN1|Add0~17_sumout  & ( (!\Extract_IN2|Add0~17_sumout  & ((!\Extract_IN2|Add0~13_sumout ) # (\Extract_IN1|Add0~13_sumout ))) # (\Extract_IN2|Add0~17_sumout  & (\Extract_IN1|Add0~13_sumout  & !\Extract_IN2|Add0~13_sumout 
+// )) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( (\Extract_IN1|Add0~13_sumout  & !\Extract_IN2|Add0~13_sumout ) ) )
+
+	.dataa(!\Extract_IN2|Add0~17_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN1|Add0~13_sumout ),
+	.datad(!\Extract_IN2|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~12 .extended_lut = "off";
+defparam \LessThan0~12 .lut_mask = 64'h0F000F00AF0AAF0A;
+defparam \LessThan0~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N9
+cyclonev_lcell_comb \LessThan0~11 (
+// Equation(s):
+// \LessThan0~11_combout  = (\Extract_IN2|Add0~13_sumout  & !\Extract_IN1|Add0~13_sumout )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN1|Add0~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~11 .extended_lut = "off";
+defparam \LessThan0~11 .lut_mask = 64'h5050505050505050;
+defparam \LessThan0~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N54
+cyclonev_lcell_comb \LessThan0~13 (
+// Equation(s):
+// \LessThan0~13_combout  = ( \Extract_IN1|Add0~9_sumout  & ( \Extract_IN2|Add0~9_sumout  & ( (!\LessThan0~10_combout  & (((\LessThan0~0_combout  & !\LessThan0~11_combout )) # (\LessThan0~12_combout ))) ) ) ) # ( \Extract_IN1|Add0~9_sumout  & ( 
+// !\Extract_IN2|Add0~9_sumout  & ( !\LessThan0~10_combout  ) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( !\Extract_IN2|Add0~9_sumout  & ( (!\LessThan0~10_combout  & (((\LessThan0~0_combout  & !\LessThan0~11_combout )) # (\LessThan0~12_combout ))) ) ) )
+
+	.dataa(!\LessThan0~0_combout ),
+	.datab(!\LessThan0~10_combout ),
+	.datac(!\LessThan0~12_combout ),
+	.datad(!\LessThan0~11_combout ),
+	.datae(!\Extract_IN1|Add0~9_sumout ),
+	.dataf(!\Extract_IN2|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~13 .extended_lut = "off";
+defparam \LessThan0~13 .lut_mask = 64'h4C0CCCCC00004C0C;
+defparam \LessThan0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N54
+cyclonev_lcell_comb \LessThan0~9 (
+// Equation(s):
+// \LessThan0~9_combout  = ( !\Extract_IN2|Add0~5_sumout  & ( \Extract_IN1|Add0~5_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~9 .extended_lut = "off";
+defparam \LessThan0~9 .lut_mask = 64'h00FF00FF00000000;
+defparam \LessThan0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N24
+cyclonev_lcell_comb \Add1~0 (
+// Equation(s):
+// \Add1~0_combout  = ( \Extract_IN2|ShiftLeft0~5_combout  & ( \Extract_IN1|Add0~1_sumout  & ( (!\Extract_IN1|ShiftLeft0~4_combout  & ((!\Extract_IN2|Add0~1_sumout ) # ((\LessThan0~9_combout ) # (\LessThan0~13_combout )))) ) ) ) # ( 
+// !\Extract_IN2|ShiftLeft0~5_combout  & ( \Extract_IN1|Add0~1_sumout  & ( (\Extract_IN2|Add0~1_sumout  & (!\LessThan0~13_combout  & (\Extract_IN1|ShiftLeft0~4_combout  & !\LessThan0~9_combout ))) ) ) ) # ( \Extract_IN2|ShiftLeft0~5_combout  & ( 
+// !\Extract_IN1|Add0~1_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & (!\Extract_IN1|ShiftLeft0~4_combout  & ((\LessThan0~9_combout ) # (\LessThan0~13_combout )))) ) ) ) # ( !\Extract_IN2|ShiftLeft0~5_combout  & ( !\Extract_IN1|Add0~1_sumout  & ( 
+// (\Extract_IN1|ShiftLeft0~4_combout  & (((!\LessThan0~13_combout  & !\LessThan0~9_combout )) # (\Extract_IN2|Add0~1_sumout ))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\LessThan0~13_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datad(!\LessThan0~9_combout ),
+	.datae(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.dataf(!\Extract_IN1|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~0 .extended_lut = "off";
+defparam \Add1~0 .lut_mask = 64'h0D0520A00400B0F0;
+defparam \Add1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N30
+cyclonev_lcell_comb \Add1~1 (
+// Equation(s):
+// \Add1~1_combout  = ( \Extract_IN2|ShiftLeft0~7_combout  & ( \Add1~0_combout  & ( !\Extract_IN1|ShiftLeft0~2_combout  $ (!\Extract_IN2|ShiftLeft0~3_combout  $ (((!\LessThan0~3_combout  & !\Extract_IN1|ShiftLeft0~6_combout )))) ) ) ) # ( 
+// !\Extract_IN2|ShiftLeft0~7_combout  & ( \Add1~0_combout  & ( !\Extract_IN1|ShiftLeft0~2_combout  $ (!\Extract_IN2|ShiftLeft0~3_combout  $ (((\LessThan0~3_combout  & \Extract_IN1|ShiftLeft0~6_combout )))) ) ) ) # ( \Extract_IN2|ShiftLeft0~7_combout  & ( 
+// !\Add1~0_combout  & ( !\Extract_IN1|ShiftLeft0~2_combout  $ (!\Extract_IN2|ShiftLeft0~3_combout  $ (((!\LessThan0~3_combout ) # (\Extract_IN1|ShiftLeft0~6_combout )))) ) ) ) # ( !\Extract_IN2|ShiftLeft0~7_combout  & ( !\Add1~0_combout  & ( 
+// !\Extract_IN1|ShiftLeft0~2_combout  $ (!\Extract_IN2|ShiftLeft0~3_combout  $ (((!\Extract_IN1|ShiftLeft0~6_combout ) # (\LessThan0~3_combout )))) ) ) )
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~2_combout ),
+	.datad(!\Extract_IN2|ShiftLeft0~3_combout ),
+	.datae(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.dataf(!\Add1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add1~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~1 .extended_lut = "off";
+defparam \Add1~1 .lut_mask = 64'hD22DB44B1EE18778;
+defparam \Add1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N54
+cyclonev_lcell_comb \SE[2]~0 (
+// Equation(s):
+// \SE[2]~0_combout  = ( \Extract_IN1|ShiftLeft0~2_combout  & ( \Extract_IN2|ShiftLeft0~3_combout  ) ) # ( !\Extract_IN1|ShiftLeft0~2_combout  & ( \Extract_IN2|ShiftLeft0~3_combout  & ( (!\Extract_IN1|Add0~1_sumout  & (!\Extract_IN2|Add0~1_sumout  & 
+// ((\LessThan0~9_combout ) # (\LessThan0~13_combout )))) # (\Extract_IN1|Add0~1_sumout  & (((!\Extract_IN2|Add0~1_sumout ) # (\LessThan0~9_combout )) # (\LessThan0~13_combout ))) ) ) ) # ( \Extract_IN1|ShiftLeft0~2_combout  & ( 
+// !\Extract_IN2|ShiftLeft0~3_combout  & ( (!\Extract_IN1|Add0~1_sumout  & (((!\LessThan0~13_combout  & !\LessThan0~9_combout )) # (\Extract_IN2|Add0~1_sumout ))) # (\Extract_IN1|Add0~1_sumout  & (!\LessThan0~13_combout  & (\Extract_IN2|Add0~1_sumout  & 
+// !\LessThan0~9_combout ))) ) ) )
+
+	.dataa(!\LessThan0~13_combout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(!\LessThan0~9_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~2_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SE[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SE[2]~0 .extended_lut = "off";
+defparam \SE[2]~0 .lut_mask = 64'h00008E0C71F3FFFF;
+defparam \SE[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N57
+cyclonev_lcell_comb \LE[2]~0 (
+// Equation(s):
+// \LE[2]~0_combout  = ( \Extract_IN2|ShiftLeft0~3_combout  & ( \Extract_IN1|ShiftLeft0~2_combout  ) ) # ( !\Extract_IN2|ShiftLeft0~3_combout  & ( \Extract_IN1|ShiftLeft0~2_combout  & ( (!\Extract_IN1|Add0~1_sumout  & (!\Extract_IN2|Add0~1_sumout  & 
+// ((\LessThan0~9_combout ) # (\LessThan0~13_combout )))) # (\Extract_IN1|Add0~1_sumout  & (((!\Extract_IN2|Add0~1_sumout ) # (\LessThan0~9_combout )) # (\LessThan0~13_combout ))) ) ) ) # ( \Extract_IN2|ShiftLeft0~3_combout  & ( 
+// !\Extract_IN1|ShiftLeft0~2_combout  & ( (!\Extract_IN1|Add0~1_sumout  & (((!\LessThan0~13_combout  & !\LessThan0~9_combout )) # (\Extract_IN2|Add0~1_sumout ))) # (\Extract_IN1|Add0~1_sumout  & (!\LessThan0~13_combout  & (!\LessThan0~9_combout  & 
+// \Extract_IN2|Add0~1_sumout ))) ) ) )
+
+	.dataa(!\LessThan0~13_combout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\LessThan0~9_combout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(!\Extract_IN2|ShiftLeft0~3_combout ),
+	.dataf(!\Extract_IN1|ShiftLeft0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LE[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LE[2]~0 .extended_lut = "off";
+defparam \LE[2]~0 .lut_mask = 64'h000080EC7F13FFFF;
+defparam \LE[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N12
+cyclonev_lcell_comb \Add1~2 (
+// Equation(s):
+// \Add1~2_combout  = ( \Extract_IN1|ShiftLeft0~4_combout  & ( \Extract_IN1|ShiftLeft0~6_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & ((!\Extract_IN2|ShiftLeft0~5_combout ) # (!\Extract_IN2|ShiftLeft0~7_combout )))) ) ) ) # ( 
+// !\Extract_IN1|ShiftLeft0~4_combout  & ( \Extract_IN1|ShiftLeft0~6_combout  & ( (!\Extract_IN2|ShiftLeft0~7_combout  & (((!\LessThan0~4_combout  & !\LessThan0~8_combout )))) # (\Extract_IN2|ShiftLeft0~7_combout  & (\Extract_IN2|ShiftLeft0~5_combout  & 
+// ((\LessThan0~8_combout ) # (\LessThan0~4_combout )))) ) ) ) # ( \Extract_IN1|ShiftLeft0~4_combout  & ( !\Extract_IN1|ShiftLeft0~6_combout  & ( (!\Extract_IN2|ShiftLeft0~7_combout  & (!\Extract_IN2|ShiftLeft0~5_combout  & (!\LessThan0~4_combout  & 
+// !\LessThan0~8_combout ))) # (\Extract_IN2|ShiftLeft0~7_combout  & (((\LessThan0~8_combout ) # (\LessThan0~4_combout )))) ) ) ) # ( !\Extract_IN1|ShiftLeft0~4_combout  & ( !\Extract_IN1|ShiftLeft0~6_combout  & ( (!\Extract_IN2|ShiftLeft0~5_combout  & 
+// (\Extract_IN2|ShiftLeft0~7_combout  & ((\LessThan0~8_combout ) # (\LessThan0~4_combout )))) # (\Extract_IN2|ShiftLeft0~5_combout  & (((\LessThan0~8_combout ) # (\LessThan0~4_combout )))) ) ) )
+
+	.dataa(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datac(!\LessThan0~4_combout ),
+	.datad(!\LessThan0~8_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.dataf(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add1~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~2 .extended_lut = "off";
+defparam \Add1~2 .lut_mask = 64'h07778333C111E000;
+defparam \Add1~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N9
+cyclonev_lcell_comb \ShiftRight0~7 (
+// Equation(s):
+// \ShiftRight0~7_combout  = !\Add0~13_sumout  $ (((!\SE[2]~0_combout  & ((!\Add1~2_combout ) # (\LE[2]~0_combout ))) # (\SE[2]~0_combout  & (\LE[2]~0_combout  & !\Add1~2_combout ))))
+
+	.dataa(!\SE[2]~0_combout ),
+	.datab(!\Add0~13_sumout ),
+	.datac(!\LE[2]~0_combout ),
+	.datad(!\Add1~2_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~7 .extended_lut = "off";
+defparam \ShiftRight0~7 .lut_mask = 64'h63C663C663C663C6;
+defparam \ShiftRight0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N36
+cyclonev_lcell_comb \Add3~26 (
+// Equation(s):
+// \Add3~26_combout  = ( !\Add0~9_sumout  & ( (!\Add0~5_sumout  & (!\Add0~1_sumout  & (\Add1~1_combout  & !\ShiftRight0~7_combout ))) ) )
+
+	.dataa(!\Add0~5_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add1~1_combout ),
+	.datad(!\ShiftRight0~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~26 .extended_lut = "off";
+defparam \Add3~26 .lut_mask = 64'h0800080000000000;
+defparam \Add3~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N24
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~8 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~8_combout  = ( \Extract_IN2|Add0~25_sumout  & ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (!\Extract_IN2|LBD1|EndPosition[0]~0_combout ) # (\Extract_IN2|Add0~13_sumout ) ) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( 
+// \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( (\Extract_IN2|LBD1|EndPosition[0]~0_combout  & \Extract_IN2|Add0~13_sumout ) ) ) ) # ( \Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( 
+// (!\Extract_IN2|LBD1|EndPosition[0]~0_combout  & (\Extract_IN2|Add0~17_sumout )) # (\Extract_IN2|LBD1|EndPosition[0]~0_combout  & ((\Extract_IN2|Add0~21_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( 
+// (!\Extract_IN2|LBD1|EndPosition[0]~0_combout  & (\Extract_IN2|Add0~17_sumout )) # (\Extract_IN2|LBD1|EndPosition[0]~0_combout  & ((\Extract_IN2|Add0~21_sumout ))) ) ) )
+
+	.dataa(!\Extract_IN2|LBD1|EndPosition[0]~0_combout ),
+	.datab(!\Extract_IN2|Add0~17_sumout ),
+	.datac(!\Extract_IN2|Add0~21_sumout ),
+	.datad(!\Extract_IN2|Add0~13_sumout ),
+	.datae(!\Extract_IN2|Add0~25_sumout ),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~8 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~8 .lut_mask = 64'h272727270055AAFF;
+defparam \Extract_IN2|ShiftLeft0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N54
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~8 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~8_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (((\Extract_IN1|LBD1|EndPosition[0]~1_combout ) # (\Extract_IN1|Add0~21_sumout )))) # 
+// (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (((!\Extract_IN1|LBD1|EndPosition[0]~1_combout )) # (\Extract_IN1|Add0~25_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|LBD1|EndPosition[1]~0_combout  
+// & (((\Extract_IN1|Add0~21_sumout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) # (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (((!\Extract_IN1|LBD1|EndPosition[0]~1_combout )) # (\Extract_IN1|Add0~25_sumout ))) ) ) ) # ( 
+// \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (((\Extract_IN1|LBD1|EndPosition[0]~1_combout ) # (\Extract_IN1|Add0~21_sumout )))) # (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & 
+// (\Extract_IN1|Add0~25_sumout  & ((\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (((\Extract_IN1|Add0~21_sumout  & 
+// !\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) # (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & (\Extract_IN1|Add0~25_sumout  & ((\Extract_IN1|LBD1|EndPosition[0]~1_combout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~8 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~8 .lut_mask = 64'h0C110CDD3F113FDD;
+defparam \Extract_IN1|ShiftLeft0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N42
+cyclonev_lcell_comb \LM[6]~0 (
+// Equation(s):
+// \LM[6]~0_combout  = ( \Extract_IN1|ShiftLeft0~8_combout  & ( \Extract_IN1|Add3~0_combout  & ( (((\Extract_IN2|ShiftLeft0~8_combout  & !\Extract_IN2|ShiftLeft0~0_combout )) # (\LessThan0~8_combout )) # (\LessThan0~4_combout ) ) ) ) # ( 
+// !\Extract_IN1|ShiftLeft0~8_combout  & ( \Extract_IN1|Add3~0_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN2|ShiftLeft0~8_combout  & !\Extract_IN2|ShiftLeft0~0_combout ))) ) ) ) # ( \Extract_IN1|ShiftLeft0~8_combout  & ( 
+// !\Extract_IN1|Add3~0_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN2|ShiftLeft0~8_combout  & !\Extract_IN2|ShiftLeft0~0_combout ))) ) ) ) # ( !\Extract_IN1|ShiftLeft0~8_combout  & ( !\Extract_IN1|Add3~0_combout  & ( 
+// (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN2|ShiftLeft0~8_combout  & !\Extract_IN2|ShiftLeft0~0_combout ))) ) ) )
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~8_combout ),
+	.datad(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~8_combout ),
+	.dataf(!\Extract_IN1|Add3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LM[6]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LM[6]~0 .extended_lut = "off";
+defparam \LM[6]~0 .lut_mask = 64'h0800080008007F77;
+defparam \LM[6]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N6
+cyclonev_lcell_comb Operation(
+// Equation(s):
+// \Operation~combout  = !\IN2[7]~input_o  $ (!\IN1[7]~input_o )
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(!\IN1[7]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Operation~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam Operation.extended_lut = "off";
+defparam Operation.lut_mask = 64'h6666666666666666;
+defparam Operation.shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N57
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~9 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~9_combout  = (\Extract_IN2|ShiftLeft0~8_combout  & !\Extract_IN2|ShiftLeft0~0_combout )
+
+	.dataa(!\Extract_IN2|ShiftLeft0~8_combout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~9 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~9 .lut_mask = 64'h5050505050505050;
+defparam \Extract_IN2|ShiftLeft0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N54
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~9 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~9_combout  = ( \Extract_IN1|Add3~0_combout  & ( \Extract_IN1|ShiftLeft0~8_combout  ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|ShiftLeft0~8_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~9 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~9 .lut_mask = 64'h0000000033333333;
+defparam \Extract_IN1|ShiftLeft0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N0
+cyclonev_lcell_comb \Add3~42 (
+// Equation(s):
+// \Add3~42_combout  = ( !\LessThan0~3_combout  & ( (!\Extract_IN1|ShiftLeft0~9_combout  & ((!\Extract_IN1|ShiftLeft0~4_combout  & (\Extract_IN2|ShiftLeft0~5_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ (\Extract_IN2|ShiftLeft0~7_combout )))) # 
+// (\Extract_IN1|ShiftLeft0~4_combout  & (!\Extract_IN2|ShiftLeft0~5_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ (!\Extract_IN2|ShiftLeft0~7_combout )))))) # (\Extract_IN1|ShiftLeft0~9_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ 
+// (!\Extract_IN2|ShiftLeft0~7_combout  $ (((!\Extract_IN1|ShiftLeft0~4_combout ) # (\Extract_IN2|ShiftLeft0~5_combout )))))) ) ) # ( \LessThan0~3_combout  & ( (!\Extract_IN2|ShiftLeft0~9_combout  & ((!\Extract_IN1|ShiftLeft0~4_combout  & 
+// (\Extract_IN2|ShiftLeft0~5_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ (!\Extract_IN2|ShiftLeft0~7_combout )))) # (\Extract_IN1|ShiftLeft0~4_combout  & (!\Extract_IN2|ShiftLeft0~5_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ 
+// (\Extract_IN2|ShiftLeft0~7_combout )))))) # (\Extract_IN2|ShiftLeft0~9_combout  & (!\Extract_IN1|ShiftLeft0~6_combout  $ (!\Extract_IN2|ShiftLeft0~7_combout  $ (((!\Extract_IN2|ShiftLeft0~5_combout ) # (\Extract_IN1|ShiftLeft0~4_combout )))))) ) )
+
+	.dataa(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datab(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~9_combout ),
+	.datad(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datae(!\LessThan0~3_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(!\Extract_IN1|ShiftLeft0~9_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~42_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~42 .extended_lut = "on";
+defparam \Add3~42 .lut_mask = 64'h19464C138C232689;
+defparam \Add3~42 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N6
+cyclonev_lcell_comb \ShiftRight0~0 (
+// Equation(s):
+// \ShiftRight0~0_combout  = ( \LE[2]~0_combout  & ( (!\Add0~9_sumout  & (!\Add0~13_sumout  $ (((\SE[2]~0_combout  & \Add1~2_combout ))))) ) ) # ( !\LE[2]~0_combout  & ( (!\Add0~9_sumout  & (!\Add0~13_sumout  $ (((\Add1~2_combout ) # (\SE[2]~0_combout ))))) 
+// ) )
+
+	.dataa(!\SE[2]~0_combout ),
+	.datab(!\Add0~13_sumout ),
+	.datac(!\Add0~9_sumout ),
+	.datad(!\Add1~2_combout ),
+	.datae(gnd),
+	.dataf(!\LE[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~0 .extended_lut = "off";
+defparam \ShiftRight0~0 .lut_mask = 64'h90309030C090C090;
+defparam \ShiftRight0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N18
+cyclonev_lcell_comb \Add3~25 (
+// Equation(s):
+// \Add3~25_combout  = ( \Add3~42_combout  & ( \ShiftRight0~0_combout  & ( !\Operation~combout  $ ((((!\Add1~1_combout ) # (\Add0~5_sumout )) # (\Add0~1_sumout ))) ) ) ) # ( !\Add3~42_combout  & ( \ShiftRight0~0_combout  & ( \Operation~combout  ) ) ) # ( 
+// \Add3~42_combout  & ( !\ShiftRight0~0_combout  & ( \Operation~combout  ) ) ) # ( !\Add3~42_combout  & ( !\ShiftRight0~0_combout  & ( \Operation~combout  ) ) )
+
+	.dataa(!\Operation~combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~5_sumout ),
+	.datad(!\Add1~1_combout ),
+	.datae(!\Add3~42_combout ),
+	.dataf(!\ShiftRight0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~25_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~25 .extended_lut = "off";
+defparam \Add3~25 .lut_mask = 64'h5555555555555595;
+defparam \Add3~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N24
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~10 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~10_combout  = (\Extract_IN2|Add0~25_sumout  & (!\Extract_IN2|Add0~1_sumout  $ (!\Extract_IN2|Add0~5_sumout )))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~10 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~10 .lut_mask = 64'h003C003C003C003C;
+defparam \Extract_IN2|ShiftLeft0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N51
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~10 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~10_combout  = ( \Extract_IN1|ShiftLeft0~1_combout  ) # ( !\Extract_IN1|ShiftLeft0~1_combout  & ( (\Extract_IN1|Add0~25_sumout  & (!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout )) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datac(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|ShiftLeft0~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~10 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~10 .lut_mask = 64'h40404040FFFFFFFF;
+defparam \Extract_IN1|ShiftLeft0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N15
+cyclonev_lcell_comb \Add1~4 (
+// Equation(s):
+// \Add1~4_combout  = ( \Extract_IN2|ShiftLeft0~5_combout  & ( !\Extract_IN1|ShiftLeft0~4_combout  ) ) # ( !\Extract_IN2|ShiftLeft0~5_combout  & ( \Extract_IN1|ShiftLeft0~4_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add1~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~4 .extended_lut = "off";
+defparam \Add1~4 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \Add1~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y10_N12
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~12 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~12_combout  = (\Extract_IN1|Add0~25_sumout  & (!\Extract_IN1|Add0~1_sumout  $ (!\Extract_IN1|Add0~5_sumout )))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add0~25_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~12 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~12 .lut_mask = 64'h0330033003300330;
+defparam \Extract_IN1|ShiftLeft0~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N36
+cyclonev_lcell_comb \ShiftRight0~5 (
+// Equation(s):
+// \ShiftRight0~5_combout  = ( \Extract_IN2|ShiftLeft0~9_combout  & ( \Extract_IN1|ShiftLeft0~12_combout  & ( (!\Add1~4_combout  & (((!\LessThan0~3_combout )) # (\Extract_IN2|ShiftLeft0~10_combout ))) # (\Add1~4_combout  & (((\LessThan0~3_combout ) # 
+// (\Extract_IN1|ShiftLeft0~9_combout )))) ) ) ) # ( !\Extract_IN2|ShiftLeft0~9_combout  & ( \Extract_IN1|ShiftLeft0~12_combout  & ( (!\Add1~4_combout  & (((!\LessThan0~3_combout )) # (\Extract_IN2|ShiftLeft0~10_combout ))) # (\Add1~4_combout  & 
+// (((\Extract_IN1|ShiftLeft0~9_combout  & !\LessThan0~3_combout )))) ) ) ) # ( \Extract_IN2|ShiftLeft0~9_combout  & ( !\Extract_IN1|ShiftLeft0~12_combout  & ( (!\Add1~4_combout  & (\Extract_IN2|ShiftLeft0~10_combout  & ((\LessThan0~3_combout )))) # 
+// (\Add1~4_combout  & (((\LessThan0~3_combout ) # (\Extract_IN1|ShiftLeft0~9_combout )))) ) ) ) # ( !\Extract_IN2|ShiftLeft0~9_combout  & ( !\Extract_IN1|ShiftLeft0~12_combout  & ( (!\Add1~4_combout  & (\Extract_IN2|ShiftLeft0~10_combout  & 
+// ((\LessThan0~3_combout )))) # (\Add1~4_combout  & (((\Extract_IN1|ShiftLeft0~9_combout  & !\LessThan0~3_combout )))) ) ) )
+
+	.dataa(!\Add1~4_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~10_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~9_combout ),
+	.datad(!\LessThan0~3_combout ),
+	.datae(!\Extract_IN2|ShiftLeft0~9_combout ),
+	.dataf(!\Extract_IN1|ShiftLeft0~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~5 .extended_lut = "off";
+defparam \ShiftRight0~5 .lut_mask = 64'h05220577AF22AF77;
+defparam \ShiftRight0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N54
+cyclonev_lcell_comb \ShiftRight0~4 (
+// Equation(s):
+// \ShiftRight0~4_combout  = ( \Add1~2_combout  & ( \Add0~9_sumout  ) ) # ( !\Add1~2_combout  & ( \Add0~9_sumout  ) ) # ( \Add1~2_combout  & ( !\Add0~9_sumout  & ( (!\Add0~13_sumout  $ (((\LE[2]~0_combout  & !\SE[2]~0_combout )))) # (\Add0~5_sumout ) ) ) ) # 
+// ( !\Add1~2_combout  & ( !\Add0~9_sumout  & ( (!\Add0~13_sumout  $ (((!\SE[2]~0_combout ) # (\LE[2]~0_combout )))) # (\Add0~5_sumout ) ) ) )
+
+	.dataa(!\Add0~5_sumout ),
+	.datab(!\LE[2]~0_combout ),
+	.datac(!\SE[2]~0_combout ),
+	.datad(!\Add0~13_sumout ),
+	.datae(!\Add1~2_combout ),
+	.dataf(!\Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~4 .extended_lut = "off";
+defparam \ShiftRight0~4 .lut_mask = 64'h5DF7DF75FFFFFFFF;
+defparam \ShiftRight0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N48
+cyclonev_lcell_comb \Add1~3 (
+// Equation(s):
+// \Add1~3_combout  = ( \Extract_IN1|ShiftLeft0~4_combout  & ( \Extract_IN1|ShiftLeft0~6_combout  & ( !\Extract_IN2|ShiftLeft0~7_combout  $ ((((\LessThan0~8_combout ) # (\LessThan0~4_combout )) # (\Extract_IN2|ShiftLeft0~5_combout ))) ) ) ) # ( 
+// !\Extract_IN1|ShiftLeft0~4_combout  & ( \Extract_IN1|ShiftLeft0~6_combout  & ( !\Extract_IN2|ShiftLeft0~7_combout  $ (((!\Extract_IN2|ShiftLeft0~5_combout ) # ((!\LessThan0~4_combout  & !\LessThan0~8_combout )))) ) ) ) # ( 
+// \Extract_IN1|ShiftLeft0~4_combout  & ( !\Extract_IN1|ShiftLeft0~6_combout  & ( !\Extract_IN2|ShiftLeft0~7_combout  $ (((!\Extract_IN2|ShiftLeft0~5_combout  & (!\LessThan0~4_combout  & !\LessThan0~8_combout )))) ) ) ) # ( !\Extract_IN1|ShiftLeft0~4_combout 
+//  & ( !\Extract_IN1|ShiftLeft0~6_combout  & ( !\Extract_IN2|ShiftLeft0~7_combout  $ (((\Extract_IN2|ShiftLeft0~5_combout  & ((\LessThan0~8_combout ) # (\LessThan0~4_combout ))))) ) ) )
+
+	.dataa(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datac(!\LessThan0~4_combout ),
+	.datad(!\LessThan0~8_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.dataf(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add1~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~3 .extended_lut = "off";
+defparam \Add1~3 .lut_mask = 64'hC9996CCC36669333;
+defparam \Add1~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N0
+cyclonev_lcell_comb \Add3~46 (
+// Equation(s):
+// \Add3~46_combout  = ( !\Add1~3_combout  & ( !\Operation~combout  $ (((((!\Add1~1_combout ) # (\ShiftRight0~4_combout )) # (\Add1~4_combout )) # (\Add0~1_sumout ))) ) ) # ( \Add1~3_combout  & ( !\Operation~combout  $ ((((!\ShiftRight0~5_combout ) # 
+// ((!\Add1~1_combout ) # (\ShiftRight0~4_combout ))) # (\Add0~1_sumout ))) ) )
+
+	.dataa(!\Operation~combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\ShiftRight0~5_combout ),
+	.datad(!\ShiftRight0~4_combout ),
+	.datae(!\Add1~3_combout ),
+	.dataf(!\Add1~1_combout ),
+	.datag(!\Add1~4_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~46_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~46 .extended_lut = "on";
+defparam \Add3~46 .lut_mask = 64'h5555555595555955;
+defparam \Add3~46 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N30
+cyclonev_lcell_comb \ShiftRight0~2 (
+// Equation(s):
+// \ShiftRight0~2_combout  = ( \Extract_IN2|ShiftLeft0~10_combout  & ( (\Add1~4_combout  & ((\Extract_IN1|ShiftLeft0~12_combout ) # (\LessThan0~3_combout ))) ) ) # ( !\Extract_IN2|ShiftLeft0~10_combout  & ( (\Add1~4_combout  & (!\LessThan0~3_combout  & 
+// \Extract_IN1|ShiftLeft0~12_combout )) ) )
+
+	.dataa(!\Add1~4_combout ),
+	.datab(!\LessThan0~3_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~12_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|ShiftLeft0~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~2 .extended_lut = "off";
+defparam \ShiftRight0~2 .lut_mask = 64'h0404040415151515;
+defparam \ShiftRight0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N33
+cyclonev_lcell_comb \ShiftRight0~1 (
+// Equation(s):
+// \ShiftRight0~1_combout  = (!\Add1~4_combout  & ((!\LessThan0~3_combout  & ((!\Extract_IN1|ShiftLeft0~9_combout ))) # (\LessThan0~3_combout  & (!\Extract_IN2|ShiftLeft0~9_combout ))))
+
+	.dataa(!\Add1~4_combout ),
+	.datab(!\LessThan0~3_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~9_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~9_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~1 .extended_lut = "off";
+defparam \ShiftRight0~1 .lut_mask = 64'hA820A820A820A820;
+defparam \ShiftRight0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N12
+cyclonev_lcell_comb \ShiftRight0~3 (
+// Equation(s):
+// \ShiftRight0~3_combout  = (!\Add1~3_combout  & ((!\ShiftRight0~1_combout ))) # (\Add1~3_combout  & (\ShiftRight0~2_combout ))
+
+	.dataa(gnd),
+	.datab(!\Add1~3_combout ),
+	.datac(!\ShiftRight0~2_combout ),
+	.datad(!\ShiftRight0~1_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~3 .extended_lut = "off";
+defparam \ShiftRight0~3 .lut_mask = 64'hCF03CF03CF03CF03;
+defparam \ShiftRight0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N21
+cyclonev_lcell_comb \Add3~20 (
+// Equation(s):
+// \Add3~20_combout  = ( \ShiftRight0~0_combout  & ( \ShiftRight0~3_combout  & ( !\Operation~combout  $ ((((!\Add1~1_combout ) # (\Add0~5_sumout )) # (\Add0~1_sumout ))) ) ) ) # ( !\ShiftRight0~0_combout  & ( \ShiftRight0~3_combout  & ( \Operation~combout  ) 
+// ) ) # ( \ShiftRight0~0_combout  & ( !\ShiftRight0~3_combout  & ( \Operation~combout  ) ) ) # ( !\ShiftRight0~0_combout  & ( !\ShiftRight0~3_combout  & ( \Operation~combout  ) ) )
+
+	.dataa(!\Operation~combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add1~1_combout ),
+	.datad(!\Add0~5_sumout ),
+	.datae(!\ShiftRight0~0_combout ),
+	.dataf(!\ShiftRight0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~20 .extended_lut = "off";
+defparam \Add3~20 .lut_mask = 64'h5555555555555955;
+defparam \Add3~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N48
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~7 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~7_combout  = ( \Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( (\Extract_IN1|Add0~25_sumout  & !\Extract_IN1|LBD1|EndPosition[1]~0_combout ) ) ) # ( !\Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( 
+// (\Extract_IN1|LBD1|EndPosition[1]~0_combout  & \Extract_IN1|Add0~21_sumout ) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~7 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~7 .lut_mask = 64'h0303030344444444;
+defparam \Extract_IN1|ShiftLeft0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y10_N39
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~11 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~11_combout  = ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( (\Extract_IN1|Add0~25_sumout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout ) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~11 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~11 .lut_mask = 64'h0000000044444444;
+defparam \Extract_IN1|ShiftLeft0~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N18
+cyclonev_lcell_comb \ShiftRight0~8 (
+// Equation(s):
+// \ShiftRight0~8_combout  = ( \Extract_IN1|ShiftLeft0~11_combout  & ( \Extract_IN2|ShiftLeft0~5_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~4_combout ))) ) ) ) # ( 
+// \Extract_IN1|ShiftLeft0~11_combout  & ( !\Extract_IN2|ShiftLeft0~5_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN1|Add3~0_combout  & !\Extract_IN1|ShiftLeft0~4_combout ))) ) ) )
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|Add3~0_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~11_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~8 .extended_lut = "off";
+defparam \ShiftRight0~8 .lut_mask = 64'h0000080000000008;
+defparam \ShiftRight0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N42
+cyclonev_lcell_comb \Add3~27 (
+// Equation(s):
+// \Add3~27_combout  = ( \Add1~1_combout  & ( (!\Add1~3_combout  & ((\ShiftRight0~5_combout ))) # (\Add1~3_combout  & (\ShiftRight0~8_combout )) ) ) # ( !\Add1~1_combout  & ( (!\Add1~4_combout  & \Add1~3_combout ) ) )
+
+	.dataa(!\Add1~4_combout ),
+	.datab(!\ShiftRight0~8_combout ),
+	.datac(!\ShiftRight0~5_combout ),
+	.datad(!\Add1~3_combout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~27_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~27 .extended_lut = "off";
+defparam \Add3~27 .lut_mask = 64'h00AA00AA0F330F33;
+defparam \Add3~27 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N48
+cyclonev_lcell_comb \Add3~28 (
+// Equation(s):
+// \Add3~28_combout  = ( \Add3~27_combout  & ( !\Operation~combout  $ (((!\ShiftRight0~0_combout ) # ((\Add0~5_sumout ) # (\Add0~1_sumout )))) ) ) # ( !\Add3~27_combout  & ( \Operation~combout  ) )
+
+	.dataa(!\ShiftRight0~0_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~5_sumout ),
+	.datad(!\Operation~combout ),
+	.datae(gnd),
+	.dataf(!\Add3~27_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~28_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~28 .extended_lut = "off";
+defparam \Add3~28 .lut_mask = 64'h00FF00FF40BF40BF;
+defparam \Add3~28 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N24
+cyclonev_lcell_comb \Add3~33 (
+// Equation(s):
+// \Add3~33_combout  = ( \Extract_IN1|ShiftLeft0~11_combout  & ( \Extract_IN2|ShiftLeft0~5_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN1|Add3~0_combout  & !\Extract_IN1|ShiftLeft0~4_combout ))) ) ) ) # ( 
+// \Extract_IN1|ShiftLeft0~11_combout  & ( !\Extract_IN2|ShiftLeft0~5_combout  & ( (!\LessThan0~4_combout  & (!\LessThan0~8_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~4_combout ))) ) ) )
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|Add3~0_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~11_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~33_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~33 .extended_lut = "off";
+defparam \Add3~33 .lut_mask = 64'h0000000800000800;
+defparam \Add3~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N24
+cyclonev_lcell_comb \Add3~34 (
+// Equation(s):
+// \Add3~34_combout  = ( \Add3~33_combout  & ( (!\Add1~3_combout  & (\ShiftRight0~2_combout  & (\Add1~1_combout ))) # (\Add1~3_combout  & (((!\ShiftRight0~1_combout ) # (\Add1~1_combout )))) ) ) # ( !\Add3~33_combout  & ( (!\Add1~3_combout  & 
+// (\ShiftRight0~2_combout  & (\Add1~1_combout ))) # (\Add1~3_combout  & (((!\Add1~1_combout  & !\ShiftRight0~1_combout )))) ) )
+
+	.dataa(!\ShiftRight0~2_combout ),
+	.datab(!\Add1~3_combout ),
+	.datac(!\Add1~1_combout ),
+	.datad(!\ShiftRight0~1_combout ),
+	.datae(gnd),
+	.dataf(!\Add3~33_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~34_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~34 .extended_lut = "off";
+defparam \Add3~34 .lut_mask = 64'h3404340437073707;
+defparam \Add3~34 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N51
+cyclonev_lcell_comb \Add3~35 (
+// Equation(s):
+// \Add3~35_combout  = ( \Operation~combout  & ( (!\ShiftRight0~0_combout ) # (((!\Add3~34_combout ) # (\Add0~5_sumout )) # (\Add0~1_sumout )) ) ) # ( !\Operation~combout  & ( (\ShiftRight0~0_combout  & (!\Add0~1_sumout  & (\Add3~34_combout  & 
+// !\Add0~5_sumout ))) ) )
+
+	.dataa(!\ShiftRight0~0_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add3~34_combout ),
+	.datad(!\Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Operation~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~35_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~35 .extended_lut = "off";
+defparam \Add3~35 .lut_mask = 64'h04000400FBFFFBFF;
+defparam \Add3~35 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N33
+cyclonev_lcell_comb \ShiftRight0~9 (
+// Equation(s):
+// \ShiftRight0~9_combout  = ( \Add0~9_sumout  ) # ( !\Add0~9_sumout  & ( ((\Add0~1_sumout ) # (\ShiftRight0~7_combout )) # (\Add0~5_sumout ) ) )
+
+	.dataa(!\Add0~5_sumout ),
+	.datab(gnd),
+	.datac(!\ShiftRight0~7_combout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~9 .extended_lut = "off";
+defparam \ShiftRight0~9 .lut_mask = 64'h5FFF5FFFFFFFFFFF;
+defparam \ShiftRight0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N27
+cyclonev_lcell_comb \ShiftRight0~10 (
+// Equation(s):
+// \ShiftRight0~10_combout  = ( \Add1~1_combout  & ( (!\Add1~3_combout  & \Add3~33_combout ) ) ) # ( !\Add1~1_combout  & ( (!\Add1~3_combout  & ((!\ShiftRight0~1_combout ))) # (\Add1~3_combout  & (\ShiftRight0~2_combout )) ) )
+
+	.dataa(!\ShiftRight0~2_combout ),
+	.datab(!\Add1~3_combout ),
+	.datac(!\Add3~33_combout ),
+	.datad(!\ShiftRight0~1_combout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~10 .extended_lut = "off";
+defparam \ShiftRight0~10 .lut_mask = 64'hDD11DD110C0C0C0C;
+defparam \ShiftRight0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N45
+cyclonev_lcell_comb \Add3~40 (
+// Equation(s):
+// \Add3~40_combout  = ( \ShiftRight0~5_combout  & ( (!\Add1~1_combout  & ((!\Add1~4_combout ) # ((\Add1~3_combout )))) # (\Add1~1_combout  & (((\ShiftRight0~8_combout  & !\Add1~3_combout )))) ) ) # ( !\ShiftRight0~5_combout  & ( (!\Add1~3_combout  & 
+// ((!\Add1~1_combout  & (!\Add1~4_combout )) # (\Add1~1_combout  & ((\ShiftRight0~8_combout ))))) ) )
+
+	.dataa(!\Add1~4_combout ),
+	.datab(!\ShiftRight0~8_combout ),
+	.datac(!\Add1~1_combout ),
+	.datad(!\Add1~3_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~40_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~40 .extended_lut = "off";
+defparam \Add3~40 .lut_mask = 64'hA300A300A3F0A3F0;
+defparam \Add3~40 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y11_N39
+cyclonev_lcell_comb \Add3~41 (
+// Equation(s):
+// \Add3~41_combout  = ( \ShiftRight0~0_combout  & ( !\Operation~combout  $ ((((!\Add3~40_combout ) # (\Add0~1_sumout )) # (\Add0~5_sumout ))) ) ) # ( !\ShiftRight0~0_combout  & ( \Operation~combout  ) )
+
+	.dataa(!\Add0~5_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add3~40_combout ),
+	.datad(!\Operation~combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~41_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~41 .extended_lut = "off";
+defparam \Add3~41 .lut_mask = 64'h00FF00FF08F708F7;
+defparam \Add3~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N0
+cyclonev_lcell_comb \Add3~38 (
+// Equation(s):
+// \Add3~38_cout  = CARRY(( (!\ShiftRight0~9_combout  & (!\ShiftRight0~10_combout  & (!\IN2[7]~input_o  $ (!\IN1[7]~input_o )))) # (\ShiftRight0~9_combout  & (!\IN2[7]~input_o  $ ((!\IN1[7]~input_o )))) ) + ( \Add3~41_combout  ) + ( !VCC ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(!\ShiftRight0~9_combout ),
+	.datac(!\IN1[7]~input_o ),
+	.datad(!\ShiftRight0~10_combout ),
+	.datae(gnd),
+	.dataf(!\Add3~41_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\Add3~38_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~38 .extended_lut = "off";
+defparam \Add3~38 .lut_mask = 64'h0000FF0000005A12;
+defparam \Add3~38 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N3
+cyclonev_lcell_comb \Add3~31 (
+// Equation(s):
+// \Add3~31_cout  = CARRY(( \Add3~35_combout  ) + ( GND ) + ( \Add3~38_cout  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add3~35_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add3~38_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\Add3~31_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~31 .extended_lut = "off";
+defparam \Add3~31 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \Add3~31 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N6
+cyclonev_lcell_comb \Add3~22 (
+// Equation(s):
+// \Add3~22_sumout  = SUM(( \Add3~28_combout  ) + ( (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~11_combout )) ) + ( \Add3~31_cout  ))
+// \Add3~23  = CARRY(( \Add3~28_combout  ) + ( (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~11_combout )) ) + ( \Add3~31_cout  ))
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\Extract_IN1|Add3~0_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~11_combout ),
+	.datad(!\Add3~28_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add3~31_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~22_sumout ),
+	.cout(\Add3~23 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~22 .extended_lut = "off";
+defparam \Add3~22 .lut_mask = 64'h0000FEFE000000FF;
+defparam \Add3~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N9
+cyclonev_lcell_comb \Add3~1 (
+// Equation(s):
+// \Add3~1_sumout  = SUM(( \Add3~20_combout  ) + ( (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~7_combout )) ) + ( \Add3~23  ))
+// \Add3~2  = CARRY(( \Add3~20_combout  ) + ( (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & \Extract_IN1|ShiftLeft0~7_combout )) ) + ( \Add3~23  ))
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\Extract_IN1|Add3~0_combout ),
+	.datac(!\Add3~20_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|ShiftLeft0~7_combout ),
+	.datag(gnd),
+	.cin(\Add3~23 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~1_sumout ),
+	.cout(\Add3~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~1 .extended_lut = "off";
+defparam \Add3~1 .lut_mask = 64'h0000FFEE00000F0F;
+defparam \Add3~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N12
+cyclonev_lcell_comb \Add3~5 (
+// Equation(s):
+// \Add3~5_sumout  = SUM(( (!\LessThan0~3_combout  & (((\Extract_IN2|ShiftLeft0~10_combout )))) # (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & ((\Extract_IN1|ShiftLeft0~10_combout )))) ) + ( \Add3~46_combout  ) + ( \Add3~2  ))
+// \Add3~6  = CARRY(( (!\LessThan0~3_combout  & (((\Extract_IN2|ShiftLeft0~10_combout )))) # (\LessThan0~3_combout  & (\Extract_IN1|Add3~0_combout  & ((\Extract_IN1|ShiftLeft0~10_combout )))) ) + ( \Add3~46_combout  ) + ( \Add3~2  ))
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\Extract_IN1|Add3~0_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~10_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~10_combout ),
+	.datae(gnd),
+	.dataf(!\Add3~46_combout ),
+	.datag(gnd),
+	.cin(\Add3~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~5_sumout ),
+	.cout(\Add3~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~5 .extended_lut = "off";
+defparam \Add3~5 .lut_mask = 64'h0000FF0000000A1B;
+defparam \Add3~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N15
+cyclonev_lcell_comb \Add3~9 (
+// Equation(s):
+// \Add3~9_sumout  = SUM(( \LM[6]~0_combout  ) + ( \Add3~25_combout  ) + ( \Add3~6  ))
+// \Add3~10  = CARRY(( \LM[6]~0_combout  ) + ( \Add3~25_combout  ) + ( \Add3~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\LM[6]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add3~25_combout ),
+	.datag(gnd),
+	.cin(\Add3~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~9_sumout ),
+	.cout(\Add3~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~9 .extended_lut = "off";
+defparam \Add3~9 .lut_mask = 64'h0000FF0000000F0F;
+defparam \Add3~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N18
+cyclonev_lcell_comb \Add3~13 (
+// Equation(s):
+// \Add3~13_sumout  = SUM(( VCC ) + ( !\IN2[7]~input_o  $ (!\IN1[7]~input_o  $ (((!\ShiftRight0~6_combout  & \Add3~26_combout )))) ) + ( \Add3~10  ))
+// \Add3~14  = CARRY(( VCC ) + ( !\IN2[7]~input_o  $ (!\IN1[7]~input_o  $ (((!\ShiftRight0~6_combout  & \Add3~26_combout )))) ) + ( \Add3~10  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(!\ShiftRight0~6_combout ),
+	.datac(!\IN1[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add3~26_combout ),
+	.datag(gnd),
+	.cin(\Add3~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~13_sumout ),
+	.cout(\Add3~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~13 .extended_lut = "off";
+defparam \Add3~13 .lut_mask = 64'h0000A5690000FFFF;
+defparam \Add3~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N21
+cyclonev_lcell_comb \Add3~17 (
+// Equation(s):
+// \Add3~17_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN1[7]~input_o ) ) + ( GND ) + ( \Add3~14  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN1[7]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add3~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add3~17_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~17 .extended_lut = "off";
+defparam \Add3~17 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add3~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N0
+cyclonev_lcell_comb \Add5~17 (
+// Equation(s):
+// \Add5~17_sumout  = SUM(( \Add3~17_sumout  ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~5_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~4_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|ShiftLeft0~4_combout )))) ) + ( !VCC ))
+// \Add5~18  = CARRY(( \Add3~17_sumout  ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~5_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~4_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|ShiftLeft0~4_combout )))) ) + ( !VCC ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datad(!\Add3~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~17_sumout ),
+	.cout(\Add5~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~17 .extended_lut = "off";
+defparam \Add5~17 .lut_mask = 64'h0000F870000000FF;
+defparam \Add5~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N3
+cyclonev_lcell_comb \Add5~21 (
+// Equation(s):
+// \Add5~21_sumout  = SUM(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~7_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~6_combout )))) # (\LessThan0~4_combout  & (((\Extract_IN1|ShiftLeft0~6_combout )))) ) 
+// + ( GND ) + ( \Add5~18  ))
+// \Add5~22  = CARRY(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~7_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~6_combout )))) # (\LessThan0~4_combout  & (((\Extract_IN1|ShiftLeft0~6_combout )))) ) + ( 
+// GND ) + ( \Add5~18  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datad(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~21_sumout ),
+	.cout(\Add5~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~21 .extended_lut = "off";
+defparam \Add5~21 .lut_mask = 64'h0000FFFF0000078F;
+defparam \Add5~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N6
+cyclonev_lcell_comb \Add5~13 (
+// Equation(s):
+// \Add5~13_sumout  = SUM(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~3_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~2_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|ShiftLeft0~2_combout )))) ) + ( \Add5~22  ))
+// \Add5~14  = CARRY(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|ShiftLeft0~3_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|ShiftLeft0~2_combout )))) # (\LessThan0~4_combout  & (((\Extract_IN1|ShiftLeft0~2_combout 
+// )))) ) + ( \Add5~22  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|ShiftLeft0~2_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|ShiftLeft0~3_combout ),
+	.datag(gnd),
+	.cin(\Add5~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~13_sumout ),
+	.cout(\Add5~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~13 .extended_lut = "off";
+defparam \Add5~13 .lut_mask = 64'h0000F87000000000;
+defparam \Add5~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N9
+cyclonev_lcell_comb \Add5~9 (
+// Equation(s):
+// \Add5~9_sumout  = SUM(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[1]~1_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[1]~1_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[1]~1_combout )))) ) + ( \Add5~14  ))
+// \Add5~10  = CARRY(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & ((\Extract_IN2|RegimeValue[1]~1_combout ))) # (\LessThan0~8_combout  & (\Extract_IN1|RegimeValue[1]~1_combout )))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[1]~1_combout )))) ) + ( \Add5~14  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN1|RegimeValue[1]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|RegimeValue[1]~1_combout ),
+	.datag(gnd),
+	.cin(\Add5~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~9_sumout ),
+	.cout(\Add5~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~9 .extended_lut = "off";
+defparam \Add5~9 .lut_mask = 64'h0000F87000000000;
+defparam \Add5~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N12
+cyclonev_lcell_comb \Add5~25 (
+// Equation(s):
+// \Add5~25_sumout  = SUM(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (\Extract_IN2|RegimeValue[1]~2_combout )) # (\LessThan0~8_combout  & ((\Extract_IN1|RegimeValue[1]~2_combout ))))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[1]~2_combout )))) ) + ( GND ) + ( \Add5~10  ))
+// \Add5~26  = CARRY(( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (\Extract_IN2|RegimeValue[1]~2_combout )) # (\LessThan0~8_combout  & ((\Extract_IN1|RegimeValue[1]~2_combout ))))) # (\LessThan0~4_combout  & (((\Extract_IN1|RegimeValue[1]~2_combout 
+// )))) ) + ( GND ) + ( \Add5~10  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN2|RegimeValue[1]~2_combout ),
+	.datad(!\Extract_IN1|RegimeValue[1]~2_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~25_sumout ),
+	.cout(\Add5~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~25 .extended_lut = "off";
+defparam \Add5~25 .lut_mask = 64'h0000FFFF0000087F;
+defparam \Add5~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N15
+cyclonev_lcell_comb \Add5~5 (
+// Equation(s):
+// \Add5~5_sumout  = SUM(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (\Extract_IN2|RegimeValue[2]~0_combout )) # (\LessThan0~8_combout  & ((\Extract_IN1|RegimeValue[2]~0_combout ))))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[2]~0_combout )))) ) + ( \Add5~26  ))
+// \Add5~6  = CARRY(( GND ) + ( (!\LessThan0~4_combout  & ((!\LessThan0~8_combout  & (\Extract_IN2|RegimeValue[2]~0_combout )) # (\LessThan0~8_combout  & ((\Extract_IN1|RegimeValue[2]~0_combout ))))) # (\LessThan0~4_combout  & 
+// (((\Extract_IN1|RegimeValue[2]~0_combout )))) ) + ( \Add5~26  ))
+
+	.dataa(!\LessThan0~4_combout ),
+	.datab(!\LessThan0~8_combout ),
+	.datac(!\Extract_IN2|RegimeValue[2]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|RegimeValue[2]~0_combout ),
+	.datag(gnd),
+	.cin(\Add5~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~5_sumout ),
+	.cout(\Add5~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~5 .extended_lut = "off";
+defparam \Add5~5 .lut_mask = 64'h0000F78000000000;
+defparam \Add5~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N18
+cyclonev_lcell_comb \Add5~1 (
+// Equation(s):
+// \Add5~1_sumout  = SUM(( (!\LessThan0~3_combout  & (!\Extract_IN2|Add0~1_sumout )) # (\LessThan0~3_combout  & ((!\Extract_IN1|Add0~1_sumout ))) ) + ( VCC ) + ( \Add5~6  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~1 .extended_lut = "off";
+defparam \Add5~1 .lut_mask = 64'h000000000000ACAC;
+defparam \Add5~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N48
+cyclonev_lcell_comb \LessThan1~0 (
+// Equation(s):
+// \LessThan1~0_combout  = ( \Add5~25_sumout  & ( (\Add5~5_sumout  & ((!\Add5~1_sumout ) # (\Add5~9_sumout ))) ) ) # ( !\Add5~25_sumout  & ( (!\Add5~5_sumout  & ((!\Add5~9_sumout ) # (\Add5~1_sumout ))) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan1~0 .extended_lut = "off";
+defparam \LessThan1~0 .lut_mask = 64'hD0D0D0D00B0B0B0B;
+defparam \LessThan1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N9
+cyclonev_lcell_comb \LS~0 (
+// Equation(s):
+// \LS~0_combout  = (!\LessThan0~3_combout  & (\IN2[7]~input_o )) # (\LessThan0~3_combout  & ((\IN1[7]~input_o )))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(!\IN1[7]~input_o ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LS~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LS~0 .extended_lut = "off";
+defparam \LS~0 .lut_mask = 64'h5353535353535353;
+defparam \LS~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N0
+cyclonev_lcell_comb \Add6~0 (
+// Equation(s):
+// \Add6~0_combout  = ( !\Add5~21_sumout  & ( !\Add5~17_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\Add5~21_sumout ),
+	.dataf(!\Add5~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add6~0 .extended_lut = "off";
+defparam \Add6~0 .lut_mask = 64'hFFFF000000000000;
+defparam \Add6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N30
+cyclonev_lcell_comb \R_O[3]~0 (
+// Equation(s):
+// \R_O[3]~0_combout  = ( \Add5~13_sumout  & ( \Add6~0_combout  & ( (!\Add5~5_sumout  & (!\Add5~9_sumout  & (!\Add5~1_sumout  & !\Add5~25_sumout ))) # (\Add5~5_sumout  & (\Add5~9_sumout  & (\Add5~1_sumout  & \Add5~25_sumout ))) ) ) ) # ( !\Add5~13_sumout  & 
+// ( \Add6~0_combout  & ( (\Add5~5_sumout  & (\Add5~9_sumout  & (\Add5~1_sumout  & \Add5~25_sumout ))) ) ) ) # ( \Add5~13_sumout  & ( !\Add6~0_combout  & ( (!\Add5~5_sumout  & (!\Add5~9_sumout  & (!\Add5~1_sumout  & !\Add5~25_sumout ))) # (\Add5~5_sumout  & 
+// (\Add5~9_sumout  & (\Add5~1_sumout  & \Add5~25_sumout ))) ) ) ) # ( !\Add5~13_sumout  & ( !\Add6~0_combout  & ( (!\Add5~5_sumout  & (!\Add5~9_sumout  & (!\Add5~1_sumout  & !\Add5~25_sumout ))) # (\Add5~5_sumout  & (\Add5~9_sumout  & (\Add5~1_sumout  & 
+// \Add5~25_sumout ))) ) ) )
+
+	.dataa(!\Add5~5_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~25_sumout ),
+	.datae(!\Add5~13_sumout ),
+	.dataf(!\Add6~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[3]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[3]~0 .extended_lut = "off";
+defparam \R_O[3]~0 .lut_mask = 64'h8001800100018001;
+defparam \R_O[3]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N39
+cyclonev_lcell_comb \R_O[2]~1 (
+// Equation(s):
+// \R_O[2]~1_combout  = ( \Add5~25_sumout  & ( !\Add5~5_sumout  $ (((\Add5~1_sumout  & !\Add5~9_sumout ))) ) ) # ( !\Add5~25_sumout  & ( !\Add5~5_sumout  $ (((!\Add5~9_sumout ) # (\Add5~1_sumout ))) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(gnd),
+	.datac(!\Add5~9_sumout ),
+	.datad(!\Add5~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[2]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[2]~1 .extended_lut = "off";
+defparam \R_O[2]~1 .lut_mask = 64'h0AF50AF5AF50AF50;
+defparam \R_O[2]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N27
+cyclonev_lcell_comb \R_O[0]~2 (
+// Equation(s):
+// \R_O[0]~2_combout  = ( \Add5~1_sumout  & ( !\Add5~9_sumout  ) ) # ( !\Add5~1_sumout  & ( \Add5~9_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add5~9_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add5~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[0]~2 .extended_lut = "off";
+defparam \R_O[0]~2 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \R_O[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N36
+cyclonev_lcell_comb \ShiftRight1~0 (
+// Equation(s):
+// \ShiftRight1~0_combout  = ( \Add5~25_sumout  & ( (!\Add5~9_sumout ) # ((!\Add5~1_sumout  & (\Add5~13_sumout )) # (\Add5~1_sumout  & ((\Add5~21_sumout )))) ) ) # ( !\Add5~25_sumout  & ( (!\Add5~9_sumout  & ((!\Add5~1_sumout  & ((\Add5~21_sumout ))) # 
+// (\Add5~1_sumout  & (\Add5~13_sumout )))) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~13_sumout ),
+	.datad(!\Add5~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~0 .extended_lut = "off";
+defparam \ShiftRight1~0 .lut_mask = 64'h048C048CCEDFCEDF;
+defparam \ShiftRight1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N45
+cyclonev_lcell_comb \Add_Mant[6]~0 (
+// Equation(s):
+// \Add_Mant[6]~0_combout  = ( \Add3~9_sumout  & ( (\Add3~5_sumout ) # (\Add3~17_sumout ) ) ) # ( !\Add3~9_sumout  & ( (!\Add3~17_sumout  & \Add3~5_sumout ) ) )
+
+	.dataa(!\Add3~17_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\Add3~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Add3~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add_Mant[6]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add_Mant[6]~0 .extended_lut = "off";
+defparam \Add_Mant[6]~0 .lut_mask = 64'h00AA00AA55FF55FF;
+defparam \Add_Mant[6]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N15
+cyclonev_lcell_comb \ShiftRight1~2 (
+// Equation(s):
+// \ShiftRight1~2_combout  = ( \Add5~17_sumout  & ( (!\Add5~25_sumout  $ (!\Add5~9_sumout )) # (\Add_Mant[6]~0_combout ) ) ) # ( !\Add5~17_sumout  & ( (\Add_Mant[6]~0_combout  & (!\Add5~25_sumout  $ (\Add5~9_sumout ))) ) )
+
+	.dataa(!\Add5~25_sumout ),
+	.datab(gnd),
+	.datac(!\Add5~9_sumout ),
+	.datad(!\Add_Mant[6]~0_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~2 .extended_lut = "off";
+defparam \ShiftRight1~2 .lut_mask = 64'h00A500A55AFF5AFF;
+defparam \ShiftRight1~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N33
+cyclonev_lcell_comb \R_O[1]~3 (
+// Equation(s):
+// \R_O[1]~3_combout  = !\Add5~25_sumout  $ (!\Add5~9_sumout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add5~25_sumout ),
+	.datad(!\Add5~9_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[1]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[1]~3 .extended_lut = "off";
+defparam \R_O[1]~3 .lut_mask = 64'h0FF00FF00FF00FF0;
+defparam \R_O[1]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N36
+cyclonev_lcell_comb \ShiftRight1~1 (
+// Equation(s):
+// \ShiftRight1~1_combout  = ( \Add3~17_sumout  & ( \Add3~5_sumout  & ( (!\R_O[1]~3_combout ) # (\Add3~13_sumout ) ) ) ) # ( !\Add3~17_sumout  & ( \Add3~5_sumout  & ( (!\R_O[1]~3_combout  & (\Add3~1_sumout )) # (\R_O[1]~3_combout  & ((\Add3~9_sumout ))) ) ) 
+// ) # ( \Add3~17_sumout  & ( !\Add3~5_sumout  & ( (\Add3~13_sumout  & \R_O[1]~3_combout ) ) ) ) # ( !\Add3~17_sumout  & ( !\Add3~5_sumout  & ( (!\R_O[1]~3_combout  & (\Add3~1_sumout )) # (\R_O[1]~3_combout  & ((\Add3~9_sumout ))) ) ) )
+
+	.dataa(!\Add3~13_sumout ),
+	.datab(!\Add3~1_sumout ),
+	.datac(!\R_O[1]~3_combout ),
+	.datad(!\Add3~9_sumout ),
+	.datae(!\Add3~17_sumout ),
+	.dataf(!\Add3~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~1 .extended_lut = "off";
+defparam \ShiftRight1~1 .lut_mask = 64'h303F0505303FF5F5;
+defparam \ShiftRight1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N0
+cyclonev_lcell_comb \ShiftRight1~3 (
+// Equation(s):
+// \ShiftRight1~3_combout  = ( \ShiftRight1~1_combout  & ( (!\R_O[2]~1_combout  & ((!\R_O[0]~2_combout ) # ((\ShiftRight1~2_combout )))) # (\R_O[2]~1_combout  & (((\ShiftRight1~0_combout )))) ) ) # ( !\ShiftRight1~1_combout  & ( (!\R_O[2]~1_combout  & 
+// (\R_O[0]~2_combout  & ((\ShiftRight1~2_combout )))) # (\R_O[2]~1_combout  & (((\ShiftRight1~0_combout )))) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[0]~2_combout ),
+	.datac(!\ShiftRight1~0_combout ),
+	.datad(!\ShiftRight1~2_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~3 .extended_lut = "off";
+defparam \ShiftRight1~3 .lut_mask = 64'h052705278DAF8DAF;
+defparam \ShiftRight1~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N6
+cyclonev_lcell_comb \ShiftRight1~4 (
+// Equation(s):
+// \ShiftRight1~4_combout  = (!\R_O[3]~0_combout  & ((\ShiftRight1~3_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout ))
+
+	.dataa(gnd),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\ShiftRight1~3_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~4 .extended_lut = "off";
+defparam \ShiftRight1~4 .lut_mask = 64'h03CF03CF03CF03CF;
+defparam \ShiftRight1~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N42
+cyclonev_lcell_comb \Add_Mant[4]~2 (
+// Equation(s):
+// \Add_Mant[4]~2_combout  = (!\Add3~17_sumout  & ((\Add3~22_sumout ))) # (\Add3~17_sumout  & (\Add3~1_sumout ))
+
+	.dataa(!\Add3~17_sumout ),
+	.datab(!\Add3~1_sumout ),
+	.datac(!\Add3~22_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add_Mant[4]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add_Mant[4]~2 .extended_lut = "off";
+defparam \Add_Mant[4]~2 .lut_mask = 64'h1B1B1B1B1B1B1B1B;
+defparam \Add_Mant[4]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N12
+cyclonev_lcell_comb \ShiftRight1~15 (
+// Equation(s):
+// \ShiftRight1~15_combout  = ( \Add5~25_sumout  & ( (!\Add5~9_sumout  & (\Add_Mant[6]~0_combout )) # (\Add5~9_sumout  & ((\Add_Mant[4]~2_combout ))) ) ) # ( !\Add5~25_sumout  & ( (!\Add5~9_sumout  & ((\Add_Mant[4]~2_combout ))) # (\Add5~9_sumout  & 
+// (\Add_Mant[6]~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add_Mant[6]~0_combout ),
+	.datad(!\Add_Mant[4]~2_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~15 .extended_lut = "off";
+defparam \ShiftRight1~15 .lut_mask = 64'h03CF03CF0C3F0C3F;
+defparam \ShiftRight1~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N6
+cyclonev_lcell_comb \ShiftRight1~11 (
+// Equation(s):
+// \ShiftRight1~11_combout  = ( \Add5~9_sumout  & ( \Add5~17_sumout  & ( (!\Add5~25_sumout  & (((!\Add5~1_sumout )) # (\Add5~13_sumout ))) # (\Add5~25_sumout  & (((\Add5~21_sumout ) # (\Add5~1_sumout )))) ) ) ) # ( !\Add5~9_sumout  & ( \Add5~17_sumout  & ( 
+// (!\Add5~25_sumout  & (((!\Add5~1_sumout ) # (\Add5~21_sumout )))) # (\Add5~25_sumout  & (\Add5~13_sumout  & (!\Add5~1_sumout ))) ) ) ) # ( \Add5~9_sumout  & ( !\Add5~17_sumout  & ( (!\Add5~25_sumout  & (((!\Add5~1_sumout )) # (\Add5~13_sumout ))) # 
+// (\Add5~25_sumout  & (((!\Add5~1_sumout  & \Add5~21_sumout )))) ) ) ) # ( !\Add5~9_sumout  & ( !\Add5~17_sumout  & ( (!\Add5~25_sumout  & (((\Add5~1_sumout  & \Add5~21_sumout )))) # (\Add5~25_sumout  & (\Add5~13_sumout  & (!\Add5~1_sumout ))) ) ) )
+
+	.dataa(!\Add5~13_sumout ),
+	.datab(!\Add5~25_sumout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~21_sumout ),
+	.datae(!\Add5~9_sumout ),
+	.dataf(!\Add5~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~11 .extended_lut = "off";
+defparam \ShiftRight1~11 .lut_mask = 64'h101CC4F4D0DCC7F7;
+defparam \ShiftRight1~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N3
+cyclonev_lcell_comb \ShiftRight1~16 (
+// Equation(s):
+// \ShiftRight1~16_combout  = ( \ShiftRight1~1_combout  & ( (!\R_O[2]~1_combout  & (((\ShiftRight1~15_combout )) # (\R_O[0]~2_combout ))) # (\R_O[2]~1_combout  & (((\ShiftRight1~11_combout )))) ) ) # ( !\ShiftRight1~1_combout  & ( (!\R_O[2]~1_combout  & 
+// (!\R_O[0]~2_combout  & (\ShiftRight1~15_combout ))) # (\R_O[2]~1_combout  & (((\ShiftRight1~11_combout )))) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[0]~2_combout ),
+	.datac(!\ShiftRight1~15_combout ),
+	.datad(!\ShiftRight1~11_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~16 .extended_lut = "off";
+defparam \ShiftRight1~16 .lut_mask = 64'h085D085D2A7F2A7F;
+defparam \ShiftRight1~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N51
+cyclonev_lcell_comb \ulp~3 (
+// Equation(s):
+// \ulp~3_combout  = ( \Add5~25_sumout  & ( (\Add5~1_sumout  & (\Add5~9_sumout  & (!\Add5~21_sumout  & !\Add5~13_sumout ))) ) ) # ( !\Add5~25_sumout  & ( (\Add5~1_sumout  & (!\Add5~9_sumout  & !\Add5~13_sumout )) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~21_sumout ),
+	.datad(!\Add5~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~3 .extended_lut = "off";
+defparam \ulp~3 .lut_mask = 64'h4400440010001000;
+defparam \ulp~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N57
+cyclonev_lcell_comb \ulp~2 (
+// Equation(s):
+// \ulp~2_combout  = ( \Add5~25_sumout  & ( (\Add5~1_sumout  & !\Add5~9_sumout ) ) ) # ( !\Add5~25_sumout  & ( (!\Add5~1_sumout  & \Add5~9_sumout ) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~2 .extended_lut = "off";
+defparam \ulp~2 .lut_mask = 64'h2222222244444444;
+defparam \ulp~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N3
+cyclonev_lcell_comb \ulp~4 (
+// Equation(s):
+// \ulp~4_combout  = ( \R_O[3]~0_combout  & ( (\ulp~3_combout  & (!\ShiftRight1~11_combout  & ((!\ulp~2_combout ) # (!\Add_Mant[4]~2_combout )))) ) ) # ( !\R_O[3]~0_combout  & ( (!\ulp~2_combout ) # (!\Add_Mant[4]~2_combout ) ) )
+
+	.dataa(!\ulp~3_combout ),
+	.datab(!\ShiftRight1~11_combout ),
+	.datac(!\ulp~2_combout ),
+	.datad(!\Add_Mant[4]~2_combout ),
+	.datae(gnd),
+	.dataf(!\R_O[3]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~4 .extended_lut = "off";
+defparam \ulp~4 .lut_mask = 64'hFFF0FFF044404440;
+defparam \ulp~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N24
+cyclonev_lcell_comb \ulp~7 (
+// Equation(s):
+// \ulp~7_combout  = ( !\Add3~17_sumout  & ( (!\Add5~9_sumout  & ((!\Add5~25_sumout ) # ((!\Add3~1_sumout  & ((!\Add3~22_sumout ) # (\Add5~1_sumout )))))) # (\Add5~9_sumout  & (((!\Add3~1_sumout  & ((!\Add3~22_sumout ) # (!\Add5~1_sumout )))) # 
+// (\Add5~25_sumout ))) ) ) # ( \Add3~17_sumout  & ( (!\Add5~9_sumout  & ((!\Add5~25_sumout ) # ((!\Add3~5_sumout  & ((!\Add3~1_sumout ) # (\Add5~1_sumout )))))) # (\Add5~9_sumout  & (((!\Add3~5_sumout  & ((!\Add3~1_sumout ) # (!\Add5~1_sumout )))) # 
+// (\Add5~25_sumout ))) ) )
+
+	.dataa(!\Add5~9_sumout ),
+	.datab(!\Add3~1_sumout ),
+	.datac(!\Add3~5_sumout ),
+	.datad(!\Add5~1_sumout ),
+	.datae(!\Add3~17_sumout ),
+	.dataf(!\Add5~25_sumout ),
+	.datag(!\Add3~22_sumout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~7 .extended_lut = "on";
+defparam \ulp~7 .lut_mask = 64'hEEEAFAEAD5DDD5F5;
+defparam \ulp~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N18
+cyclonev_lcell_comb \ulp~0 (
+// Equation(s):
+// \ulp~0_combout  = ( \Add5~13_sumout  & ( \Add6~0_combout  & ( (!\Add5~5_sumout  & (\Add5~1_sumout  & ((!\Add5~9_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (!\Add5~1_sumout  & ((\Add5~25_sumout ) # (\Add5~9_sumout )))) ) ) ) # ( 
+// !\Add5~13_sumout  & ( \Add6~0_combout  & ( (!\Add5~1_sumout  & (!\Add5~5_sumout  $ (((\Add5~25_sumout ) # (\Add5~9_sumout ))))) # (\Add5~1_sumout  & (!\Add5~5_sumout  & ((!\Add5~9_sumout ) # (!\Add5~25_sumout )))) ) ) ) # ( \Add5~13_sumout  & ( 
+// !\Add6~0_combout  & ( (!\Add5~5_sumout  & (\Add5~1_sumout  & ((!\Add5~9_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (!\Add5~1_sumout  & ((\Add5~25_sumout ) # (\Add5~9_sumout )))) ) ) ) # ( !\Add5~13_sumout  & ( !\Add6~0_combout  & ( 
+// (!\Add5~5_sumout  & (\Add5~1_sumout  & ((!\Add5~9_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (!\Add5~1_sumout  & ((\Add5~25_sumout ) # (\Add5~9_sumout )))) ) ) )
+
+	.dataa(!\Add5~5_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~25_sumout ),
+	.datae(!\Add5~13_sumout ),
+	.dataf(!\Add6~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~0 .extended_lut = "off";
+defparam \ulp~0 .lut_mask = 64'h1A581A589A581A58;
+defparam \ulp~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N24
+cyclonev_lcell_comb \ulp~5 (
+// Equation(s):
+// \ulp~5_combout  = ( \R_O[0]~2_combout  & ( \ShiftRight1~15_combout  & ( (\R_O[2]~1_combout  & \ulp~0_combout ) ) ) ) # ( !\R_O[0]~2_combout  & ( \ShiftRight1~15_combout  & ( (\ulp~0_combout  & ((\ulp~7_combout ) # (\R_O[2]~1_combout ))) ) ) ) # ( 
+// \R_O[0]~2_combout  & ( !\ShiftRight1~15_combout  & ( (!\ulp~7_combout  & (\R_O[2]~1_combout  & ((\ulp~0_combout )))) # (\ulp~7_combout  & (((!\ShiftRight1~1_combout ) # (\ulp~0_combout )))) ) ) ) # ( !\R_O[0]~2_combout  & ( !\ShiftRight1~15_combout  & ( 
+// ((\R_O[2]~1_combout  & \ulp~0_combout )) # (\ulp~7_combout ) ) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\ShiftRight1~1_combout ),
+	.datac(!\ulp~7_combout ),
+	.datad(!\ulp~0_combout ),
+	.datae(!\R_O[0]~2_combout ),
+	.dataf(!\ShiftRight1~15_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~5 .extended_lut = "off";
+defparam \ulp~5 .lut_mask = 64'h0F5F0C5F005F0055;
+defparam \ulp~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N30
+cyclonev_lcell_comb \Add_Mant[7]~1 (
+// Equation(s):
+// \Add_Mant[7]~1_combout  = ( \Add3~9_sumout  & ( (!\Add3~17_sumout ) # (\Add3~13_sumout ) ) ) # ( !\Add3~9_sumout  & ( (\Add3~17_sumout  & \Add3~13_sumout ) ) )
+
+	.dataa(!\Add3~17_sumout ),
+	.datab(gnd),
+	.datac(!\Add3~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add3~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add_Mant[7]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add_Mant[7]~1 .extended_lut = "off";
+defparam \Add_Mant[7]~1 .lut_mask = 64'h05050505AFAFAFAF;
+defparam \Add_Mant[7]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N54
+cyclonev_lcell_comb \ShiftRight1~8 (
+// Equation(s):
+// \ShiftRight1~8_combout  = ( \R_O[0]~2_combout  & ( \Add5~13_sumout  & ( (\Add5~17_sumout ) # (\R_O[1]~3_combout ) ) ) ) # ( !\R_O[0]~2_combout  & ( \Add5~13_sumout  & ( (!\R_O[1]~3_combout  & ((\Add_Mant[7]~1_combout ))) # (\R_O[1]~3_combout  & 
+// (\Add5~21_sumout )) ) ) ) # ( \R_O[0]~2_combout  & ( !\Add5~13_sumout  & ( (!\R_O[1]~3_combout  & \Add5~17_sumout ) ) ) ) # ( !\R_O[0]~2_combout  & ( !\Add5~13_sumout  & ( (!\R_O[1]~3_combout  & ((\Add_Mant[7]~1_combout ))) # (\R_O[1]~3_combout  & 
+// (\Add5~21_sumout )) ) ) )
+
+	.dataa(!\Add5~21_sumout ),
+	.datab(!\Add_Mant[7]~1_combout ),
+	.datac(!\R_O[1]~3_combout ),
+	.datad(!\Add5~17_sumout ),
+	.datae(!\R_O[0]~2_combout ),
+	.dataf(!\Add5~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~8 .extended_lut = "off";
+defparam \ShiftRight1~8 .lut_mask = 64'h353500F035350FFF;
+defparam \ShiftRight1~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y11_N48
+cyclonev_lcell_comb \ShiftRight1~5 (
+// Equation(s):
+// \ShiftRight1~5_combout  = ( \Add5~21_sumout  & ( \Add5~17_sumout  & ( ((!\R_O[0]~2_combout  & ((\Add_Mant[6]~0_combout ))) # (\R_O[0]~2_combout  & (\Add_Mant[7]~1_combout ))) # (\R_O[1]~3_combout ) ) ) ) # ( !\Add5~21_sumout  & ( \Add5~17_sumout  & ( 
+// (!\R_O[0]~2_combout  & (((\Add_Mant[6]~0_combout ) # (\R_O[1]~3_combout )))) # (\R_O[0]~2_combout  & (\Add_Mant[7]~1_combout  & (!\R_O[1]~3_combout ))) ) ) ) # ( \Add5~21_sumout  & ( !\Add5~17_sumout  & ( (!\R_O[0]~2_combout  & (((!\R_O[1]~3_combout  & 
+// \Add_Mant[6]~0_combout )))) # (\R_O[0]~2_combout  & (((\R_O[1]~3_combout )) # (\Add_Mant[7]~1_combout ))) ) ) ) # ( !\Add5~21_sumout  & ( !\Add5~17_sumout  & ( (!\R_O[1]~3_combout  & ((!\R_O[0]~2_combout  & ((\Add_Mant[6]~0_combout ))) # 
+// (\R_O[0]~2_combout  & (\Add_Mant[7]~1_combout )))) ) ) )
+
+	.dataa(!\R_O[0]~2_combout ),
+	.datab(!\Add_Mant[7]~1_combout ),
+	.datac(!\R_O[1]~3_combout ),
+	.datad(!\Add_Mant[6]~0_combout ),
+	.datae(!\Add5~21_sumout ),
+	.dataf(!\Add5~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~5 .extended_lut = "off";
+defparam \ShiftRight1~5 .lut_mask = 64'h10B015B51ABA1FBF;
+defparam \ShiftRight1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N18
+cyclonev_lcell_comb \ulp~1 (
+// Equation(s):
+// \ulp~1_combout  = ( \R_O[0]~2_combout  & ( \ShiftRight1~5_combout  & ( !\ulp~0_combout  ) ) ) # ( !\R_O[0]~2_combout  & ( \ShiftRight1~5_combout  & ( !\ulp~0_combout  ) ) ) # ( \R_O[0]~2_combout  & ( !\ShiftRight1~5_combout  & ( (!\ulp~0_combout  & 
+// ((\ShiftRight1~2_combout ) # (\ShiftRight1~8_combout ))) ) ) ) # ( !\R_O[0]~2_combout  & ( !\ShiftRight1~5_combout  & ( (!\ulp~0_combout  & ((\ShiftRight1~1_combout ) # (\ShiftRight1~8_combout ))) ) ) )
+
+	.dataa(!\ShiftRight1~8_combout ),
+	.datab(!\ulp~0_combout ),
+	.datac(!\ShiftRight1~2_combout ),
+	.datad(!\ShiftRight1~1_combout ),
+	.datae(!\R_O[0]~2_combout ),
+	.dataf(!\ShiftRight1~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~1 .extended_lut = "off";
+defparam \ulp~1 .lut_mask = 64'h44CC4C4CCCCCCCCC;
+defparam \ulp~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N54
+cyclonev_lcell_comb \ulp~6 (
+// Equation(s):
+// \ulp~6_combout  = ( \R_O[3]~0_combout  & ( \ulp~1_combout  ) ) # ( !\R_O[3]~0_combout  & ( \ulp~1_combout  ) ) # ( \R_O[3]~0_combout  & ( !\ulp~1_combout  & ( (!\ulp~4_combout ) # ((!\ulp~5_combout ) # (\Add5~1_sumout )) ) ) ) # ( !\R_O[3]~0_combout  & ( 
+// !\ulp~1_combout  & ( ((!\ulp~4_combout ) # (!\ulp~5_combout )) # (\ShiftRight1~3_combout ) ) ) )
+
+	.dataa(!\ShiftRight1~3_combout ),
+	.datab(!\ulp~4_combout ),
+	.datac(!\ulp~5_combout ),
+	.datad(!\Add5~1_sumout ),
+	.datae(!\R_O[3]~0_combout ),
+	.dataf(!\ulp~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~6 .extended_lut = "off";
+defparam \ulp~6 .lut_mask = 64'hFDFDFCFFFFFFFFFF;
+defparam \ulp~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N30
+cyclonev_lcell_comb \Add8~29 (
+// Equation(s):
+// \Add8~29_sumout  = SUM(( (\ulp~6_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~16_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) ) + ( (!\R_O[3]~0_combout  & ((\ShiftRight1~16_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) + ( !VCC 
+// ))
+// \Add8~30  = CARRY(( (\ulp~6_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~16_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) ) + ( (!\R_O[3]~0_combout  & ((\ShiftRight1~16_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) + ( !VCC ))
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~16_combout ),
+	.datad(!\ulp~6_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~29_sumout ),
+	.cout(\Add8~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~29 .extended_lut = "off";
+defparam \Add8~29 .lut_mask = 64'h0000E2E20000001D;
+defparam \Add8~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N33
+cyclonev_lcell_comb \Add8~1 (
+// Equation(s):
+// \Add8~1_sumout  = SUM(( (!\R_O[3]~0_combout  & ((\ShiftRight1~3_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) + ( GND ) + ( \Add8~30  ))
+// \Add8~2  = CARRY(( (!\R_O[3]~0_combout  & ((\ShiftRight1~3_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) + ( GND ) + ( \Add8~30  ))
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(gnd),
+	.datad(!\ShiftRight1~3_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add8~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~1_sumout ),
+	.cout(\Add8~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~1 .extended_lut = "off";
+defparam \Add8~1 .lut_mask = 64'h0000FFFF000011DD;
+defparam \Add8~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N42
+cyclonev_lcell_comb \sft_tmp_o_rnd[0]~0 (
+// Equation(s):
+// \sft_tmp_o_rnd[0]~0_combout  = ( \LessThan1~0_combout  & ( \Add8~29_sumout  ) ) # ( !\LessThan1~0_combout  & ( (!\R_O[3]~0_combout  & (\ShiftRight1~16_combout )) # (\R_O[3]~0_combout  & ((\Add8~29_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~16_combout ),
+	.datad(!\Add8~29_sumout ),
+	.datae(gnd),
+	.dataf(!\LessThan1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_o_rnd[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_o_rnd[0]~0 .extended_lut = "off";
+defparam \sft_tmp_o_rnd[0]~0 .lut_mask = 64'h0C3F0C3F00FF00FF;
+defparam \sft_tmp_o_rnd[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N0
+cyclonev_lcell_comb \Add9~1 (
+// Equation(s):
+// \Add9~1_sumout  = SUM(( !\sft_tmp_o_rnd[0]~0_combout  ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & ((!\ShiftRight1~4_combout ))) # (\R_O[3]~0_combout  & (!\Add8~1_sumout )))) # (\LessThan1~0_combout  & (((!\Add8~1_sumout )))) ) + ( !VCC ))
+// \Add9~2  = CARRY(( !\sft_tmp_o_rnd[0]~0_combout  ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & ((!\ShiftRight1~4_combout ))) # (\R_O[3]~0_combout  & (!\Add8~1_sumout )))) # (\LessThan1~0_combout  & (((!\Add8~1_sumout )))) ) + ( !VCC ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add8~1_sumout ),
+	.datad(!\sft_tmp_o_rnd[0]~0_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~1_sumout ),
+	.cout(\Add9~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~1 .extended_lut = "off";
+defparam \Add9~1 .lut_mask = 64'h0000078F0000FF00;
+defparam \Add9~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N33
+cyclonev_lcell_comb \sft_tmp_oN~0 (
+// Equation(s):
+// \sft_tmp_oN~0_combout  = ( \Add8~1_sumout  & ( (!\LS~0_combout  & (((\ShiftRight1~4_combout )) # (\LessThan1~0_combout ))) # (\LS~0_combout  & (((\Add9~1_sumout )))) ) ) # ( !\Add8~1_sumout  & ( (!\LS~0_combout  & (!\LessThan1~0_combout  & 
+// (\ShiftRight1~4_combout ))) # (\LS~0_combout  & (((\Add9~1_sumout )))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\ShiftRight1~4_combout ),
+	.datad(!\Add9~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Add8~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~0 .extended_lut = "off";
+defparam \sft_tmp_oN~0 .lut_mask = 64'h083B083B4C7F4C7F;
+defparam \sft_tmp_oN~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N54
+cyclonev_lcell_comb \ShiftRight1~6 (
+// Equation(s):
+// \ShiftRight1~6_combout  = ( \Add5~25_sumout  & ( (!\Add5~1_sumout  & (\Add5~9_sumout )) # (\Add5~1_sumout  & ((!\Add5~9_sumout ) # (\Add5~13_sumout ))) ) ) # ( !\Add5~25_sumout  & ( (!\Add5~1_sumout  & (!\Add5~9_sumout  & \Add5~13_sumout )) # 
+// (\Add5~1_sumout  & (\Add5~9_sumout )) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~6 .extended_lut = "off";
+defparam \ShiftRight1~6 .lut_mask = 64'h1919191967676767;
+defparam \ShiftRight1~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N15
+cyclonev_lcell_comb \ShiftRight1~7 (
+// Equation(s):
+// \ShiftRight1~7_combout  = ( \ShiftRight1~6_combout  & ( (!\R_O[3]~0_combout  & (((\ShiftRight1~5_combout ) # (\R_O[2]~1_combout )))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) ) # ( !\ShiftRight1~6_combout  & ( (!\R_O[3]~0_combout  & 
+// (((!\R_O[2]~1_combout  & \ShiftRight1~5_combout )))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )) ) )
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(!\ShiftRight1~5_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~7 .extended_lut = "off";
+defparam \ShiftRight1~7 .lut_mask = 64'h11D111D11DDD1DDD;
+defparam \ShiftRight1~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N36
+cyclonev_lcell_comb \Add8~5 (
+// Equation(s):
+// \Add8~5_sumout  = SUM(( GND ) + ( \ShiftRight1~7_combout  ) + ( \Add8~2  ))
+// \Add8~6  = CARRY(( GND ) + ( \ShiftRight1~7_combout  ) + ( \Add8~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~7_combout ),
+	.datag(gnd),
+	.cin(\Add8~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~5_sumout ),
+	.cout(\Add8~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~5 .extended_lut = "off";
+defparam \Add8~5 .lut_mask = 64'h0000FF0000000000;
+defparam \Add8~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N3
+cyclonev_lcell_comb \Add9~5 (
+// Equation(s):
+// \Add9~5_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & ((!\ShiftRight1~7_combout ))) # (\R_O[3]~0_combout  & (!\Add8~5_sumout )))) # (\LessThan1~0_combout  & (((!\Add8~5_sumout )))) ) + ( \Add9~2  ))
+// \Add9~6  = CARRY(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & ((!\ShiftRight1~7_combout ))) # (\R_O[3]~0_combout  & (!\Add8~5_sumout )))) # (\LessThan1~0_combout  & (((!\Add8~5_sumout )))) ) + ( \Add9~2  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add8~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~7_combout ),
+	.datag(gnd),
+	.cin(\Add9~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~5_sumout ),
+	.cout(\Add9~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~5 .extended_lut = "off";
+defparam \Add9~5 .lut_mask = 64'h0000078F00000000;
+defparam \Add9~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N36
+cyclonev_lcell_comb \sft_tmp_oN~1 (
+// Equation(s):
+// \sft_tmp_oN~1_combout  = ( \ShiftRight1~7_combout  & ( (!\LS~0_combout  & ((!\LessThan1~0_combout ) # ((\Add8~5_sumout )))) # (\LS~0_combout  & (((\Add9~5_sumout )))) ) ) # ( !\ShiftRight1~7_combout  & ( (!\LS~0_combout  & (\LessThan1~0_combout  & 
+// (\Add8~5_sumout ))) # (\LS~0_combout  & (((\Add9~5_sumout )))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\Add8~5_sumout ),
+	.datad(!\Add9~5_sumout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~1 .extended_lut = "off";
+defparam \sft_tmp_oN~1 .lut_mask = 64'h043704378CBF8CBF;
+defparam \sft_tmp_oN~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N0
+cyclonev_lcell_comb \ShiftRight1~9 (
+// Equation(s):
+// \ShiftRight1~9_combout  = ( \Add5~25_sumout  & ( (!\Add5~1_sumout ) # (!\Add5~9_sumout ) ) ) # ( !\Add5~25_sumout  & ( (\Add5~9_sumout ) # (\Add5~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~9 .extended_lut = "off";
+defparam \ShiftRight1~9 .lut_mask = 64'h0FFF0FFFFFF0FFF0;
+defparam \ShiftRight1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N45
+cyclonev_lcell_comb \ShiftRight1~10 (
+// Equation(s):
+// \ShiftRight1~10_combout  = ( \Add5~1_sumout  & ( ((!\R_O[2]~1_combout  & (\ShiftRight1~8_combout )) # (\R_O[2]~1_combout  & ((\ShiftRight1~9_combout )))) # (\R_O[3]~0_combout ) ) ) # ( !\Add5~1_sumout  & ( (!\R_O[3]~0_combout  & ((!\R_O[2]~1_combout  & 
+// (\ShiftRight1~8_combout )) # (\R_O[2]~1_combout  & ((!\ShiftRight1~9_combout ))))) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~8_combout ),
+	.datad(!\ShiftRight1~9_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~10 .extended_lut = "off";
+defparam \ShiftRight1~10 .lut_mask = 64'h4C084C083B7F3B7F;
+defparam \ShiftRight1~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N42
+cyclonev_lcell_comb \ShiftRight1~17 (
+// Equation(s):
+// \ShiftRight1~17_combout  = ( \Add5~13_sumout  & ( \Add6~0_combout  & ( (!\Add5~5_sumout  & ((!\Add5~9_sumout ) # ((!\Add5~1_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (((\Add5~25_sumout ) # (\Add5~1_sumout )) # (\Add5~9_sumout ))) ) ) ) # ( 
+// !\Add5~13_sumout  & ( \Add6~0_combout  & ( (!\Add5~9_sumout  & (((\Add5~25_sumout ) # (\Add5~1_sumout )))) # (\Add5~9_sumout  & (((!\Add5~1_sumout ) # (!\Add5~25_sumout )) # (\Add5~5_sumout ))) ) ) ) # ( \Add5~13_sumout  & ( !\Add6~0_combout  & ( 
+// (!\Add5~5_sumout  & ((!\Add5~9_sumout ) # ((!\Add5~1_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (((\Add5~25_sumout ) # (\Add5~1_sumout )) # (\Add5~9_sumout ))) ) ) ) # ( !\Add5~13_sumout  & ( !\Add6~0_combout  & ( (!\Add5~5_sumout  & 
+// ((!\Add5~9_sumout ) # ((!\Add5~1_sumout ) # (!\Add5~25_sumout )))) # (\Add5~5_sumout  & (((\Add5~25_sumout ) # (\Add5~1_sumout )) # (\Add5~9_sumout ))) ) ) )
+
+	.dataa(!\Add5~5_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~25_sumout ),
+	.datae(!\Add5~13_sumout ),
+	.dataf(!\Add6~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~17 .extended_lut = "off";
+defparam \ShiftRight1~17 .lut_mask = 64'hBFFDBFFD3FFDBFFD;
+defparam \ShiftRight1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N12
+cyclonev_lcell_comb \ShiftRight1~18 (
+// Equation(s):
+// \ShiftRight1~18_combout  = (!\R_O[3]~0_combout  & ((\ShiftRight1~8_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout ))
+
+	.dataa(!\Add5~1_sumout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(gnd),
+	.datad(!\ShiftRight1~8_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~18 .extended_lut = "off";
+defparam \ShiftRight1~18 .lut_mask = 64'h11DD11DD11DD11DD;
+defparam \ShiftRight1~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N39
+cyclonev_lcell_comb \Add8~9 (
+// Equation(s):
+// \Add8~9_sumout  = SUM(( GND ) + ( (!\R_O[2]~1_combout  & (((\ShiftRight1~18_combout )))) # (\R_O[2]~1_combout  & (!\ShiftRight1~17_combout  $ ((\Add5~1_sumout )))) ) + ( \Add8~6  ))
+// \Add8~10  = CARRY(( GND ) + ( (!\R_O[2]~1_combout  & (((\ShiftRight1~18_combout )))) # (\R_O[2]~1_combout  & (!\ShiftRight1~17_combout  $ ((\Add5~1_sumout )))) ) + ( \Add8~6  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\ShiftRight1~17_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~18_combout ),
+	.datag(gnd),
+	.cin(\Add8~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~9_sumout ),
+	.cout(\Add8~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~9 .extended_lut = "off";
+defparam \Add8~9 .lut_mask = 64'h0000BE1400000000;
+defparam \Add8~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N6
+cyclonev_lcell_comb \Add9~9 (
+// Equation(s):
+// \Add9~9_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~10_combout )) # (\R_O[3]~0_combout  & ((!\Add8~9_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~9_sumout )))) ) + ( \Add9~6  ))
+// \Add9~10  = CARRY(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~10_combout )) # (\R_O[3]~0_combout  & ((!\Add8~9_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~9_sumout )))) ) + ( \Add9~6  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~10_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add8~9_sumout ),
+	.datag(gnd),
+	.cin(\Add9~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~9_sumout ),
+	.cout(\Add9~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~9 .extended_lut = "off";
+defparam \Add9~9 .lut_mask = 64'h0000087F00000000;
+defparam \Add9~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N39
+cyclonev_lcell_comb \sft_tmp_oN~2 (
+// Equation(s):
+// \sft_tmp_oN~2_combout  = ( \Add8~9_sumout  & ( (!\LS~0_combout  & (((\ShiftRight1~10_combout )) # (\LessThan1~0_combout ))) # (\LS~0_combout  & (((\Add9~9_sumout )))) ) ) # ( !\Add8~9_sumout  & ( (!\LS~0_combout  & (!\LessThan1~0_combout  & 
+// ((\ShiftRight1~10_combout )))) # (\LS~0_combout  & (((\Add9~9_sumout )))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\Add9~9_sumout ),
+	.datad(!\ShiftRight1~10_combout ),
+	.datae(gnd),
+	.dataf(!\Add8~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~2 .extended_lut = "off";
+defparam \sft_tmp_oN~2 .lut_mask = 64'h038B038B47CF47CF;
+defparam \sft_tmp_oN~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N42
+cyclonev_lcell_comb \Add8~13 (
+// Equation(s):
+// \Add8~13_sumout  = SUM(( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~11_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( GND ) + ( \Add8~10  ))
+// \Add8~14  = CARRY(( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~11_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( GND ) + ( \Add8~10  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\ShiftRight1~11_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add8~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~13_sumout ),
+	.cout(\Add8~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~13 .extended_lut = "off";
+defparam \Add8~13 .lut_mask = 64'h0000FFFF0000078F;
+defparam \Add8~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N24
+cyclonev_lcell_comb \ShiftRight1~19 (
+// Equation(s):
+// \ShiftRight1~19_combout  = ( \Add5~13_sumout  & ( \Add5~25_sumout  & ( (!\Add5~9_sumout  & (\Add5~5_sumout )) # (\Add5~9_sumout  & (((\Add5~5_sumout  & \Add5~21_sumout )) # (\Add5~1_sumout ))) ) ) ) # ( !\Add5~13_sumout  & ( \Add5~25_sumout  & ( 
+// (!\Add5~5_sumout  & (\Add5~9_sumout  & (\Add5~1_sumout ))) # (\Add5~5_sumout  & (((\Add5~9_sumout  & \Add5~21_sumout )) # (\Add5~1_sumout ))) ) ) ) # ( \Add5~13_sumout  & ( !\Add5~25_sumout  & ( (!\Add5~5_sumout  & (\Add5~1_sumout  & ((\Add5~21_sumout ) # 
+// (\Add5~9_sumout )))) # (\Add5~5_sumout  & (((\Add5~1_sumout )) # (\Add5~9_sumout ))) ) ) ) # ( !\Add5~13_sumout  & ( !\Add5~25_sumout  & ( (!\Add5~9_sumout  & (\Add5~1_sumout  & ((\Add5~21_sumout ) # (\Add5~5_sumout )))) # (\Add5~9_sumout  & 
+// (\Add5~5_sumout )) ) ) )
+
+	.dataa(!\Add5~5_sumout ),
+	.datab(!\Add5~9_sumout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(!\Add5~21_sumout ),
+	.datae(!\Add5~13_sumout ),
+	.dataf(!\Add5~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~19 .extended_lut = "off";
+defparam \ShiftRight1~19 .lut_mask = 64'h151D171F07174757;
+defparam \ShiftRight1~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N9
+cyclonev_lcell_comb \Add9~13 (
+// Equation(s):
+// \Add9~13_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~19_combout )) # (\R_O[3]~0_combout  & ((!\Add8~13_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~13_sumout )))) ) + ( \Add9~10  ))
+// \Add9~14  = CARRY(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~19_combout )) # (\R_O[3]~0_combout  & ((!\Add8~13_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~13_sumout )))) ) + ( \Add9~10  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~19_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add8~13_sumout ),
+	.datag(gnd),
+	.cin(\Add9~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~13_sumout ),
+	.cout(\Add9~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~13 .extended_lut = "off";
+defparam \Add9~13 .lut_mask = 64'h0000087F00000000;
+defparam \Add9~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N48
+cyclonev_lcell_comb \sft_tmp_oN~3 (
+// Equation(s):
+// \sft_tmp_oN~3_combout  = ( \Add9~13_sumout  & ( ((!\LessThan1~0_combout  & ((\ShiftRight1~19_combout ))) # (\LessThan1~0_combout  & (\Add8~13_sumout ))) # (\LS~0_combout ) ) ) # ( !\Add9~13_sumout  & ( (!\LS~0_combout  & ((!\LessThan1~0_combout  & 
+// ((\ShiftRight1~19_combout ))) # (\LessThan1~0_combout  & (\Add8~13_sumout )))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\Add8~13_sumout ),
+	.datad(!\ShiftRight1~19_combout ),
+	.datae(gnd),
+	.dataf(!\Add9~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~3 .extended_lut = "off";
+defparam \sft_tmp_oN~3 .lut_mask = 64'h048C048C37BF37BF;
+defparam \sft_tmp_oN~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N54
+cyclonev_lcell_comb \ShiftRight1~12 (
+// Equation(s):
+// \ShiftRight1~12_combout  = ( \Add5~1_sumout  & ( ((\ShiftRight1~0_combout ) # (\R_O[3]~0_combout )) # (\R_O[2]~1_combout ) ) ) # ( !\Add5~1_sumout  & ( (!\R_O[2]~1_combout  & (!\R_O[3]~0_combout  & \ShiftRight1~0_combout )) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add5~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~12 .extended_lut = "off";
+defparam \ShiftRight1~12 .lut_mask = 64'h080808087F7F7F7F;
+defparam \ShiftRight1~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N45
+cyclonev_lcell_comb \Add8~17 (
+// Equation(s):
+// \Add8~17_sumout  = SUM(( GND ) + ( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~0_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( \Add8~14  ))
+// \Add8~18  = CARRY(( GND ) + ( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~0_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( \Add8~14  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~0_combout ),
+	.datag(gnd),
+	.cin(\Add8~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~17_sumout ),
+	.cout(\Add8~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~17 .extended_lut = "off";
+defparam \Add8~17 .lut_mask = 64'h0000F87000000000;
+defparam \Add8~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N12
+cyclonev_lcell_comb \Add9~17 (
+// Equation(s):
+// \Add9~17_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~12_combout )) # (\R_O[3]~0_combout  & ((!\Add8~17_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~17_sumout )))) ) + ( \Add9~14  ))
+// \Add9~18  = CARRY(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~12_combout )) # (\R_O[3]~0_combout  & ((!\Add8~17_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~17_sumout )))) ) + ( \Add9~14  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~12_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add8~17_sumout ),
+	.datag(gnd),
+	.cin(\Add9~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~17_sumout ),
+	.cout(\Add9~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~17 .extended_lut = "off";
+defparam \Add9~17 .lut_mask = 64'h0000087F00000000;
+defparam \Add9~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N24
+cyclonev_lcell_comb \sft_tmp_oN~4 (
+// Equation(s):
+// \sft_tmp_oN~4_combout  = ( \LS~0_combout  & ( \Add9~17_sumout  ) ) # ( !\LS~0_combout  & ( (!\LessThan1~0_combout  & ((\ShiftRight1~12_combout ))) # (\LessThan1~0_combout  & (\Add8~17_sumout )) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\Add9~17_sumout ),
+	.datac(!\Add8~17_sumout ),
+	.datad(!\ShiftRight1~12_combout ),
+	.datae(gnd),
+	.dataf(!\LS~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~4 .extended_lut = "off";
+defparam \sft_tmp_oN~4 .lut_mask = 64'h05AF05AF33333333;
+defparam \sft_tmp_oN~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N48
+cyclonev_lcell_comb \Add8~21 (
+// Equation(s):
+// \Add8~21_sumout  = SUM(( GND ) + ( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~6_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( \Add8~18  ))
+// \Add8~22  = CARRY(( GND ) + ( (!\R_O[2]~1_combout  & ((!\R_O[3]~0_combout  & ((\ShiftRight1~6_combout ))) # (\R_O[3]~0_combout  & (\Add5~1_sumout )))) # (\R_O[2]~1_combout  & (((\Add5~1_sumout )))) ) + ( \Add8~18  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~6_combout ),
+	.datag(gnd),
+	.cin(\Add8~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~21_sumout ),
+	.cout(\Add8~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~21 .extended_lut = "off";
+defparam \Add8~21 .lut_mask = 64'h0000F87000000000;
+defparam \Add8~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N9
+cyclonev_lcell_comb \ShiftRight1~13 (
+// Equation(s):
+// \ShiftRight1~13_combout  = ( \ShiftRight1~6_combout  & ( ((!\R_O[2]~1_combout  & !\R_O[3]~0_combout )) # (\Add5~1_sumout ) ) ) # ( !\ShiftRight1~6_combout  & ( (\Add5~1_sumout  & ((\R_O[3]~0_combout ) # (\R_O[2]~1_combout ))) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~13 .extended_lut = "off";
+defparam \ShiftRight1~13 .lut_mask = 64'h070707078F8F8F8F;
+defparam \ShiftRight1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N15
+cyclonev_lcell_comb \Add9~21 (
+// Equation(s):
+// \Add9~21_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~13_combout )) # (\R_O[3]~0_combout  & ((!\Add8~21_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~21_sumout )))) ) + ( \Add9~18  ))
+// \Add9~22  = CARRY(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~13_combout )) # (\R_O[3]~0_combout  & ((!\Add8~21_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~21_sumout )))) ) + ( \Add9~18  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~13_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add8~21_sumout ),
+	.datag(gnd),
+	.cin(\Add9~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~21_sumout ),
+	.cout(\Add9~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~21 .extended_lut = "off";
+defparam \Add9~21 .lut_mask = 64'h0000087F00000000;
+defparam \Add9~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N51
+cyclonev_lcell_comb \sft_tmp_oN~5 (
+// Equation(s):
+// \sft_tmp_oN~5_combout  = ( \Add9~21_sumout  & ( ((!\LessThan1~0_combout  & ((\ShiftRight1~13_combout ))) # (\LessThan1~0_combout  & (\Add8~21_sumout ))) # (\LS~0_combout ) ) ) # ( !\Add9~21_sumout  & ( (!\LS~0_combout  & ((!\LessThan1~0_combout  & 
+// ((\ShiftRight1~13_combout ))) # (\LessThan1~0_combout  & (\Add8~21_sumout )))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\Add8~21_sumout ),
+	.datad(!\ShiftRight1~13_combout ),
+	.datae(gnd),
+	.dataf(!\Add9~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~5 .extended_lut = "off";
+defparam \sft_tmp_oN~5 .lut_mask = 64'h048C048C37BF37BF;
+defparam \sft_tmp_oN~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N57
+cyclonev_lcell_comb \ShiftRight1~14 (
+// Equation(s):
+// \ShiftRight1~14_combout  = ( \Add5~1_sumout  & ( (!\R_O[2]~1_combout  & ((\ShiftRight1~9_combout ) # (\R_O[3]~0_combout ))) # (\R_O[2]~1_combout  & (!\R_O[3]~0_combout )) ) ) # ( !\Add5~1_sumout  & ( (!\R_O[2]~1_combout  & (!\R_O[3]~0_combout  & 
+// !\ShiftRight1~9_combout )) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(gnd),
+	.datad(!\ShiftRight1~9_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight1~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight1~14 .extended_lut = "off";
+defparam \ShiftRight1~14 .lut_mask = 64'h8800880066EE66EE;
+defparam \ShiftRight1~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N51
+cyclonev_lcell_comb \Add8~25 (
+// Equation(s):
+// \Add8~25_sumout  = SUM(( GND ) + ( (!\R_O[2]~1_combout  & (!\Add5~1_sumout  $ (((\ShiftRight1~9_combout ) # (\R_O[3]~0_combout ))))) # (\R_O[2]~1_combout  & (!\R_O[3]~0_combout  & (\Add5~1_sumout ))) ) + ( \Add8~22  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\Add5~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight1~9_combout ),
+	.datag(gnd),
+	.cin(\Add8~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add8~25_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add8~25 .extended_lut = "off";
+defparam \Add8~25 .lut_mask = 64'h000079F100000000;
+defparam \Add8~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N18
+cyclonev_lcell_comb \Add9~25 (
+// Equation(s):
+// \Add9~25_sumout  = SUM(( GND ) + ( (!\LessThan1~0_combout  & ((!\R_O[3]~0_combout  & (!\ShiftRight1~14_combout )) # (\R_O[3]~0_combout  & ((!\Add8~25_sumout ))))) # (\LessThan1~0_combout  & (((!\Add8~25_sumout )))) ) + ( \Add9~22  ))
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\R_O[3]~0_combout ),
+	.datac(!\ShiftRight1~14_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add8~25_sumout ),
+	.datag(gnd),
+	.cin(\Add9~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add9~25_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add9~25 .extended_lut = "off";
+defparam \Add9~25 .lut_mask = 64'h0000087F00000000;
+defparam \Add9~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N30
+cyclonev_lcell_comb \sft_tmp_oN~6 (
+// Equation(s):
+// \sft_tmp_oN~6_combout  = ( \Add9~25_sumout  & ( ((!\LessThan1~0_combout  & (\ShiftRight1~14_combout )) # (\LessThan1~0_combout  & ((\Add8~25_sumout )))) # (\LS~0_combout ) ) ) # ( !\Add9~25_sumout  & ( (!\LS~0_combout  & ((!\LessThan1~0_combout  & 
+// (\ShiftRight1~14_combout )) # (\LessThan1~0_combout  & ((\Add8~25_sumout ))))) ) )
+
+	.dataa(!\LessThan1~0_combout ),
+	.datab(!\LS~0_combout ),
+	.datac(!\ShiftRight1~14_combout ),
+	.datad(!\Add8~25_sumout ),
+	.datae(gnd),
+	.dataf(!\Add9~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~6 .extended_lut = "off";
+defparam \sft_tmp_oN~6 .lut_mask = 64'h084C084C3B7F3B7F;
+defparam \sft_tmp_oN~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X22_Y9_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/vsim.wlf b/Individual_Project/Posit_Adder/Core_Arithmetic/vsim.wlf
index 3e1619371dab48b051d0e27a144a2d0c30ce0a52..48dc75ba10a30558195742c3517c3f5dc22650ae 100644
Binary files a/Individual_Project/Posit_Adder/Core_Arithmetic/vsim.wlf and b/Individual_Project/Posit_Adder/Core_Arithmetic/vsim.wlf differ
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib.qdb b/Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib.qdb
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deleted file mode 100644
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qdb b/Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib1_26.qdb
similarity index 92%
rename from Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_lib1_1.qdb
rename to Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib1_26.qdb
index e9b342a610f85af9bbba2e5c67ecfd8ed61b922a..d420e15104272c78aea9fbffbdd7e2de81a34717 100644
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index 0000000000000000000000000000000000000000..7df9a3b01ea3e9a31651db7f62e59dbe0650cd7d
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib1_26.qtl b/Individual_Project/Posit_Adder/Core_Arithmetic/work/_lib1_26.qtl
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index 0000000000000000000000000000000000000000..61bcdc8c81429ca88a2ecac052d78f25630d8c99
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diff --git a/Individual_Project/Posit_Adder_Arithmetic.sv b/Individual_Project/Posit_Adder_Arithmetic.sv
deleted file mode 100644
index 51c8e77031c052f14698f6cff6bb72f51b732551..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Adder_Arithmetic.sv
+++ /dev/null
@@ -1,140 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: Posit Adder Arithmetic
-//            :
-// File name  : Posit_Adder_Arithmetic.sv
-//            :
-// Description: Mantissa addition and subtraction
-//            : exponent and regime computation
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.0 01/12/2022
-/////////////////////////////////////////////////////////////////////
-
-function [31:0] log2;
-    input reg [31:0] value;
-        begin
-            value = value-1;
-            for (log2=0; value>0; log2=log2+1)
-                value = value>>1;
-        end
-endfunction
-
-module Alignment #(parameter N = 8, parameter ES = 3, parameter RS = log2(N)) 
-(
-    input logic signed [N-2:0] InRemain1, InRemain2,
-    input logic Sign1, Sign2,
-    input logic signed [RS:0] RegimeValue1, RegimeValue2,
-    input logic [ES-1:0] Exponent1, Exponent2,
-    input logic [N-ES+2:0] Mantissa1, Mantissa2,
-    output logic [N-1:0] E_diff,
-    output logic [N:0] Add_Mant,
-    output logic signed [ES+RS:0] LE_O,
-    output logic [ES-1:0] E_O,
-    output logic signed [RS:0] R_O
-);
-    logic Operation;
-    // components to corresponding logic, L - Large S - Small
-    logic LS, SS;
-    logic [RS:0] LR, SR;
-    logic LRC, SRC;
-    logic [ES-1:0]LE, SE;
-    logic [N-ES+2:0]LM, SM, SM_tmp;
-    // logic SS;
-    // logic [RS:0]SR;
-    // logic SRC;
-    // logic [ES-1:0]SE;
-    // logic [N-ES+2:0]SM, SM_tmp;
-
-    logic Greater_Than;
-    logic signed [RS:0] R_diff;
-    logic Mant_Ovf;
-    logic signed [RS:0] shift;
-    logic [ES+RS:0] LE_ON;
-    //Leading_Bit_Detector_8b #(.N(N), .ES(ES)) LBD_Mant (.*);
-
-always_comb
-begin
-    // Confirm the operation (s1 XNOR s2)
-    Operation = Sign1 ~^ Sign2 ;
-
-
-    // Find the greater input
-    Greater_Than = (InRemain1[N-2:0] >  InRemain2[N-2:0])? 1'b1 : 1'b0;
-    // Assign components to corresponding logic, L - Large S - Small
-    LS = Greater_Than ? Sign1 : Sign2;
-    LR = Greater_Than ? RegimeValue1 : RegimeValue2;
-    LRC = Greater_Than? InRemain1[N-2] : InRemain2[N-2];
-    LE = Greater_Than ? Exponent1 : Exponent2;
-    LM = Greater_Than ? Mantissa1 : Mantissa2;
-
-    SS = Greater_Than ? Sign2 : Sign1;
-    SR = Greater_Than ? RegimeValue2 : RegimeValue1;
-    SE = Greater_Than ? Exponent2 : Exponent1;
-    SM = Greater_Than ? Mantissa2 : Mantissa1;
-
-
-    // Mantissa Addition
-    /*
-    find regime difference, 
-    when both of them are +ve, the difference is RV1 - RV2
-    when RV1 +ve but RV2 -ve, the difference is RV1 + RV2
-    when RV1 -ve and RV2 also -ve, still RV1 - RV2
-    */
-
-    // if (RegimeValue1 >= 0 && RegimeValue2 >= 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 >= 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    // else if (RegimeValue1 < 0 && RegimeValue2 < 0)
-    //     R_diff = RegimeValue1 - RegimeValue2;
-    R_diff = RegimeValue1 - RegimeValue2;
-
-    /*
-    after the R_diff found, remember that the regime contributes into the exponent
-    as (Useed ^ RegimeValue) where Useed = 2^(2^ES) 
-    so the E_diff is (R_diff x log2(useed) + LE - SE)
-    the reason why it is R_diff x log2(useed) is
-    the exponent (2 ^ what)is what we want to find
-    for exponent bits, it is the difference
-    for regime bits, they are log2(Useed ^ RegimeValue) which is RegimeValue x (2^ES)
-    */
-    E_diff = (R_diff*(2**(ES))) + (LE - SE); 
-
-    SM_tmp = SM >> E_diff;
-    Add_Mant = Operation ?  LM + SM_tmp : LM - SM_tmp;
-
-    // check for Mantissa Overflow
-    Mant_Ovf = Add_Mant[N];
-    Add_Mant = Mant_Ovf ? Add_Mant : (Add_Mant << 1);
-
-    /*
-     In the case of subtraction between two close numbers
-     some MSBs may lost, it is useful to detect the 
-     Leading ONE and left shift accordingly
-    */
-    
-    //Add_Mant = Add_Mant << shift;
-
-    
-    // Compute regime and exponent of final result
-    
-    /* 
-    The exponent is mainly based on the larger input
-    taking overflow and left shift into account
-    */
-    LE_O = {LR, LE} + Mant_Ovf; //- shift;
-
-    LE_ON =  LE_O[RS+ES] ? (-LE_O) : LE_O;
-
-    E_O = (LE_O[ES+RS] & (|LE_ON[ES-1:0])) ? (~LE_O[ES-1:0] + 1'b1) : LE_ON[ES-1:0];
-
-    //R_O = LE_O[ES+RS:ES];
-    R_O = !LE_O[ES+RS]|(LE_O[ES+RS]&(|LE_ON[ES-1 : 0])) ? (LE_ON[ES+RS-1 : ES] +1'b1) : LE_ON[ES+RS-1 : ES];
-end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Extraction.sv b/Individual_Project/Posit_Extraction.sv
deleted file mode 100644
index 167c4bf2b47280e5f15f2c82e0a0dea555cfc0d5..0000000000000000000000000000000000000000
--- a/Individual_Project/Posit_Extraction.sv
+++ /dev/null
@@ -1,73 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: DataExtraction
-//            :
-// File name  : Posit_Extraction.sv
-//            :
-// Description: Extracting posit element from n bits binary number
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.1 30/11/2022
-/////////////////////////////////////////////////////////////////////
-
-// `ifndef log_2
-// `define log_2
-// `include "log_2.sv"
-
-function [31:0] log2;
-    input reg [31:0] value;
-        begin
-            value = value-1;
-            for (log2=0; value>0; log2=log2+1)
-                value = value>>1;
-        end
-endfunction
-
-module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
-(
-    input logic signed [N-1:0] In,
-    output logic Sign,
-    output logic signed [RS:0] RegimeValue,
-    output logic [ES-1:0] Exponent,
-    output logic [N-ES+2:0] Mantissa,
-    output logic signed [N-2:0] InRemain
-);
-
-//logic signed [N-2:0] InRemain;
-logic RegimeCheck; 
-logic [RS:0] EndPosition;
-logic signed [N-2:0] ShiftedRemain;
-logic [(N-ES+2)-1-(N-ES-2)-1:0] ZERO = '0;
-int i;
-Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
-
-always_comb
-begin
-    // Sign Bit Extraction
-    Sign = In[N-1];
-    InRemain = Sign ? (~In[N-2:0] + 1'b1) : In[N-2:0]; // if sign bit is true, then 2's compliment
-
-    // Regime Bits Extraction
-    /*
-     There is a Leading_Bit_Detector defined before the always_comb block 
-     which takes the input without sign bit as module input and outputs 
-     EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
-    */
-    if(RegimeCheck == 1'b1)
-        RegimeValue = EndPosition - 1;
-    else if (RegimeCheck == 0)
-        RegimeValue = -EndPosition;
-
-    //Exponent Bits Extraction
-    ShiftedRemain = InRemain << (EndPosition + 1 );
-    Exponent = ShiftedRemain[N-1:((N-1)-ES)];
-
-    //Mantissa Bits Extraction
-    Mantissa = {1'b1, ShiftedRemain[N-ES-2:0], ZERO};
-end
-endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv b/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv
index 807a5d00ff9098afaff5782c6da75da72bf12ca5..75aee70f69ac2ac3dab8e92424268734956b1000 100644
--- a/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv
+++ b/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv
@@ -16,31 +16,23 @@
 // Revision   : Version 1.0 21/11/2022
 /////////////////////////////////////////////////////////////////////
 
-module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = log2(N))
+module Leading_Bit_Detector #( parameter N = 8, parameter ES = 3, parameter RS = $clog2(N))
 (
     input logic signed [N-2:0] InRemain,
     output logic signed [RS:0] EndPosition,
     output logic RegimeCheck
 );
 
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
 //logic RegimeCheck; 
 int i;
+logic signed [RS:0] EP;
 
 always_comb
 begin
     RegimeCheck = InRemain[N-2]; //the MSB of InRemain (In[6])is the number to be checked
     
-    EndPosition = '0;
-    EndPosition = EndPosition + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
+    EP = '0;
+    EndPosition = EP + 1'b1; // initial EP starts from InRemain[1] as InRemain[0] is RC
 
     for(i = 1; i < (N-2); i++) 
         begin
diff --git a/Individual_Project/Posit_Multiplier/Pin1_8bit.txt b/Individual_Project/Posit_Multiplier/Pin1_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4f5ea0548198f759ae9ad076eda235d13bbb40b4
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Pin1_8bit.txt
@@ -0,0 +1,65496 @@
+00000000
+00000001
+00000010
+00000011
+00000100
+00000101
+00000110
+00000111
+00001000
+00001001
+00001010
+00001011
+00001100
+00001101
+00001110
+00001111
+00010000
+00010001
+00010010
+00010011
+00010100
+00010101
+00010110
+00010111
+00011000
+00011001
+00011010
+00011011
+00011100
+00011101
+00011110
+00011111
+00100000
+00100001
+00100010
+00100011
+00100100
+00100101
+00100110
+00100111
+00101000
+00101001
+00101010
+00101011
+00101100
+00101101
+00101110
+00101111
+00110000
+00110001
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diff --git a/Individual_Project/Posit_Multiplier/Pin2_8bit.txt b/Individual_Project/Posit_Multiplier/Pin2_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..bf39a985ef195ff8218ac224c598a6c49af0b28f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Pin2_8bit.txt
@@ -0,0 +1,65278 @@
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diff --git a/Individual_Project/Posit_Multiplier/Posit_Extraction.sv b/Individual_Project/Posit_Multiplier/Posit_Extraction.sv
index 7e27896b4be232d468f2dc7ac6897899564a31d0..08de8de2fdeba4a7748f6e4fb56d69d29e02f412 100644
--- a/Individual_Project/Posit_Multiplier/Posit_Extraction.sv
+++ b/Individual_Project/Posit_Multiplier/Posit_Extraction.sv
@@ -26,10 +26,12 @@ module Data_Extraction #( parameter N = 8, parameter ES = 3, parameter RS = $clo
     output logic signed [RS+1:0] RegimeValue,
     output logic [ES-1:0] Exponent,
     output logic [N-ES+2:0] Mantissa,
-    output logic signed [N-2:0] InRemain
+    output logic signed [N-2:0] InRemain,
+    output logic inf,
+    output logic zero
 );
 
-assign Sign = In[N-1];
+logic zero_check;
 logic RegimeCheck; 
 logic signed [RS:0] EndPosition;
 logic signed [N-2:0] ShiftedRemain;
@@ -39,7 +41,13 @@ Leading_Bit_Detector #(.N(N), .ES(ES)) LBD1 (.*);
 
 always_comb
 begin
+    //infinity & zero check;
+    zero_check = |In[N-2:0];
+    inf = In[N-1] & (~zero_check);
+    zero = ~(In[N-1] | zero_check);
+
     // Sign Bit Extraction
+    Sign = In[N-1];
 
     // if sign bit is 1, then 2's compliment
     if (Sign)
@@ -54,11 +62,10 @@ begin
      which takes the input without sign bit as module input and outputs 
      EndPosition of Regime Bits and RegimeCheck which is the 1st bit of Regime bits
     */
-    if(RegimeCheck == 1'b1)
+    if(RegimeCheck)
         RegimeValue = EndPosition - 1'b1;
-    else if (RegimeCheck == 1'b0)
+    else 
         RegimeValue = -EndPosition;
-
     //Exponent Bits Extraction
     ShiftedRemain = InRemain << (EndPosition + 1'b1 );
     Exponent = ShiftedRemain[N-2:((N-1)-ES)];
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier.cr.mti b/Individual_Project/Posit_Multiplier/Posit_Multiplier.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..6c7e55f110e0643dbbf29ee0a5bda9e4c5ef7e8c
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier.cr.mti
@@ -0,0 +1,22 @@
+{H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Posit_Multiplier_tb
+
+Top level modules:
+	Posit_Multiplier_tb
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Leading_Bit_Detector
+
+Top level modules:
+	Leading_Bit_Detector
+
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv} {1 {vlog -work work -sv -stats=none {H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module Data_Extraction
+
+Top level modules:
+	Data_Extraction
+
+} {} {}}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.mpf b/Individual_Project/Posit_Multiplier/Posit_Multiplier.mpf
similarity index 93%
rename from Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.mpf
rename to Individual_Project/Posit_Multiplier/Posit_Multiplier.mpf
index bc32cd5889fd7c580e725aba96321ab61f4bcbe7..8a3b37bae94ef7ea4e783f97d213ff9bb840e1a3 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Arithmetic.mpf
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier.mpf
@@ -220,7 +220,7 @@ Resolution = ps
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 200 ns
+RunLength = 1 us
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -410,13 +410,15 @@ ConcurrentFileLimit = 40
 Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
-Project_Files_Count = 3
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Leading_Bit_Detector_8b.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1675369552 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Arithmetic_tb.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1675376482 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Posit_Adder_Arithmetic.sv
-Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1675363700 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Files_Count = 4
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677009779 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1677007322 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1676404420 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1677001075 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier.qpf b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..690292bdc8c0abf0fc8fa494d6eccea7d08c2423
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 16:36:10  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "16:36:10  February 14, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "Posit_Multiplier"
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier.qsf b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..434f1d22ca0d6be2b4e4223b85a895514af464c4
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qsf
@@ -0,0 +1,63 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 16:36:10  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Posit_Multiplier_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY Posit_Multiplier
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:36:10  FEBRUARY 14, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name SYSTEMVERILOG_FILE Leading_Bit_Detector.sv
+set_global_assignment -name SYSTEMVERILOG_FILE Posit_Extraction.sv
+set_global_assignment -name SYSTEMVERILOG_FILE Posit_Multiplier.sv
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier.qws b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qws
new file mode 100644
index 0000000000000000000000000000000000000000..bf1e54df58bd9f1aa6a3ade70cee4e5a4b948a1e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/Posit_Multiplier.qws differ
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv b/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv
index 3b2b319f460fb292e5930c8510bb07fa2d3744c9..8fbb5bdc8c59eb094088dcca23357e317a2388dd 100644
--- a/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv
@@ -12,7 +12,7 @@
 // Author     : Xiaoan(Jasper) He 
 //            : xh2g20@soton.ac.uk
 //
-// Revision   : Version 1.0 08/02/2023
+// Revision   : Version 1.1 21/02/2023
 /////////////////////////////////////////////////////////////////////
 
 module Posit_Multiplier #(parameter N = 8, parameter ES = 3, parameter RS = $clog2(N)) 
@@ -20,15 +20,15 @@ module Posit_Multiplier #(parameter N = 8, parameter ES = 3, parameter RS = $clo
     input logic[N-1:0] IN1, IN2,
     output logic [N-1:0] OUT
 );
-
+logic inf1, inf2, zero1, zero2, inf, zero;
 logic Sign1, Sign2;
 logic signed [N-2:0] InRemain1, InRemain2;
 logic signed [RS+1:0] RegimeValue1,RegimeValue2;
 logic [ES-1:0] Exponent1, Exponent2;
 logic [N-ES+2:0] Mantissa1, Mantissa2;
 
-Data_Extraction #(.N(N), .ES(ES)) Extract_IN1 (.In(IN1), .Sign(Sign1), .RegimeValue(RegimeValue1), .Exponent(Exponent1), .Mantissa(Mantissa1), .InRemain(InRemain1));
-Data_Extraction #(.N(N), .ES(ES)) Extract_IN2 (.In(IN2), .Sign(Sign2), .RegimeValue(RegimeValue2), .Exponent(Exponent2), .Mantissa(Mantissa2), .InRemain(InRemain2));
+Data_Extraction #(.N(N), .ES(ES)) Extract_IN1 (.In(IN1), .Sign(Sign1), .RegimeValue(RegimeValue1), .Exponent(Exponent1), .Mantissa(Mantissa1), .InRemain(InRemain1), .inf(inf1), .zero(zero1));
+Data_Extraction #(.N(N), .ES(ES)) Extract_IN2 (.In(IN2), .Sign(Sign2), .RegimeValue(RegimeValue2), .Exponent(Exponent2), .Mantissa(Mantissa2), .InRemain(InRemain2), .inf(inf2), .zero(zero2));
 
 /*  the output of multipilcation between 2 N-bit inputs is 2N bit long
     '+1' is used for overflow check
@@ -50,6 +50,9 @@ logic [N-1:0] sft_tmp_oN;
 
 always_comb
 begin
+    //  check infinity and zero
+    inf = inf1 | inf2;
+	zero = zero1 | zero2;
 
     Operation = Sign1 ^ Sign2;
     //  Mantissa Multiplication Handling
@@ -74,7 +77,10 @@ begin
 
     tmp_o = { {N{~Total_EO[ES+RS+1]}}, Total_EO[ES+RS+1], E_O, Mult_Mant_N[(2*N-1)-1:(((2*N-1)-1)-(N-1-ES))+1], Mult_Mant_N[(((2*N-1)-1)-(N-1-ES)):(((2*N-1)-1)-(N-1-ES))-1], |Mult_Mant_N[(((2*N-1)-1)-(N-1-ES))-2:0]};
     sft_tmp_o = {tmp_o, {N{1'b0}}};
-    sft_tmp_o = sft_tmp_o >> R_O;
+    if (R_O[RS])
+        sft_tmp_o = sft_tmp_o >> {RS{1'b1}};
+    else
+        sft_tmp_o = sft_tmp_o >> R_O; 
 
     L = sft_tmp_o[N+4]; 
     G = sft_tmp_o[N+3]; 
@@ -94,6 +100,7 @@ begin
     //Final Output
     
     sft_tmp_oN = Operation ? -sft_tmp_o_rnd : sft_tmp_o_rnd;
-    OUT = {Operation, sft_tmp_oN[N-1:1]};
+    OUT = inf|zero ? {inf,{N-1{1'b0}}} : {Operation, sft_tmp_oN[N-1:1]};
+    //OUT = {Operation, sft_tmp_oN[N-1:1]};
 end
 endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv b/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv
index 5dfb04828ee2cca22ecbee9c4fb1ad42127841e4..3001a7aa0d792999a3cce73d22d2f4329c26bd74 100644
--- a/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv
+++ b/Individual_Project/Posit_Multiplier/Posit_Multiplier_tb.sv
@@ -14,17 +14,8 @@
 //
 // Revision   : Version 1.0 08/02/2023
 /////////////////////////////////////////////////////////////////////
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
 module Posit_Multiplier_tb;
-parameter N = 8, RS = log2(N), ES = 3;
+parameter N = 8, RS = $clog2(N), ES = 3;
 
 //input logic
 logic signed [N-1:0] IN1, IN2;
@@ -32,89 +23,140 @@ logic signed [N-1:0] IN1, IN2;
 //output logic
 logic signed [N-1:0] OUT;
 
-Posit_Multiplier #(.N(N), .ES(ES)) Posit_Adder_testing (.*);
-
-initial 
-    begin
-        #10ns 
-        IN1 = 8'b0_0000000;
-        IN2 = 8'b0_0000000;
-        OUT = 8'b0_0000000;
-
-        #50ns   //  65536 112
-        IN1 = 8'b0_1110_000;
-        IN2 = 8'b0_10_110_11;
-
-        #50ns   // 524288 1024
-        IN1 = 8'b0_1110_011;
-        IN2 = 8'b0_110_010_0;
-
-        #50ns   // 10 12
-        IN1 = 8'b0_10_011_01;
-        IN2 = 8'b0_10_011_10;
+Posit_Multiplier #(.N(N), .ES(ES)) Posit_Mult (.*);
+
+reg clk;
+integer outfile;
+
+reg [N-1:0] data1 [1:65536];
+reg [N-1:0] data2 [1:65536];
+initial $readmemb("Pin1_8bit.txt",data1);
+initial $readmemb("Pin2_8bit.txt",data2);
+
+reg [15:0] i;
+	
+	initial begin
+		// Initialize Inputs
+		IN1 = 0;
+		IN2 = 0;
+		clk = 0;
+		//start = 0;
+	
+		
+		// Wait 100 ns for global reset to finish
+		#100 i=0;
+		//#20 start = 1;
+                #655500 //start = 0;
+		#100;
+		
+		$fclose(outfile);
+		$finish;
+	end
+
+ always #5 clk=~clk;
+
+  always @(posedge clk) begin			
+ 	IN1=data1[i];	
+	IN2=data2[i];
+	if(i==16'hffff)
+  	      $finish;
+	else i = i + 1;
+ end
+
+initial outfile = $fopen("error_8bit.txt", "wb");
+
+reg [N-1:0] result [1:65536];
+initial $readmemb("Pout_8bit_ES4.txt",result);
+reg [N-1:0] diff;
+always @(negedge clk) begin
+	if(1)begin
+     	diff = (result[i-1] > OUT) ? result[i-1]-OUT : OUT-result[i-1];
+     	//$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\n",in1, in2, out,result[i-1],diff);
+     	$fwrite(outfile, "%d\n",diff);
+     	end
+end
+
+// initial 
+//     begin
+//         #10ns 
+//         IN1 = 8'b0_0000000;
+//         IN2 = 8'b0_0000000;
+//         OUT = 8'b0_0000000;
+
+//         #50ns   //  65536 112
+//         IN1 = 8'b00000001;
+//         IN2 = 8'b00000001;
+
+//         #50ns   // 524288 1024
+//         IN1 = 8'b0_1110_011;
+//         IN2 = 8'b0_110_010_0;
+
+//         #50ns   // 10 12
+//         IN1 = 8'b0_10_011_01;
+//         IN2 = 8'b0_10_011_10;
         
-        #50ns   // 40 24
-        IN1 = 8'b0_10_101_01;
-        IN2 = 8'b0_10_100_10;
+//         #50ns   // 40 24
+//         IN1 = 8'b0_10_101_01;
+//         IN2 = 8'b0_10_100_10;
 
-        #50ns   // 0.0234375 0.01953125
-        IN1 = 8'b0_01_010_01;
-        IN2 = 8'b0_10_001_10;
+//         #50ns   // 0.0234375 0.01953125
+//         IN1 = 8'b0_01_010_01;
+//         IN2 = 8'b0_10_001_10;
         
-        #50ns   // 0.125 0.15625
-        IN1 = 8'b0_01_101_00;
-        IN2 = 8'b0_01_101_01;
+//         #50ns   // 0.125 0.15625
+//         IN1 = 8'b0_01_101_00;
+//         IN2 = 8'b0_01_101_01;
         
         
-        // -ve * +ve
-        #50ns   //  -0.0000152587890625  112
-        IN1 = 8'b1_1110_000;
-        IN2 = 8'b0_10_110_11;
-
-        #50ns   // -0.0000019073486328125   1024
-        IN1 = 8'b1_1110_011;
-        IN2 = 8'b0_110_010_0;
-
-        #50ns   // -0.109375 12
-        IN1 = 8'b1_10_011_01;
-        IN2 = 8'b0_10_011_10;
+//         // -ve * +ve
+//         #50ns   //  -0.0000152587890625  112
+//         IN1 = 8'b1_1110_000;
+//         IN2 = 8'b0_10_110_11;
+
+//         #50ns   // -0.0000019073486328125   1024
+//         IN1 = 8'b1_1110_011;
+//         IN2 = 8'b0_110_010_0;
+
+//         #50ns   // -0.109375 12
+//         IN1 = 8'b1_10_011_01;
+//         IN2 = 8'b0_10_011_10;
         
-        #50ns   // -0.02734375 24
-        IN1 = 8'b1_10_101_01;
-        IN2 = 8'b0_10_100_10;
+//         #50ns   // -0.02734375 24
+//         IN1 = 8'b1_10_101_01;
+//         IN2 = 8'b0_10_100_10;
 
-        #50ns   // -56 3
-        IN1 = 8'b1_01_010_01;
-        IN2 = 8'b0_10_001_10;
+//         #50ns   // -56 3
+//         IN1 = 8'b1_01_010_01;
+//         IN2 = 8'b0_10_001_10;
         
-        #50ns   // -8 0.15625
-        IN1 = 8'b1_01_101_00;
-        IN2 = 8'b0_01_101_01;
+//         #50ns   // -8 0.15625
+//         IN1 = 8'b1_01_101_00;
+//         IN2 = 8'b0_01_101_01;
 
 
-        // -ve * -ve
-        #50ns   //  -0.0000152587890625 -0.009765625  
-        IN1 = 8'b1_1110_000;
-        IN2 = 8'b1_10_110_11;
+//         // -ve * -ve
+//         #50ns   //  -0.0000152587890625 -0.009765625  
+//         IN1 = 8'b1_1110_000;
+//         IN2 = 8'b1_10_110_11;
 
-        #50ns   // -0.0000019073486328125 -0.0009765625
-        IN1 = 8'b1_1110_011;
-        IN2 = 8'b1_110_010_0;
+//         #50ns   // -0.0000019073486328125 -0.0009765625
+//         IN1 = 8'b1_1110_011;
+//         IN2 = 8'b1_110_010_0;
 
-        #50ns   // -0.109375 -0.09375  
-        IN1 = 8'b1_10_011_01;
-        IN2 = 8'b1_10_011_10;
+//         #50ns   // -0.109375 -0.09375  
+//         IN1 = 8'b1_10_011_01;
+//         IN2 = 8'b1_10_011_10;
         
-        #50ns   // -0.02734375 -0.046875 
-        IN1 = 8'b1_10_101_01;
-        IN2 = 8'b1_10_100_10;
+//         #50ns   // -0.02734375 -0.046875 
+//         IN1 = 8'b1_10_101_01;
+//         IN2 = 8'b1_10_100_10;
 
-        #50ns   // -56 -0.375
-        IN1 = 8'b1_01_010_01;
-        IN2 = 8'b1_10_001_10;
+//         #50ns   // -56 -0.375
+//         IN1 = 8'b1_01_010_01;
+//         IN2 = 8'b1_10_001_10;
         
-        #50ns   // -8 -7
-        IN1 = 8'b1_01_101_00;
-        IN2 = 8'b1_01_101_01;
-    end
+//         #50ns   // -8 -7
+//         IN1 = 8'b1_01_101_00;
+//         IN2 = 8'b1_01_101_01;
+//      end
 endmodule
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/Pout_8bit_ES4.txt b/Individual_Project/Posit_Multiplier/Pout_8bit_ES4.txt
new file mode 100644
index 0000000000000000000000000000000000000000..ad4012ad8d0468cc7a6719621e619d1e16973812
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/Pout_8bit_ES4.txt
@@ -0,0 +1,65278 @@
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diff --git a/Individual_Project/Posit_Multiplier/c5_pin_model_dump.txt b/Individual_Project/Posit_Multiplier/c5_pin_model_dump.txt
new file mode 100644
index 0000000000000000000000000000000000000000..31bb72c180c644b5936c76019879f6dabecae944
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/Individual_Project/Posit_Multiplier/db/.cmp.kpt b/Individual_Project/Posit_Multiplier/db/.cmp.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..3c23d86c9b6bb3667f8bdaefb0d4b5f712d61f6c
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/.cmp.kpt differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..5a1f3be06adea7c1af7694c75e8e7d11478198c0
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..73e600fea697179231d1bbe77b9a1c5bc11b4bd3
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(0).cnf.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..9becb341e1ac2f1a29a5a0e136cdfea6ceffa725
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..37bcea50c11c5dd7597b166883309c9ecdac858b
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(1).cnf.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..320480923df2a1915c8821021fe28aab78d7e3e5
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..8bb799502261a3b95b0584778efcd8aa92d8ce6e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.(2).cnf.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..b9bd15db87247b118164fa0a1fde8f2859f3e296
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676403418291 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676403418292 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:36:58 2023 " "Processing started: Tue Feb 14 19:36:58 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676403418292 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1676403418292 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1676403418293 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1676403419030 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1676403423158 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4878 " "Peak virtual memory: 4878 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403423555 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:37:03 2023 " "Processing ended: Tue Feb 14 19:37:03 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403423555 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403423555 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403423555 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1676403423555 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.rdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..561b0ae9e6427fe59a293b1bfddffdc63cfe861c
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.asm.rdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cbx.xml b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cbx.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b81b85b75ced64bb68b791f771521bd1d375b03e
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="Posit_Multiplier">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.idb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.idb
new file mode 100644
index 0000000000000000000000000000000000000000..b4ad572c5b73dbe76a8796ce6508f6d40f8eedf8
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.idb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.rdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..1b89dbdfe365174df1b6ac5b0b377fd7632fc55b
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp.rdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp_merge.kpt b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp_merge.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..e2a3d81dd5d89491ca9e997b52a295d3b95cb306
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cmp_merge.kpt differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..77944d6a2908529431399039342406842a787951
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_0c_fast.hsd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..3651200a0bf065de37c8578bdb32954144c933d1
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.ff_85c_fast.hsd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_0c_slow.hsd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..6ff63fe34500be6b7f11c866a65d5a8b1abbe12e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_0c_slow.hsd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_85c_slow.hsd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..2a1684c45f87357567a3597d3accb4fa4bfd17e1
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.cyclonev_io_sim_cache.tt_85c_slow.hsd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.db_info b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..40d3a672787ee7980d3f533f5ff3ff93978a1dcb
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 21 16:14:07 2023
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.eda.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.eda.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..8844048c5a109b2f691f7dd99f3ac1fdff799f55
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.eda.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676403430012 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676403430013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:37:09 2023 " "Processing started: Tue Feb 14 19:37:09 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676403430013 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676403430013 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676403430013 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1676403430987 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Posit_Multiplier.vo H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/simulation/questa/ simulation " "Generated file Posit_Multiplier.vo in folder \"H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1676403431071 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4733 " "Peak virtual memory: 4733 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403431109 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:37:11 2023 " "Processing ended: Tue Feb 14 19:37:11 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403431109 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403431109 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403431109 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1676403431109 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.fit.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.fit.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..d1444b3f93f9d3c303bf216d850ef52225489fa8
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1676403375962 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1676403375962 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "Posit_Multiplier 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"Posit_Multiplier\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1676403375979 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676403376029 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676403376029 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1676403376378 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1676403376462 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1676403376753 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "24 24 " "No exact pin location assignment(s) for 24 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1676403376981 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1676403385046 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403385111 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1676403385137 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676403385139 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676403385139 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1676403385139 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1676403385141 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1676403385141 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1676403385142 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1676403385142 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1676403385142 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:09 " "Fitter preparation operations ending: elapsed time is 00:00:09" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403385163 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Posit_Multiplier.sdc " "Synopsys Design Constraints File file not found: 'Posit_Multiplier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1676403389739 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1676403389740 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1676403389740 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1676403389741 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1676403389742 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1676403389742 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1676403389742 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1676403389758 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1676403389834 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:11 " "Fitter placement preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403400282 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1676403407961 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1676403408397 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403408397 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1676403409279 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" {  } { { "loc" "" { Generic "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1676403412579 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1676403412579 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1676403412793 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1676403412793 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1676403412793 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403412796 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1676403413864 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676403413901 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676403414190 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676403414190 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676403414459 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676403416200 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg " "Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1676403416531 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6729 " "Peak virtual memory: 6729 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403416972 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:36:56 2023 " "Processing ended: Tue Feb 14 19:36:56 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403416972 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403416972 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Total CPU time (on all processors): 00:00:36" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403416972 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1676403416972 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hier_info b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hier_info
new file mode 100644
index 0000000000000000000000000000000000000000..94bfac8c934c0e6d69074eab18184743dd6af052
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hier_info
@@ -0,0 +1,165 @@
+|Posit_Multiplier
+IN1[0] => IN1[0].IN1
+IN1[1] => IN1[1].IN1
+IN1[2] => IN1[2].IN1
+IN1[3] => IN1[3].IN1
+IN1[4] => IN1[4].IN1
+IN1[5] => IN1[5].IN1
+IN1[6] => IN1[6].IN1
+IN1[7] => IN1[7].IN1
+IN2[0] => IN2[0].IN1
+IN2[1] => IN2[1].IN1
+IN2[2] => IN2[2].IN1
+IN2[3] => IN2[3].IN1
+IN2[4] => IN2[4].IN1
+IN2[5] => IN2[5].IN1
+IN2[6] => IN2[6].IN1
+IN2[7] => IN2[7].IN1
+OUT[0] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[1] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[2] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[3] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[4] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[5] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[6] << sft_tmp_oN.DB_MAX_OUTPUT_PORT_TYPE
+OUT[7] << Operation.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Multiplier|Data_Extraction:Extract_IN1
+In[0] => InRemain.DATAA
+In[0] => Add0.IN8
+In[1] => InRemain.DATAA
+In[1] => Add0.IN7
+In[2] => InRemain.DATAA
+In[2] => Add0.IN6
+In[3] => InRemain.DATAA
+In[3] => Add0.IN5
+In[4] => InRemain.DATAA
+In[4] => Add0.IN4
+In[5] => InRemain.DATAA
+In[5] => Add0.IN3
+In[6] => InRemain.DATAA
+In[6] => Add0.IN2
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => Sign.DATAIN
+Sign <= In[7].DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[0] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[1] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[2] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[3] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[4] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[0] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[1] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[2] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[0] <= <GND>
+Mantissa[1] <= <GND>
+Mantissa[2] <= <GND>
+Mantissa[3] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[4] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[5] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[6] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[7] <= <VCC>
+InRemain[0] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[1] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[2] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[3] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[4] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[5] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[6] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Multiplier|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1
+InRemain[0] => ~NO_FANOUT~
+InRemain[1] => always0.IN0
+InRemain[2] => always0.IN0
+InRemain[3] => always0.IN0
+InRemain[4] => always0.IN0
+InRemain[5] => always0.IN0
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => RegimeCheck.DATAIN
+EndPosition[0] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[1] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[2] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[3] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+RegimeCheck <= InRemain[6].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Multiplier|Data_Extraction:Extract_IN2
+In[0] => InRemain.DATAA
+In[0] => Add0.IN8
+In[1] => InRemain.DATAA
+In[1] => Add0.IN7
+In[2] => InRemain.DATAA
+In[2] => Add0.IN6
+In[3] => InRemain.DATAA
+In[3] => Add0.IN5
+In[4] => InRemain.DATAA
+In[4] => Add0.IN4
+In[5] => InRemain.DATAA
+In[5] => Add0.IN3
+In[6] => InRemain.DATAA
+In[6] => Add0.IN2
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => InRemain.OUTPUTSELECT
+In[7] => Sign.DATAIN
+Sign <= In[7].DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[0] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[1] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[2] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[3] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+RegimeValue[4] <= RegimeValue.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[0] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[1] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Exponent[2] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[0] <= <GND>
+Mantissa[1] <= <GND>
+Mantissa[2] <= <GND>
+Mantissa[3] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[4] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[5] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[6] <= ShiftLeft0.DB_MAX_OUTPUT_PORT_TYPE
+Mantissa[7] <= <VCC>
+InRemain[0] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[1] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[2] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[3] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[4] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[5] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+InRemain[6] <= InRemain.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Posit_Multiplier|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1
+InRemain[0] => ~NO_FANOUT~
+InRemain[1] => always0.IN0
+InRemain[2] => always0.IN0
+InRemain[3] => always0.IN0
+InRemain[4] => always0.IN0
+InRemain[5] => always0.IN0
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => always0.IN1
+InRemain[6] => RegimeCheck.DATAIN
+EndPosition[0] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[1] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[2] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+EndPosition[3] <= EndPosition.DB_MAX_OUTPUT_PORT_TYPE
+RegimeCheck <= InRemain[6].DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hif b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hif
new file mode 100644
index 0000000000000000000000000000000000000000..bda7230257a2b180a4daf404113ae1c81fce3c40
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.hif differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.html b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.html
new file mode 100644
index 0000000000000000000000000000000000000000..b5cb2da9d900aa49105944b66c7165aa11f07167
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.html
@@ -0,0 +1,82 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >Extract_IN2|LBD1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN2</TD>
+<TD >8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >24</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN1|LBD1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >Extract_IN1</TD>
+<TD >8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >24</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.rdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..50021fe74b206748b62bde1acf8937effa4e0fa6
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.rdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.txt b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9229ad7714cbf2ea0600cfe6f576150b4bbde980
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.lpc.txt
@@ -0,0 +1,10 @@
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                            ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy        ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Extract_IN2|LBD1 ; 7     ; 0              ; 1            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN2      ; 8     ; 4              ; 0            ; 4              ; 24     ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN1|LBD1 ; 7     ; 0              ; 1            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; Extract_IN1      ; 8     ; 4              ; 0            ; 4              ; 24     ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.ammdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..abcb3fcadbb7dc2eda53aadaab31a267a693fbe4
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.bpm b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..b7bd9d672ec6a5deb6264847dfa6dc1406ef0fea
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.bpm differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..d229e722f8f07a2e2f110f446877b4eb2bdfea7e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..a4485e9e0d265b362f00696fb819d5c9d00afb0e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.kpt b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..04bb40d30172725f864da6835cc5f6a09883d47b
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.kpt differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.logdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..0dcb28291ef9147b2463c3fd1ec1fd6a4011a214
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map.qmsg
@@ -0,0 +1,16 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676996059605 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676996059606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 21 16:14:19 2023 " "Processing started: Tue Feb 21 16:14:19 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676996059606 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996059606 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996059606 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676996060280 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676996060280 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "leading_bit_detector.sv 1 1 " "Found 1 design units, including 1 entities, in source file leading_bit_detector.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Leading_Bit_Detector " "Found entity 1: Leading_Bit_Detector" {  } { { "Leading_Bit_Detector.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676996067255 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996067255 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_extraction.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_extraction.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Extraction " "Found entity 1: Data_Extraction" {  } { { "Posit_Extraction.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676996067262 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996067262 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_multiplier.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_multiplier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Posit_Multiplier " "Found entity 1: Posit_Multiplier" {  } { { "Posit_Multiplier.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676996067265 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996067265 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Posit_Multiplier " "Elaborating entity \"Posit_Multiplier\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676996067324 ""}
+{ "Warning" "WVRFX_VERI_2086_UNCONVERTED" "Posit_Multiplier.sv(77) " "Verilog HDL warning at Posit_Multiplier.sv(77): converting signed shift amount to unsigned" {  } { { "Posit_Multiplier.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 77 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Analysis & Synthesis" 0 -1 1676996067337 "|Posit_Multiplier"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Data_Extraction Data_Extraction:Extract_IN1 " "Elaborating entity \"Data_Extraction\" for hierarchy \"Data_Extraction:Extract_IN1\"" {  } { { "Posit_Multiplier.sv" "Extract_IN1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 30 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676996067339 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Leading_Bit_Detector Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1 " "Elaborating entity \"Leading_Bit_Detector\" for hierarchy \"Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1\"" {  } { { "Posit_Extraction.sv" "LBD1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676996067374 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676996068532 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676996069103 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676996069103 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676996069334 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676996069334 ""} { "Info" "ICUT_CUT_TM_LCELLS" "153 " "Implemented 153 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676996069334 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "1 " "Implemented 1 DSP elements" {  } {  } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1676996069334 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676996069334 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4838 " "Peak virtual memory: 4838 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676996069354 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 21 16:14:29 2023 " "Processing ended: Tue Feb 21 16:14:29 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676996069354 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676996069354 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676996069354 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676996069354 ""}
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map_bb.logdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map_bb.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.mif_update.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.mif_update.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..e2c4f2b141172b13a0d3ae8a3ae71cc764dc8a34
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.mif_update.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676398507910 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus Prime " "Running Quartus Prime MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676398507910 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 18:15:07 2023 " "Processing started: Tue Feb 14 18:15:07 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676398507910 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1676398507910 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb Posit_Multiplier -c Posit_Multiplier --update_mif " "Command: quartus_cdb Posit_Multiplier -c Posit_Multiplier --update_mif" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1676398507911 ""}
+{ "Error" "EQATM_QSYN_NOT_RUN" "Posit_Multiplier " "Run Analysis and Synthesis (quartus_map) with revision \"Posit_Multiplier\" for --rev option before running Compiler Database Interface (quartus_cdb)" {  } {  } 0 39003 "Run Analysis and Synthesis (quartus_map) with revision \"%1!s!\" for --rev option before running Compiler Database Interface (quartus_cdb)" 0 0 "Design Software" 0 -1 1676398507925 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "MIF/HEX Update 1  0 s Quartus Prime " "Quartus Prime MIF/HEX Update was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4657 " "Peak virtual memory: 4657 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676398507926 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Feb 14 18:15:07 2023 " "Processing ended: Tue Feb 14 18:15:07 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676398507926 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676398507926 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676398507926 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1676398507926 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.npp.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.npp.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..407a5f69c901f4a01179c716f8c139ae5ad652ff
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.npp.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676403461964 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676403461964 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:37:41 2023 " "Processing started: Tue Feb 14 19:37:41 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676403461964 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1676403461964 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp Posit_Multiplier -c Posit_Multiplier --netlist_type=sgate " "Command: quartus_npp Posit_Multiplier -c Posit_Multiplier --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1676403461964 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1676403462202 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1  Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4562 " "Peak virtual memory: 4562 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403462213 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:37:42 2023 " "Processing ended: Tue Feb 14 19:37:42 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403462213 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403462213 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403462213 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1676403462213 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.pre_map.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.pre_map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..87fe2939401db29e62007f2fdecf6c8f37c68f71
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.root_partition.map.reg_db.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..258a369bc85e4b6ee21fbe2341b4d374d5b5d2df
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.root_partition.map.reg_db.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.routing.rdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.routing.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..6ce4bf0a4f08715350ecb2d05e42d0cd810c6375
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.routing.rdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv.hdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..d0c98da477ba96b19829eaa7ac622071039c18db
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..f1a31a0d5c96d2406df818e081c816e252605f20
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg_swap.cdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg_swap.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..2039ef1f85ea29c4138d3dad2c545371ef88a731
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.rtlv_sg_swap.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate.nvd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate.nvd
new file mode 100644
index 0000000000000000000000000000000000000000..fe89005900e065b16541ac5ed0b4c9a851fa6a66
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate.nvd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate_sm.nvd b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate_sm.nvd
new file mode 100644
index 0000000000000000000000000000000000000000..5b4f8c2e8e3ebff9ff1b12d91c4ecbe9011bc357
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sgate_sm.nvd differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry.sci b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry.sci
new file mode 100644
index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry.sci differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry_dsc.sci b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry_dsc.sci
new file mode 100644
index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sld_design_entry_dsc.sci differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.smart_action.txt b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.smart_action.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e04bbcfecfa47784a5fc67ffb30a5d652da87a98
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sta.qmsg b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sta.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..31025eceb73bcf6817216a41dc09f124c6fcc49b
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sta.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676403424958 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676403424958 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:37:04 2023 " "Processing started: Tue Feb 14 19:37:04 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676403424958 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1676403424958 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Posit_Multiplier -c Posit_Multiplier " "Command: quartus_sta Posit_Multiplier -c Posit_Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1676403424958 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1676403425124 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1676403425781 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1676403425781 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403425818 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403425818 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Posit_Multiplier.sdc " "Synopsys Design Constraints File file not found: 'Posit_Multiplier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1676403426223 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403426223 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676403426223 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676403426224 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1676403426224 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676403426224 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1676403426226 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1676403426236 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676403426239 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426242 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426252 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426254 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426257 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426259 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426261 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676403426265 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676403426291 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676403426932 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403426976 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676403426976 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676403426977 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676403426977 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426979 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426984 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426987 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426990 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426993 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403426996 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676403426999 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676403427142 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676403427660 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403427710 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676403427710 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676403427710 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676403427711 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427714 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427717 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427720 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427723 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427725 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676403427729 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676403427858 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676403427859 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676403427859 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676403427859 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427862 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427865 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427868 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427872 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676403427874 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676403428911 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676403428914 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5172 " "Peak virtual memory: 5172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403428961 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:37:08 2023 " "Processing ended: Tue Feb 14 19:37:08 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403428961 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403428961 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403428961 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1676403428961 ""}
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sta.rdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.sta.rdb
new file mode 100644
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.fast_1100mv_85c.ddb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.fast_1100mv_85c.ddb
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.slow_1100mv_0c.ddb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.slow_1100mv_0c.ddb
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.slow_1100mv_85c.ddb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tiscmp.slow_1100mv_85c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..230078d9e336865cc6bb4733be77572d56c2f3c3
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diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tmw_info b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tmw_info
new file mode 100644
index 0000000000000000000000000000000000000000..ab2baaed6cefe1f9f7e29617b3b2145de252403b
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.tmw_info
@@ -0,0 +1,2 @@
+start_analysis_synthesis:s:00:00:12
+start_analysis_elaboration:s
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.vpr.ammdb b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.vpr.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..5210d6311d7c3e24fcaebfbb5374859b3c2df714
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier.vpr.ammdb differ
diff --git a/Individual_Project/Posit_Multiplier/db/Posit_Multiplier_partition_pins.json b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier_partition_pins.json
new file mode 100644
index 0000000000000000000000000000000000000000..aaf1ab1ca02782218e51c9c6afe72b29addaa0f7
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/Posit_Multiplier_partition_pins.json
@@ -0,0 +1,105 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "OUT[0]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[1]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[2]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[3]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[4]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[5]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[6]",
+					"strict" : false
+				},
+				{
+					"name" : "OUT[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[7]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "IN1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "IN2[0]",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/db/prev_cmp_Posit_Multiplier.qmsg b/Individual_Project/Posit_Multiplier/db/prev_cmp_Posit_Multiplier.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..69288da073adb11453fa60bc7db255c1d77c3e9f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/db/prev_cmp_Posit_Multiplier.qmsg
@@ -0,0 +1,16 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676403329765 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676403329765 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 19:35:29 2023 " "Processing started: Tue Feb 14 19:35:29 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676403329765 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403329765 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403329766 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676403330448 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676403330448 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "leading_bit_detector.sv 1 1 " "Found 1 design units, including 1 entities, in source file leading_bit_detector.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Leading_Bit_Detector " "Found entity 1: Leading_Bit_Detector" {  } { { "Leading_Bit_Detector.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676403337706 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403337706 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_extraction.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_extraction.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Extraction " "Found entity 1: Data_Extraction" {  } { { "Posit_Extraction.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676403337708 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403337708 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_multiplier.sv 1 1 " "Found 1 design units, including 1 entities, in source file posit_multiplier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 Posit_Multiplier " "Found entity 1: Posit_Multiplier" {  } { { "Posit_Multiplier.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676403337711 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403337711 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Posit_Multiplier " "Elaborating entity \"Posit_Multiplier\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676403337751 ""}
+{ "Warning" "WVRFX_VERI_2086_UNCONVERTED" "Posit_Multiplier.sv(77) " "Verilog HDL warning at Posit_Multiplier.sv(77): converting signed shift amount to unsigned" {  } { { "Posit_Multiplier.sv" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 77 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Analysis & Synthesis" 0 -1 1676403337752 "|Posit_Multiplier"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Data_Extraction Data_Extraction:Extract_IN1 " "Elaborating entity \"Data_Extraction\" for hierarchy \"Data_Extraction:Extract_IN1\"" {  } { { "Posit_Multiplier.sv" "Extract_IN1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv" 30 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676403337754 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Leading_Bit_Detector Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1 " "Elaborating entity \"Leading_Bit_Detector\" for hierarchy \"Data_Extraction:Extract_IN1\|Leading_Bit_Detector:LBD1\"" {  } { { "Posit_Extraction.sv" "LBD1" { Text "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676403337787 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676403338916 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676403339425 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676403339425 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676403339585 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676403339585 ""} { "Info" "ICUT_CUT_TM_LCELLS" "153 " "Implemented 153 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676403339585 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "1 " "Implemented 1 DSP elements" {  } {  } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1676403339585 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676403339585 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4838 " "Peak virtual memory: 4838 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676403339600 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 19:35:39 2023 " "Processing ended: Tue Feb 14 19:35:39 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676403339600 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676403339600 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676403339600 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676403339600 ""}
diff --git a/Individual_Project/Posit_Multiplier/error_8bit.txt b/Individual_Project/Posit_Multiplier/error_8bit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..ecf734f7c859f9ca3aad626d354148d5591520ec
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/error_8bit.txt
@@ -0,0 +1,65546 @@
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diff --git a/Individual_Project/Posit_Multiplier/incremental_db/README b/Individual_Project/Posit_Multiplier/incremental_db/README
new file mode 100644
index 0000000000000000000000000000000000000000..9f62dcda0512fec7b5b55c11a13d70f91548996f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.db_info b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..09f04ab71300338dae73ce8afebc743c2d3bdac5
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 14 19:04:01 2023
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.ammdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..0b61a4ed095ba2cc2daf9cc1bfb36349e03a5827
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.ammdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.cdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..33f2110df5370d7076c7f03bfec1cca0c9e9354c
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.dfp b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.dfp
new file mode 100644
index 0000000000000000000000000000000000000000..b1c67d625638bb473b681fa4acb00be38889ece3
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.dfp differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.cdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..e00a6aed214d988a3af6a1e9ad6fa3e9fd379282
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.hdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..789e954c7f246334a0a9006df11ab915f09b9918
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.sig b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..1b33c80719c7ddc21535cac73904b9fa885d16c7
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.logdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.rcfdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.cmp.rcfdb
new file mode 100644
index 0000000000000000000000000000000000000000..645c4c1e8c22cec6ba3b5386066a1980a85a3b6c
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diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.cdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.cdb
new file mode 100644
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Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.dpi b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.dpi
new file mode 100644
index 0000000000000000000000000000000000000000..59d77569c9c1ae2b699277a9587d16c1e32f5989
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.dpi differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.cdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..5ab59a8d3e5c7af6e33dc2f911525f929e75988b
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hb_info b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000000000000000000000000000000000000..8210c55998f9226aeba57897397a9e541102c45e
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hb_info differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..53f9510b45c83f6d0fa164add644e6e5f200aa17
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.sig b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..45a5437825e0405260f29b3040fe9bb4a8ed57dd
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diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.kpt b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.kpt
new file mode 100644
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Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.root_partition.map.kpt differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrp.hdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..f61920ab07a7881c32c79a2a60e2faba57c31fc2
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrp.hdb differ
diff --git a/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrs.cdb b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrs.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..f788d5c461854a59d0f4db21a205a51cde9a62dd
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/incremental_db/compiled_partitions/Posit_Multiplier.rrs.cdb differ
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.asm.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.asm.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d286a11d22b188581f78b9fa9ee003625022779a
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.asm.rpt
@@ -0,0 +1,91 @@
+Assembler report for Posit_Multiplier
+Tue Feb 14 19:37:03 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Feb 14 19:37:03 2023 ;
+; Revision Name         ; Posit_Multiplier                      ;
+; Top-level Entity Name ; Posit_Multiplier                      ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                         ;
++---------------------------------------------------------------------------------------------------+
+; File Name                                                                                         ;
++---------------------------------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof ;
++---------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof ;
++----------------+------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                    ;
++----------------+------------------------------------------------------------------------------------------------------------+
+; JTAG usercode  ; 0x00B236B7                                                                                                 ;
+; Checksum       ; 0x00B236B7                                                                                                 ;
++----------------+------------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:36:58 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4878 megabytes
+    Info: Processing ended: Tue Feb 14 19:37:03 2023
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.done b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.done
new file mode 100644
index 0000000000000000000000000000000000000000..2174e6fc4fa1b41bdde0de142c6c7be7eab9c34a
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.done
@@ -0,0 +1 @@
+Tue Feb 21 16:14:30 2023
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.eda.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.eda.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7dd1e71cdb269950decacbf208a1f011909554d9
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.eda.rpt
@@ -0,0 +1,94 @@
+EDA Netlist Writer report for Posit_Multiplier
+Tue Feb 14 19:37:11 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Tue Feb 14 19:37:11 2023 ;
+; Revision Name             ; Posit_Multiplier                      ;
+; Top-level Entity Name     ; Posit_Multiplier                      ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                             ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Option                                                                                            ; Setting                     ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Tool Name                                                                                         ; Questa Intel FPGA (Verilog) ;
+; Generate functional simulation netlist                                                            ; On                          ;
+; Truncate long hierarchy paths                                                                     ; Off                         ;
+; Map illegal HDL characters                                                                        ; Off                         ;
+; Flatten buses into individual nodes                                                               ; Off                         ;
+; Maintain hierarchy                                                                                ; Off                         ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                         ;
+; Enable glitch filtering                                                                           ; Off                         ;
+; Do not write top level VHDL entity                                                                ; Off                         ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                         ;
+; Architecture name in VHDL output netlist                                                          ; structure                   ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                         ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                         ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                            ;
++-------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                       ;
++-------------------------------------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.vo ;
++-------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:37:09 2023
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Posit_Multiplier -c Posit_Multiplier
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (204019): Generated file Posit_Multiplier.vo in folder "H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/simulation/questa/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4733 megabytes
+    Info: Processing ended: Tue Feb 14 19:37:11 2023
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..42c2c409582f85950cb7ff2fddd13f7727aa3f05
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.rpt
@@ -0,0 +1,1806 @@
+Fitter report for Posit_Multiplier
+Tue Feb 14 19:36:56 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Incremental Compilation Preservation Summary
+  6. Incremental Compilation Partition Settings
+  7. Incremental Compilation Placement Preservation
+  8. Pin-Out File
+  9. Fitter Resource Usage Summary
+ 10. Fitter Partition Statistics
+ 11. Input Pins
+ 12. Output Pins
+ 13. I/O Bank Usage
+ 14. All Package Pins
+ 15. I/O Assignment Warnings
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Fitter DSP Block Usage Summary
+ 20. DSP Block Details
+ 21. Routing Usage Summary
+ 22. I/O Rules Summary
+ 23. I/O Rules Details
+ 24. I/O Rules Matrix
+ 25. Fitter Device Options
+ 26. Operating Settings and Conditions
+ 27. Fitter Messages
+ 28. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++---------------------------------+------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Feb 14 19:36:56 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Multiplier                               ;
+; Top-level Entity Name           ; Posit_Multiplier                               ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24 / 457 ( 5 % )                               ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                          ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                ;
+; Total DSP Blocks                ; 1 / 87 ( 1 % )                                 ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                  ;
++---------------------------------+------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                             ; Setting                               ; Default Value                         ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                             ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                  ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                  ; 85                                    ;                                       ;
+; Use smart compilation                                              ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                                    ; On                                    ;
+; Enable compact report table                                        ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                   ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                  ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                        ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                 ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                               ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                       ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                        ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                   ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                                  ; Care                                  ;
+; Power Optimization During Fitting                                  ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                   ; Off                                   ; Off                                   ;
+; Optimize Timing                                                    ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                           ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                         ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                      ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                      ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization               ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                              ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                          ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                              ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                  ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                              ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                       ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                          ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                             ; Off                                   ; Off                                   ;
+; Fitter Effort                                                      ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                    ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                          ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                  ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                               ; On                                    ; On                                    ;
+; Reserve all unused pins                                            ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                        ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                  ; On                                    ; On                                    ;
+; Active Serial clock source                                         ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
+; Clamping Diode                                                     ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode   ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                     ; On                                    ; On                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.3%      ;
+;     Processor 3            ;   0.3%      ;
+;     Processor 4            ;   0.2%      ;
+;     Processor 5            ;   0.2%      ;
+;     Processor 6            ;   0.2%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 203 ) ; 0.00 % ( 0 / 203 )         ; 0.00 % ( 0 / 203 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 203 ) ; 0.00 % ( 0 / 203 )         ; 0.00 % ( 0 / 203 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 203 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32,070        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 99                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 99 / 32,070        ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 0                  ;       ;
+;         [b] ALMs used for LUT logic                         ; 99                 ;       ;
+;         [c] ALMs used for registers                         ; 0                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32,070         ; 0 %   ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 13 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 13                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 154                ;       ;
+;     -- 7 input functions                                    ; 2                  ;       ;
+;     -- 6 input functions                                    ; 40                 ;       ;
+;     -- 5 input functions                                    ; 32                 ;       ;
+;     -- 4 input functions                                    ; 24                 ;       ;
+;     -- <=3 input functions                                  ; 56                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Dedicated logic registers                                   ; 0                  ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 0 / 64,140         ; 0 %   ;
+;         -- Secondary logic registers                        ; 0 / 64,140         ; 0 %   ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 0                  ;       ;
+;         -- Routing optimization registers                   ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 24 / 457           ; 5 %   ;
+;     -- Clock pins                                           ; 0 / 8              ; 0 %   ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 1 / 87             ; 1 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global signals                                              ; 0                  ;       ;
+;     -- Global clocks                                        ; 0 / 16             ; 0 %   ;
+;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
+;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 1.1% / 1.2% / 1.0% ;       ;
+; Maximum fan-out                                             ; 39                 ;       ;
+; Highest non-global fan-out                                  ; 31                 ;       ;
+; Total fan-out                                               ; 677                ;       ;
+; Average fan-out                                             ; 3.33               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                         ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 99                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 99 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 0                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 99                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 0                    ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Difficulty packing design                                   ; Low                  ; Low                            ;
+;                                                             ;                      ;                                ;
+; Total LABs:  partially or completely used                   ; 13 / 3207 ( < 1 % )  ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 13                   ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Combinational ALUT usage for logic                          ; 154                  ; 0                              ;
+;     -- 7 input functions                                    ; 2                    ; 0                              ;
+;     -- 6 input functions                                    ; 40                   ; 0                              ;
+;     -- 5 input functions                                    ; 32                   ; 0                              ;
+;     -- 4 input functions                                    ; 24                   ; 0                              ;
+;     -- <=3 input functions                                  ; 56                   ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 0                    ; 0                              ;
+; Memory ALUT usage                                           ; 0                    ; 0                              ;
+;     -- 64-address deep                                      ; 0                    ; 0                              ;
+;     -- 32-address deep                                      ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Dedicated logic registers                                   ; 0                    ; 0                              ;
+;     -- By type:                                             ;                      ;                                ;
+;         -- Primary logic registers                          ; 0 / 64140 ( 0 % )    ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 0 / 64140 ( 0 % )    ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                      ;                                ;
+;         -- Design implementation registers                  ; 0                    ; 0                              ;
+;         -- Routing optimization registers                   ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+;                                                             ;                      ;                                ;
+; Virtual pins                                                ; 0                    ; 0                              ;
+; I/O pins                                                    ; 24                   ; 0                              ;
+; I/O registers                                               ; 0                    ; 0                              ;
+; Total block memory bits                                     ; 0                    ; 0                              ;
+; Total block memory implementation bits                      ; 0                    ; 0                              ;
+; DSP block                                                   ; 1 / 87 ( 1 % )       ; 0 / 87 ( 0 % )                 ;
+;                                                             ;                      ;                                ;
+; Connections                                                 ;                      ;                                ;
+;     -- Input Connections                                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections                         ; 0                    ; 0                              ;
+;     -- Output Connections                                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections                        ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Internal Connections                                        ;                      ;                                ;
+;     -- Total Connections                                    ; 704                  ; 0                              ;
+;     -- Registered Connections                               ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; External Connections                                        ;                      ;                                ;
+;     -- Top                                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Partition Interface                                         ;                      ;                                ;
+;     -- Input Ports                                          ; 16                   ; 0                              ;
+;     -- Output Ports                                         ; 8                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Registered Ports                                            ;                      ;                                ;
+;     -- Registered Input Ports                               ; 0                    ; 0                              ;
+;     -- Registered Output Ports                              ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Port Connectivity                                           ;                      ;                                ;
+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                            ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; IN1[0] ; W25   ; 5B       ; 89           ; 20           ; 43           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[1] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[2] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[3] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[4] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[6] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN1[7] ; W24   ; 5A       ; 89           ; 15           ; 20           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[0] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[1] ; W22   ; 5A       ; 89           ; 8            ; 20           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[2] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[3] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[5] ; W21   ; 5A       ; 89           ; 8            ; 3            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[6] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; IN2[7] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; OUT[0] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[1] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[2] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[3] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[4] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[5] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[6] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; OUT[7] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 4A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 5A       ; 23 / 32 ( 72 % ) ; 2.5V          ; --           ; 2.5V          ;
+; 5B       ; 1 / 16 ( 6 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; OUT[1]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; OUT[5]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; IN2[0]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; IN1[2]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; OUT[3]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; OUT[2]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC28     ; 245        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC29     ; 247        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC30     ; 259        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; IN2[3]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; OUT[0]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD30     ; 257        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; OUT[4]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; OUT[7]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; IN2[7]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; IN2[4]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; IN1[6]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; IN2[6]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AG28     ; 233        ; 5A             ; IN1[5]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; IN1[4]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AH29     ; 218        ; 5A             ; IN2[2]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; OUT[6]                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; IN2[5]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; IN2[1]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; IN1[7]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; IN1[0]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; IN1[3]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; IN1[1]                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; OUT[0]   ; Incomplete set of assignments ;
+; OUT[1]   ; Incomplete set of assignments ;
+; OUT[2]   ; Incomplete set of assignments ;
+; OUT[3]   ; Incomplete set of assignments ;
+; OUT[4]   ; Incomplete set of assignments ;
+; OUT[5]   ; Incomplete set of assignments ;
+; OUT[6]   ; Incomplete set of assignments ;
+; OUT[7]   ; Incomplete set of assignments ;
+; IN1[7]   ; Incomplete set of assignments ;
+; IN2[7]   ; Incomplete set of assignments ;
+; IN2[6]   ; Incomplete set of assignments ;
+; IN2[4]   ; Incomplete set of assignments ;
+; IN2[3]   ; Incomplete set of assignments ;
+; IN2[5]   ; Incomplete set of assignments ;
+; IN2[2]   ; Incomplete set of assignments ;
+; IN2[1]   ; Incomplete set of assignments ;
+; IN1[6]   ; Incomplete set of assignments ;
+; IN1[4]   ; Incomplete set of assignments ;
+; IN1[3]   ; Incomplete set of assignments ;
+; IN1[5]   ; Incomplete set of assignments ;
+; IN1[2]   ; Incomplete set of assignments ;
+; IN1[1]   ; Incomplete set of assignments ;
+; IN1[0]   ; Incomplete set of assignments ;
+; IN2[0]   ; Incomplete set of assignments ;
+; OUT[0]   ; Missing location assignment   ;
+; OUT[1]   ; Missing location assignment   ;
+; OUT[2]   ; Missing location assignment   ;
+; OUT[3]   ; Missing location assignment   ;
+; OUT[4]   ; Missing location assignment   ;
+; OUT[5]   ; Missing location assignment   ;
+; OUT[6]   ; Missing location assignment   ;
+; OUT[7]   ; Missing location assignment   ;
+; IN1[7]   ; Missing location assignment   ;
+; IN2[7]   ; Missing location assignment   ;
+; IN2[6]   ; Missing location assignment   ;
+; IN2[4]   ; Missing location assignment   ;
+; IN2[3]   ; Missing location assignment   ;
+; IN2[5]   ; Missing location assignment   ;
+; IN2[2]   ; Missing location assignment   ;
+; IN2[1]   ; Missing location assignment   ;
+; IN1[6]   ; Missing location assignment   ;
+; IN1[4]   ; Missing location assignment   ;
+; IN1[3]   ; Missing location assignment   ;
+; IN1[5]   ; Missing location assignment   ;
+; IN1[2]   ; Missing location assignment   ;
+; IN1[1]   ; Missing location assignment   ;
+; IN1[0]   ; Missing location assignment   ;
+; IN2[0]   ; Missing location assignment   ;
++----------+-------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+; Compilation Hierarchy Node        ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                     ; Entity Name          ; Library Name ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+; |Posit_Multiplier                 ; 98.5 (61.0)          ; 99.0 (61.5)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 154 (94)            ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 1          ; 24   ; 0            ; |Posit_Multiplier                                                       ; Posit_Multiplier     ; work         ;
+;    |Data_Extraction:Extract_IN1|  ; 16.5 (13.0)          ; 16.5 (13.0)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 26 (22)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN1                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
+;    |Data_Extraction:Extract_IN2|  ; 21.0 (14.5)          ; 21.0 (14.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 34 (26)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN2                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 8 (8)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
++-----------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                   ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name   ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; OUT[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; OUT[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; IN1[7] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[7] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[6] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[4] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[3] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[5] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[2] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[1] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[6] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[4] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[3] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[5] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[2] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[1] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN1[0] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; IN2[0] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++--------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                           ;
++--------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                        ; Pad To Core Index ; Setting ;
++--------------------------------------------+-------------------+---------+
+; IN1[7]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~25 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~21 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~17 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~9  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~5  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~13 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN1|Add0~1  ; 0                 ; 0       ;
+;      - Operation~0                         ; 0                 ; 0       ;
+; IN2[7]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~25 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~21 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~17 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~9  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~5  ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~13 ; 0                 ; 0       ;
+;      - Data_Extraction:Extract_IN2|Add0~1  ; 0                 ; 0       ;
+;      - Operation~0                         ; 0                 ; 0       ;
+; IN2[6]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~1  ; 1                 ; 0       ;
+; IN2[4]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~5  ; 1                 ; 0       ;
+; IN2[3]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~9  ; 0                 ; 0       ;
+; IN2[5]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~13 ; 1                 ; 0       ;
+; IN2[2]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~17 ; 1                 ; 0       ;
+; IN2[1]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~21 ; 0                 ; 0       ;
+; IN1[6]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~1  ; 1                 ; 0       ;
+; IN1[4]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~5  ; 1                 ; 0       ;
+; IN1[3]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~9  ; 1                 ; 0       ;
+; IN1[5]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~13 ; 1                 ; 0       ;
+; IN1[2]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~17 ; 0                 ; 0       ;
+; IN1[1]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~21 ; 1                 ; 0       ;
+; IN1[0]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN1|Add0~25 ; 1                 ; 0       ;
+; IN2[0]                                     ;                   ;         ;
+;      - Data_Extraction:Extract_IN2|Add0~25 ; 1                 ; 0       ;
++--------------------------------------------+-------------------+---------+
+
+
++-----------------------------------------------+
+; Fitter DSP Block Usage Summary                ;
++---------------------------------+-------------+
+; Statistic                       ; Number Used ;
++---------------------------------+-------------+
+; Independent 9x9                 ; 1           ;
+; Total number of DSP blocks      ; 1           ;
+;                                 ;             ;
+; Fixed Point Unsigned Multiplier ; 1           ;
++---------------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; DSP Block Details                                                                                                                                                                                                                                                                                                                                                                               ;
++-----------+-----------------+----------------+---------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------+--------------------------------+---------------------+-------------------------------+------------------------------+------------------------------+
+; Name      ; Mode            ; Location       ; Sign Representation ; Data AX Input Register ; Data AY Input Register ; Data AZ Input Register ; Data BX Input Register ; Data BY Input Register ; Data BZ Input Register ; Output Register ; Dedicated Shift Register Chain ; Dedicated Pre-Adder ; Dedicated Coefficient Storage ; Dedicated Output Adder Chain ; Dedicated Output Accumulator ;
++-----------+-----------------+----------------+---------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------+--------------------------------+---------------------+-------------------------------+------------------------------+------------------------------+
+; Mult0~mac ; Independent 9x9 ; DSP_X86_Y10_N0 ; Unsigned            ; no                     ; no                     ; --                     ; --                     ; --                     ; --                     ; no              ; no                             ; no                  ; no                            ; no                           ; no                           ;
++-----------+-----------------+----------------+---------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------+--------------------------------+---------------------+-------------------------------+------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 222 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 0 / 13,420 ( 0 % )      ;
+; C2 interconnects                            ; 62 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 31 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 33 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 0 / 16 ( 0 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 67 / 84,580 ( < 1 % )   ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 4 / 12,676 ( < 1 % )    ;
+; R14/C12 interconnect drivers                ; 0 / 20,720 ( 0 % )      ;
+; R3 interconnects                            ; 82 / 130,992 ( < 1 % )  ;
+; R6 interconnects                            ; 83 / 266,960 ( < 1 % )  ;
+; Spine clocks                                ; 0 / 360 ( 0 % )         ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                 ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 24        ; 0            ; 0            ; 24        ; 24        ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 24           ; 24           ; 24           ; 24           ; 24           ; 0         ; 24           ; 24           ; 0         ; 0         ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 16           ; 24           ; 24           ; 24           ; 24           ; 24           ; 24           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; OUT[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; OUT[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN1[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; IN2[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "Posit_Multiplier"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 24 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:09
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Posit_Multiplier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:11
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Info (144001): Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 6729 megabytes
+    Info: Processing ended: Tue Feb 14 19:36:56 2023
+    Info: Elapsed time: 00:00:41
+    Info: Total CPU time (on all processors): 00:00:36
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg.
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg
new file mode 100644
index 0000000000000000000000000000000000000000..930291945870c27fa8ede0009c58b1d66c8d95a3
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.summary b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.summary
new file mode 100644
index 0000000000000000000000000000000000000000..a76a301966d070f2e2d4d3052ceac12f70fb5176
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Feb 14 19:36:56 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : Posit_Multiplier
+Top-level Entity Name : Posit_Multiplier
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 24 / 457 ( 5 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 1 / 87 ( 1 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.flow.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.flow.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..88717a1103d18dda653df9d4c539172cb16dadc2
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.flow.rpt
@@ -0,0 +1,124 @@
+Flow report for Posit_Multiplier
+Tue Feb 21 16:14:29 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++---------------------------------+------------------------------------------------+
+; Flow Status                     ; Successful - Tue Feb 21 16:14:29 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Multiplier                               ;
+; Top-level Entity Name           ; Posit_Multiplier                               ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 1                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/21/2023 16:14:20 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; Posit_Multiplier    ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                               ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID               ; 1099276844422.167699605914108          ; --            ; --          ; --                                ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
+; EDA_SIMULATION_TOOL                 ; Questa Intel FPGA (Verilog)            ; <None>        ; --          ; --                                ;
+; EDA_TIME_SCALE                      ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --                                ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --                                ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --                                ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:09     ; 1.0                     ; 4838 MB             ; 00:00:10                           ;
+; Total                ; 00:00:09     ; --                      ; --                  ; 00:00:10                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier
+
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.jdi b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.jdi
new file mode 100644
index 0000000000000000000000000000000000000000..d1af96847676ceebf17982586b8a5a356091e6d7
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="d141cb6a7603ac5aa25b"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="Posit_Multiplier.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3188dfedbd9dd1d94cb226ff6dac15f15111eea0
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.rpt
@@ -0,0 +1,427 @@
+Analysis & Synthesis report for Posit_Multiplier
+Tue Feb 21 16:14:29 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis DSP Block Usage Summary
+  9. General Register Statistics
+ 10. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 11. Parameter Settings for User Entity Instance: Top-level Entity: |Posit_Multiplier
+ 12. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1
+ 13. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1
+ 14. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2
+ 15. Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1
+ 16. Port Connectivity Checks: "Data_Extraction:Extract_IN2"
+ 17. Port Connectivity Checks: "Data_Extraction:Extract_IN1"
+ 18. Post-Synthesis Netlist Statistics for Top Partition
+ 19. Elapsed Time Per Partition
+ 20. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++---------------------------------+------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Feb 21 16:14:29 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Multiplier                               ;
+; Top-level Entity Name           ; Posit_Multiplier                               ;
+; Family                          ; Cyclone V                                      ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 24                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 1                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; Posit_Multiplier   ; Posit_Multiplier   ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                ;
++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                            ; Library ;
++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+---------+
+; Leading_Bit_Detector.sv          ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv ;         ;
+; Posit_Extraction.sv              ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv     ;         ;
+; Posit_Multiplier.sv              ; yes             ; User SystemVerilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv     ;         ;
++----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                      ;
++---------------------------------------------+------------------------------------+
+; Resource                                    ; Usage                              ;
++---------------------------------------------+------------------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 98                                 ;
+;                                             ;                                    ;
+; Combinational ALUT usage for logic          ; 153                                ;
+;     -- 7 input functions                    ; 2                                  ;
+;     -- 6 input functions                    ; 40                                 ;
+;     -- 5 input functions                    ; 32                                 ;
+;     -- 4 input functions                    ; 24                                 ;
+;     -- <=3 input functions                  ; 55                                 ;
+;                                             ;                                    ;
+; Dedicated logic registers                   ; 0                                  ;
+;                                             ;                                    ;
+; I/O pins                                    ; 24                                 ;
+;                                             ;                                    ;
+; Total DSP Blocks                            ; 1                                  ;
+;                                             ;                                    ;
+; Maximum fan-out node                        ; Data_Extraction:Extract_IN2|Add1~1 ;
+; Maximum fan-out                             ; 31                                 ;
+; Total fan-out                               ; 677                                ;
+; Average fan-out                             ; 3.35                               ;
++---------------------------------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                        ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+; Compilation Hierarchy Node        ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                     ; Entity Name          ; Library Name ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+; |Posit_Multiplier                 ; 153 (93)            ; 0 (0)                     ; 0                 ; 1          ; 24   ; 0            ; |Posit_Multiplier                                                       ; Posit_Multiplier     ; work         ;
+;    |Data_Extraction:Extract_IN1|  ; 26 (22)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN1                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
+;    |Data_Extraction:Extract_IN2|  ; 34 (26)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN2                           ; Data_Extraction      ; work         ;
+;       |Leading_Bit_Detector:LBD1| ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |Posit_Multiplier|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ; Leading_Bit_Detector ; work         ;
++-----------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------------------------------------------+----------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------+
+; Analysis & Synthesis DSP Block Usage Summary  ;
++---------------------------------+-------------+
+; Statistic                       ; Number Used ;
++---------------------------------+-------------+
+; Independent 9x9                 ; 1           ;
+; Total number of DSP blocks      ; 1           ;
+;                                 ;             ;
+; Fixed Point Unsigned Multiplier ; 1           ;
++---------------------------------+-------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                       ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                             ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------+
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN1|ShiftLeft0                               ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN2|ShiftLeft0                               ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |Posit_Multiplier|ShiftRight0                                                          ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1|EndPosition[1] ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN1|ShiftLeft0                               ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1|EndPosition[0] ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Posit_Multiplier|Data_Extraction:Extract_IN2|ShiftLeft0                               ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |Posit_Multiplier ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; N              ; 8     ; Signed Integer                                          ;
+; ES             ; 3     ; Signed Integer                                          ;
+; RS             ; 3     ; Signed Integer                                          ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; N              ; 8     ; Signed Integer                                  ;
+; ES             ; 3     ; Signed Integer                                  ;
+; RS             ; 3     ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1 ;
++----------------+-------+---------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                      ;
++----------------+-------+---------------------------------------------------------------------------+
+; N              ; 8     ; Signed Integer                                                            ;
+; ES             ; 3     ; Signed Integer                                                            ;
+; RS             ; 3     ; Signed Integer                                                            ;
++----------------+-------+---------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; N              ; 8     ; Signed Integer                                  ;
+; ES             ; 3     ; Signed Integer                                  ;
+; RS             ; 3     ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Data_Extraction:Extract_IN2|Leading_Bit_Detector:LBD1 ;
++----------------+-------+---------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                      ;
++----------------+-------+---------------------------------------------------------------------------+
+; N              ; 8     ; Signed Integer                                                            ;
+; ES             ; 3     ; Signed Integer                                                            ;
+; RS             ; 3     ; Signed Integer                                                            ;
++----------------+-------+---------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "Data_Extraction:Extract_IN2"                                                            ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; InRemain ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "Data_Extraction:Extract_IN1"                                                            ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; InRemain ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb     ; 153                         ;
+;     arith             ; 49                          ;
+;         1 data inputs ; 13                          ;
+;         2 data inputs ; 20                          ;
+;         3 data inputs ; 2                           ;
+;         4 data inputs ; 9                           ;
+;         5 data inputs ; 5                           ;
+;     extend            ; 2                           ;
+;         7 data inputs ; 2                           ;
+;     normal            ; 102                         ;
+;         2 data inputs ; 3                           ;
+;         3 data inputs ; 17                          ;
+;         4 data inputs ; 15                          ;
+;         5 data inputs ; 27                          ;
+;         6 data inputs ; 40                          ;
+; arriav_mac            ; 1                           ;
+; boundary_port         ; 24                          ;
+;                       ;                             ;
+; Max LUT depth         ; 17.40                       ;
+; Average LUT depth     ; 15.50                       ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 21 16:14:19 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Multiplier -c Posit_Multiplier
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file leading_bit_detector.sv
+    Info (12023): Found entity 1: Leading_Bit_Detector File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Leading_Bit_Detector.sv Line: 19
+Info (12021): Found 1 design units, including 1 entities, in source file posit_extraction.sv
+    Info (12023): Found entity 1: Data_Extraction File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv Line: 22
+Info (12021): Found 1 design units, including 1 entities, in source file posit_multiplier.sv
+    Info (12023): Found entity 1: Posit_Multiplier File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv Line: 18
+Info (12127): Elaborating entity "Posit_Multiplier" for the top level hierarchy
+Warning (10764): Verilog HDL warning at Posit_Multiplier.sv(77): converting signed shift amount to unsigned File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv Line: 77
+Info (12128): Elaborating entity "Data_Extraction" for hierarchy "Data_Extraction:Extract_IN1" File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Multiplier.sv Line: 30
+Info (12128): Elaborating entity "Leading_Bit_Detector" for hierarchy "Data_Extraction:Extract_IN1|Leading_Bit_Detector:LBD1" File: H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Posit_Multiplier/Posit_Extraction.sv Line: 38
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 8 output pins
+    Info (21061): Implemented 153 logic cells
+    Info (21062): Implemented 1 DSP elements
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 4838 megabytes
+    Info: Processing ended: Tue Feb 21 16:14:29 2023
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:10
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.summary b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.summary
new file mode 100644
index 0000000000000000000000000000000000000000..bed17214fd2c7c60a86729c5d8984766e0e22fff
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Feb 21 16:14:29 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : Posit_Multiplier
+Top-level Entity Name : Posit_Multiplier
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 24
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 1
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.pin b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.pin
new file mode 100644
index 0000000000000000000000000000000000000000..522dcb15328652a2f98bcc2d9ae3061a2b831f31
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.pin
@@ -0,0 +1,977 @@
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       2.5V
+ --                  Bank 4A:       2.5V
+ --                  Bank 5A:       2.5V
+ --                  Bank 5B:       2.5V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+CHIP  "Posit_Multiplier"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+OUT[1]                       : AA24      : output : 2.5 V             :         : 5A        : N              
+OUT[5]                       : AA25      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 2.5V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+IN2[0]                       : AB22      : input  : 2.5 V             :         : 5A        : N              
+IN1[2]                       : AB23      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AB24      : power  :                   : 2.5V    : 5A        :                
+OUT[3]                       : AB25      : output : 2.5 V             :         : 5A        : N              
+OUT[2]                       : AB26      : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30      :        :                   :         : 5B        :                
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+IN2[3]                       : AD26      : input  : 2.5 V             :         : 5A        : N              
+OUT[0]                       : AD27      : output : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AD28      : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30      :        :                   :         : 5B        :                
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 2.5V    : 4A        :                
+OUT[4]                       : AE26      : output : 2.5 V             :         : 5A        : N              
+OUT[7]                       : AE27      : output : 2.5 V             :         : 5A        : N              
+IN2[7]                       : AE28      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29      :        :                   :         : 5B        :                
+VCCIO5B                      : AE30      : power  :                   : 2.5V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+IN2[4]                       : AF28      : input  : 2.5 V             :         : 5A        : N              
+IN1[6]                       : AF29      : input  : 2.5 V             :         : 5A        : N              
+IN2[6]                       : AF30      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG27      :        :                   :         : 5A        :                
+IN1[5]                       : AG28      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AG29      : power  :                   : 2.5V    : 5A        :                
+IN1[4]                       : AG30      : input  : 2.5 V             :         : 5A        : N              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH28      :        :                   :         : 5A        :                
+IN2[2]                       : AH29      : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH30      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29      :        :                   :         : 5A        :                
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 2.5V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 2.5V    : 5A        :                
+OUT[6]                       : V23       : output : 2.5 V             :         : 5A        : N              
+VCCPD5A                      : V24       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+IN2[5]                       : W21       : input  : 2.5 V             :         : 5A        : N              
+IN2[1]                       : W22       : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : W23       : power  :                   : 2.5V    : 5A        :                
+IN1[7]                       : W24       : input  : 2.5 V             :         : 5A        : N              
+IN1[0]                       : W25       : input  : 2.5 V             :         : 5B        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+IN1[3]                       : Y23       : input  : 2.5 V             :         : 5A        : N              
+IN1[1]                       : Y24       : input  : 2.5 V             :         : 5A        : N              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sld b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sld
new file mode 100644
index 0000000000000000000000000000000000000000..f7d3ed7cc6abd95c50005b31855c0eec845cbeed
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof
new file mode 100644
index 0000000000000000000000000000000000000000..80b0497fa716e12fbb79c2c369101490ceb66ef6
Binary files /dev/null and b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sof differ
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.rpt b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7002a54f40736fd03b9a87531404a6bf5b9eb09c
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.rpt
@@ -0,0 +1,579 @@
+Timing Analyzer report for Posit_Multiplier
+Tue Feb 14 19:37:08 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++--------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                        ;
++-----------------------+--------------------------------------------------------+
+; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                                 ;
+; Revision Name         ; Posit_Multiplier                                       ;
+; Device Family         ; Cyclone V                                              ;
+; Device Name           ; 5CSEMA5F31C6                                           ;
+; Timing Models         ; Final                                                  ;
+; Delay Model           ; Combined                                               ;
+; Rise/Fall Delays      ; Enabled                                                ;
++-----------------------+--------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.15        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.1%      ;
+;     Processor 3            ;   3.0%      ;
+;     Processor 4            ;   3.0%      ;
+;     Processor 5            ;   3.0%      ;
+;     Processor 6            ;   3.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                             ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin    ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; OUT[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[4] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[5] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[6] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; OUT[7] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++--------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-----------------------------------------------------------+
+; Input Transition Times                                    ;
++--------+--------------+-----------------+-----------------+
+; Pin    ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++--------+--------------+-----------------+-----------------+
+; IN1[7] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[7] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[6] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[4] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[3] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[5] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[2] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[1] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[6] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[4] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[3] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[5] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[2] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[1] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN1[0] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IN2[0] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++--------+--------------+-----------------+-----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0568 V           ; 0.173 V                              ; 0.113 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0568 V          ; 0.173 V                             ; 0.113 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0568 V           ; 0.173 V                              ; 0.113 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0568 V          ; 0.173 V                             ; 0.113 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0568 V           ; 0.173 V                              ; 0.113 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0568 V          ; 0.173 V                             ; 0.113 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.0374 V           ; 0.189 V                              ; 0.158 V                              ; 4.66e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.0374 V          ; 0.189 V                             ; 0.158 V                             ; 4.66e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.0374 V           ; 0.189 V                              ; 0.158 V                              ; 4.66e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.0374 V          ; 0.189 V                             ; 0.158 V                             ; 4.66e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.0374 V           ; 0.189 V                              ; 0.158 V                              ; 4.66e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.0374 V          ; 0.189 V                             ; 0.158 V                             ; 4.66e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin    ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; OUT[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; OUT[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; OUT[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; OUT[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; OUT[7] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
++--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 16    ; 16   ;
+; Unconstrained Input Port Paths  ; 114   ; 114  ;
+; Unconstrained Output Ports      ; 8     ; 8    ;
+; Unconstrained Output Port Paths ; 114   ; 114  ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; IN1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; OUT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; IN1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; IN2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; OUT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; OUT[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 19:37:04 2023
+Info: Command: quartus_sta Posit_Multiplier -c Posit_Multiplier
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Posit_Multiplier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 5172 megabytes
+    Info: Processing ended: Tue Feb 14 19:37:08 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.summary b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.summary
new file mode 100644
index 0000000000000000000000000000000000000000..aa5b327ca51ad51bc2474f1a8c822d1c6b0b3acf
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/output_files/Posit_Multiplier.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/Individual_Project/Posit_Multiplier/posit_add_8bit_tb.v b/Individual_Project/Posit_Multiplier/posit_add_8bit_tb.v
new file mode 100644
index 0000000000000000000000000000000000000000..a131ff688db01127db58f5827dacb7c3f3181c01
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/posit_add_8bit_tb.v
@@ -0,0 +1,84 @@
+//`timescale 1ns / 1ps
+module posit_add_8bit_tb_v;
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+parameter N=8;
+parameter Bs=log2(N);
+parameter es=3;
+
+//input logic
+logic signed [N-1:0] IN1, IN2;
+
+//output logic
+logic signed [N-1:0] OUT;
+//reg start; 
+// wire out_s;
+// wire [Bs-1:0] out_r;
+// wire [Bs+es-1:0]out_e;
+// wire [N-1:0] out_m, out;
+// wire done;
+
+	reg clk;
+	integer outfile;
+
+
+// Instantiate the Unit Under Test (UUT)
+Posit_Multiplier #(.N(N), .es(es)) uut (.*);
+
+reg [N-1:0] data1 [1:65536];
+reg [N-1:0] data2 [1:65536];
+initial $readmemb("Pin1_8bit.txt",data1);
+initial $readmemb("Pin2_8bit.txt",data2);
+
+reg [15:0] i;
+	
+	initial begin
+		// Initialize Inputs
+		IN1 = 0;
+		IN2 = 0;
+		clk = 0;
+		//start = 0;
+	
+		
+		// Wait 100 ns for global reset to finish
+		#100 i=0;
+		#20 start = 1;
+                #655500 start = 0;
+		#100;
+		
+		$fclose(outfile);
+		$finish;
+	end
+	
+ always #5 clk=~clk;
+
+  always @(posedge clk) begin			
+ 	IN1=data1[i];	
+	IN2=data2[i];
+	if(i==16'hffff)
+  	      $finish;
+	else i = i + 1;
+ end
+
+initial outfile = $fopen("error_8bit.txt", "wb");
+
+reg [N-1:0] result [1:65536];
+initial $readmemb("Pout_8bit_ES4.txt",result);
+reg [N-1:0] diff;
+always @(negedge clk) begin
+	if(start)begin
+     	diff = (result[i-1] > OUT) ? result[i-1]-OUT : OUT-result[i-1];
+     	//$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\n",in1, in2, out,result[i-1],diff);
+     	$fwrite(outfile, "%d\n",diff);
+     	end
+end
+endmodule
+
diff --git a/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.sft b/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.sft
new file mode 100644
index 0000000000000000000000000000000000000000..9a92a1ec74c2e6108c1769581ffc131af7afc4e6
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.sft
@@ -0,0 +1 @@
+set tool_name "Questa Intel FPGA (Verilog)"
diff --git a/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.vo b/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.vo
new file mode 100644
index 0000000000000000000000000000000000000000..dc7d46f2a948fee1a8c603de7f078cb93f692d41
--- /dev/null
+++ b/Individual_Project/Posit_Multiplier/simulation/questa/Posit_Multiplier.vo
@@ -0,0 +1,4696 @@
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition"
+
+// DATE "02/14/2023 19:37:11"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for Questa Intel FPGA (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module Posit_Multiplier (
+	IN1,
+	IN2,
+	OUT);
+input 	[7:0] IN1;
+input 	[7:0] IN2;
+output 	[7:0] OUT;
+
+// Design Ports Information
+// OUT[0]	=>  Location: PIN_AD27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[1]	=>  Location: PIN_AA24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[2]	=>  Location: PIN_AB26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[3]	=>  Location: PIN_AB25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[4]	=>  Location: PIN_AE26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[5]	=>  Location: PIN_AA25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[6]	=>  Location: PIN_V23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// OUT[7]	=>  Location: PIN_AE27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[7]	=>  Location: PIN_W24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[7]	=>  Location: PIN_AE28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[6]	=>  Location: PIN_AF30,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[4]	=>  Location: PIN_AF28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[3]	=>  Location: PIN_AD26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[5]	=>  Location: PIN_W21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[2]	=>  Location: PIN_AH29,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[1]	=>  Location: PIN_W22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[6]	=>  Location: PIN_AF29,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[4]	=>  Location: PIN_AG30,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[3]	=>  Location: PIN_Y23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[5]	=>  Location: PIN_AG28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[2]	=>  Location: PIN_AB23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[1]	=>  Location: PIN_Y24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN1[0]	=>  Location: PIN_W25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// IN2[0]	=>  Location: PIN_AB22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \Mult0~8 ;
+wire \Mult0~9 ;
+wire \Mult0~10 ;
+wire \Mult0~11 ;
+wire \Mult0~12 ;
+wire \Mult0~13 ;
+wire \Mult0~14 ;
+wire \Mult0~15 ;
+wire \Mult0~16 ;
+wire \Mult0~17 ;
+wire \Mult0~18 ;
+wire \Mult0~19 ;
+wire \Mult0~20 ;
+wire \Mult0~21 ;
+wire \Mult0~22 ;
+wire \Mult0~23 ;
+wire \Mult0~24 ;
+wire \Mult0~25 ;
+wire \Mult0~26 ;
+wire \Mult0~27 ;
+wire \Mult0~28 ;
+wire \Mult0~29 ;
+wire \Mult0~30 ;
+wire \Mult0~31 ;
+wire \Mult0~32 ;
+wire \Mult0~33 ;
+wire \Mult0~34 ;
+wire \Mult0~35 ;
+wire \Mult0~36 ;
+wire \Mult0~37 ;
+wire \Mult0~38 ;
+wire \Mult0~39 ;
+wire \Mult0~40 ;
+wire \Mult0~41 ;
+wire \Mult0~42 ;
+wire \Mult0~43 ;
+wire \Mult0~44 ;
+wire \Mult0~45 ;
+wire \Mult0~46 ;
+wire \Mult0~47 ;
+wire \Mult0~48 ;
+wire \Mult0~49 ;
+wire \Mult0~50 ;
+wire \Mult0~51 ;
+wire \Mult0~52 ;
+wire \Mult0~53 ;
+wire \Mult0~54 ;
+wire \Mult0~55 ;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \IN2[7]~input_o ;
+wire \IN1[7]~input_o ;
+wire \Operation~0_combout ;
+wire \IN1[6]~input_o ;
+wire \IN1[5]~input_o ;
+wire \IN1[4]~input_o ;
+wire \IN1[3]~input_o ;
+wire \IN1[2]~input_o ;
+wire \IN1[1]~input_o ;
+wire \IN1[0]~input_o ;
+wire \Extract_IN1|Add0~26 ;
+wire \Extract_IN1|Add0~22 ;
+wire \Extract_IN1|Add0~18 ;
+wire \Extract_IN1|Add0~10 ;
+wire \Extract_IN1|Add0~6 ;
+wire \Extract_IN1|Add0~14 ;
+wire \Extract_IN1|Add0~1_sumout ;
+wire \IN2[6]~input_o ;
+wire \IN2[5]~input_o ;
+wire \IN2[4]~input_o ;
+wire \IN2[3]~input_o ;
+wire \IN2[2]~input_o ;
+wire \IN2[1]~input_o ;
+wire \IN2[0]~input_o ;
+wire \Extract_IN2|Add0~26 ;
+wire \Extract_IN2|Add0~22 ;
+wire \Extract_IN2|Add0~18 ;
+wire \Extract_IN2|Add0~10 ;
+wire \Extract_IN2|Add0~6 ;
+wire \Extract_IN2|Add0~14 ;
+wire \Extract_IN2|Add0~1_sumout ;
+wire \Extract_IN1|Add0~13_sumout ;
+wire \Extract_IN1|Add0~5_sumout ;
+wire \Extract_IN1|Add0~9_sumout ;
+wire \Extract_IN1|LBD1|always0~0_combout ;
+wire \Extract_IN1|Add0~17_sumout ;
+wire \Extract_IN1|Add0~21_sumout ;
+wire \Extract_IN1|LBD1|EndPosition[2]~2_combout ;
+wire \Extract_IN1|LBD1|EndPosition[1]~0_combout ;
+wire \Extract_IN1|Add1~6 ;
+wire \Extract_IN1|Add1~11 ;
+wire \Extract_IN1|Add1~15 ;
+wire \Extract_IN1|Add1~1_sumout ;
+wire \Extract_IN1|Add1~14_sumout ;
+wire \Extract_IN2|Add0~17_sumout ;
+wire \Extract_IN2|Add0~5_sumout ;
+wire \Extract_IN2|Add0~13_sumout ;
+wire \Extract_IN2|Add0~9_sumout ;
+wire \Extract_IN2|LBD1|always0~0_combout ;
+wire \Extract_IN2|Add0~21_sumout ;
+wire \Extract_IN2|LBD1|EndPosition[2]~3_combout ;
+wire \Extract_IN1|Add1~10_sumout ;
+wire \Extract_IN2|LBD1|EndPosition~0_combout ;
+wire \Extract_IN2|LBD1|Add2~0_combout ;
+wire \Extract_IN2|LBD1|EndPosition[1]~1_combout ;
+wire \Extract_IN1|Add1~5_sumout ;
+wire \Extract_IN2|LBD1|Add2~1_combout ;
+wire \Extract_IN1|Add1~8_combout ;
+wire \Extract_IN2|LBD1|EndPosition[0]~2_combout ;
+wire \Extract_IN1|Add0~25_sumout ;
+wire \Extract_IN1|ShiftLeft0~1_combout ;
+wire \Extract_IN1|LBD1|EndPosition[0]~1_combout ;
+wire \Extract_IN1|ShiftLeft0~0_combout ;
+wire \Extract_IN1|ShiftLeft0~2_combout ;
+wire \Extract_IN1|ShiftLeft0~3_combout ;
+wire \Extract_IN2|LBD1|EndPosition[0]~4_combout ;
+wire \Extract_IN2|ShiftLeft0~1_combout ;
+wire \Extract_IN2|Add0~25_sumout ;
+wire \Extract_IN2|ShiftLeft0~2_combout ;
+wire \Extract_IN2|ShiftLeft0~0_combout ;
+wire \Extract_IN2|ShiftLeft0~3_combout ;
+wire \Extract_IN2|ShiftLeft0~4_combout ;
+wire \Extract_IN2|ShiftLeft0~5_combout ;
+wire \Extract_IN1|ShiftLeft0~4_combout ;
+wire \Extract_IN1|ShiftLeft0~5_combout ;
+wire \Extract_IN1|ShiftLeft0~6_combout ;
+wire \Extract_IN1|ShiftLeft0~7_combout ;
+wire \Extract_IN2|ShiftLeft0~6_combout ;
+wire \Extract_IN2|ShiftLeft0~7_combout ;
+wire \Extract_IN1|ShiftLeft0~9_combout ;
+wire \Extract_IN1|ShiftLeft0~8_combout ;
+wire \Extract_IN2|ShiftLeft0~9_combout ;
+wire \Extract_IN2|ShiftLeft0~8_combout ;
+wire \Extract_IN2|Add1~34_cout ;
+wire \Extract_IN2|Add1~30 ;
+wire \Extract_IN2|Add1~26 ;
+wire \Extract_IN2|Add1~22 ;
+wire \Extract_IN2|Add1~10 ;
+wire \Extract_IN2|Add1~6 ;
+wire \Extract_IN2|Add1~14 ;
+wire \Extract_IN2|Add1~18 ;
+wire \Extract_IN2|Add1~1_sumout ;
+wire \Extract_IN2|Add1~25_sumout ;
+wire \Extract_IN2|Add1~29_sumout ;
+wire \Add2~18 ;
+wire \Add2~13_sumout ;
+wire \Extract_IN2|Add1~21_sumout ;
+wire \Add2~14 ;
+wire \Add2~9_sumout ;
+wire \Add2~17_sumout ;
+wire \R_O~0_combout ;
+wire \Extract_IN2|Add1~13_sumout ;
+wire \Extract_IN2|Add1~5_sumout ;
+wire \Extract_IN2|Add1~9_sumout ;
+wire \Add2~10 ;
+wire \Add2~6 ;
+wire \Add2~2 ;
+wire \Add2~21_sumout ;
+wire \Add2~1_sumout ;
+wire \Add2~5_sumout ;
+wire \Add3~0_combout ;
+wire \R_O[2]~1_combout ;
+wire \ShiftRight0~0_combout ;
+wire \LessThan0~0_combout ;
+wire \Extract_IN2|Add1~17_sumout ;
+wire \Add2~22 ;
+wire \Add2~25_sumout ;
+wire \R_O[3]~4_combout ;
+wire \LessThan0~1_combout ;
+wire \R_O[0]~2_combout ;
+wire \R_O[1]~3_combout ;
+wire \ShiftRight0~3_combout ;
+wire \Mult_Mant_N[13]~0_combout ;
+wire \ShiftRight0~4_combout ;
+wire \Total_EON[4]~0_combout ;
+wire \ShiftRight0~1_combout ;
+wire \Total_EON[3]~1_combout ;
+wire \ShiftRight0~2_combout ;
+wire \ShiftRight0~5_combout ;
+wire \Mult_Mant_N[11]~2_combout ;
+wire \ShiftRight0~19_combout ;
+wire \ShiftRight0~14_combout ;
+wire \ShiftRight0~20_combout ;
+wire \Mult_Mant_N[14]~1_combout ;
+wire \ShiftRight0~7_combout ;
+wire \ShiftRight0~11_combout ;
+wire \ulp~3_combout ;
+wire \ShiftRight0~25_combout ;
+wire \Mult_Mant_N[10]~3_combout ;
+wire \WideOr1~0_combout ;
+wire \WideOr1~1_combout ;
+wire \WideOr1~2_combout ;
+wire \ShiftRight0~26_combout ;
+wire \Mult_Mant_N[12]~4_combout ;
+wire \ShiftRight0~33_combout ;
+wire \ShiftRight0~28_combout ;
+wire \ShiftRight0~23_combout ;
+wire \ulp~2_combout ;
+wire \ulp~5_combout ;
+wire \ShiftRight0~21_combout ;
+wire \ulp~0_combout ;
+wire \ShiftRight0~36_combout ;
+wire \ShiftRight0~35_combout ;
+wire \ShiftRight0~37_combout ;
+wire \ShiftRight0~9_combout ;
+wire \ShiftRight0~34_combout ;
+wire \ulp~1_combout ;
+wire \ShiftRight0~31_combout ;
+wire \ShiftRight0~29_combout ;
+wire \ShiftRight0~32_combout ;
+wire \ShiftRight0~22_combout ;
+wire \ShiftRight0~24_combout ;
+wire \ShiftRight0~30_combout ;
+wire \ShiftRight0~27_combout ;
+wire \ulp~4_combout ;
+wire \Add4~30 ;
+wire \Add4~1_sumout ;
+wire \Add4~29_sumout ;
+wire \sft_tmp_o_rnd[0]~0_combout ;
+wire \Add5~1_sumout ;
+wire \sft_tmp_oN~0_combout ;
+wire \ShiftRight0~6_combout ;
+wire \ShiftRight0~8_combout ;
+wire \Add4~2 ;
+wire \Add4~5_sumout ;
+wire \Add5~2 ;
+wire \Add5~5_sumout ;
+wire \sft_tmp_oN~1_combout ;
+wire \ShiftRight0~12_combout ;
+wire \ShiftRight0~10_combout ;
+wire \Add4~6 ;
+wire \Add4~9_sumout ;
+wire \ShiftRight0~13_combout ;
+wire \Add5~6 ;
+wire \Add5~9_sumout ;
+wire \sft_tmp_oN~2_combout ;
+wire \ShiftRight0~15_combout ;
+wire \Add4~10 ;
+wire \Add4~13_sumout ;
+wire \Add5~10 ;
+wire \Add5~13_sumout ;
+wire \sft_tmp_oN~3_combout ;
+wire \ShiftRight0~16_combout ;
+wire \Add4~14 ;
+wire \Add4~17_sumout ;
+wire \Add5~14 ;
+wire \Add5~17_sumout ;
+wire \sft_tmp_oN~4_combout ;
+wire \ShiftRight0~17_combout ;
+wire \Add4~18 ;
+wire \Add4~21_sumout ;
+wire \Add5~18 ;
+wire \Add5~21_sumout ;
+wire \sft_tmp_oN~5_combout ;
+wire \Add4~22 ;
+wire \Add4~25_sumout ;
+wire \ShiftRight0~18_combout ;
+wire \Add5~22 ;
+wire \Add5~25_sumout ;
+wire \sft_tmp_oN~6_combout ;
+wire [15:0] Mult_Mant;
+
+wire [63:0] \Mult0~mac_RESULTA_bus ;
+
+assign Mult_Mant[0] = \Mult0~mac_RESULTA_bus [0];
+assign Mult_Mant[1] = \Mult0~mac_RESULTA_bus [1];
+assign Mult_Mant[2] = \Mult0~mac_RESULTA_bus [2];
+assign Mult_Mant[3] = \Mult0~mac_RESULTA_bus [3];
+assign Mult_Mant[4] = \Mult0~mac_RESULTA_bus [4];
+assign Mult_Mant[5] = \Mult0~mac_RESULTA_bus [5];
+assign Mult_Mant[6] = \Mult0~mac_RESULTA_bus [6];
+assign Mult_Mant[7] = \Mult0~mac_RESULTA_bus [7];
+assign Mult_Mant[8] = \Mult0~mac_RESULTA_bus [8];
+assign Mult_Mant[9] = \Mult0~mac_RESULTA_bus [9];
+assign Mult_Mant[10] = \Mult0~mac_RESULTA_bus [10];
+assign Mult_Mant[11] = \Mult0~mac_RESULTA_bus [11];
+assign Mult_Mant[12] = \Mult0~mac_RESULTA_bus [12];
+assign Mult_Mant[13] = \Mult0~mac_RESULTA_bus [13];
+assign Mult_Mant[14] = \Mult0~mac_RESULTA_bus [14];
+assign Mult_Mant[15] = \Mult0~mac_RESULTA_bus [15];
+assign \Mult0~8  = \Mult0~mac_RESULTA_bus [16];
+assign \Mult0~9  = \Mult0~mac_RESULTA_bus [17];
+assign \Mult0~10  = \Mult0~mac_RESULTA_bus [18];
+assign \Mult0~11  = \Mult0~mac_RESULTA_bus [19];
+assign \Mult0~12  = \Mult0~mac_RESULTA_bus [20];
+assign \Mult0~13  = \Mult0~mac_RESULTA_bus [21];
+assign \Mult0~14  = \Mult0~mac_RESULTA_bus [22];
+assign \Mult0~15  = \Mult0~mac_RESULTA_bus [23];
+assign \Mult0~16  = \Mult0~mac_RESULTA_bus [24];
+assign \Mult0~17  = \Mult0~mac_RESULTA_bus [25];
+assign \Mult0~18  = \Mult0~mac_RESULTA_bus [26];
+assign \Mult0~19  = \Mult0~mac_RESULTA_bus [27];
+assign \Mult0~20  = \Mult0~mac_RESULTA_bus [28];
+assign \Mult0~21  = \Mult0~mac_RESULTA_bus [29];
+assign \Mult0~22  = \Mult0~mac_RESULTA_bus [30];
+assign \Mult0~23  = \Mult0~mac_RESULTA_bus [31];
+assign \Mult0~24  = \Mult0~mac_RESULTA_bus [32];
+assign \Mult0~25  = \Mult0~mac_RESULTA_bus [33];
+assign \Mult0~26  = \Mult0~mac_RESULTA_bus [34];
+assign \Mult0~27  = \Mult0~mac_RESULTA_bus [35];
+assign \Mult0~28  = \Mult0~mac_RESULTA_bus [36];
+assign \Mult0~29  = \Mult0~mac_RESULTA_bus [37];
+assign \Mult0~30  = \Mult0~mac_RESULTA_bus [38];
+assign \Mult0~31  = \Mult0~mac_RESULTA_bus [39];
+assign \Mult0~32  = \Mult0~mac_RESULTA_bus [40];
+assign \Mult0~33  = \Mult0~mac_RESULTA_bus [41];
+assign \Mult0~34  = \Mult0~mac_RESULTA_bus [42];
+assign \Mult0~35  = \Mult0~mac_RESULTA_bus [43];
+assign \Mult0~36  = \Mult0~mac_RESULTA_bus [44];
+assign \Mult0~37  = \Mult0~mac_RESULTA_bus [45];
+assign \Mult0~38  = \Mult0~mac_RESULTA_bus [46];
+assign \Mult0~39  = \Mult0~mac_RESULTA_bus [47];
+assign \Mult0~40  = \Mult0~mac_RESULTA_bus [48];
+assign \Mult0~41  = \Mult0~mac_RESULTA_bus [49];
+assign \Mult0~42  = \Mult0~mac_RESULTA_bus [50];
+assign \Mult0~43  = \Mult0~mac_RESULTA_bus [51];
+assign \Mult0~44  = \Mult0~mac_RESULTA_bus [52];
+assign \Mult0~45  = \Mult0~mac_RESULTA_bus [53];
+assign \Mult0~46  = \Mult0~mac_RESULTA_bus [54];
+assign \Mult0~47  = \Mult0~mac_RESULTA_bus [55];
+assign \Mult0~48  = \Mult0~mac_RESULTA_bus [56];
+assign \Mult0~49  = \Mult0~mac_RESULTA_bus [57];
+assign \Mult0~50  = \Mult0~mac_RESULTA_bus [58];
+assign \Mult0~51  = \Mult0~mac_RESULTA_bus [59];
+assign \Mult0~52  = \Mult0~mac_RESULTA_bus [60];
+assign \Mult0~53  = \Mult0~mac_RESULTA_bus [61];
+assign \Mult0~54  = \Mult0~mac_RESULTA_bus [62];
+assign \Mult0~55  = \Mult0~mac_RESULTA_bus [63];
+
+// Location: IOOBUF_X89_Y8_N56
+cyclonev_io_obuf \OUT[0]~output (
+	.i(\sft_tmp_oN~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[0]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[0]~output .bus_hold = "false";
+defparam \OUT[0]~output .open_drain_output = "false";
+defparam \OUT[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N45
+cyclonev_io_obuf \OUT[1]~output (
+	.i(\sft_tmp_oN~1_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[1]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[1]~output .bus_hold = "false";
+defparam \OUT[1]~output .open_drain_output = "false";
+defparam \OUT[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N56
+cyclonev_io_obuf \OUT[2]~output (
+	.i(\sft_tmp_oN~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[2]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[2]~output .bus_hold = "false";
+defparam \OUT[2]~output .open_drain_output = "false";
+defparam \OUT[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N62
+cyclonev_io_obuf \OUT[3]~output (
+	.i(\sft_tmp_oN~3_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[3]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[3]~output .bus_hold = "false";
+defparam \OUT[3]~output .open_drain_output = "false";
+defparam \OUT[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N39
+cyclonev_io_obuf \OUT[4]~output (
+	.i(\sft_tmp_oN~4_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[4]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[4]~output .bus_hold = "false";
+defparam \OUT[4]~output .open_drain_output = "false";
+defparam \OUT[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N39
+cyclonev_io_obuf \OUT[5]~output (
+	.i(\sft_tmp_oN~5_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[5]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[5]~output .bus_hold = "false";
+defparam \OUT[5]~output .open_drain_output = "false";
+defparam \OUT[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N5
+cyclonev_io_obuf \OUT[6]~output (
+	.i(\sft_tmp_oN~6_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[6]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[6]~output .bus_hold = "false";
+defparam \OUT[6]~output .open_drain_output = "false";
+defparam \OUT[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N79
+cyclonev_io_obuf \OUT[7]~output (
+	.i(\Operation~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(OUT[7]),
+	.obar());
+// synopsys translate_off
+defparam \OUT[7]~output .bus_hold = "false";
+defparam \OUT[7]~output .open_drain_output = "false";
+defparam \OUT[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y11_N95
+cyclonev_io_ibuf \IN2[7]~input (
+	.i(IN2[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[7]~input_o ));
+// synopsys translate_off
+defparam \IN2[7]~input .bus_hold = "false";
+defparam \IN2[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y15_N21
+cyclonev_io_ibuf \IN1[7]~input (
+	.i(IN1[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[7]~input_o ));
+// synopsys translate_off
+defparam \IN1[7]~input .bus_hold = "false";
+defparam \IN1[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N57
+cyclonev_lcell_comb \Operation~0 (
+// Equation(s):
+// \Operation~0_combout  = ( \IN1[7]~input_o  & ( !\IN2[7]~input_o  ) ) # ( !\IN1[7]~input_o  & ( \IN2[7]~input_o  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\IN2[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[7]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Operation~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Operation~0 .extended_lut = "off";
+defparam \Operation~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \Operation~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y15_N38
+cyclonev_io_ibuf \IN1[6]~input (
+	.i(IN1[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[6]~input_o ));
+// synopsys translate_off
+defparam \IN1[6]~input .bus_hold = "false";
+defparam \IN1[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N38
+cyclonev_io_ibuf \IN1[5]~input (
+	.i(IN1[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[5]~input_o ));
+// synopsys translate_off
+defparam \IN1[5]~input .bus_hold = "false";
+defparam \IN1[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y16_N55
+cyclonev_io_ibuf \IN1[4]~input (
+	.i(IN1[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[4]~input_o ));
+// synopsys translate_off
+defparam \IN1[4]~input .bus_hold = "false";
+defparam \IN1[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N4
+cyclonev_io_ibuf \IN1[3]~input (
+	.i(IN1[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[3]~input_o ));
+// synopsys translate_off
+defparam \IN1[3]~input .bus_hold = "false";
+defparam \IN1[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N21
+cyclonev_io_ibuf \IN1[2]~input (
+	.i(IN1[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[2]~input_o ));
+// synopsys translate_off
+defparam \IN1[2]~input .bus_hold = "false";
+defparam \IN1[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N21
+cyclonev_io_ibuf \IN1[1]~input (
+	.i(IN1[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[1]~input_o ));
+// synopsys translate_off
+defparam \IN1[1]~input .bus_hold = "false";
+defparam \IN1[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y20_N44
+cyclonev_io_ibuf \IN1[0]~input (
+	.i(IN1[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN1[0]~input_o ));
+// synopsys translate_off
+defparam \IN1[0]~input .bus_hold = "false";
+defparam \IN1[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N30
+cyclonev_lcell_comb \Extract_IN1|Add0~25 (
+// Equation(s):
+// \Extract_IN1|Add0~25_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[0]~input_o ) ) + ( \IN1[7]~input_o  ) + ( !VCC ))
+// \Extract_IN1|Add0~26  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[0]~input_o ) ) + ( \IN1[7]~input_o  ) + ( !VCC ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN1[0]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~25_sumout ),
+	.cout(\Extract_IN1|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~25 .extended_lut = "off";
+defparam \Extract_IN1|Add0~25 .lut_mask = 64'h0000AAAA00005A5A;
+defparam \Extract_IN1|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N33
+cyclonev_lcell_comb \Extract_IN1|Add0~21 (
+// Equation(s):
+// \Extract_IN1|Add0~21_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[1]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~26  ))
+// \Extract_IN1|Add0~22  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[1]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~26  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN1[1]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~21_sumout ),
+	.cout(\Extract_IN1|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~21 .extended_lut = "off";
+defparam \Extract_IN1|Add0~21 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Extract_IN1|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N36
+cyclonev_lcell_comb \Extract_IN1|Add0~17 (
+// Equation(s):
+// \Extract_IN1|Add0~17_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[2]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~22  ))
+// \Extract_IN1|Add0~18  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[2]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~22  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN1[2]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~17_sumout ),
+	.cout(\Extract_IN1|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~17 .extended_lut = "off";
+defparam \Extract_IN1|Add0~17 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN1|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N39
+cyclonev_lcell_comb \Extract_IN1|Add0~9 (
+// Equation(s):
+// \Extract_IN1|Add0~9_sumout  = SUM(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[3]~input_o ) ) + ( \Extract_IN1|Add0~18  ))
+// \Extract_IN1|Add0~10  = CARRY(( GND ) + ( !\IN1[7]~input_o  $ (!\IN1[3]~input_o ) ) + ( \Extract_IN1|Add0~18  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN1[3]~input_o ),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~9_sumout ),
+	.cout(\Extract_IN1|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~9 .extended_lut = "off";
+defparam \Extract_IN1|Add0~9 .lut_mask = 64'h0000AA5500000000;
+defparam \Extract_IN1|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N42
+cyclonev_lcell_comb \Extract_IN1|Add0~5 (
+// Equation(s):
+// \Extract_IN1|Add0~5_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[4]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~10  ))
+// \Extract_IN1|Add0~6  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[4]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~10  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN1[4]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~5_sumout ),
+	.cout(\Extract_IN1|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~5 .extended_lut = "off";
+defparam \Extract_IN1|Add0~5 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN1|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N45
+cyclonev_lcell_comb \Extract_IN1|Add0~13 (
+// Equation(s):
+// \Extract_IN1|Add0~13_sumout  = SUM(( !\IN1[7]~input_o  $ (!\IN1[5]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~6  ))
+// \Extract_IN1|Add0~14  = CARRY(( !\IN1[7]~input_o  $ (!\IN1[5]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~6  ))
+
+	.dataa(!\IN1[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN1[5]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~13_sumout ),
+	.cout(\Extract_IN1|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~13 .extended_lut = "off";
+defparam \Extract_IN1|Add0~13 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Extract_IN1|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N48
+cyclonev_lcell_comb \Extract_IN1|Add0~1 (
+// Equation(s):
+// \Extract_IN1|Add0~1_sumout  = SUM(( !\IN1[6]~input_o  $ (!\IN1[7]~input_o ) ) + ( GND ) + ( \Extract_IN1|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(!\IN1[6]~input_o ),
+	.datac(!\IN1[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add0~1 .extended_lut = "off";
+defparam \Extract_IN1|Add0~1 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Extract_IN1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y15_N55
+cyclonev_io_ibuf \IN2[6]~input (
+	.i(IN2[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[6]~input_o ));
+// synopsys translate_off
+defparam \IN2[6]~input .bus_hold = "false";
+defparam \IN2[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N4
+cyclonev_io_ibuf \IN2[5]~input (
+	.i(IN2[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[5]~input_o ));
+// synopsys translate_off
+defparam \IN2[5]~input .bus_hold = "false";
+defparam \IN2[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y13_N55
+cyclonev_io_ibuf \IN2[4]~input (
+	.i(IN2[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[4]~input_o ));
+// synopsys translate_off
+defparam \IN2[4]~input .bus_hold = "false";
+defparam \IN2[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y16_N4
+cyclonev_io_ibuf \IN2[3]~input (
+	.i(IN2[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[3]~input_o ));
+// synopsys translate_off
+defparam \IN2[3]~input .bus_hold = "false";
+defparam \IN2[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y6_N55
+cyclonev_io_ibuf \IN2[2]~input (
+	.i(IN2[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[2]~input_o ));
+// synopsys translate_off
+defparam \IN2[2]~input .bus_hold = "false";
+defparam \IN2[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N21
+cyclonev_io_ibuf \IN2[1]~input (
+	.i(IN2[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[1]~input_o ));
+// synopsys translate_off
+defparam \IN2[1]~input .bus_hold = "false";
+defparam \IN2[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y9_N4
+cyclonev_io_ibuf \IN2[0]~input (
+	.i(IN2[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\IN2[0]~input_o ));
+// synopsys translate_off
+defparam \IN2[0]~input .bus_hold = "false";
+defparam \IN2[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N0
+cyclonev_lcell_comb \Extract_IN2|Add0~25 (
+// Equation(s):
+// \Extract_IN2|Add0~25_sumout  = SUM(( \IN2[7]~input_o  ) + ( !\IN2[7]~input_o  $ (!\IN2[0]~input_o ) ) + ( !VCC ))
+// \Extract_IN2|Add0~26  = CARRY(( \IN2[7]~input_o  ) + ( !\IN2[7]~input_o  $ (!\IN2[0]~input_o ) ) + ( !VCC ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\IN2[0]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~25_sumout ),
+	.cout(\Extract_IN2|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~25 .extended_lut = "off";
+defparam \Extract_IN2|Add0~25 .lut_mask = 64'h0000AA5500005555;
+defparam \Extract_IN2|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N3
+cyclonev_lcell_comb \Extract_IN2|Add0~21 (
+// Equation(s):
+// \Extract_IN2|Add0~21_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[1]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~26  ))
+// \Extract_IN2|Add0~22  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[1]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~26  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN2[1]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~21_sumout ),
+	.cout(\Extract_IN2|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~21 .extended_lut = "off";
+defparam \Extract_IN2|Add0~21 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN2|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N6
+cyclonev_lcell_comb \Extract_IN2|Add0~17 (
+// Equation(s):
+// \Extract_IN2|Add0~17_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[2]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~22  ))
+// \Extract_IN2|Add0~18  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[2]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~22  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN2[2]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~17_sumout ),
+	.cout(\Extract_IN2|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~17 .extended_lut = "off";
+defparam \Extract_IN2|Add0~17 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Extract_IN2|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N9
+cyclonev_lcell_comb \Extract_IN2|Add0~9 (
+// Equation(s):
+// \Extract_IN2|Add0~9_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[3]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~18  ))
+// \Extract_IN2|Add0~10  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[3]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~18  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN2[3]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~9_sumout ),
+	.cout(\Extract_IN2|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~9 .extended_lut = "off";
+defparam \Extract_IN2|Add0~9 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN2|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N12
+cyclonev_lcell_comb \Extract_IN2|Add0~5 (
+// Equation(s):
+// \Extract_IN2|Add0~5_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[4]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~10  ))
+// \Extract_IN2|Add0~6  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[4]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~10  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(!\IN2[4]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~5_sumout ),
+	.cout(\Extract_IN2|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~5 .extended_lut = "off";
+defparam \Extract_IN2|Add0~5 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN2|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N15
+cyclonev_lcell_comb \Extract_IN2|Add0~13 (
+// Equation(s):
+// \Extract_IN2|Add0~13_sumout  = SUM(( !\IN2[7]~input_o  $ (!\IN2[5]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~6  ))
+// \Extract_IN2|Add0~14  = CARRY(( !\IN2[7]~input_o  $ (!\IN2[5]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~6  ))
+
+	.dataa(!\IN2[7]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\IN2[5]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~13_sumout ),
+	.cout(\Extract_IN2|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~13 .extended_lut = "off";
+defparam \Extract_IN2|Add0~13 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Extract_IN2|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N18
+cyclonev_lcell_comb \Extract_IN2|Add0~1 (
+// Equation(s):
+// \Extract_IN2|Add0~1_sumout  = SUM(( !\IN2[6]~input_o  $ (!\IN2[7]~input_o ) ) + ( GND ) + ( \Extract_IN2|Add0~14  ))
+
+	.dataa(!\IN2[6]~input_o ),
+	.datab(gnd),
+	.datac(!\IN2[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add0~1 .extended_lut = "off";
+defparam \Extract_IN2|Add0~1 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Extract_IN2|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N39
+cyclonev_lcell_comb \Extract_IN1|LBD1|always0~0 (
+// Equation(s):
+// \Extract_IN1|LBD1|always0~0_combout  = ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout ) # ((!\Extract_IN1|Add0~1_sumout ) # (!\Extract_IN1|Add0~5_sumout )) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( ((\Extract_IN1|Add0~5_sumout ) # 
+// (\Extract_IN1|Add0~1_sumout )) # (\Extract_IN1|Add0~13_sumout ) ) )
+
+	.dataa(!\Extract_IN1|Add0~13_sumout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\Extract_IN1|Add0~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|always0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|always0~0 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|always0~0 .lut_mask = 64'h7F7F7F7FFEFEFEFE;
+defparam \Extract_IN1|LBD1|always0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N6
+cyclonev_lcell_comb \Extract_IN1|LBD1|EndPosition[2]~2 (
+// Equation(s):
+// \Extract_IN1|LBD1|EndPosition[2]~2_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( !\Extract_IN1|Add0~1_sumout  $ (((!\Extract_IN1|Add0~21_sumout  & (!\Extract_IN1|Add0~13_sumout  & !\Extract_IN1|Add0~5_sumout )))) ) ) ) # ( 
+// !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( !\Extract_IN1|Add0~1_sumout  $ (((!\Extract_IN1|Add0~21_sumout  & ((!\Extract_IN1|Add0~13_sumout ) # (!\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~21_sumout  & 
+// (!\Extract_IN1|Add0~13_sumout  & !\Extract_IN1|Add0~5_sumout )))) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( !\Extract_IN1|Add0~1_sumout  $ (((!\Extract_IN1|Add0~21_sumout  & ((!\Extract_IN1|Add0~13_sumout ) # 
+// (!\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~21_sumout  & (!\Extract_IN1|Add0~13_sumout  & !\Extract_IN1|Add0~5_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( !\Extract_IN1|Add0~1_sumout  $ 
+// (((!\Extract_IN1|Add0~21_sumout ) # ((!\Extract_IN1|Add0~13_sumout ) # (!\Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~13_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|EndPosition[2]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|EndPosition[2]~2 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|EndPosition[2]~2 .lut_mask = 64'h0F1E1E781E7878F0;
+defparam \Extract_IN1|LBD1|EndPosition[2]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N12
+cyclonev_lcell_comb \Extract_IN1|LBD1|EndPosition[1]~0 (
+// Equation(s):
+// \Extract_IN1|LBD1|EndPosition[1]~0_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (((!\Extract_IN1|Add0~1_sumout )))) # (\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~1_sumout  & 
+// ((!\Extract_IN1|Add0~5_sumout ) # (\Extract_IN1|Add0~21_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & ((!\Extract_IN1|Add0~1_sumout ))) # (\Extract_IN1|Add0~13_sumout  & 
+// (!\Extract_IN1|Add0~5_sumout  & \Extract_IN1|Add0~1_sumout )) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~5_sumout  & !\Extract_IN1|Add0~1_sumout )) # 
+// (\Extract_IN1|Add0~13_sumout  & ((\Extract_IN1|Add0~1_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (!\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~21_sumout ) # 
+// (\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~13_sumout  & (((\Extract_IN1|Add0~1_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(!\Extract_IN1|Add0~13_sumout ),
+	.datad(!\Extract_IN1|Add0~1_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .lut_mask = 64'hB00F300FF00CF00D;
+defparam \Extract_IN1|LBD1|EndPosition[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N0
+cyclonev_lcell_comb \Extract_IN1|Add1~5 (
+// Equation(s):
+// \Extract_IN1|Add1~5_sumout  = SUM(( !\Extract_IN1|Add0~1_sumout  $ (\Extract_IN2|Add0~1_sumout ) ) + ( !\Extract_IN1|Add0~1_sumout  $ (\Extract_IN1|LBD1|EndPosition[1]~0_combout ) ) + ( !VCC ))
+// \Extract_IN1|Add1~6  = CARRY(( !\Extract_IN1|Add0~1_sumout  $ (\Extract_IN2|Add0~1_sumout ) ) + ( !\Extract_IN1|Add0~1_sumout  $ (\Extract_IN1|LBD1|EndPosition[1]~0_combout ) ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add1~5_sumout ),
+	.cout(\Extract_IN1|Add1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add1~5 .extended_lut = "off";
+defparam \Extract_IN1|Add1~5 .lut_mask = 64'h000033CC0000C3C3;
+defparam \Extract_IN1|Add1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N3
+cyclonev_lcell_comb \Extract_IN1|Add1~10 (
+// Equation(s):
+// \Extract_IN1|Add1~10_sumout  = SUM(( (\Extract_IN1|Add0~1_sumout  & \Extract_IN2|Add0~1_sumout ) ) + ( (!\Extract_IN1|LBD1|always0~0_combout  & ((!\Extract_IN1|LBD1|EndPosition[2]~2_combout  & (\Extract_IN1|Add0~1_sumout )) # 
+// (\Extract_IN1|LBD1|EndPosition[2]~2_combout  & ((!\Extract_IN1|Add0~17_sumout ))))) # (\Extract_IN1|LBD1|always0~0_combout  & (!\Extract_IN1|Add0~1_sumout )) ) + ( \Extract_IN1|Add1~6  ))
+// \Extract_IN1|Add1~11  = CARRY(( (\Extract_IN1|Add0~1_sumout  & \Extract_IN2|Add0~1_sumout ) ) + ( (!\Extract_IN1|LBD1|always0~0_combout  & ((!\Extract_IN1|LBD1|EndPosition[2]~2_combout  & (\Extract_IN1|Add0~1_sumout )) # 
+// (\Extract_IN1|LBD1|EndPosition[2]~2_combout  & ((!\Extract_IN1|Add0~17_sumout ))))) # (\Extract_IN1|LBD1|always0~0_combout  & (!\Extract_IN1|Add0~1_sumout )) ) + ( \Extract_IN1|Add1~6  ))
+
+	.dataa(!\Extract_IN1|LBD1|always0~0_combout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\Extract_IN1|Add0~17_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[2]~2_combout ),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add1~10_sumout ),
+	.cout(\Extract_IN1|Add1~11 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add1~10 .extended_lut = "off";
+defparam \Extract_IN1|Add1~10 .lut_mask = 64'h0000991B00000033;
+defparam \Extract_IN1|Add1~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N6
+cyclonev_lcell_comb \Extract_IN1|Add1~14 (
+// Equation(s):
+// \Extract_IN1|Add1~14_sumout  = SUM(( !\Extract_IN1|Add0~1_sumout  ) + ( (\Extract_IN1|Add0~1_sumout  & \Extract_IN2|Add0~1_sumout ) ) + ( \Extract_IN1|Add1~11  ))
+// \Extract_IN1|Add1~15  = CARRY(( !\Extract_IN1|Add0~1_sumout  ) + ( (\Extract_IN1|Add0~1_sumout  & \Extract_IN2|Add0~1_sumout ) ) + ( \Extract_IN1|Add1~11  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add1~11 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add1~14_sumout ),
+	.cout(\Extract_IN1|Add1~15 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add1~14 .extended_lut = "off";
+defparam \Extract_IN1|Add1~14 .lut_mask = 64'h0000FCFC0000CCCC;
+defparam \Extract_IN1|Add1~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N9
+cyclonev_lcell_comb \Extract_IN1|Add1~1 (
+// Equation(s):
+// \Extract_IN1|Add1~1_sumout  = SUM(( (\Extract_IN2|Add0~1_sumout ) # (\Extract_IN1|Add0~1_sumout ) ) + ( VCC ) + ( \Extract_IN1|Add1~15  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN1|Add1~15 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN1|Add1~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add1~1 .extended_lut = "off";
+defparam \Extract_IN1|Add1~1 .lut_mask = 64'h00000000000033FF;
+defparam \Extract_IN1|Add1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N42
+cyclonev_lcell_comb \Extract_IN2|LBD1|always0~0 (
+// Equation(s):
+// \Extract_IN2|LBD1|always0~0_combout  = ( \Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~5_sumout ) # (!\Extract_IN2|Add0~13_sumout ) ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  ) ) # ( 
+// \Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~1_sumout  ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~1_sumout  & ( (\Extract_IN2|Add0~13_sumout ) # (\Extract_IN2|Add0~5_sumout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add0~5_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(gnd),
+	.datae(!\Extract_IN2|Add0~9_sumout ),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|always0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|always0~0 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|always0~0 .lut_mask = 64'h3F3FFFFFFFFFFCFC;
+defparam \Extract_IN2|LBD1|always0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N48
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[2]~3 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[2]~3_combout  = ( \Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~21_sumout ) # (!\Extract_IN2|Add0~17_sumout ))) # 
+// (\Extract_IN2|Add0~5_sumout  & (!\Extract_IN2|Add0~21_sumout  & !\Extract_IN2|Add0~17_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~5_sumout  & (!\Extract_IN2|Add0~21_sumout  & !\Extract_IN2|Add0~17_sumout ))) ) ) ) # ( 
+// !\Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~5_sumout ) # ((!\Extract_IN2|Add0~21_sumout ) # (!\Extract_IN2|Add0~17_sumout )))) # (\Extract_IN2|Add0~13_sumout  & 
+// ((!\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~21_sumout ) # (!\Extract_IN2|Add0~17_sumout ))) # (\Extract_IN2|Add0~5_sumout  & (!\Extract_IN2|Add0~21_sumout  & !\Extract_IN2|Add0~17_sumout )))) ) ) ) # ( \Extract_IN2|Add0~9_sumout  & ( 
+// !\Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~21_sumout  & \Extract_IN2|Add0~17_sumout )) # (\Extract_IN2|Add0~5_sumout  & ((\Extract_IN2|Add0~17_sumout ) # 
+// (\Extract_IN2|Add0~21_sumout ))))) # (\Extract_IN2|Add0~13_sumout  & (((\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~21_sumout )) # (\Extract_IN2|Add0~5_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~1_sumout  & ( 
+// (!\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~21_sumout  & \Extract_IN2|Add0~17_sumout ))) # (\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~21_sumout  & \Extract_IN2|Add0~17_sumout 
+// )) # (\Extract_IN2|Add0~5_sumout  & ((\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~21_sumout ))))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~5_sumout ),
+	.datac(!\Extract_IN2|Add0~21_sumout ),
+	.datad(!\Extract_IN2|Add0~17_sumout ),
+	.datae(!\Extract_IN2|Add0~9_sumout ),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[2]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[2]~3 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[2]~3 .lut_mask = 64'h0117177FFEE8E880;
+defparam \Extract_IN2|LBD1|EndPosition[2]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N30
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition~0 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition~0_combout  = ( \Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (((\Extract_IN2|Add0~1_sumout ) # (\Extract_IN2|Add0~5_sumout )) # 
+// (\Extract_IN2|Add0~9_sumout )) # (\Extract_IN2|Add0~13_sumout ) ) ) ) # ( \Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout ) # ((!\Extract_IN2|Add0~9_sumout ) # ((!\Extract_IN2|Add0~5_sumout ) # 
+// (!\Extract_IN2|Add0~1_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(!\Extract_IN2|Add0~17_sumout ),
+	.dataf(!\Extract_IN2|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition~0 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition~0 .lut_mask = 64'hFFFFFFFE7FFFFFFF;
+defparam \Extract_IN2|LBD1|EndPosition~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N9
+cyclonev_lcell_comb \Extract_IN2|LBD1|Add2~0 (
+// Equation(s):
+// \Extract_IN2|LBD1|Add2~0_combout  = ( \Extract_IN2|Add0~13_sumout  & ( (!\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~9_sumout ))) # (\Extract_IN2|Add0~1_sumout  & 
+// ((!\Extract_IN2|Add0~9_sumout ) # (!\Extract_IN2|Add0~17_sumout ))))) # (\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (!\Extract_IN2|Add0~17_sumout ))) # (\Extract_IN2|Add0~1_sumout  & 
+// (!\Extract_IN2|Add0~9_sumout  & !\Extract_IN2|Add0~17_sumout )))) ) ) # ( !\Extract_IN2|Add0~13_sumout  & ( (!\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~1_sumout  & (\Extract_IN2|Add0~9_sumout  & \Extract_IN2|Add0~17_sumout )) # 
+// (\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~9_sumout ))))) # (\Extract_IN2|Add0~5_sumout  & ((!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~17_sumout ) # (\Extract_IN2|Add0~9_sumout ))) # 
+// (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (!\Extract_IN2|Add0~17_sumout ))))) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~9_sumout ),
+	.datad(!\Extract_IN2|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|Add2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|Add2~0 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|Add2~0 .lut_mask = 64'h177E177E7EE87EE8;
+defparam \Extract_IN2|LBD1|Add2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N42
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[1]~1 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[1]~1_combout  = ( \Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~9_sumout )))) # 
+// (\Extract_IN2|Add0~13_sumout  & (((\Extract_IN2|Add0~1_sumout )))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~5_sumout ) # 
+// (\Extract_IN2|Add0~9_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (!\Extract_IN2|Add0~5_sumout )))) ) ) ) # ( \Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  & ( 
+// (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~9_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # 
+// (!\Extract_IN2|Add0~5_sumout )))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (((!\Extract_IN2|Add0~1_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & 
+// ((!\Extract_IN2|Add0~9_sumout ) # (!\Extract_IN2|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(!\Extract_IN2|Add0~17_sumout ),
+	.dataf(!\Extract_IN2|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .lut_mask = 64'hAA542A542A542A55;
+defparam \Extract_IN2|LBD1|EndPosition[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N0
+cyclonev_lcell_comb \Extract_IN2|LBD1|Add2~1 (
+// Equation(s):
+// \Extract_IN2|LBD1|Add2~1_combout  = ( \Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~5_sumout  $ (!\Extract_IN2|Add0~13_sumout ) ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~17_sumout  & ( 
+// !\Extract_IN2|Add0~5_sumout  $ (\Extract_IN2|Add0~13_sumout ) ) ) ) # ( \Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~5_sumout  $ (\Extract_IN2|Add0~13_sumout ) ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( 
+// !\Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~5_sumout  $ (!\Extract_IN2|Add0~13_sumout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add0~5_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(gnd),
+	.datae(!\Extract_IN2|Add0~9_sumout ),
+	.dataf(!\Extract_IN2|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|Add2~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|Add2~1 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|Add2~1 .lut_mask = 64'h3C3CC3C3C3C33C3C;
+defparam \Extract_IN2|LBD1|Add2~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N0
+cyclonev_lcell_comb \Extract_IN1|Add1~8 (
+// Equation(s):
+// \Extract_IN1|Add1~8_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (((!\Extract_IN1|Add0~1_sumout  & !\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~13_sumout  & 
+// (((!\Extract_IN1|Add0~1_sumout ) # (!\Extract_IN1|Add0~5_sumout )) # (\Extract_IN1|Add0~21_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( ((!\Extract_IN1|Add0~1_sumout  & !\Extract_IN1|Add0~5_sumout )) # 
+// (\Extract_IN1|Add0~13_sumout ) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( (\Extract_IN1|Add0~13_sumout  & ((!\Extract_IN1|Add0~1_sumout ) # (!\Extract_IN1|Add0~5_sumout ))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( 
+// !\Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~21_sumout  & (!\Extract_IN1|Add0~1_sumout  & !\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~13_sumout  & (((!\Extract_IN1|Add0~1_sumout ) # 
+// (!\Extract_IN1|Add0~5_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~13_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|Add1~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|Add1~8 .extended_lut = "off";
+defparam \Extract_IN1|Add1~8 .lut_mask = 64'h73303330F333F331;
+defparam \Extract_IN1|Add1~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N9
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[0]~2 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[0]~2_combout  = ( \Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  & ( !\Extract_IN2|Add0~13_sumout  ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( \Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~13_sumout ) # 
+// (\Extract_IN2|Add0~5_sumout ) ) ) ) # ( \Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~1_sumout  & ( (!\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~13_sumout ) ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( !\Extract_IN2|Add0~1_sumout  & ( 
+// \Extract_IN2|Add0~13_sumout  ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(gnd),
+	.datae(!\Extract_IN2|Add0~9_sumout ),
+	.dataf(!\Extract_IN2|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[0]~2 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[0]~2 .lut_mask = 64'h5555F5F5AFAFAAAA;
+defparam \Extract_IN2|LBD1|EndPosition[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N30
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~1 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~5_sumout  & (!\Extract_IN1|Add0~13_sumout  & !\Extract_IN1|Add0~1_sumout )) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( 
+// \Extract_IN1|Add0~9_sumout  & ( (\Extract_IN1|Add0~21_sumout  & (\Extract_IN1|Add0~5_sumout  & (\Extract_IN1|Add0~13_sumout  & \Extract_IN1|Add0~1_sumout ))) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( 
+// (!\Extract_IN1|Add0~5_sumout  & (\Extract_IN1|Add0~21_sumout  & (!\Extract_IN1|Add0~13_sumout  & !\Extract_IN1|Add0~1_sumout ))) # (\Extract_IN1|Add0~5_sumout  & (((\Extract_IN1|Add0~13_sumout  & \Extract_IN1|Add0~1_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(!\Extract_IN1|Add0~13_sumout ),
+	.datad(!\Extract_IN1|Add0~1_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~1 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~1 .lut_mask = 64'h000040030001C000;
+defparam \Extract_IN1|ShiftLeft0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N48
+cyclonev_lcell_comb \Extract_IN1|LBD1|EndPosition[0]~1 (
+// Equation(s):
+// \Extract_IN1|LBD1|EndPosition[0]~1_combout  = ( \Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (((\Extract_IN1|Add0~5_sumout  & !\Extract_IN1|Add0~1_sumout )))) # (\Extract_IN1|Add0~13_sumout  & 
+// (\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~5_sumout ) # (\Extract_IN1|Add0~21_sumout )))) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~5_sumout  & 
+// !\Extract_IN1|Add0~1_sumout )) # (\Extract_IN1|Add0~13_sumout  & ((\Extract_IN1|Add0~1_sumout ))) ) ) ) # ( \Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & ((!\Extract_IN1|Add0~1_sumout ))) # 
+// (\Extract_IN1|Add0~13_sumout  & (!\Extract_IN1|Add0~5_sumout  & \Extract_IN1|Add0~1_sumout )) ) ) ) # ( !\Extract_IN1|Add0~17_sumout  & ( !\Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (!\Extract_IN1|Add0~1_sumout  & 
+// ((!\Extract_IN1|Add0~21_sumout ) # (\Extract_IN1|Add0~5_sumout )))) # (\Extract_IN1|Add0~13_sumout  & (((!\Extract_IN1|Add0~5_sumout  & \Extract_IN1|Add0~1_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~21_sumout ),
+	.datab(!\Extract_IN1|Add0~5_sumout ),
+	.datac(!\Extract_IN1|Add0~13_sumout ),
+	.datad(!\Extract_IN1|Add0~1_sumout ),
+	.datae(!\Extract_IN1|Add0~17_sumout ),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .extended_lut = "off";
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .lut_mask = 64'hB00CF00C300F300D;
+defparam \Extract_IN1|LBD1|EndPosition[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N57
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~0 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~0_combout  = ( \Extract_IN1|Add0~13_sumout  & ( (\Extract_IN1|Add0~5_sumout  & \Extract_IN1|Add0~1_sumout ) ) ) # ( !\Extract_IN1|Add0~13_sumout  & ( (!\Extract_IN1|Add0~5_sumout  & !\Extract_IN1|Add0~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN1|Add0~5_sumout ),
+	.datad(!\Extract_IN1|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~0 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~0 .lut_mask = 64'hF000F000000F000F;
+defparam \Extract_IN1|ShiftLeft0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N36
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~2 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~2_combout  = ( \Extract_IN1|Add0~9_sumout  & ( ((\Extract_IN1|Add0~13_sumout  & \Extract_IN1|Add0~1_sumout )) # (\Extract_IN1|Add0~5_sumout ) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( (\Extract_IN1|Add0~5_sumout  & 
+// ((\Extract_IN1|Add0~1_sumout ) # (\Extract_IN1|Add0~13_sumout ))) ) )
+
+	.dataa(!\Extract_IN1|Add0~13_sumout ),
+	.datab(!\Extract_IN1|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~2 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~2 .lut_mask = 64'h0077007711FF11FF;
+defparam \Extract_IN1|ShiftLeft0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N42
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~3 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~3_combout  = ( \Extract_IN1|ShiftLeft0~2_combout  & ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( (!\Extract_IN1|ShiftLeft0~0_combout ) # (\Extract_IN1|ShiftLeft0~1_combout ) ) ) ) # ( !\Extract_IN1|ShiftLeft0~2_combout  & ( 
+// \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( (\Extract_IN1|ShiftLeft0~1_combout  & \Extract_IN1|ShiftLeft0~0_combout ) ) ) ) # ( \Extract_IN1|ShiftLeft0~2_combout  & ( !\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( 
+// ((!\Extract_IN1|ShiftLeft0~0_combout ) # ((\Extract_IN1|Add0~25_sumout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout ))) # (\Extract_IN1|ShiftLeft0~1_combout ) ) ) ) # ( !\Extract_IN1|ShiftLeft0~2_combout  & ( !\Extract_IN1|LBD1|EndPosition[1]~0_combout  
+// & ( (\Extract_IN1|ShiftLeft0~0_combout  & (((\Extract_IN1|Add0~25_sumout  & !\Extract_IN1|LBD1|EndPosition[0]~1_combout )) # (\Extract_IN1|ShiftLeft0~1_combout ))) ) ) )
+
+	.dataa(!\Extract_IN1|Add0~25_sumout ),
+	.datab(!\Extract_IN1|ShiftLeft0~1_combout ),
+	.datac(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~0_combout ),
+	.datae(!\Extract_IN1|ShiftLeft0~2_combout ),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~3 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~3 .lut_mask = 64'h0073FF730033FF33;
+defparam \Extract_IN1|ShiftLeft0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N18
+cyclonev_lcell_comb \Extract_IN2|LBD1|EndPosition[0]~4 (
+// Equation(s):
+// \Extract_IN2|LBD1|EndPosition[0]~4_combout  = ( \Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (\Extract_IN2|Add0~5_sumout )))) # 
+// (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~9_sumout )))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & 
+// (((\Extract_IN2|Add0~5_sumout  & !\Extract_IN2|Add0~1_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~9_sumout )))) ) ) ) # ( \Extract_IN2|Add0~17_sumout  & ( 
+// !\Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (\Extract_IN2|Add0~5_sumout )))) # (\Extract_IN2|Add0~13_sumout  & (((!\Extract_IN2|Add0~5_sumout  & 
+// \Extract_IN2|Add0~1_sumout )))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~9_sumout ) # (\Extract_IN2|Add0~5_sumout )))) # 
+// (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~5_sumout ) # (\Extract_IN2|Add0~9_sumout )))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(!\Extract_IN2|Add0~17_sumout ),
+	.dataf(!\Extract_IN2|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|LBD1|EndPosition[0]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|LBD1|EndPosition[0]~4 .extended_lut = "off";
+defparam \Extract_IN2|LBD1|EndPosition[0]~4 .lut_mask = 64'h8A518A500A518A51;
+defparam \Extract_IN2|LBD1|EndPosition[0]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N6
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~1 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~1_combout  = ( \Extract_IN2|Add0~9_sumout  & ( ((\Extract_IN2|Add0~1_sumout  & \Extract_IN2|Add0~13_sumout )) # (\Extract_IN2|Add0~5_sumout ) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( (\Extract_IN2|Add0~5_sumout  & 
+// ((\Extract_IN2|Add0~13_sumout ) # (\Extract_IN2|Add0~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~1 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~1 .lut_mask = 64'h030F030F0F3F0F3F;
+defparam \Extract_IN2|ShiftLeft0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N24
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~2 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~2_combout  = ( \Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (((!\Extract_IN2|Add0~5_sumout  & !\Extract_IN2|Add0~1_sumout )))) # (\Extract_IN2|Add0~13_sumout  & 
+// (!\Extract_IN2|Add0~9_sumout  & (\Extract_IN2|Add0~5_sumout  & \Extract_IN2|Add0~1_sumout ))) ) ) ) # ( !\Extract_IN2|Add0~17_sumout  & ( \Extract_IN2|Add0~21_sumout  & ( (\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~9_sumout  & 
+// (\Extract_IN2|Add0~5_sumout  & \Extract_IN2|Add0~1_sumout ))) ) ) ) # ( \Extract_IN2|Add0~17_sumout  & ( !\Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~9_sumout  & (!\Extract_IN2|Add0~5_sumout  & 
+// !\Extract_IN2|Add0~1_sumout ))) # (\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~9_sumout  & (\Extract_IN2|Add0~5_sumout  & \Extract_IN2|Add0~1_sumout ))) ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~9_sumout ),
+	.datac(!\Extract_IN2|Add0~5_sumout ),
+	.datad(!\Extract_IN2|Add0~1_sumout ),
+	.datae(!\Extract_IN2|Add0~17_sumout ),
+	.dataf(!\Extract_IN2|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~2 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~2 .lut_mask = 64'h000020040001A004;
+defparam \Extract_IN2|ShiftLeft0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N27
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~0 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~0_combout  = ( \Extract_IN2|Add0~5_sumout  & ( (\Extract_IN2|Add0~1_sumout  & \Extract_IN2|Add0~13_sumout ) ) ) # ( !\Extract_IN2|Add0~5_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & !\Extract_IN2|Add0~13_sumout ) ) )
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~0 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~0 .lut_mask = 64'hA0A0A0A005050505;
+defparam \Extract_IN2|ShiftLeft0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N0
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~3 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~3_combout  = ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~2_combout  ) ) ) # ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  
+// & ( ((!\Extract_IN2|LBD1|EndPosition[0]~4_combout  & \Extract_IN2|Add0~25_sumout )) # (\Extract_IN2|ShiftLeft0~2_combout ) ) ) ) # ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~1_combout  
+// ) ) ) # ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~1_combout  ) ) )
+
+	.dataa(!\Extract_IN2|LBD1|EndPosition[0]~4_combout ),
+	.datab(!\Extract_IN2|ShiftLeft0~1_combout ),
+	.datac(!\Extract_IN2|Add0~25_sumout ),
+	.datad(!\Extract_IN2|ShiftLeft0~2_combout ),
+	.datae(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~3 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~3 .lut_mask = 64'h333333330AFF00FF;
+defparam \Extract_IN2|ShiftLeft0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N36
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~4 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~4_combout  = ( \Extract_IN2|Add0~9_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & (((\Extract_IN2|Add0~5_sumout  & \Extract_IN2|Add0~17_sumout )) # (\Extract_IN2|Add0~13_sumout ))) # (\Extract_IN2|Add0~1_sumout  & 
+// ((!\Extract_IN2|Add0~13_sumout ) # ((!\Extract_IN2|Add0~5_sumout  & \Extract_IN2|Add0~17_sumout )))) ) ) # ( !\Extract_IN2|Add0~9_sumout  & ( (\Extract_IN2|Add0~17_sumout  & ((!\Extract_IN2|Add0~5_sumout  & (\Extract_IN2|Add0~1_sumout  & 
+// \Extract_IN2|Add0~13_sumout )) # (\Extract_IN2|Add0~5_sumout  & (!\Extract_IN2|Add0~1_sumout  & !\Extract_IN2|Add0~13_sumout )))) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~17_sumout ),
+	.datad(!\Extract_IN2|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~4 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~4 .lut_mask = 64'h0402040237CE37CE;
+defparam \Extract_IN2|ShiftLeft0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N12
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~5 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~5_combout  = ( \Extract_IN2|ShiftLeft0~4_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  ) ) # ( !\Extract_IN2|ShiftLeft0~4_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( (!\Extract_IN2|LBD1|EndPosition[1]~1_combout  & 
+// (((\Extract_IN2|Add0~25_sumout  & \Extract_IN2|LBD1|EndPosition[0]~4_combout )))) # (\Extract_IN2|LBD1|EndPosition[1]~1_combout  & (\Extract_IN2|Add0~21_sumout  & ((!\Extract_IN2|LBD1|EndPosition[0]~4_combout )))) ) ) ) # ( 
+// \Extract_IN2|ShiftLeft0~4_combout  & ( !\Extract_IN2|ShiftLeft0~0_combout  ) )
+
+	.dataa(!\Extract_IN2|Add0~21_sumout ),
+	.datab(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datac(!\Extract_IN2|Add0~25_sumout ),
+	.datad(!\Extract_IN2|LBD1|EndPosition[0]~4_combout ),
+	.datae(!\Extract_IN2|ShiftLeft0~4_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~5 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~5 .lut_mask = 64'h0000FFFF110CFFFF;
+defparam \Extract_IN2|ShiftLeft0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N18
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~4 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~4_combout  = ( \Extract_IN1|Add0~9_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & (((\Extract_IN1|Add0~17_sumout  & \Extract_IN1|Add0~5_sumout )) # (\Extract_IN1|Add0~1_sumout ))) # (\Extract_IN1|Add0~13_sumout  & 
+// ((!\Extract_IN1|Add0~1_sumout ) # ((\Extract_IN1|Add0~17_sumout  & !\Extract_IN1|Add0~5_sumout )))) ) ) # ( !\Extract_IN1|Add0~9_sumout  & ( (\Extract_IN1|Add0~17_sumout  & ((!\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~5_sumout  & 
+// !\Extract_IN1|Add0~1_sumout )) # (\Extract_IN1|Add0~13_sumout  & (!\Extract_IN1|Add0~5_sumout  & \Extract_IN1|Add0~1_sumout )))) ) )
+
+	.dataa(!\Extract_IN1|Add0~13_sumout ),
+	.datab(!\Extract_IN1|Add0~17_sumout ),
+	.datac(!\Extract_IN1|Add0~5_sumout ),
+	.datad(!\Extract_IN1|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~4 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~4 .lut_mask = 64'h0210021057BA57BA;
+defparam \Extract_IN1|ShiftLeft0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N24
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~5 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~5_combout  = ( \Extract_IN1|ShiftLeft0~0_combout  & ( \Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( ((!\Extract_IN1|LBD1|EndPosition[1]~0_combout  & \Extract_IN1|Add0~25_sumout )) # (\Extract_IN1|ShiftLeft0~4_combout ) ) ) ) # ( 
+// !\Extract_IN1|ShiftLeft0~0_combout  & ( \Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( \Extract_IN1|ShiftLeft0~4_combout  ) ) ) # ( \Extract_IN1|ShiftLeft0~0_combout  & ( !\Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( 
+// ((\Extract_IN1|LBD1|EndPosition[1]~0_combout  & \Extract_IN1|Add0~21_sumout )) # (\Extract_IN1|ShiftLeft0~4_combout ) ) ) ) # ( !\Extract_IN1|ShiftLeft0~0_combout  & ( !\Extract_IN1|LBD1|EndPosition[0]~1_combout  & ( \Extract_IN1|ShiftLeft0~4_combout  ) ) 
+// )
+
+	.dataa(!\Extract_IN1|ShiftLeft0~4_combout ),
+	.datab(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datac(!\Extract_IN1|Add0~25_sumout ),
+	.datad(!\Extract_IN1|Add0~21_sumout ),
+	.datae(!\Extract_IN1|ShiftLeft0~0_combout ),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~5 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~5 .lut_mask = 64'h5555557755555D5D;
+defparam \Extract_IN1|ShiftLeft0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N21
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~6 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~6_combout  = ( \Extract_IN1|Add0~21_sumout  & ( (!\Extract_IN1|Add0~13_sumout  & ((!\Extract_IN1|Add0~1_sumout  & ((\Extract_IN1|Add0~5_sumout ))) # (\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~17_sumout )))) # 
+// (\Extract_IN1|Add0~13_sumout  & ((!\Extract_IN1|Add0~1_sumout  & (\Extract_IN1|Add0~17_sumout )) # (\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~5_sumout ))))) ) ) # ( !\Extract_IN1|Add0~21_sumout  & ( (\Extract_IN1|Add0~17_sumout  & 
+// (!\Extract_IN1|Add0~13_sumout  $ (!\Extract_IN1|Add0~1_sumout ))) ) )
+
+	.dataa(!\Extract_IN1|Add0~13_sumout ),
+	.datab(!\Extract_IN1|Add0~17_sumout ),
+	.datac(!\Extract_IN1|Add0~1_sumout ),
+	.datad(!\Extract_IN1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~6 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~6 .lut_mask = 64'h1212121217B217B2;
+defparam \Extract_IN1|ShiftLeft0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N54
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~7 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~7_combout  = ( \Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( ((!\Extract_IN1|LBD1|EndPosition[0]~1_combout  & (\Extract_IN1|ShiftLeft0~0_combout  & \Extract_IN1|Add0~25_sumout ))) # (\Extract_IN1|ShiftLeft0~6_combout ) ) ) # ( 
+// !\Extract_IN1|LBD1|EndPosition[1]~0_combout  & ( \Extract_IN1|ShiftLeft0~6_combout  ) )
+
+	.dataa(!\Extract_IN1|LBD1|EndPosition[0]~1_combout ),
+	.datab(!\Extract_IN1|ShiftLeft0~0_combout ),
+	.datac(!\Extract_IN1|Add0~25_sumout ),
+	.datad(!\Extract_IN1|ShiftLeft0~6_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|LBD1|EndPosition[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~7 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~7 .lut_mask = 64'h00FF00FF02FF02FF;
+defparam \Extract_IN1|ShiftLeft0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N39
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~6 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~6_combout  = ( \Extract_IN2|Add0~21_sumout  & ( (!\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~13_sumout  & (\Extract_IN2|Add0~5_sumout )) # (\Extract_IN2|Add0~13_sumout  & ((\Extract_IN2|Add0~17_sumout ))))) # 
+// (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~13_sumout  & ((\Extract_IN2|Add0~17_sumout ))) # (\Extract_IN2|Add0~13_sumout  & (!\Extract_IN2|Add0~5_sumout )))) ) ) # ( !\Extract_IN2|Add0~21_sumout  & ( (\Extract_IN2|Add0~17_sumout  & 
+// (!\Extract_IN2|Add0~1_sumout  $ (!\Extract_IN2|Add0~13_sumout ))) ) )
+
+	.dataa(!\Extract_IN2|Add0~5_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~13_sumout ),
+	.datad(!\Extract_IN2|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~6 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~6 .lut_mask = 64'h003C003C427E427E;
+defparam \Extract_IN2|ShiftLeft0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N48
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~7 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~7_combout  = ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( ((\Extract_IN2|Add0~25_sumout  & !\Extract_IN2|LBD1|EndPosition[0]~4_combout )) # (\Extract_IN2|ShiftLeft0~6_combout ) ) ) ) # ( 
+// !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( \Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~6_combout  ) ) ) # ( \Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~6_combout  
+// ) ) ) # ( !\Extract_IN2|LBD1|EndPosition[1]~1_combout  & ( !\Extract_IN2|ShiftLeft0~0_combout  & ( \Extract_IN2|ShiftLeft0~6_combout  ) ) )
+
+	.dataa(!\Extract_IN2|Add0~25_sumout ),
+	.datab(!\Extract_IN2|ShiftLeft0~6_combout ),
+	.datac(!\Extract_IN2|LBD1|EndPosition[0]~4_combout ),
+	.datad(gnd),
+	.datae(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.dataf(!\Extract_IN2|ShiftLeft0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~7 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~7 .lut_mask = 64'h3333333333337373;
+defparam \Extract_IN2|ShiftLeft0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N15
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~9 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~9_combout  = (\Extract_IN1|Add0~25_sumout  & (!\Extract_IN1|Add0~1_sumout  $ (!\Extract_IN1|Add0~13_sumout )))
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN1|Add0~25_sumout ),
+	.datad(!\Extract_IN1|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~9 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~9 .lut_mask = 64'h050A050A050A050A;
+defparam \Extract_IN1|ShiftLeft0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y13_N12
+cyclonev_lcell_comb \Extract_IN1|ShiftLeft0~8 (
+// Equation(s):
+// \Extract_IN1|ShiftLeft0~8_combout  = ( \Extract_IN1|Add0~5_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~25_sumout )) # (\Extract_IN1|Add0~13_sumout  & ((\Extract_IN1|Add0~21_sumout ))))) # 
+// (\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~21_sumout  & !\Extract_IN1|Add0~13_sumout )))) ) ) # ( !\Extract_IN1|Add0~5_sumout  & ( (!\Extract_IN1|Add0~1_sumout  & (((\Extract_IN1|Add0~21_sumout  & \Extract_IN1|Add0~13_sumout )))) # 
+// (\Extract_IN1|Add0~1_sumout  & ((!\Extract_IN1|Add0~13_sumout  & ((\Extract_IN1|Add0~21_sumout ))) # (\Extract_IN1|Add0~13_sumout  & (\Extract_IN1|Add0~25_sumout )))) ) )
+
+	.dataa(!\Extract_IN1|Add0~1_sumout ),
+	.datab(!\Extract_IN1|Add0~25_sumout ),
+	.datac(!\Extract_IN1|Add0~21_sumout ),
+	.datad(!\Extract_IN1|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN1|ShiftLeft0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN1|ShiftLeft0~8 .extended_lut = "off";
+defparam \Extract_IN1|ShiftLeft0~8 .lut_mask = 64'h051B051B270A270A;
+defparam \Extract_IN1|ShiftLeft0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N57
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~9 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~9_combout  = ( \Extract_IN2|Add0~25_sumout  & ( !\Extract_IN2|Add0~13_sumout  $ (!\Extract_IN2|Add0~1_sumout ) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~9 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~9 .lut_mask = 64'h0000000066666666;
+defparam \Extract_IN2|ShiftLeft0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y12_N54
+cyclonev_lcell_comb \Extract_IN2|ShiftLeft0~8 (
+// Equation(s):
+// \Extract_IN2|ShiftLeft0~8_combout  = ( \Extract_IN2|Add0~25_sumout  & ( (!\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~1_sumout  & ((\Extract_IN2|Add0~5_sumout ))) # (\Extract_IN2|Add0~1_sumout  & (\Extract_IN2|Add0~21_sumout )))) # 
+// (\Extract_IN2|Add0~13_sumout  & ((!\Extract_IN2|Add0~1_sumout  & (\Extract_IN2|Add0~21_sumout )) # (\Extract_IN2|Add0~1_sumout  & ((!\Extract_IN2|Add0~5_sumout ))))) ) ) # ( !\Extract_IN2|Add0~25_sumout  & ( (\Extract_IN2|Add0~21_sumout  & 
+// (!\Extract_IN2|Add0~13_sumout  $ (!\Extract_IN2|Add0~1_sumout ))) ) )
+
+	.dataa(!\Extract_IN2|Add0~13_sumout ),
+	.datab(!\Extract_IN2|Add0~1_sumout ),
+	.datac(!\Extract_IN2|Add0~21_sumout ),
+	.datad(!\Extract_IN2|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Extract_IN2|ShiftLeft0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|ShiftLeft0~8 .extended_lut = "off";
+defparam \Extract_IN2|ShiftLeft0~8 .lut_mask = 64'h06060606178E178E;
+defparam \Extract_IN2|ShiftLeft0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: DSP_X86_Y10_N0
+cyclonev_mac \Mult0~mac (
+	.sub(gnd),
+	.negate(gnd),
+	.accumulate(gnd),
+	.loadconst(gnd),
+	.ax({vcc,\Extract_IN1|ShiftLeft0~8_combout ,\Extract_IN1|ShiftLeft0~9_combout ,gnd,gnd,gnd,gnd,gnd}),
+	.ay({vcc,\Extract_IN2|ShiftLeft0~8_combout ,\Extract_IN2|ShiftLeft0~9_combout ,gnd,gnd,gnd,gnd,gnd}),
+	.az(26'b00000000000000000000000000),
+	.bx(18'b000000000000000000),
+	.by(19'b0000000000000000000),
+	.bz(18'b000000000000000000),
+	.coefsela(3'b000),
+	.coefselb(3'b000),
+	.clk(3'b000),
+	.aclr(2'b00),
+	.ena(3'b111),
+	.scanin(27'b000000000000000000000000000),
+	.chainin(1'b0),
+	.dftout(),
+	.resulta(\Mult0~mac_RESULTA_bus ),
+	.resultb(),
+	.scanout(),
+	.chainout());
+// synopsys translate_off
+defparam \Mult0~mac .accumulate_clock = "none";
+defparam \Mult0~mac .ax_clock = "none";
+defparam \Mult0~mac .ax_width = 8;
+defparam \Mult0~mac .ay_scan_in_clock = "none";
+defparam \Mult0~mac .ay_scan_in_width = 8;
+defparam \Mult0~mac .ay_use_scan_in = "false";
+defparam \Mult0~mac .az_clock = "none";
+defparam \Mult0~mac .bx_clock = "none";
+defparam \Mult0~mac .by_clock = "none";
+defparam \Mult0~mac .by_use_scan_in = "false";
+defparam \Mult0~mac .bz_clock = "none";
+defparam \Mult0~mac .coef_a_0 = 0;
+defparam \Mult0~mac .coef_a_1 = 0;
+defparam \Mult0~mac .coef_a_2 = 0;
+defparam \Mult0~mac .coef_a_3 = 0;
+defparam \Mult0~mac .coef_a_4 = 0;
+defparam \Mult0~mac .coef_a_5 = 0;
+defparam \Mult0~mac .coef_a_6 = 0;
+defparam \Mult0~mac .coef_a_7 = 0;
+defparam \Mult0~mac .coef_b_0 = 0;
+defparam \Mult0~mac .coef_b_1 = 0;
+defparam \Mult0~mac .coef_b_2 = 0;
+defparam \Mult0~mac .coef_b_3 = 0;
+defparam \Mult0~mac .coef_b_4 = 0;
+defparam \Mult0~mac .coef_b_5 = 0;
+defparam \Mult0~mac .coef_b_6 = 0;
+defparam \Mult0~mac .coef_b_7 = 0;
+defparam \Mult0~mac .coef_sel_a_clock = "none";
+defparam \Mult0~mac .coef_sel_b_clock = "none";
+defparam \Mult0~mac .delay_scan_out_ay = "false";
+defparam \Mult0~mac .delay_scan_out_by = "false";
+defparam \Mult0~mac .enable_double_accum = "false";
+defparam \Mult0~mac .load_const_clock = "none";
+defparam \Mult0~mac .load_const_value = 0;
+defparam \Mult0~mac .mode_sub_location = 0;
+defparam \Mult0~mac .negate_clock = "none";
+defparam \Mult0~mac .operand_source_max = "input";
+defparam \Mult0~mac .operand_source_may = "input";
+defparam \Mult0~mac .operand_source_mbx = "input";
+defparam \Mult0~mac .operand_source_mby = "input";
+defparam \Mult0~mac .operation_mode = "m9x9";
+defparam \Mult0~mac .output_clock = "none";
+defparam \Mult0~mac .preadder_subtract_a = "false";
+defparam \Mult0~mac .preadder_subtract_b = "false";
+defparam \Mult0~mac .result_a_width = 64;
+defparam \Mult0~mac .signed_max = "false";
+defparam \Mult0~mac .signed_may = "false";
+defparam \Mult0~mac .signed_mbx = "false";
+defparam \Mult0~mac .signed_mby = "false";
+defparam \Mult0~mac .sub_clock = "none";
+defparam \Mult0~mac .use_chainadder = "false";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N0
+cyclonev_lcell_comb \Extract_IN2|Add1~34 (
+// Equation(s):
+// \Extract_IN2|Add1~34_cout  = CARRY(( Mult_Mant[15] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!Mult_Mant[15]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\Extract_IN2|Add1~34_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~34 .extended_lut = "off";
+defparam \Extract_IN2|Add1~34 .lut_mask = 64'h0000000000000F0F;
+defparam \Extract_IN2|Add1~34 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N3
+cyclonev_lcell_comb \Extract_IN2|Add1~29 (
+// Equation(s):
+// \Extract_IN2|Add1~29_sumout  = SUM(( \Extract_IN1|ShiftLeft0~7_combout  ) + ( \Extract_IN2|ShiftLeft0~7_combout  ) + ( \Extract_IN2|Add1~34_cout  ))
+// \Extract_IN2|Add1~30  = CARRY(( \Extract_IN1|ShiftLeft0~7_combout  ) + ( \Extract_IN2|ShiftLeft0~7_combout  ) + ( \Extract_IN2|Add1~34_cout  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|ShiftLeft0~7_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~7_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~34_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~29_sumout ),
+	.cout(\Extract_IN2|Add1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~29 .extended_lut = "off";
+defparam \Extract_IN2|Add1~29 .lut_mask = 64'h0000F0F000003333;
+defparam \Extract_IN2|Add1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N6
+cyclonev_lcell_comb \Extract_IN2|Add1~25 (
+// Equation(s):
+// \Extract_IN2|Add1~25_sumout  = SUM(( \Extract_IN1|ShiftLeft0~5_combout  ) + ( \Extract_IN2|ShiftLeft0~5_combout  ) + ( \Extract_IN2|Add1~30  ))
+// \Extract_IN2|Add1~26  = CARRY(( \Extract_IN1|ShiftLeft0~5_combout  ) + ( \Extract_IN2|ShiftLeft0~5_combout  ) + ( \Extract_IN2|Add1~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|ShiftLeft0~5_combout ),
+	.datad(!\Extract_IN1|ShiftLeft0~5_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~25_sumout ),
+	.cout(\Extract_IN2|Add1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~25 .extended_lut = "off";
+defparam \Extract_IN2|Add1~25 .lut_mask = 64'h0000F0F0000000FF;
+defparam \Extract_IN2|Add1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N9
+cyclonev_lcell_comb \Extract_IN2|Add1~21 (
+// Equation(s):
+// \Extract_IN2|Add1~21_sumout  = SUM(( \Extract_IN1|ShiftLeft0~3_combout  ) + ( \Extract_IN2|ShiftLeft0~3_combout  ) + ( \Extract_IN2|Add1~26  ))
+// \Extract_IN2|Add1~22  = CARRY(( \Extract_IN1|ShiftLeft0~3_combout  ) + ( \Extract_IN2|ShiftLeft0~3_combout  ) + ( \Extract_IN2|Add1~26  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|ShiftLeft0~3_combout ),
+	.datac(!\Extract_IN2|ShiftLeft0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~21_sumout ),
+	.cout(\Extract_IN2|Add1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~21 .extended_lut = "off";
+defparam \Extract_IN2|Add1~21 .lut_mask = 64'h0000F0F000003333;
+defparam \Extract_IN2|Add1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N12
+cyclonev_lcell_comb \Extract_IN2|Add1~9 (
+// Equation(s):
+// \Extract_IN2|Add1~9_sumout  = SUM(( !\Extract_IN1|Add1~8_combout  ) + ( !\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition~0_combout  & (!\Extract_IN2|LBD1|Add2~1_combout )) # (\Extract_IN2|LBD1|EndPosition~0_combout  & 
+// ((\Extract_IN2|LBD1|EndPosition[0]~2_combout ))))) ) + ( \Extract_IN2|Add1~22  ))
+// \Extract_IN2|Add1~10  = CARRY(( !\Extract_IN1|Add1~8_combout  ) + ( !\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition~0_combout  & (!\Extract_IN2|LBD1|Add2~1_combout )) # (\Extract_IN2|LBD1|EndPosition~0_combout  & 
+// ((\Extract_IN2|LBD1|EndPosition[0]~2_combout ))))) ) + ( \Extract_IN2|Add1~22  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\Extract_IN2|LBD1|EndPosition~0_combout ),
+	.datac(!\Extract_IN2|LBD1|Add2~1_combout ),
+	.datad(!\Extract_IN1|Add1~8_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|LBD1|EndPosition[0]~2_combout ),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~9_sumout ),
+	.cout(\Extract_IN2|Add1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~9 .extended_lut = "off";
+defparam \Extract_IN2|Add1~9 .lut_mask = 64'h000095A60000FF00;
+defparam \Extract_IN2|Add1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N15
+cyclonev_lcell_comb \Extract_IN2|Add1~5 (
+// Equation(s):
+// \Extract_IN2|Add1~5_sumout  = SUM(( !\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition~0_combout  & (\Extract_IN2|LBD1|Add2~0_combout )) # (\Extract_IN2|LBD1|EndPosition~0_combout  & ((\Extract_IN2|LBD1|EndPosition[1]~1_combout ))))) ) + ( 
+// \Extract_IN1|Add1~5_sumout  ) + ( \Extract_IN2|Add1~10  ))
+// \Extract_IN2|Add1~6  = CARRY(( !\Extract_IN2|Add0~1_sumout  $ (((!\Extract_IN2|LBD1|EndPosition~0_combout  & (\Extract_IN2|LBD1|Add2~0_combout )) # (\Extract_IN2|LBD1|EndPosition~0_combout  & ((\Extract_IN2|LBD1|EndPosition[1]~1_combout ))))) ) + ( 
+// \Extract_IN1|Add1~5_sumout  ) + ( \Extract_IN2|Add1~10  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\Extract_IN2|LBD1|EndPosition~0_combout ),
+	.datac(!\Extract_IN2|LBD1|Add2~0_combout ),
+	.datad(!\Extract_IN2|LBD1|EndPosition[1]~1_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add1~5_sumout ),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~5_sumout ),
+	.cout(\Extract_IN2|Add1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~5 .extended_lut = "off";
+defparam \Extract_IN2|Add1~5 .lut_mask = 64'h0000FF000000A695;
+defparam \Extract_IN2|Add1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N18
+cyclonev_lcell_comb \Extract_IN2|Add1~13 (
+// Equation(s):
+// \Extract_IN2|Add1~13_sumout  = SUM(( (!\Extract_IN2|LBD1|always0~0_combout  & ((!\Extract_IN2|LBD1|EndPosition[2]~3_combout  & (\Extract_IN2|Add0~1_sumout )) # (\Extract_IN2|LBD1|EndPosition[2]~3_combout  & ((!\Extract_IN2|Add0~17_sumout ))))) # 
+// (\Extract_IN2|LBD1|always0~0_combout  & (!\Extract_IN2|Add0~1_sumout )) ) + ( \Extract_IN1|Add1~10_sumout  ) + ( \Extract_IN2|Add1~6  ))
+// \Extract_IN2|Add1~14  = CARRY(( (!\Extract_IN2|LBD1|always0~0_combout  & ((!\Extract_IN2|LBD1|EndPosition[2]~3_combout  & (\Extract_IN2|Add0~1_sumout )) # (\Extract_IN2|LBD1|EndPosition[2]~3_combout  & ((!\Extract_IN2|Add0~17_sumout ))))) # 
+// (\Extract_IN2|LBD1|always0~0_combout  & (!\Extract_IN2|Add0~1_sumout )) ) + ( \Extract_IN1|Add1~10_sumout  ) + ( \Extract_IN2|Add1~6  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(!\Extract_IN2|Add0~17_sumout ),
+	.datac(!\Extract_IN2|LBD1|always0~0_combout ),
+	.datad(!\Extract_IN2|LBD1|EndPosition[2]~3_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN1|Add1~10_sumout ),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~13_sumout ),
+	.cout(\Extract_IN2|Add1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~13 .extended_lut = "off";
+defparam \Extract_IN2|Add1~13 .lut_mask = 64'h0000FF0000005ACA;
+defparam \Extract_IN2|Add1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N21
+cyclonev_lcell_comb \Extract_IN2|Add1~17 (
+// Equation(s):
+// \Extract_IN2|Add1~17_sumout  = SUM(( !\Extract_IN2|Add0~1_sumout  ) + ( \Extract_IN1|Add1~14_sumout  ) + ( \Extract_IN2|Add1~14  ))
+// \Extract_IN2|Add1~18  = CARRY(( !\Extract_IN2|Add0~1_sumout  ) + ( \Extract_IN1|Add1~14_sumout  ) + ( \Extract_IN2|Add1~14  ))
+
+	.dataa(!\Extract_IN2|Add0~1_sumout ),
+	.datab(gnd),
+	.datac(!\Extract_IN1|Add1~14_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~17_sumout ),
+	.cout(\Extract_IN2|Add1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~17 .extended_lut = "off";
+defparam \Extract_IN2|Add1~17 .lut_mask = 64'h0000F0F00000AAAA;
+defparam \Extract_IN2|Add1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N24
+cyclonev_lcell_comb \Extract_IN2|Add1~1 (
+// Equation(s):
+// \Extract_IN2|Add1~1_sumout  = SUM(( VCC ) + ( !\Extract_IN1|Add1~1_sumout  ) + ( \Extract_IN2|Add1~18  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN1|Add1~1_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Extract_IN2|Add1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Extract_IN2|Add1~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Extract_IN2|Add1~1 .extended_lut = "off";
+defparam \Extract_IN2|Add1~1 .lut_mask = 64'h000033330000FFFF;
+defparam \Extract_IN2|Add1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N30
+cyclonev_lcell_comb \Add2~17 (
+// Equation(s):
+// \Add2~17_sumout  = SUM(( !\Extract_IN2|Add1~29_sumout  ) + ( VCC ) + ( !VCC ))
+// \Add2~18  = CARRY(( !\Extract_IN2|Add1~29_sumout  ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~29_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~17_sumout ),
+	.cout(\Add2~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~17 .extended_lut = "off";
+defparam \Add2~17 .lut_mask = 64'h000000000000F0F0;
+defparam \Add2~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N33
+cyclonev_lcell_comb \Add2~13 (
+// Equation(s):
+// \Add2~13_sumout  = SUM(( !\Extract_IN2|Add1~25_sumout  ) + ( GND ) + ( \Add2~18  ))
+// \Add2~14  = CARRY(( !\Extract_IN2|Add1~25_sumout  ) + ( GND ) + ( \Add2~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~25_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~13_sumout ),
+	.cout(\Add2~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~13 .extended_lut = "off";
+defparam \Add2~13 .lut_mask = 64'h0000FFFF0000F0F0;
+defparam \Add2~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N36
+cyclonev_lcell_comb \Add2~9 (
+// Equation(s):
+// \Add2~9_sumout  = SUM(( !\Extract_IN2|Add1~21_sumout  ) + ( GND ) + ( \Add2~14  ))
+// \Add2~10  = CARRY(( !\Extract_IN2|Add1~21_sumout  ) + ( GND ) + ( \Add2~14  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add1~21_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~9_sumout ),
+	.cout(\Add2~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~9 .extended_lut = "off";
+defparam \Add2~9 .lut_mask = 64'h0000FFFF0000CCCC;
+defparam \Add2~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N33
+cyclonev_lcell_comb \R_O~0 (
+// Equation(s):
+// \R_O~0_combout  = ( \Add2~17_sumout  ) # ( !\Add2~17_sumout  & ( ((\Add2~9_sumout ) # (\Add2~13_sumout )) # (\Extract_IN2|Add1~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~13_sumout ),
+	.datad(!\Add2~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Add2~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O~0 .extended_lut = "off";
+defparam \R_O~0 .lut_mask = 64'h3FFF3FFFFFFFFFFF;
+defparam \R_O~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N39
+cyclonev_lcell_comb \Add2~5 (
+// Equation(s):
+// \Add2~5_sumout  = SUM(( !\Extract_IN2|Add1~9_sumout  ) + ( GND ) + ( \Add2~10  ))
+// \Add2~6  = CARRY(( !\Extract_IN2|Add1~9_sumout  ) + ( GND ) + ( \Add2~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~9_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~5_sumout ),
+	.cout(\Add2~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~5 .extended_lut = "off";
+defparam \Add2~5 .lut_mask = 64'h0000FFFF0000F0F0;
+defparam \Add2~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N42
+cyclonev_lcell_comb \Add2~1 (
+// Equation(s):
+// \Add2~1_sumout  = SUM(( !\Extract_IN2|Add1~5_sumout  ) + ( GND ) + ( \Add2~6  ))
+// \Add2~2  = CARRY(( !\Extract_IN2|Add1~5_sumout  ) + ( GND ) + ( \Add2~6  ))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add1~5_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~1_sumout ),
+	.cout(\Add2~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~1 .extended_lut = "off";
+defparam \Add2~1 .lut_mask = 64'h0000FFFF0000CCCC;
+defparam \Add2~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N45
+cyclonev_lcell_comb \Add2~21 (
+// Equation(s):
+// \Add2~21_sumout  = SUM(( !\Extract_IN2|Add1~13_sumout  ) + ( GND ) + ( \Add2~2  ))
+// \Add2~22  = CARRY(( !\Extract_IN2|Add1~13_sumout  ) + ( GND ) + ( \Add2~2  ))
+
+	.dataa(!\Extract_IN2|Add1~13_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~21_sumout ),
+	.cout(\Add2~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~21 .extended_lut = "off";
+defparam \Add2~21 .lut_mask = 64'h0000FFFF0000AAAA;
+defparam \Add2~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N12
+cyclonev_lcell_comb \Add3~0 (
+// Equation(s):
+// \Add3~0_combout  = ( \Extract_IN2|Add1~5_sumout  & ( (!\Extract_IN2|Add1~1_sumout  & (((\Add2~1_sumout  & \Add2~5_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (\Extract_IN2|Add1~9_sumout )) ) ) # ( !\Extract_IN2|Add1~5_sumout  & ( 
+// (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout  & \Add2~5_sumout )) ) )
+
+	.dataa(!\Extract_IN2|Add1~9_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~1_sumout ),
+	.datad(!\Add2~5_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Add3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add3~0 .extended_lut = "off";
+defparam \Add3~0 .lut_mask = 64'h000C000C111D111D;
+defparam \Add3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N30
+cyclonev_lcell_comb \R_O[2]~1 (
+// Equation(s):
+// \R_O[2]~1_combout  = ( \Add3~0_combout  & ( !\R_O~0_combout  $ (((!\Extract_IN2|Add1~1_sumout  & ((!\Add2~21_sumout ))) # (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~13_sumout )))) ) ) # ( !\Add3~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & 
+// ((\Add2~21_sumout ))) # (\Extract_IN2|Add1~1_sumout  & (\Extract_IN2|Add1~13_sumout )) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Extract_IN2|Add1~13_sumout ),
+	.datad(!\Add2~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Add3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[2]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[2]~1 .extended_lut = "off";
+defparam \R_O[2]~1 .lut_mask = 64'h03CF03CF569A569A;
+defparam \R_O[2]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N36
+cyclonev_lcell_comb \ShiftRight0~0 (
+// Equation(s):
+// \ShiftRight0~0_combout  = ( \Add2~5_sumout  & ( \R_O~0_combout  & ( (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )) ) ) ) # ( !\Add2~5_sumout  & ( \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & 
+// (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & (((!\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )))) ) ) ) # ( \Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & 
+// (((\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )))) ) ) ) # ( !\Add2~5_sumout  & ( !\R_O~0_combout  & ( (\Extract_IN2|Add1~1_sumout  & (\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )) ) ) )
+
+	.dataa(!\Add2~1_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Extract_IN2|Add1~9_sumout ),
+	.datad(!\Extract_IN2|Add1~5_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\R_O~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~0 .extended_lut = "off";
+defparam \ShiftRight0~0 .lut_mask = 64'h0003444744740030;
+defparam \ShiftRight0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N0
+cyclonev_lcell_comb \LessThan0~0 (
+// Equation(s):
+// \LessThan0~0_combout  = ( !\R_O[2]~1_combout  & ( !\ShiftRight0~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~0 .extended_lut = "off";
+defparam \LessThan0~0 .lut_mask = 64'hFFFF000000000000;
+defparam \LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N48
+cyclonev_lcell_comb \Add2~25 (
+// Equation(s):
+// \Add2~25_sumout  = SUM(( !\Extract_IN2|Add1~17_sumout  ) + ( GND ) + ( \Add2~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~25_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~25 .extended_lut = "off";
+defparam \Add2~25 .lut_mask = 64'h0000FFFF0000F0F0;
+defparam \Add2~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y12_N54
+cyclonev_lcell_comb \R_O[3]~4 (
+// Equation(s):
+// \R_O[3]~4_combout  = ( !\Extract_IN2|Add1~1_sumout  & ( (!\Add2~25_sumout  $ (((!\Add3~0_combout ) # ((!\Add2~21_sumout ) # (!\R_O~0_combout ))))) ) ) # ( \Extract_IN2|Add1~1_sumout  & ( !\Extract_IN2|Add1~17_sumout  $ (((!\Add3~0_combout ) # 
+// ((!\Extract_IN2|Add1~13_sumout ) # ((!\R_O~0_combout ))))) ) )
+
+	.dataa(!\Extract_IN2|Add1~17_sumout ),
+	.datab(!\Add3~0_combout ),
+	.datac(!\Extract_IN2|Add1~13_sumout ),
+	.datad(!\R_O~0_combout ),
+	.datae(!\Extract_IN2|Add1~1_sumout ),
+	.dataf(!\Add2~25_sumout ),
+	.datag(!\Add2~21_sumout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[3]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[3]~4 .extended_lut = "on";
+defparam \R_O[3]~4 .lut_mask = 64'h00035556FFFC5556;
+defparam \R_O[3]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N30
+cyclonev_lcell_comb \LessThan0~1 (
+// Equation(s):
+// \LessThan0~1_combout  = ( !\R_O[3]~4_combout  & ( !\LessThan0~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\LessThan0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\R_O[3]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~1 .extended_lut = "off";
+defparam \LessThan0~1 .lut_mask = 64'hF0F0F0F000000000;
+defparam \LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N0
+cyclonev_lcell_comb \R_O[0]~2 (
+// Equation(s):
+// \R_O[0]~2_combout  = ( \Add2~5_sumout  & ( \Add2~17_sumout  & ( (!\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~1_sumout ) ) ) ) # ( !\Add2~5_sumout  & ( \Add2~17_sumout  & ( (!\Extract_IN2|Add1~9_sumout ) # (!\Extract_IN2|Add1~1_sumout ) ) ) ) # ( 
+// \Add2~5_sumout  & ( !\Add2~17_sumout  & ( (!\Extract_IN2|Add1~1_sumout  & (((!\Add2~13_sumout  & !\Add2~9_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~9_sumout )) ) ) ) # ( !\Add2~5_sumout  & ( !\Add2~17_sumout  & ( 
+// (!\Extract_IN2|Add1~1_sumout  & (((\Add2~9_sumout ) # (\Add2~13_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~9_sumout )) ) ) )
+
+	.dataa(!\Extract_IN2|Add1~9_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~13_sumout ),
+	.datad(!\Add2~9_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\Add2~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[0]~2 .extended_lut = "off";
+defparam \R_O[0]~2 .lut_mask = 64'h2EEEE222EEEE2222;
+defparam \R_O[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N6
+cyclonev_lcell_comb \R_O[1]~3 (
+// Equation(s):
+// \R_O[1]~3_combout  = ( \Add2~5_sumout  & ( \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & ((!\Extract_IN2|Add1~9_sumout  $ (!\Extract_IN2|Add1~5_sumout )))) ) ) ) # ( !\Add2~5_sumout  & ( 
+// \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & ((!\Extract_IN2|Add1~9_sumout  $ (!\Extract_IN2|Add1~5_sumout )))) ) ) ) # ( \Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & 
+// (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & ((\Extract_IN2|Add1~5_sumout ))) ) ) ) # ( !\Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & ((\Extract_IN2|Add1~5_sumout ))) ) 
+// ) )
+
+	.dataa(!\Add2~1_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Extract_IN2|Add1~9_sumout ),
+	.datad(!\Extract_IN2|Add1~5_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\R_O~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\R_O[1]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \R_O[1]~3 .extended_lut = "off";
+defparam \R_O[1]~3 .lut_mask = 64'h4477447747748BB8;
+defparam \R_O[1]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N0
+cyclonev_lcell_comb \ShiftRight0~3 (
+// Equation(s):
+// \ShiftRight0~3_combout  = ( \R_O[1]~3_combout  & ( Mult_Mant[11] & ( (!Mult_Mant[15] & (Mult_Mant[13])) # (Mult_Mant[15] & ((Mult_Mant[14]))) ) ) ) # ( !\R_O[1]~3_combout  & ( Mult_Mant[11] & ( (!Mult_Mant[15]) # (Mult_Mant[12]) ) ) ) # ( 
+// \R_O[1]~3_combout  & ( !Mult_Mant[11] & ( (!Mult_Mant[15] & (Mult_Mant[13])) # (Mult_Mant[15] & ((Mult_Mant[14]))) ) ) ) # ( !\R_O[1]~3_combout  & ( !Mult_Mant[11] & ( (Mult_Mant[12] & Mult_Mant[15]) ) ) )
+
+	.dataa(!Mult_Mant[12]),
+	.datab(!Mult_Mant[15]),
+	.datac(!Mult_Mant[13]),
+	.datad(!Mult_Mant[14]),
+	.datae(!\R_O[1]~3_combout ),
+	.dataf(!Mult_Mant[11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~3 .extended_lut = "off";
+defparam \ShiftRight0~3 .lut_mask = 64'h11110C3FDDDD0C3F;
+defparam \ShiftRight0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N6
+cyclonev_lcell_comb \Mult_Mant_N[13]~0 (
+// Equation(s):
+// \Mult_Mant_N[13]~0_combout  = (!Mult_Mant[15] & (Mult_Mant[12])) # (Mult_Mant[15] & ((Mult_Mant[13])))
+
+	.dataa(!Mult_Mant[12]),
+	.datab(!Mult_Mant[15]),
+	.datac(!Mult_Mant[13]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Mult_Mant_N[13]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Mult_Mant_N[13]~0 .extended_lut = "off";
+defparam \Mult_Mant_N[13]~0 .lut_mask = 64'h4747474747474747;
+defparam \Mult_Mant_N[13]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N15
+cyclonev_lcell_comb \ShiftRight0~4 (
+// Equation(s):
+// \ShiftRight0~4_combout  = ( \Mult_Mant_N[13]~0_combout  & ( (!\R_O[0]~2_combout  & (((\ShiftRight0~3_combout )))) # (\R_O[0]~2_combout  & ((!\R_O[1]~3_combout ) # ((\Extract_IN2|Add1~29_sumout )))) ) ) # ( !\Mult_Mant_N[13]~0_combout  & ( 
+// (!\R_O[0]~2_combout  & (((\ShiftRight0~3_combout )))) # (\R_O[0]~2_combout  & (\R_O[1]~3_combout  & (\Extract_IN2|Add1~29_sumout ))) ) )
+
+	.dataa(!\R_O[0]~2_combout ),
+	.datab(!\R_O[1]~3_combout ),
+	.datac(!\Extract_IN2|Add1~29_sumout ),
+	.datad(!\ShiftRight0~3_combout ),
+	.datae(gnd),
+	.dataf(!\Mult_Mant_N[13]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~4 .extended_lut = "off";
+defparam \ShiftRight0~4 .lut_mask = 64'h01AB01AB45EF45EF;
+defparam \ShiftRight0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N48
+cyclonev_lcell_comb \Total_EON[4]~0 (
+// Equation(s):
+// \Total_EON[4]~0_combout  = ( \Extract_IN2|Add1~5_sumout  & ( (\Add2~1_sumout ) # (\Extract_IN2|Add1~1_sumout ) ) ) # ( !\Extract_IN2|Add1~5_sumout  & ( (!\Extract_IN2|Add1~1_sumout  & \Add2~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Total_EON[4]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Total_EON[4]~0 .extended_lut = "off";
+defparam \Total_EON[4]~0 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
+defparam \Total_EON[4]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N24
+cyclonev_lcell_comb \ShiftRight0~1 (
+// Equation(s):
+// \ShiftRight0~1_combout  = ( \Add2~5_sumout  & ( \Add2~17_sumout  & ( (!\Extract_IN2|Add1~9_sumout ) # (!\Extract_IN2|Add1~1_sumout ) ) ) ) # ( !\Add2~5_sumout  & ( \Add2~17_sumout  & ( (!\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~1_sumout ) ) ) ) # ( 
+// \Add2~5_sumout  & ( !\Add2~17_sumout  & ( (!\Extract_IN2|Add1~1_sumout  & (((\Add2~9_sumout ) # (\Add2~13_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~9_sumout )) ) ) ) # ( !\Add2~5_sumout  & ( !\Add2~17_sumout  & ( 
+// (!\Extract_IN2|Add1~1_sumout  & (((!\Add2~13_sumout  & !\Add2~9_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (!\Extract_IN2|Add1~9_sumout )) ) ) )
+
+	.dataa(!\Extract_IN2|Add1~9_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~13_sumout ),
+	.datad(!\Add2~9_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\Add2~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~1 .extended_lut = "off";
+defparam \ShiftRight0~1 .lut_mask = 64'hE2222EEE2222EEEE;
+defparam \ShiftRight0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N51
+cyclonev_lcell_comb \Total_EON[3]~1 (
+// Equation(s):
+// \Total_EON[3]~1_combout  = (!\Extract_IN2|Add1~1_sumout  & (\Add2~5_sumout )) # (\Extract_IN2|Add1~1_sumout  & ((\Extract_IN2|Add1~9_sumout )))
+
+	.dataa(gnd),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~5_sumout ),
+	.datad(!\Extract_IN2|Add1~9_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Total_EON[3]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Total_EON[3]~1 .extended_lut = "off";
+defparam \Total_EON[3]~1 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
+defparam \Total_EON[3]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N0
+cyclonev_lcell_comb \ShiftRight0~2 (
+// Equation(s):
+// \ShiftRight0~2_combout  = ( \Extract_IN2|Add1~25_sumout  & ( \R_O~0_combout  & ( (!\Total_EON[4]~0_combout  & ((!\Total_EON[3]~1_combout  & ((\Extract_IN2|Add1~21_sumout ))) # (\Total_EON[3]~1_combout  & (\ShiftRight0~1_combout )))) # 
+// (\Total_EON[4]~0_combout  & (((\Total_EON[3]~1_combout )) # (\ShiftRight0~1_combout ))) ) ) ) # ( !\Extract_IN2|Add1~25_sumout  & ( \R_O~0_combout  & ( (!\Total_EON[4]~0_combout  & ((!\Total_EON[3]~1_combout  & ((\Extract_IN2|Add1~21_sumout ))) # 
+// (\Total_EON[3]~1_combout  & (\ShiftRight0~1_combout )))) # (\Total_EON[4]~0_combout  & (\ShiftRight0~1_combout  & ((!\Total_EON[3]~1_combout )))) ) ) ) # ( \Extract_IN2|Add1~25_sumout  & ( !\R_O~0_combout  & ( (!\Total_EON[4]~0_combout  & 
+// (((!\Total_EON[3]~1_combout ) # (\Extract_IN2|Add1~21_sumout )))) # (\Total_EON[4]~0_combout  & (\ShiftRight0~1_combout )) ) ) ) # ( !\Extract_IN2|Add1~25_sumout  & ( !\R_O~0_combout  & ( (!\Total_EON[4]~0_combout  & (((\Extract_IN2|Add1~21_sumout  & 
+// \Total_EON[3]~1_combout )))) # (\Total_EON[4]~0_combout  & (\ShiftRight0~1_combout )) ) ) )
+
+	.dataa(!\Total_EON[4]~0_combout ),
+	.datab(!\ShiftRight0~1_combout ),
+	.datac(!\Extract_IN2|Add1~21_sumout ),
+	.datad(!\Total_EON[3]~1_combout ),
+	.datae(!\Extract_IN2|Add1~25_sumout ),
+	.dataf(!\R_O~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~2 .extended_lut = "off";
+defparam \ShiftRight0~2 .lut_mask = 64'h111BBB1B1B221B77;
+defparam \ShiftRight0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N6
+cyclonev_lcell_comb \ShiftRight0~5 (
+// Equation(s):
+// \ShiftRight0~5_combout  = ( \R_O[2]~1_combout  & ( \ShiftRight0~2_combout  & ( (!\R_O[3]~4_combout ) # ((!\ShiftRight0~0_combout  & \Extract_IN2|Add1~1_sumout )) ) ) ) # ( !\R_O[2]~1_combout  & ( \ShiftRight0~2_combout  & ( (!\R_O[3]~4_combout  & 
+// ((\ShiftRight0~4_combout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout )) ) ) ) # ( \R_O[2]~1_combout  & ( !\ShiftRight0~2_combout  & ( (!\ShiftRight0~0_combout  & (\Extract_IN2|Add1~1_sumout  & \R_O[3]~4_combout )) ) ) ) # ( !\R_O[2]~1_combout  
+// & ( !\ShiftRight0~2_combout  & ( (!\R_O[3]~4_combout  & ((\ShiftRight0~4_combout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout )) ) ) )
+
+	.dataa(!\ShiftRight0~0_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\ShiftRight0~4_combout ),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~5 .extended_lut = "off";
+defparam \ShiftRight0~5 .lut_mask = 64'h03F3020203F3F2F2;
+defparam \ShiftRight0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N24
+cyclonev_lcell_comb \Mult_Mant_N[11]~2 (
+// Equation(s):
+// \Mult_Mant_N[11]~2_combout  = ( Mult_Mant[11] & ( (Mult_Mant[15]) # (Mult_Mant[10]) ) ) # ( !Mult_Mant[11] & ( (Mult_Mant[10] & !Mult_Mant[15]) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!Mult_Mant[10]),
+	.datad(!Mult_Mant[15]),
+	.datae(gnd),
+	.dataf(!Mult_Mant[11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Mult_Mant_N[11]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Mult_Mant_N[11]~2 .extended_lut = "off";
+defparam \Mult_Mant_N[11]~2 .lut_mask = 64'h0F000F000FFF0FFF;
+defparam \Mult_Mant_N[11]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N27
+cyclonev_lcell_comb \ShiftRight0~19 (
+// Equation(s):
+// \ShiftRight0~19_combout  = ( \Mult_Mant_N[13]~0_combout  & ( (!\R_O~0_combout  & (!\Total_EON[3]~1_combout  & ((\Total_EON[4]~0_combout ) # (\Mult_Mant_N[11]~2_combout )))) # (\R_O~0_combout  & (\Total_EON[3]~1_combout  & ((!\Total_EON[4]~0_combout ) # 
+// (\Mult_Mant_N[11]~2_combout )))) ) ) # ( !\Mult_Mant_N[13]~0_combout  & ( (\Mult_Mant_N[11]~2_combout  & ((!\R_O~0_combout  & (!\Total_EON[3]~1_combout  & !\Total_EON[4]~0_combout )) # (\R_O~0_combout  & (\Total_EON[3]~1_combout  & \Total_EON[4]~0_combout 
+// )))) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Total_EON[3]~1_combout ),
+	.datac(!\Mult_Mant_N[11]~2_combout ),
+	.datad(!\Total_EON[4]~0_combout ),
+	.datae(gnd),
+	.dataf(!\Mult_Mant_N[13]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~19 .extended_lut = "off";
+defparam \ShiftRight0~19 .lut_mask = 64'h0801080119891989;
+defparam \ShiftRight0~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N18
+cyclonev_lcell_comb \ShiftRight0~14 (
+// Equation(s):
+// \ShiftRight0~14_combout  = ( \R_O[0]~2_combout  & ( \Extract_IN2|Add1~1_sumout  & ( (!\R_O[1]~3_combout  & \Extract_IN2|Add1~25_sumout ) ) ) ) # ( !\R_O[0]~2_combout  & ( \Extract_IN2|Add1~1_sumout  & ( (!\R_O[1]~3_combout  & (\Extract_IN2|Add1~29_sumout 
+// )) # (\R_O[1]~3_combout  & ((\Extract_IN2|Add1~21_sumout ))) ) ) ) # ( \R_O[0]~2_combout  & ( !\Extract_IN2|Add1~1_sumout  & ( (\Extract_IN2|Add1~25_sumout ) # (\R_O[1]~3_combout ) ) ) ) # ( !\R_O[0]~2_combout  & ( !\Extract_IN2|Add1~1_sumout  & ( 
+// (!\R_O[1]~3_combout  & (\Extract_IN2|Add1~29_sumout )) # (\R_O[1]~3_combout  & ((\Extract_IN2|Add1~21_sumout ))) ) ) )
+
+	.dataa(!\R_O[1]~3_combout ),
+	.datab(!\Extract_IN2|Add1~29_sumout ),
+	.datac(!\Extract_IN2|Add1~21_sumout ),
+	.datad(!\Extract_IN2|Add1~25_sumout ),
+	.datae(!\R_O[0]~2_combout ),
+	.dataf(!\Extract_IN2|Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~14 .extended_lut = "off";
+defparam \ShiftRight0~14 .lut_mask = 64'h272755FF272700AA;
+defparam \ShiftRight0~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N33
+cyclonev_lcell_comb \ShiftRight0~20 (
+// Equation(s):
+// \ShiftRight0~20_combout  = ( \ShiftRight0~14_combout  & ( (((\ShiftRight0~3_combout  & \R_O[0]~2_combout )) # (\R_O[2]~1_combout )) # (\ShiftRight0~19_combout ) ) ) # ( !\ShiftRight0~14_combout  & ( (!\R_O[2]~1_combout  & (((\ShiftRight0~3_combout  & 
+// \R_O[0]~2_combout )) # (\ShiftRight0~19_combout ))) ) )
+
+	.dataa(!\ShiftRight0~19_combout ),
+	.datab(!\ShiftRight0~3_combout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(!\R_O[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~20 .extended_lut = "off";
+defparam \ShiftRight0~20 .lut_mask = 64'h507050705F7F5F7F;
+defparam \ShiftRight0~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N21
+cyclonev_lcell_comb \Mult_Mant_N[14]~1 (
+// Equation(s):
+// \Mult_Mant_N[14]~1_combout  = ( Mult_Mant[13] & ( (!Mult_Mant[15]) # (Mult_Mant[14]) ) ) # ( !Mult_Mant[13] & ( (Mult_Mant[14] & Mult_Mant[15]) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!Mult_Mant[14]),
+	.datad(!Mult_Mant[15]),
+	.datae(gnd),
+	.dataf(!Mult_Mant[13]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Mult_Mant_N[14]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Mult_Mant_N[14]~1 .extended_lut = "off";
+defparam \Mult_Mant_N[14]~1 .lut_mask = 64'h000F000FFF0FFF0F;
+defparam \Mult_Mant_N[14]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N6
+cyclonev_lcell_comb \ShiftRight0~7 (
+// Equation(s):
+// \ShiftRight0~7_combout  = ( \Extract_IN2|Add1~25_sumout  & ( \Mult_Mant_N[13]~0_combout  & ( (!\R_O[0]~2_combout  & (((!\R_O[1]~3_combout )) # (\Extract_IN2|Add1~29_sumout ))) # (\R_O[0]~2_combout  & (((\Mult_Mant_N[14]~1_combout ) # (\R_O[1]~3_combout 
+// )))) ) ) ) # ( !\Extract_IN2|Add1~25_sumout  & ( \Mult_Mant_N[13]~0_combout  & ( (!\R_O[0]~2_combout  & (((!\R_O[1]~3_combout )) # (\Extract_IN2|Add1~29_sumout ))) # (\R_O[0]~2_combout  & (((!\R_O[1]~3_combout  & \Mult_Mant_N[14]~1_combout )))) ) ) ) # ( 
+// \Extract_IN2|Add1~25_sumout  & ( !\Mult_Mant_N[13]~0_combout  & ( (!\R_O[0]~2_combout  & (\Extract_IN2|Add1~29_sumout  & (\R_O[1]~3_combout ))) # (\R_O[0]~2_combout  & (((\Mult_Mant_N[14]~1_combout ) # (\R_O[1]~3_combout )))) ) ) ) # ( 
+// !\Extract_IN2|Add1~25_sumout  & ( !\Mult_Mant_N[13]~0_combout  & ( (!\R_O[0]~2_combout  & (\Extract_IN2|Add1~29_sumout  & (\R_O[1]~3_combout ))) # (\R_O[0]~2_combout  & (((!\R_O[1]~3_combout  & \Mult_Mant_N[14]~1_combout )))) ) ) )
+
+	.dataa(!\R_O[0]~2_combout ),
+	.datab(!\Extract_IN2|Add1~29_sumout ),
+	.datac(!\R_O[1]~3_combout ),
+	.datad(!\Mult_Mant_N[14]~1_combout ),
+	.datae(!\Extract_IN2|Add1~25_sumout ),
+	.dataf(!\Mult_Mant_N[13]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~7 .extended_lut = "off";
+defparam \ShiftRight0~7 .lut_mask = 64'h02520757A2F2A7F7;
+defparam \ShiftRight0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N12
+cyclonev_lcell_comb \ShiftRight0~11 (
+// Equation(s):
+// \ShiftRight0~11_combout  = ( \R_O[0]~2_combout  & ( \Mult_Mant_N[14]~1_combout  & ( (!\R_O[1]~3_combout  & (\Extract_IN2|Add1~29_sumout )) # (\R_O[1]~3_combout  & ((\Extract_IN2|Add1~21_sumout ))) ) ) ) # ( !\R_O[0]~2_combout  & ( 
+// \Mult_Mant_N[14]~1_combout  & ( (!\R_O[1]~3_combout ) # (\Extract_IN2|Add1~25_sumout ) ) ) ) # ( \R_O[0]~2_combout  & ( !\Mult_Mant_N[14]~1_combout  & ( (!\R_O[1]~3_combout  & (\Extract_IN2|Add1~29_sumout )) # (\R_O[1]~3_combout  & 
+// ((\Extract_IN2|Add1~21_sumout ))) ) ) ) # ( !\R_O[0]~2_combout  & ( !\Mult_Mant_N[14]~1_combout  & ( (\R_O[1]~3_combout  & \Extract_IN2|Add1~25_sumout ) ) ) )
+
+	.dataa(!\R_O[1]~3_combout ),
+	.datab(!\Extract_IN2|Add1~29_sumout ),
+	.datac(!\Extract_IN2|Add1~21_sumout ),
+	.datad(!\Extract_IN2|Add1~25_sumout ),
+	.datae(!\R_O[0]~2_combout ),
+	.dataf(!\Mult_Mant_N[14]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~11 .extended_lut = "off";
+defparam \ShiftRight0~11 .lut_mask = 64'h00552727AAFF2727;
+defparam \ShiftRight0~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N27
+cyclonev_lcell_comb \ulp~3 (
+// Equation(s):
+// \ulp~3_combout  = ( \ShiftRight0~11_combout  ) # ( !\ShiftRight0~11_combout  & ( ((\ShiftRight0~14_combout ) # (\ShiftRight0~7_combout )) # (\ShiftRight0~2_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\ShiftRight0~2_combout ),
+	.datac(!\ShiftRight0~7_combout ),
+	.datad(!\ShiftRight0~14_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~11_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~3 .extended_lut = "off";
+defparam \ulp~3 .lut_mask = 64'h3FFF3FFFFFFFFFFF;
+defparam \ulp~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N42
+cyclonev_lcell_comb \ShiftRight0~25 (
+// Equation(s):
+// \ShiftRight0~25_combout  = ( Mult_Mant[9] & ( Mult_Mant[11] & ( ((!\R_O[1]~3_combout  & ((Mult_Mant[8]))) # (\R_O[1]~3_combout  & (Mult_Mant[10]))) # (Mult_Mant[15]) ) ) ) # ( !Mult_Mant[9] & ( Mult_Mant[11] & ( (!Mult_Mant[15] & ((!\R_O[1]~3_combout  & 
+// ((Mult_Mant[8]))) # (\R_O[1]~3_combout  & (Mult_Mant[10])))) # (Mult_Mant[15] & (((\R_O[1]~3_combout )))) ) ) ) # ( Mult_Mant[9] & ( !Mult_Mant[11] & ( (!Mult_Mant[15] & ((!\R_O[1]~3_combout  & ((Mult_Mant[8]))) # (\R_O[1]~3_combout  & (Mult_Mant[10])))) 
+// # (Mult_Mant[15] & (((!\R_O[1]~3_combout )))) ) ) ) # ( !Mult_Mant[9] & ( !Mult_Mant[11] & ( (!Mult_Mant[15] & ((!\R_O[1]~3_combout  & ((Mult_Mant[8]))) # (\R_O[1]~3_combout  & (Mult_Mant[10])))) ) ) )
+
+	.dataa(!Mult_Mant[10]),
+	.datab(!Mult_Mant[15]),
+	.datac(!\R_O[1]~3_combout ),
+	.datad(!Mult_Mant[8]),
+	.datae(!Mult_Mant[9]),
+	.dataf(!Mult_Mant[11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~25_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~25 .extended_lut = "off";
+defparam \ShiftRight0~25 .lut_mask = 64'h04C434F407C737F7;
+defparam \ShiftRight0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N39
+cyclonev_lcell_comb \Mult_Mant_N[10]~3 (
+// Equation(s):
+// \Mult_Mant_N[10]~3_combout  = ( Mult_Mant[10] & ( (Mult_Mant[15]) # (Mult_Mant[9]) ) ) # ( !Mult_Mant[10] & ( (Mult_Mant[9] & !Mult_Mant[15]) ) )
+
+	.dataa(!Mult_Mant[9]),
+	.datab(!Mult_Mant[15]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!Mult_Mant[10]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Mult_Mant_N[10]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Mult_Mant_N[10]~3 .extended_lut = "off";
+defparam \Mult_Mant_N[10]~3 .lut_mask = 64'h4444444477777777;
+defparam \Mult_Mant_N[10]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N18
+cyclonev_lcell_comb \WideOr1~0 (
+// Equation(s):
+// \WideOr1~0_combout  = ( !Mult_Mant[3] & ( (!Mult_Mant[1] & (!Mult_Mant[0] & !Mult_Mant[2])) ) )
+
+	.dataa(!Mult_Mant[1]),
+	.datab(!Mult_Mant[0]),
+	.datac(!Mult_Mant[2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!Mult_Mant[3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~0 .extended_lut = "off";
+defparam \WideOr1~0 .lut_mask = 64'h8080808000000000;
+defparam \WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N30
+cyclonev_lcell_comb \WideOr1~1 (
+// Equation(s):
+// \WideOr1~1_combout  = ( Mult_Mant[8] & ( (!Mult_Mant[15] & (!Mult_Mant[6] & !Mult_Mant[7])) ) ) # ( !Mult_Mant[8] & ( (!Mult_Mant[6] & !Mult_Mant[7]) ) )
+
+	.dataa(gnd),
+	.datab(!Mult_Mant[15]),
+	.datac(!Mult_Mant[6]),
+	.datad(!Mult_Mant[7]),
+	.datae(gnd),
+	.dataf(!Mult_Mant[8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~1 .extended_lut = "off";
+defparam \WideOr1~1 .lut_mask = 64'hF000F000C000C000;
+defparam \WideOr1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N33
+cyclonev_lcell_comb \WideOr1~2 (
+// Equation(s):
+// \WideOr1~2_combout  = ( \WideOr1~1_combout  & ( (\WideOr1~0_combout  & (!Mult_Mant[5] & !Mult_Mant[4])) ) )
+
+	.dataa(!\WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!Mult_Mant[5]),
+	.datad(!Mult_Mant[4]),
+	.datae(gnd),
+	.dataf(!\WideOr1~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~2 .extended_lut = "off";
+defparam \WideOr1~2 .lut_mask = 64'h0000000050005000;
+defparam \WideOr1~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N27
+cyclonev_lcell_comb \ShiftRight0~26 (
+// Equation(s):
+// \ShiftRight0~26_combout  = ( \WideOr1~2_combout  & ( (!\R_O[0]~2_combout  & (\R_O[1]~3_combout  & ((\Mult_Mant_N[10]~3_combout )))) # (\R_O[0]~2_combout  & (((\ShiftRight0~25_combout )))) ) ) # ( !\WideOr1~2_combout  & ( (!\R_O[0]~2_combout  & 
+// ((!\R_O[1]~3_combout ) # ((\Mult_Mant_N[10]~3_combout )))) # (\R_O[0]~2_combout  & (((\ShiftRight0~25_combout )))) ) )
+
+	.dataa(!\R_O[1]~3_combout ),
+	.datab(!\ShiftRight0~25_combout ),
+	.datac(!\Mult_Mant_N[10]~3_combout ),
+	.datad(!\R_O[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\WideOr1~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~26 .extended_lut = "off";
+defparam \ShiftRight0~26 .lut_mask = 64'hAF33AF3305330533;
+defparam \ShiftRight0~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N9
+cyclonev_lcell_comb \Mult_Mant_N[12]~4 (
+// Equation(s):
+// \Mult_Mant_N[12]~4_combout  = ( Mult_Mant[11] & ( (!Mult_Mant[15]) # (Mult_Mant[12]) ) ) # ( !Mult_Mant[11] & ( (Mult_Mant[12] & Mult_Mant[15]) ) )
+
+	.dataa(!Mult_Mant[12]),
+	.datab(!Mult_Mant[15]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!Mult_Mant[11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\Mult_Mant_N[12]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Mult_Mant_N[12]~4 .extended_lut = "off";
+defparam \Mult_Mant_N[12]~4 .lut_mask = 64'h11111111DDDDDDDD;
+defparam \Mult_Mant_N[12]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N48
+cyclonev_lcell_comb \ShiftRight0~33 (
+// Equation(s):
+// \ShiftRight0~33_combout  = ( \R_O[1]~3_combout  & ( \Mult_Mant_N[10]~3_combout  & ( (!\R_O[0]~2_combout  & (\Mult_Mant_N[12]~4_combout )) # (\R_O[0]~2_combout  & ((\Mult_Mant_N[13]~0_combout ))) ) ) ) # ( !\R_O[1]~3_combout  & ( \Mult_Mant_N[10]~3_combout 
+//  & ( (!\R_O[0]~2_combout ) # (\Mult_Mant_N[11]~2_combout ) ) ) ) # ( \R_O[1]~3_combout  & ( !\Mult_Mant_N[10]~3_combout  & ( (!\R_O[0]~2_combout  & (\Mult_Mant_N[12]~4_combout )) # (\R_O[0]~2_combout  & ((\Mult_Mant_N[13]~0_combout ))) ) ) ) # ( 
+// !\R_O[1]~3_combout  & ( !\Mult_Mant_N[10]~3_combout  & ( (\Mult_Mant_N[11]~2_combout  & \R_O[0]~2_combout ) ) ) )
+
+	.dataa(!\Mult_Mant_N[11]~2_combout ),
+	.datab(!\Mult_Mant_N[12]~4_combout ),
+	.datac(!\R_O[0]~2_combout ),
+	.datad(!\Mult_Mant_N[13]~0_combout ),
+	.datae(!\R_O[1]~3_combout ),
+	.dataf(!\Mult_Mant_N[10]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~33_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~33 .extended_lut = "off";
+defparam \ShiftRight0~33 .lut_mask = 64'h0505303FF5F5303F;
+defparam \ShiftRight0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N12
+cyclonev_lcell_comb \ShiftRight0~28 (
+// Equation(s):
+// \ShiftRight0~28_combout  = ( \ShiftRight0~25_combout  & ( (!\R_O[0]~2_combout ) # ((!\R_O[1]~3_combout  & ((\Mult_Mant_N[10]~3_combout ))) # (\R_O[1]~3_combout  & (\Mult_Mant_N[12]~4_combout ))) ) ) # ( !\ShiftRight0~25_combout  & ( (\R_O[0]~2_combout  & 
+// ((!\R_O[1]~3_combout  & ((\Mult_Mant_N[10]~3_combout ))) # (\R_O[1]~3_combout  & (\Mult_Mant_N[12]~4_combout )))) ) )
+
+	.dataa(!\R_O[0]~2_combout ),
+	.datab(!\R_O[1]~3_combout ),
+	.datac(!\Mult_Mant_N[12]~4_combout ),
+	.datad(!\Mult_Mant_N[10]~3_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~25_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~28_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~28 .extended_lut = "off";
+defparam \ShiftRight0~28 .lut_mask = 64'h01450145ABEFABEF;
+defparam \ShiftRight0~28 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N30
+cyclonev_lcell_comb \ShiftRight0~23 (
+// Equation(s):
+// \ShiftRight0~23_combout  = ( \ShiftRight0~3_combout  & ( (!\ShiftRight0~19_combout  & !\R_O[0]~2_combout ) ) ) # ( !\ShiftRight0~3_combout  & ( !\ShiftRight0~19_combout  ) )
+
+	.dataa(!\ShiftRight0~19_combout ),
+	.datab(gnd),
+	.datac(!\R_O[0]~2_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~23 .extended_lut = "off";
+defparam \ShiftRight0~23 .lut_mask = 64'hAAAAAAAAA0A0A0A0;
+defparam \ShiftRight0~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N48
+cyclonev_lcell_comb \ulp~2 (
+// Equation(s):
+// \ulp~2_combout  = ( \ShiftRight0~23_combout  & ( ((\ShiftRight0~28_combout ) # (\ShiftRight0~4_combout )) # (\ShiftRight0~33_combout ) ) ) # ( !\ShiftRight0~23_combout  )
+
+	.dataa(gnd),
+	.datab(!\ShiftRight0~33_combout ),
+	.datac(!\ShiftRight0~4_combout ),
+	.datad(!\ShiftRight0~28_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~23_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~2 .extended_lut = "off";
+defparam \ulp~2 .lut_mask = 64'hFFFFFFFF3FFF3FFF;
+defparam \ulp~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N0
+cyclonev_lcell_comb \ulp~5 (
+// Equation(s):
+// \ulp~5_combout  = ( !\R_O[2]~1_combout  & ( (((\R_O[3]~4_combout  & ((\ShiftRight0~26_combout ) # (\ulp~2_combout )))) # (\ShiftRight0~5_combout )) ) ) # ( \R_O[2]~1_combout  & ( ((\R_O[3]~4_combout  & (((\ShiftRight0~4_combout )) # (\ulp~3_combout )))) # 
+// (\ShiftRight0~5_combout ) ) )
+
+	.dataa(!\ulp~3_combout ),
+	.datab(!\ShiftRight0~5_combout ),
+	.datac(!\ShiftRight0~4_combout ),
+	.datad(!\R_O[3]~4_combout ),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~26_combout ),
+	.datag(!\ulp~2_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~5 .extended_lut = "on";
+defparam \ulp~5 .lut_mask = 64'h333F337F33FF337F;
+defparam \ulp~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N36
+cyclonev_lcell_comb \ShiftRight0~21 (
+// Equation(s):
+// \ShiftRight0~21_combout  = ( Mult_Mant[8] & ( (!Mult_Mant[15]) # (Mult_Mant[9]) ) ) # ( !Mult_Mant[8] & ( (Mult_Mant[9] & Mult_Mant[15]) ) )
+
+	.dataa(!Mult_Mant[9]),
+	.datab(!Mult_Mant[15]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!Mult_Mant[8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~21 .extended_lut = "off";
+defparam \ShiftRight0~21 .lut_mask = 64'h11111111DDDDDDDD;
+defparam \ShiftRight0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y10_N54
+cyclonev_lcell_comb \ulp~0 (
+// Equation(s):
+// \ulp~0_combout  = ( \R_O[1]~3_combout  & ( \WideOr1~2_combout  & ( (!\ShiftRight0~21_combout  & (!\Mult_Mant_N[10]~3_combout  & ((!\ShiftRight0~25_combout ) # (!\R_O[0]~2_combout )))) ) ) ) # ( !\R_O[1]~3_combout  & ( \WideOr1~2_combout  & ( 
+// (!\ShiftRight0~25_combout ) # (!\R_O[0]~2_combout ) ) ) )
+
+	.dataa(!\ShiftRight0~21_combout ),
+	.datab(!\ShiftRight0~25_combout ),
+	.datac(!\R_O[0]~2_combout ),
+	.datad(!\Mult_Mant_N[10]~3_combout ),
+	.datae(!\R_O[1]~3_combout ),
+	.dataf(!\WideOr1~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~0 .extended_lut = "off";
+defparam \ulp~0 .lut_mask = 64'h00000000FCFCA800;
+defparam \ulp~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N54
+cyclonev_lcell_comb \ShiftRight0~36 (
+// Equation(s):
+// \ShiftRight0~36_combout  = ( \Add2~5_sumout  & ( \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & (((\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )))) ) ) ) # ( !\Add2~5_sumout  & ( 
+// \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout ) # ((\Extract_IN2|Add1~9_sumout  & \Extract_IN2|Add1~5_sumout )) ) ) ) # ( \Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout ) # ((!\Extract_IN2|Add1~9_sumout  & 
+// !\Extract_IN2|Add1~5_sumout )) ) ) ) # ( !\Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & (((!\Extract_IN2|Add1~9_sumout  & !\Extract_IN2|Add1~5_sumout )))) ) ) )
+
+	.dataa(!\Add2~1_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Extract_IN2|Add1~9_sumout ),
+	.datad(!\Extract_IN2|Add1~5_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\R_O~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~36_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~36 .extended_lut = "off";
+defparam \ShiftRight0~36 .lut_mask = 64'h7444FCCCCCCF888B;
+defparam \ShiftRight0~36 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N24
+cyclonev_lcell_comb \ShiftRight0~35 (
+// Equation(s):
+// \ShiftRight0~35_combout  = ( \WideOr1~2_combout  & ( (\ShiftRight0~21_combout  & (\Total_EON[4]~0_combout  & (!\R_O~0_combout  $ (!\Total_EON[3]~1_combout )))) ) ) # ( !\WideOr1~2_combout  & ( (!\R_O~0_combout  & (\Total_EON[4]~0_combout  & 
+// ((!\Total_EON[3]~1_combout ) # (\ShiftRight0~21_combout )))) # (\R_O~0_combout  & ((!\Total_EON[3]~1_combout  & (\ShiftRight0~21_combout  & \Total_EON[4]~0_combout )) # (\Total_EON[3]~1_combout  & ((!\Total_EON[4]~0_combout ))))) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Total_EON[3]~1_combout ),
+	.datac(!\ShiftRight0~21_combout ),
+	.datad(!\Total_EON[4]~0_combout ),
+	.datae(gnd),
+	.dataf(!\WideOr1~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~35_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~35 .extended_lut = "off";
+defparam \ShiftRight0~35 .lut_mask = 64'h118E118E00060006;
+defparam \ShiftRight0~35 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N18
+cyclonev_lcell_comb \ShiftRight0~37 (
+// Equation(s):
+// \ShiftRight0~37_combout  = ( \ShiftRight0~11_combout  & ( \ShiftRight0~35_combout  & ( (!\R_O[2]~1_combout ) # ((!\R_O[3]~4_combout  & ((\ShiftRight0~33_combout ))) # (\R_O[3]~4_combout  & (!\ShiftRight0~36_combout ))) ) ) ) # ( !\ShiftRight0~11_combout  
+// & ( \ShiftRight0~35_combout  & ( (!\R_O[3]~4_combout  & (((!\R_O[2]~1_combout ) # (\ShiftRight0~33_combout )))) # (\R_O[3]~4_combout  & (!\ShiftRight0~36_combout  & ((\R_O[2]~1_combout )))) ) ) ) # ( \ShiftRight0~11_combout  & ( !\ShiftRight0~35_combout  
+// & ( (!\R_O[3]~4_combout  & (((\ShiftRight0~33_combout  & \R_O[2]~1_combout )))) # (\R_O[3]~4_combout  & ((!\ShiftRight0~36_combout ) # ((!\R_O[2]~1_combout )))) ) ) ) # ( !\ShiftRight0~11_combout  & ( !\ShiftRight0~35_combout  & ( (\R_O[2]~1_combout  & 
+// ((!\R_O[3]~4_combout  & ((\ShiftRight0~33_combout ))) # (\R_O[3]~4_combout  & (!\ShiftRight0~36_combout )))) ) ) )
+
+	.dataa(!\ShiftRight0~36_combout ),
+	.datab(!\ShiftRight0~33_combout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\R_O[2]~1_combout ),
+	.datae(!\ShiftRight0~11_combout ),
+	.dataf(!\ShiftRight0~35_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~37_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~37 .extended_lut = "off";
+defparam \ShiftRight0~37 .lut_mask = 64'h003A0F3AF03AFF3A;
+defparam \ShiftRight0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N42
+cyclonev_lcell_comb \ShiftRight0~9 (
+// Equation(s):
+// \ShiftRight0~9_combout  = ( \Add2~5_sumout  & ( \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & (((!\Extract_IN2|Add1~9_sumout ) # (!\Extract_IN2|Add1~5_sumout )))) ) ) ) # ( !\Add2~5_sumout  & ( 
+// \R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout ) # ((!\Extract_IN2|Add1~9_sumout ) # (!\Extract_IN2|Add1~5_sumout )) ) ) ) # ( \Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout ) # ((\Extract_IN2|Add1~5_sumout ) # 
+// (\Extract_IN2|Add1~9_sumout )) ) ) ) # ( !\Add2~5_sumout  & ( !\R_O~0_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout )) # (\Extract_IN2|Add1~1_sumout  & (((\Extract_IN2|Add1~5_sumout ) # (\Extract_IN2|Add1~9_sumout )))) ) ) )
+
+	.dataa(!\Add2~1_sumout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Extract_IN2|Add1~9_sumout ),
+	.datad(!\Extract_IN2|Add1~5_sumout ),
+	.datae(!\Add2~5_sumout ),
+	.dataf(!\R_O~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~9 .extended_lut = "off";
+defparam \ShiftRight0~9 .lut_mask = 64'h4777CFFFFFFCBBB8;
+defparam \ShiftRight0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N42
+cyclonev_lcell_comb \ShiftRight0~34 (
+// Equation(s):
+// \ShiftRight0~34_combout  = ( \ShiftRight0~11_combout  & ( \ShiftRight0~9_combout  & ( (!\R_O[3]~4_combout  & (((\ShiftRight0~33_combout )) # (\R_O[2]~1_combout ))) # (\R_O[3]~4_combout  & (((\Extract_IN2|Add1~1_sumout )))) ) ) ) # ( 
+// !\ShiftRight0~11_combout  & ( \ShiftRight0~9_combout  & ( (!\R_O[3]~4_combout  & (!\R_O[2]~1_combout  & ((\ShiftRight0~33_combout )))) # (\R_O[3]~4_combout  & (((\Extract_IN2|Add1~1_sumout )))) ) ) ) # ( \ShiftRight0~11_combout  & ( 
+// !\ShiftRight0~9_combout  & ( (!\R_O[3]~4_combout  & (((\ShiftRight0~33_combout )) # (\R_O[2]~1_combout ))) # (\R_O[3]~4_combout  & (!\R_O[2]~1_combout  $ ((\Extract_IN2|Add1~1_sumout )))) ) ) ) # ( !\ShiftRight0~11_combout  & ( !\ShiftRight0~9_combout  & 
+// ( (!\R_O[3]~4_combout  & (!\R_O[2]~1_combout  & ((\ShiftRight0~33_combout )))) # (\R_O[3]~4_combout  & (!\R_O[2]~1_combout  $ ((\Extract_IN2|Add1~1_sumout )))) ) ) )
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\ShiftRight0~33_combout ),
+	.datae(!\ShiftRight0~11_combout ),
+	.dataf(!\ShiftRight0~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~34_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~34 .extended_lut = "off";
+defparam \ShiftRight0~34 .lut_mask = 64'h09A959F903A353F3;
+defparam \ShiftRight0~34 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N12
+cyclonev_lcell_comb \ulp~1 (
+// Equation(s):
+// \ulp~1_combout  = ( !\ShiftRight0~34_combout  & ( (!\ShiftRight0~37_combout  & (((!\R_O[2]~1_combout ) # (\ulp~0_combout )) # (\R_O[3]~4_combout ))) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\ulp~0_combout ),
+	.datac(!\ShiftRight0~37_combout ),
+	.datad(!\R_O[2]~1_combout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~34_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~1 .extended_lut = "off";
+defparam \ulp~1 .lut_mask = 64'hF070F07000000000;
+defparam \ulp~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N48
+cyclonev_lcell_comb \ShiftRight0~31 (
+// Equation(s):
+// \ShiftRight0~31_combout  = ( \Extract_IN2|Add1~5_sumout  & ( !\WideOr1~2_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout  & (!\R_O~0_combout  $ (!\Total_EON[3]~1_combout )))) # (\Extract_IN2|Add1~1_sumout  & (!\R_O~0_combout  $ 
+// (((!\Total_EON[3]~1_combout ))))) ) ) ) # ( !\Extract_IN2|Add1~5_sumout  & ( !\WideOr1~2_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\Add2~1_sumout  & (!\R_O~0_combout  $ (!\Total_EON[3]~1_combout )))) ) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~1_sumout ),
+	.datad(!\Total_EON[3]~1_combout ),
+	.datae(!\Extract_IN2|Add1~5_sumout ),
+	.dataf(!\WideOr1~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~31_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~31 .extended_lut = "off";
+defparam \ShiftRight0~31 .lut_mask = 64'h0408152A00000000;
+defparam \ShiftRight0~31 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N18
+cyclonev_lcell_comb \ShiftRight0~29 (
+// Equation(s):
+// \ShiftRight0~29_combout  = ( \Extract_IN2|Add1~21_sumout  & ( \Total_EON[3]~1_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\R_O~0_combout  $ ((\Add2~1_sumout )))) # (\Extract_IN2|Add1~1_sumout  & (((\Extract_IN2|Add1~5_sumout )) # (\R_O~0_combout ))) ) 
+// ) ) # ( !\Extract_IN2|Add1~21_sumout  & ( \Total_EON[3]~1_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\R_O~0_combout  & (!\Add2~1_sumout ))) # (\Extract_IN2|Add1~1_sumout  & (!\R_O~0_combout  $ (((!\Extract_IN2|Add1~5_sumout ))))) ) ) ) # ( 
+// \Extract_IN2|Add1~21_sumout  & ( !\Total_EON[3]~1_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (((!\Add2~1_sumout )))) # (\Extract_IN2|Add1~1_sumout  & ((!\R_O~0_combout ) # ((\Extract_IN2|Add1~5_sumout )))) ) ) ) # ( !\Extract_IN2|Add1~21_sumout  & ( 
+// !\Total_EON[3]~1_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (\R_O~0_combout  & (!\Add2~1_sumout ))) # (\Extract_IN2|Add1~1_sumout  & (((\Extract_IN2|Add1~5_sumout )))) ) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\Add2~1_sumout ),
+	.datad(!\Extract_IN2|Add1~5_sumout ),
+	.datae(!\Extract_IN2|Add1~21_sumout ),
+	.dataf(!\Total_EON[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~29_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~29 .extended_lut = "off";
+defparam \ShiftRight0~29 .lut_mask = 64'h4073E2F391A295B7;
+defparam \ShiftRight0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N54
+cyclonev_lcell_comb \ShiftRight0~32 (
+// Equation(s):
+// \ShiftRight0~32_combout  = ( \ShiftRight0~28_combout  & ( \ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout  & (((\ShiftRight0~31_combout )) # (\R_O[2]~1_combout ))) # (\R_O[3]~4_combout  & ((!\R_O[2]~1_combout ) # ((\ShiftRight0~29_combout )))) ) ) ) # ( 
+// !\ShiftRight0~28_combout  & ( \ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout  & (!\R_O[2]~1_combout  & (\ShiftRight0~31_combout ))) # (\R_O[3]~4_combout  & ((!\R_O[2]~1_combout ) # ((\ShiftRight0~29_combout )))) ) ) ) # ( \ShiftRight0~28_combout  & ( 
+// !\ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout  & (((\ShiftRight0~31_combout )) # (\R_O[2]~1_combout ))) # (\R_O[3]~4_combout  & (\R_O[2]~1_combout  & ((\ShiftRight0~29_combout )))) ) ) ) # ( !\ShiftRight0~28_combout  & ( !\ShiftRight0~7_combout  & ( 
+// (!\R_O[3]~4_combout  & (!\R_O[2]~1_combout  & (\ShiftRight0~31_combout ))) # (\R_O[3]~4_combout  & (\R_O[2]~1_combout  & ((\ShiftRight0~29_combout )))) ) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\R_O[2]~1_combout ),
+	.datac(!\ShiftRight0~31_combout ),
+	.datad(!\ShiftRight0~29_combout ),
+	.datae(!\ShiftRight0~28_combout ),
+	.dataf(!\ShiftRight0~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~32_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~32 .extended_lut = "off";
+defparam \ShiftRight0~32 .lut_mask = 64'h08192A3B4C5D6E7F;
+defparam \ShiftRight0~32 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N36
+cyclonev_lcell_comb \ShiftRight0~22 (
+// Equation(s):
+// \ShiftRight0~22_combout  = ( \Total_EON[3]~1_combout  & ( \WideOr1~2_combout  & ( (!\R_O~0_combout  & (\Total_EON[4]~0_combout  & ((\Mult_Mant_N[10]~3_combout )))) # (\R_O~0_combout  & (!\Total_EON[4]~0_combout  & (\ShiftRight0~21_combout ))) ) ) ) # ( 
+// !\Total_EON[3]~1_combout  & ( \WideOr1~2_combout  & ( (\Total_EON[4]~0_combout  & ((!\R_O~0_combout  & (\ShiftRight0~21_combout )) # (\R_O~0_combout  & ((\Mult_Mant_N[10]~3_combout ))))) ) ) ) # ( \Total_EON[3]~1_combout  & ( !\WideOr1~2_combout  & ( 
+// (!\R_O~0_combout  & ((!\Total_EON[4]~0_combout ) # ((\Mult_Mant_N[10]~3_combout )))) # (\R_O~0_combout  & (!\Total_EON[4]~0_combout  & (\ShiftRight0~21_combout ))) ) ) ) # ( !\Total_EON[3]~1_combout  & ( !\WideOr1~2_combout  & ( (!\R_O~0_combout  & 
+// (\Total_EON[4]~0_combout  & (\ShiftRight0~21_combout ))) # (\R_O~0_combout  & ((!\Total_EON[4]~0_combout ) # ((\Mult_Mant_N[10]~3_combout )))) ) ) )
+
+	.dataa(!\R_O~0_combout ),
+	.datab(!\Total_EON[4]~0_combout ),
+	.datac(!\ShiftRight0~21_combout ),
+	.datad(!\Mult_Mant_N[10]~3_combout ),
+	.datae(!\Total_EON[3]~1_combout ),
+	.dataf(!\WideOr1~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~22 .extended_lut = "off";
+defparam \ShiftRight0~22 .lut_mask = 64'h46578CAE02130426;
+defparam \ShiftRight0~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N42
+cyclonev_lcell_comb \ShiftRight0~24 (
+// Equation(s):
+// \ShiftRight0~24_combout  = ( \R_O[3]~4_combout  & ( \ShiftRight0~23_combout  & ( (!\R_O[2]~1_combout  & (\ShiftRight0~14_combout )) # (\R_O[2]~1_combout  & ((\Extract_IN2|Add1~1_sumout ))) ) ) ) # ( !\R_O[3]~4_combout  & ( \ShiftRight0~23_combout  & ( 
+// (\ShiftRight0~22_combout  & !\R_O[2]~1_combout ) ) ) ) # ( \R_O[3]~4_combout  & ( !\ShiftRight0~23_combout  & ( (!\R_O[2]~1_combout  & (\ShiftRight0~14_combout )) # (\R_O[2]~1_combout  & ((\Extract_IN2|Add1~1_sumout ))) ) ) ) # ( !\R_O[3]~4_combout  & ( 
+// !\ShiftRight0~23_combout  & ( (\R_O[2]~1_combout ) # (\ShiftRight0~22_combout ) ) ) )
+
+	.dataa(!\ShiftRight0~14_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\ShiftRight0~22_combout ),
+	.datad(!\R_O[2]~1_combout ),
+	.datae(!\R_O[3]~4_combout ),
+	.dataf(!\ShiftRight0~23_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~24_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~24 .extended_lut = "off";
+defparam \ShiftRight0~24 .lut_mask = 64'h0FFF55330F005533;
+defparam \ShiftRight0~24 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N36
+cyclonev_lcell_comb \ShiftRight0~30 (
+// Equation(s):
+// \ShiftRight0~30_combout  = ( \R_O[2]~1_combout  & ( \ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout ) # (\Extract_IN2|Add1~1_sumout ) ) ) ) # ( !\R_O[2]~1_combout  & ( \ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout  & ((\ShiftRight0~28_combout ))) # 
+// (\R_O[3]~4_combout  & (\ShiftRight0~29_combout )) ) ) ) # ( \R_O[2]~1_combout  & ( !\ShiftRight0~7_combout  & ( (\Extract_IN2|Add1~1_sumout  & \R_O[3]~4_combout ) ) ) ) # ( !\R_O[2]~1_combout  & ( !\ShiftRight0~7_combout  & ( (!\R_O[3]~4_combout  & 
+// ((\ShiftRight0~28_combout ))) # (\R_O[3]~4_combout  & (\ShiftRight0~29_combout )) ) ) )
+
+	.dataa(!\ShiftRight0~29_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\ShiftRight0~28_combout ),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~30_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~30 .extended_lut = "off";
+defparam \ShiftRight0~30 .lut_mask = 64'h05F5030305F5F3F3;
+defparam \ShiftRight0~30 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N30
+cyclonev_lcell_comb \ShiftRight0~27 (
+// Equation(s):
+// \ShiftRight0~27_combout  = ( \R_O[2]~1_combout  & ( \ShiftRight0~4_combout  & ( (!\R_O[3]~4_combout ) # (\Extract_IN2|Add1~1_sumout ) ) ) ) # ( !\R_O[2]~1_combout  & ( \ShiftRight0~4_combout  & ( (!\R_O[3]~4_combout  & (\ShiftRight0~26_combout )) # 
+// (\R_O[3]~4_combout  & ((\ShiftRight0~2_combout ))) ) ) ) # ( \R_O[2]~1_combout  & ( !\ShiftRight0~4_combout  & ( (\Extract_IN2|Add1~1_sumout  & \R_O[3]~4_combout ) ) ) ) # ( !\R_O[2]~1_combout  & ( !\ShiftRight0~4_combout  & ( (!\R_O[3]~4_combout  & 
+// (\ShiftRight0~26_combout )) # (\R_O[3]~4_combout  & ((\ShiftRight0~2_combout ))) ) ) )
+
+	.dataa(!\ShiftRight0~26_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\ShiftRight0~2_combout ),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~27_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~27 .extended_lut = "off";
+defparam \ShiftRight0~27 .lut_mask = 64'h505F0303505FF3F3;
+defparam \ShiftRight0~27 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N54
+cyclonev_lcell_comb \ulp~4 (
+// Equation(s):
+// \ulp~4_combout  = ( \ShiftRight0~30_combout  & ( \ShiftRight0~27_combout  ) ) # ( !\ShiftRight0~30_combout  & ( \ShiftRight0~27_combout  ) ) # ( \ShiftRight0~30_combout  & ( !\ShiftRight0~27_combout  ) ) # ( !\ShiftRight0~30_combout  & ( 
+// !\ShiftRight0~27_combout  & ( ((!\ulp~1_combout ) # ((\ShiftRight0~24_combout ) # (\ShiftRight0~32_combout ))) # (\ulp~5_combout ) ) ) )
+
+	.dataa(!\ulp~5_combout ),
+	.datab(!\ulp~1_combout ),
+	.datac(!\ShiftRight0~32_combout ),
+	.datad(!\ShiftRight0~24_combout ),
+	.datae(!\ShiftRight0~30_combout ),
+	.dataf(!\ShiftRight0~27_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ulp~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ulp~4 .extended_lut = "off";
+defparam \ulp~4 .lut_mask = 64'hDFFFFFFFFFFFFFFF;
+defparam \ulp~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N30
+cyclonev_lcell_comb \Add4~29 (
+// Equation(s):
+// \Add4~29_sumout  = SUM(( (\ulp~4_combout  & ((!\R_O[3]~4_combout  & ((\ShiftRight0~20_combout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout )))) ) + ( (!\R_O[3]~4_combout  & ((\ShiftRight0~20_combout ))) # (\R_O[3]~4_combout  & 
+// (\Extract_IN2|Add1~1_sumout )) ) + ( !VCC ))
+// \Add4~30  = CARRY(( (\ulp~4_combout  & ((!\R_O[3]~4_combout  & ((\ShiftRight0~20_combout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout )))) ) + ( (!\R_O[3]~4_combout  & ((\ShiftRight0~20_combout ))) # (\R_O[3]~4_combout  & 
+// (\Extract_IN2|Add1~1_sumout )) ) + ( !VCC ))
+
+	.dataa(!\Extract_IN2|Add1~1_sumout ),
+	.datab(!\ShiftRight0~20_combout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(!\ulp~4_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~29_sumout ),
+	.cout(\Add4~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~29 .extended_lut = "off";
+defparam \Add4~29 .lut_mask = 64'h0000CACA00000035;
+defparam \Add4~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N33
+cyclonev_lcell_comb \Add4~1 (
+// Equation(s):
+// \Add4~1_sumout  = SUM(( \ShiftRight0~5_combout  ) + ( GND ) + ( \Add4~30  ))
+// \Add4~2  = CARRY(( \ShiftRight0~5_combout  ) + ( GND ) + ( \Add4~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ShiftRight0~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add4~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~1_sumout ),
+	.cout(\Add4~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~1 .extended_lut = "off";
+defparam \Add4~1 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \Add4~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N54
+cyclonev_lcell_comb \sft_tmp_o_rnd[0]~0 (
+// Equation(s):
+// \sft_tmp_o_rnd[0]~0_combout  = ( \ShiftRight0~20_combout  & ( ((!\LessThan0~0_combout  & !\R_O[3]~4_combout )) # (\Add4~29_sumout ) ) ) # ( !\ShiftRight0~20_combout  & ( (\Add4~29_sumout  & ((\R_O[3]~4_combout ) # (\LessThan0~0_combout ))) ) )
+
+	.dataa(!\LessThan0~0_combout ),
+	.datab(!\Add4~29_sumout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~20_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_o_rnd[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_o_rnd[0]~0 .extended_lut = "off";
+defparam \sft_tmp_o_rnd[0]~0 .lut_mask = 64'h13131313B3B3B3B3;
+defparam \sft_tmp_o_rnd[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N0
+cyclonev_lcell_comb \Add5~1 (
+// Equation(s):
+// \Add5~1_sumout  = SUM(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & ((!\ShiftRight0~5_combout ))) # (\LessThan0~0_combout  & (!\Add4~1_sumout )))) # (\R_O[3]~4_combout  & (((!\Add4~1_sumout )))) ) + ( !\sft_tmp_o_rnd[0]~0_combout  ) + ( !VCC ))
+// \Add5~2  = CARRY(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & ((!\ShiftRight0~5_combout ))) # (\LessThan0~0_combout  & (!\Add4~1_sumout )))) # (\R_O[3]~4_combout  & (((!\Add4~1_sumout )))) ) + ( !\sft_tmp_o_rnd[0]~0_combout  ) + ( !VCC ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\Add4~1_sumout ),
+	.datad(!\ShiftRight0~5_combout ),
+	.datae(gnd),
+	.dataf(!\sft_tmp_o_rnd[0]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~1_sumout ),
+	.cout(\Add5~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~1 .extended_lut = "off";
+defparam \Add5~1 .lut_mask = 64'h000000FF0000F870;
+defparam \Add5~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N39
+cyclonev_lcell_comb \sft_tmp_oN~0 (
+// Equation(s):
+// \sft_tmp_oN~0_combout  = ( \Add5~1_sumout  & ( ((!\LessThan0~1_combout  & (\Add4~1_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~5_combout )))) # (\Operation~0_combout ) ) ) # ( !\Add5~1_sumout  & ( (!\Operation~0_combout  & ((!\LessThan0~1_combout  
+// & (\Add4~1_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~5_combout ))))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\Add4~1_sumout ),
+	.datad(!\ShiftRight0~5_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~0 .extended_lut = "off";
+defparam \sft_tmp_oN~0 .lut_mask = 64'h082A082A5D7F5D7F;
+defparam \sft_tmp_oN~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y12_N15
+cyclonev_lcell_comb \ShiftRight0~6 (
+// Equation(s):
+// \ShiftRight0~6_combout  = ( \Extract_IN2|Add1~1_sumout  & ( (!\R_O[0]~2_combout  & \Extract_IN2|Add1~21_sumout ) ) ) # ( !\Extract_IN2|Add1~1_sumout  & ( (\Extract_IN2|Add1~21_sumout ) # (\R_O[0]~2_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\R_O[0]~2_combout ),
+	.datad(!\Extract_IN2|Add1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~6 .extended_lut = "off";
+defparam \ShiftRight0~6 .lut_mask = 64'h0FFF0FFF00F000F0;
+defparam \ShiftRight0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N54
+cyclonev_lcell_comb \ShiftRight0~8 (
+// Equation(s):
+// \ShiftRight0~8_combout  = ( \ShiftRight0~7_combout  & ( \ShiftRight0~6_combout  & ( (!\R_O[3]~4_combout  & ((!\R_O[1]~3_combout ) # ((!\R_O[2]~1_combout ) # (\Extract_IN2|Add1~1_sumout )))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout  & 
+// ((!\R_O[1]~3_combout ) # (!\R_O[2]~1_combout )))) ) ) ) # ( !\ShiftRight0~7_combout  & ( \ShiftRight0~6_combout  & ( (!\R_O[3]~4_combout  & (\R_O[2]~1_combout  & ((!\R_O[1]~3_combout ) # (\Extract_IN2|Add1~1_sumout )))) # (\R_O[3]~4_combout  & 
+// (\Extract_IN2|Add1~1_sumout  & ((!\R_O[1]~3_combout ) # (!\R_O[2]~1_combout )))) ) ) ) # ( \ShiftRight0~7_combout  & ( !\ShiftRight0~6_combout  & ( (!\R_O[2]~1_combout  & ((!\R_O[3]~4_combout ) # ((\Extract_IN2|Add1~1_sumout )))) # (\R_O[2]~1_combout  & 
+// (\Extract_IN2|Add1~1_sumout  & (!\R_O[3]~4_combout  $ (!\R_O[1]~3_combout )))) ) ) ) # ( !\ShiftRight0~7_combout  & ( !\ShiftRight0~6_combout  & ( (\Extract_IN2|Add1~1_sumout  & (!\R_O[3]~4_combout  $ (((!\R_O[1]~3_combout ) # (!\R_O[2]~1_combout ))))) ) 
+// ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\R_O[1]~3_combout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(!\Extract_IN2|Add1~1_sumout ),
+	.datae(!\ShiftRight0~7_combout ),
+	.dataf(!\ShiftRight0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~8 .extended_lut = "off";
+defparam \ShiftRight0~8 .lut_mask = 64'h0056A0F6085EA8FE;
+defparam \ShiftRight0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N36
+cyclonev_lcell_comb \Add4~5 (
+// Equation(s):
+// \Add4~5_sumout  = SUM(( \ShiftRight0~8_combout  ) + ( GND ) + ( \Add4~2  ))
+// \Add4~6  = CARRY(( \ShiftRight0~8_combout  ) + ( GND ) + ( \Add4~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ShiftRight0~8_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add4~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~5_sumout ),
+	.cout(\Add4~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~5 .extended_lut = "off";
+defparam \Add4~5 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \Add4~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N3
+cyclonev_lcell_comb \Add5~5 (
+// Equation(s):
+// \Add5~5_sumout  = SUM(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & ((!\ShiftRight0~8_combout ))) # (\LessThan0~0_combout  & (!\Add4~5_sumout )))) # (\R_O[3]~4_combout  & (((!\Add4~5_sumout )))) ) + ( \Add5~2  ))
+// \Add5~6  = CARRY(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & ((!\ShiftRight0~8_combout ))) # (\LessThan0~0_combout  & (!\Add4~5_sumout )))) # (\R_O[3]~4_combout  & (((!\Add4~5_sumout )))) ) + ( \Add5~2  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\Add4~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~8_combout ),
+	.datag(gnd),
+	.cin(\Add5~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~5_sumout ),
+	.cout(\Add5~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~5 .extended_lut = "off";
+defparam \Add5~5 .lut_mask = 64'h0000078F00000000;
+defparam \Add5~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N33
+cyclonev_lcell_comb \sft_tmp_oN~1 (
+// Equation(s):
+// \sft_tmp_oN~1_combout  = ( \ShiftRight0~8_combout  & ( (!\Operation~0_combout  & (((\LessThan0~1_combout )) # (\Add4~5_sumout ))) # (\Operation~0_combout  & (((\Add5~5_sumout )))) ) ) # ( !\ShiftRight0~8_combout  & ( (!\Operation~0_combout  & 
+// (\Add4~5_sumout  & (!\LessThan0~1_combout ))) # (\Operation~0_combout  & (((\Add5~5_sumout )))) ) )
+
+	.dataa(!\Add4~5_sumout ),
+	.datab(!\Operation~0_combout ),
+	.datac(!\LessThan0~1_combout ),
+	.datad(!\Add5~5_sumout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~1 .extended_lut = "off";
+defparam \sft_tmp_oN~1 .lut_mask = 64'h407340734C7F4C7F;
+defparam \sft_tmp_oN~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N51
+cyclonev_lcell_comb \ShiftRight0~12 (
+// Equation(s):
+// \ShiftRight0~12_combout  = (!\R_O[3]~4_combout  & ((\ShiftRight0~11_combout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~1_sumout ),
+	.datad(!\ShiftRight0~11_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~12 .extended_lut = "off";
+defparam \ShiftRight0~12 .lut_mask = 64'h05AF05AF05AF05AF;
+defparam \ShiftRight0~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N15
+cyclonev_lcell_comb \ShiftRight0~10 (
+// Equation(s):
+// \ShiftRight0~10_combout  = ( \ShiftRight0~9_combout  & ( (!\R_O[3]~4_combout  & \Extract_IN2|Add1~1_sumout ) ) ) # ( !\ShiftRight0~9_combout  & ( !\R_O[3]~4_combout  $ (\Extract_IN2|Add1~1_sumout ) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(gnd),
+	.datac(!\Extract_IN2|Add1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~10 .extended_lut = "off";
+defparam \ShiftRight0~10 .lut_mask = 64'hA5A5A5A50A0A0A0A;
+defparam \ShiftRight0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N39
+cyclonev_lcell_comb \Add4~9 (
+// Equation(s):
+// \Add4~9_sumout  = SUM(( (!\R_O[2]~1_combout  & (\ShiftRight0~12_combout )) # (\R_O[2]~1_combout  & ((\ShiftRight0~10_combout ))) ) + ( GND ) + ( \Add4~6  ))
+// \Add4~10  = CARRY(( (!\R_O[2]~1_combout  & (\ShiftRight0~12_combout )) # (\R_O[2]~1_combout  & ((\ShiftRight0~10_combout ))) ) + ( GND ) + ( \Add4~6  ))
+
+	.dataa(!\R_O[2]~1_combout ),
+	.datab(!\ShiftRight0~12_combout ),
+	.datac(!\ShiftRight0~10_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add4~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~9_sumout ),
+	.cout(\Add4~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~9 .extended_lut = "off";
+defparam \Add4~9 .lut_mask = 64'h0000FFFF00002727;
+defparam \Add4~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N24
+cyclonev_lcell_comb \ShiftRight0~13 (
+// Equation(s):
+// \ShiftRight0~13_combout  = ( \ShiftRight0~10_combout  & ( (\R_O[2]~1_combout ) # (\ShiftRight0~12_combout ) ) ) # ( !\ShiftRight0~10_combout  & ( (\ShiftRight0~12_combout  & !\R_O[2]~1_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\ShiftRight0~12_combout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~13 .extended_lut = "off";
+defparam \ShiftRight0~13 .lut_mask = 64'h303030303F3F3F3F;
+defparam \ShiftRight0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N6
+cyclonev_lcell_comb \Add5~9 (
+// Equation(s):
+// \Add5~9_sumout  = SUM(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~13_combout )) # (\LessThan0~0_combout  & ((!\Add4~9_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~9_sumout )))) ) + ( \Add5~6  ))
+// \Add5~10  = CARRY(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~13_combout )) # (\LessThan0~0_combout  & ((!\Add4~9_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~9_sumout )))) ) + ( \Add5~6  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\ShiftRight0~13_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add4~9_sumout ),
+	.datag(gnd),
+	.cin(\Add5~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~9_sumout ),
+	.cout(\Add5~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~9 .extended_lut = "off";
+defparam \Add5~9 .lut_mask = 64'h0000087F00000000;
+defparam \Add5~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N42
+cyclonev_lcell_comb \sft_tmp_oN~2 (
+// Equation(s):
+// \sft_tmp_oN~2_combout  = ( \Add5~9_sumout  & ( ((!\LessThan0~1_combout  & (\Add4~9_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~13_combout )))) # (\Operation~0_combout ) ) ) # ( !\Add5~9_sumout  & ( (!\Operation~0_combout  & ((!\LessThan0~1_combout 
+//  & (\Add4~9_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~13_combout ))))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\Add4~9_sumout ),
+	.datad(!\ShiftRight0~13_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~2 .extended_lut = "off";
+defparam \sft_tmp_oN~2 .lut_mask = 64'h082A082A5D7F5D7F;
+defparam \sft_tmp_oN~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N51
+cyclonev_lcell_comb \ShiftRight0~15 (
+// Equation(s):
+// \ShiftRight0~15_combout  = ( \ShiftRight0~14_combout  & ( (!\R_O[3]~4_combout  & ((!\R_O[2]~1_combout ) # (\Extract_IN2|Add1~1_sumout ))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout  & !\R_O[2]~1_combout )) ) ) # ( !\ShiftRight0~14_combout  & ( 
+// (\Extract_IN2|Add1~1_sumout  & (!\R_O[3]~4_combout  $ (!\R_O[2]~1_combout ))) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~15 .extended_lut = "off";
+defparam \ShiftRight0~15 .lut_mask = 64'h12121212B2B2B2B2;
+defparam \ShiftRight0~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N42
+cyclonev_lcell_comb \Add4~13 (
+// Equation(s):
+// \Add4~13_sumout  = SUM(( GND ) + ( (!\R_O[3]~4_combout  & ((!\R_O[2]~1_combout  & ((\ShiftRight0~14_combout ))) # (\R_O[2]~1_combout  & (\Extract_IN2|Add1~1_sumout )))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout  & (!\R_O[2]~1_combout ))) ) + ( 
+// \Add4~10  ))
+// \Add4~14  = CARRY(( GND ) + ( (!\R_O[3]~4_combout  & ((!\R_O[2]~1_combout  & ((\ShiftRight0~14_combout ))) # (\R_O[2]~1_combout  & (\Extract_IN2|Add1~1_sumout )))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout  & (!\R_O[2]~1_combout ))) ) + ( 
+// \Add4~10  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~14_combout ),
+	.datag(gnd),
+	.cin(\Add4~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~13_sumout ),
+	.cout(\Add4~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~13 .extended_lut = "off";
+defparam \Add4~13 .lut_mask = 64'h0000ED4D00000000;
+defparam \Add4~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N9
+cyclonev_lcell_comb \Add5~13 (
+// Equation(s):
+// \Add5~13_sumout  = SUM(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~15_combout )) # (\LessThan0~0_combout  & ((!\Add4~13_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~13_sumout )))) ) + ( GND ) + ( \Add5~10  ))
+// \Add5~14  = CARRY(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~15_combout )) # (\LessThan0~0_combout  & ((!\Add4~13_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~13_sumout )))) ) + ( GND ) + ( \Add5~10  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\ShiftRight0~15_combout ),
+	.datad(!\Add4~13_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~13_sumout ),
+	.cout(\Add5~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~13 .extended_lut = "off";
+defparam \Add5~13 .lut_mask = 64'h0000FFFF0000F780;
+defparam \Add5~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N45
+cyclonev_lcell_comb \sft_tmp_oN~3 (
+// Equation(s):
+// \sft_tmp_oN~3_combout  = ( \ShiftRight0~15_combout  & ( (!\Operation~0_combout  & (((\Add4~13_sumout )) # (\LessThan0~1_combout ))) # (\Operation~0_combout  & (((\Add5~13_sumout )))) ) ) # ( !\ShiftRight0~15_combout  & ( (!\Operation~0_combout  & 
+// (!\LessThan0~1_combout  & ((\Add4~13_sumout )))) # (\Operation~0_combout  & (((\Add5~13_sumout )))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\Add5~13_sumout ),
+	.datad(!\Add4~13_sumout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~15_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~3 .extended_lut = "off";
+defparam \sft_tmp_oN~3 .lut_mask = 64'h058D058D27AF27AF;
+defparam \sft_tmp_oN~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N24
+cyclonev_lcell_comb \ShiftRight0~16 (
+// Equation(s):
+// \ShiftRight0~16_combout  = ( \Extract_IN2|Add1~1_sumout  & ( (!\R_O[3]~4_combout  & (((\R_O[2]~1_combout )) # (\ShiftRight0~2_combout ))) # (\R_O[3]~4_combout  & (((!\ShiftRight0~0_combout  & !\R_O[2]~1_combout )))) ) ) # ( !\Extract_IN2|Add1~1_sumout  & 
+// ( (!\R_O[3]~4_combout  & (\ShiftRight0~2_combout  & !\R_O[2]~1_combout )) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\ShiftRight0~2_combout ),
+	.datac(!\ShiftRight0~0_combout ),
+	.datad(!\R_O[2]~1_combout ),
+	.datae(gnd),
+	.dataf(!\Extract_IN2|Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~16 .extended_lut = "off";
+defparam \ShiftRight0~16 .lut_mask = 64'h2200220072AA72AA;
+defparam \ShiftRight0~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N45
+cyclonev_lcell_comb \Add4~17 (
+// Equation(s):
+// \Add4~17_sumout  = SUM(( GND ) + ( \ShiftRight0~16_combout  ) + ( \Add4~14  ))
+// \Add4~18  = CARRY(( GND ) + ( \ShiftRight0~16_combout  ) + ( \Add4~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~16_combout ),
+	.datag(gnd),
+	.cin(\Add4~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~17_sumout ),
+	.cout(\Add4~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~17 .extended_lut = "off";
+defparam \Add4~17 .lut_mask = 64'h0000FF0000000000;
+defparam \Add4~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N12
+cyclonev_lcell_comb \Add5~17 (
+// Equation(s):
+// \Add5~17_sumout  = SUM(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~16_combout )) # (\LessThan0~0_combout  & ((!\Add4~17_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~17_sumout )))) ) + ( \Add5~14  ))
+// \Add5~18  = CARRY(( GND ) + ( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~16_combout )) # (\LessThan0~0_combout  & ((!\Add4~17_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~17_sumout )))) ) + ( \Add5~14  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\ShiftRight0~16_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add4~17_sumout ),
+	.datag(gnd),
+	.cin(\Add5~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~17_sumout ),
+	.cout(\Add5~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~17 .extended_lut = "off";
+defparam \Add5~17 .lut_mask = 64'h0000087F00000000;
+defparam \Add5~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N24
+cyclonev_lcell_comb \sft_tmp_oN~4 (
+// Equation(s):
+// \sft_tmp_oN~4_combout  = ( \Add5~17_sumout  & ( ((!\LessThan0~1_combout  & (\Add4~17_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~16_combout )))) # (\Operation~0_combout ) ) ) # ( !\Add5~17_sumout  & ( (!\Operation~0_combout  & 
+// ((!\LessThan0~1_combout  & (\Add4~17_sumout )) # (\LessThan0~1_combout  & ((\ShiftRight0~16_combout ))))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\Add4~17_sumout ),
+	.datad(!\ShiftRight0~16_combout ),
+	.datae(gnd),
+	.dataf(!\Add5~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~4 .extended_lut = "off";
+defparam \sft_tmp_oN~4 .lut_mask = 64'h082A082A5D7F5D7F;
+defparam \sft_tmp_oN~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y11_N39
+cyclonev_lcell_comb \ShiftRight0~17 (
+// Equation(s):
+// \ShiftRight0~17_combout  = ( \R_O[2]~1_combout  & ( \ShiftRight0~6_combout  & ( (\Extract_IN2|Add1~1_sumout  & !\R_O[3]~4_combout ) ) ) ) # ( !\R_O[2]~1_combout  & ( \ShiftRight0~6_combout  & ( (!\Extract_IN2|Add1~1_sumout  & (!\R_O[1]~3_combout  & 
+// !\R_O[3]~4_combout )) # (\Extract_IN2|Add1~1_sumout  & ((!\R_O[1]~3_combout ) # (!\R_O[3]~4_combout ))) ) ) ) # ( \R_O[2]~1_combout  & ( !\ShiftRight0~6_combout  & ( (\Extract_IN2|Add1~1_sumout  & !\R_O[3]~4_combout ) ) ) ) # ( !\R_O[2]~1_combout  & ( 
+// !\ShiftRight0~6_combout  & ( (\Extract_IN2|Add1~1_sumout  & (!\R_O[1]~3_combout  $ (!\R_O[3]~4_combout ))) ) ) )
+
+	.dataa(!\Extract_IN2|Add1~1_sumout ),
+	.datab(!\R_O[1]~3_combout ),
+	.datac(!\R_O[3]~4_combout ),
+	.datad(gnd),
+	.datae(!\R_O[2]~1_combout ),
+	.dataf(!\ShiftRight0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~17 .extended_lut = "off";
+defparam \ShiftRight0~17 .lut_mask = 64'h14145050D4D45050;
+defparam \ShiftRight0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N48
+cyclonev_lcell_comb \Add4~21 (
+// Equation(s):
+// \Add4~21_sumout  = SUM(( \ShiftRight0~17_combout  ) + ( GND ) + ( \Add4~18  ))
+// \Add4~22  = CARRY(( \ShiftRight0~17_combout  ) + ( GND ) + ( \Add4~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ShiftRight0~17_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add4~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~21_sumout ),
+	.cout(\Add4~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~21 .extended_lut = "off";
+defparam \Add4~21 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \Add4~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N15
+cyclonev_lcell_comb \Add5~21 (
+// Equation(s):
+// \Add5~21_sumout  = SUM(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~17_combout )) # (\LessThan0~0_combout  & ((!\Add4~21_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~21_sumout )))) ) + ( GND ) + ( \Add5~18  ))
+// \Add5~22  = CARRY(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~17_combout )) # (\LessThan0~0_combout  & ((!\Add4~21_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~21_sumout )))) ) + ( GND ) + ( \Add5~18  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\ShiftRight0~17_combout ),
+	.datad(!\Add4~21_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~21_sumout ),
+	.cout(\Add5~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~21 .extended_lut = "off";
+defparam \Add5~21 .lut_mask = 64'h0000FFFF0000F780;
+defparam \Add5~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N36
+cyclonev_lcell_comb \sft_tmp_oN~5 (
+// Equation(s):
+// \sft_tmp_oN~5_combout  = ( \Add5~21_sumout  & ( ((!\LessThan0~1_combout  & ((\Add4~21_sumout ))) # (\LessThan0~1_combout  & (\ShiftRight0~17_combout ))) # (\Operation~0_combout ) ) ) # ( !\Add5~21_sumout  & ( (!\Operation~0_combout  & 
+// ((!\LessThan0~1_combout  & ((\Add4~21_sumout ))) # (\LessThan0~1_combout  & (\ShiftRight0~17_combout )))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\ShiftRight0~17_combout ),
+	.datad(!\Add4~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Add5~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~5 .extended_lut = "off";
+defparam \sft_tmp_oN~5 .lut_mask = 64'h028A028A57DF57DF;
+defparam \sft_tmp_oN~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N51
+cyclonev_lcell_comb \Add4~25 (
+// Equation(s):
+// \Add4~25_sumout  = SUM(( (!\R_O[3]~4_combout  & (!\Extract_IN2|Add1~1_sumout  $ (((\ShiftRight0~9_combout ) # (\R_O[2]~1_combout ))))) # (\R_O[3]~4_combout  & (\Extract_IN2|Add1~1_sumout  & (!\R_O[2]~1_combout  & !\ShiftRight0~9_combout ))) ) + ( GND ) + 
+// ( \Add4~22  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\R_O[2]~1_combout ),
+	.datad(!\ShiftRight0~9_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add4~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add4~25_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add4~25 .extended_lut = "off";
+defparam \Add4~25 .lut_mask = 64'h0000FFFF00009222;
+defparam \Add4~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N48
+cyclonev_lcell_comb \ShiftRight0~18 (
+// Equation(s):
+// \ShiftRight0~18_combout  = ( \R_O[2]~1_combout  & ( (!\R_O[3]~4_combout  & \Extract_IN2|Add1~1_sumout ) ) ) # ( !\R_O[2]~1_combout  & ( (!\R_O[3]~4_combout  & (!\Extract_IN2|Add1~1_sumout  $ (\ShiftRight0~9_combout ))) # (\R_O[3]~4_combout  & 
+// (\Extract_IN2|Add1~1_sumout  & !\ShiftRight0~9_combout )) ) )
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\Extract_IN2|Add1~1_sumout ),
+	.datac(!\ShiftRight0~9_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\R_O[2]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ShiftRight0~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ShiftRight0~18 .extended_lut = "off";
+defparam \ShiftRight0~18 .lut_mask = 64'h9292929222222222;
+defparam \ShiftRight0~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N18
+cyclonev_lcell_comb \Add5~25 (
+// Equation(s):
+// \Add5~25_sumout  = SUM(( (!\R_O[3]~4_combout  & ((!\LessThan0~0_combout  & (!\ShiftRight0~18_combout )) # (\LessThan0~0_combout  & ((!\Add4~25_sumout ))))) # (\R_O[3]~4_combout  & (((!\Add4~25_sumout )))) ) + ( GND ) + ( \Add5~22  ))
+
+	.dataa(!\R_O[3]~4_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\ShiftRight0~18_combout ),
+	.datad(!\Add4~25_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add5~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add5~25_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add5~25 .extended_lut = "off";
+defparam \Add5~25 .lut_mask = 64'h0000FFFF0000F780;
+defparam \Add5~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y11_N27
+cyclonev_lcell_comb \sft_tmp_oN~6 (
+// Equation(s):
+// \sft_tmp_oN~6_combout  = ( \ShiftRight0~18_combout  & ( (!\Operation~0_combout  & (((\Add4~25_sumout )) # (\LessThan0~1_combout ))) # (\Operation~0_combout  & (((\Add5~25_sumout )))) ) ) # ( !\ShiftRight0~18_combout  & ( (!\Operation~0_combout  & 
+// (!\LessThan0~1_combout  & (\Add4~25_sumout ))) # (\Operation~0_combout  & (((\Add5~25_sumout )))) ) )
+
+	.dataa(!\Operation~0_combout ),
+	.datab(!\LessThan0~1_combout ),
+	.datac(!\Add4~25_sumout ),
+	.datad(!\Add5~25_sumout ),
+	.datae(gnd),
+	.dataf(!\ShiftRight0~18_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sft_tmp_oN~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sft_tmp_oN~6 .extended_lut = "off";
+defparam \sft_tmp_oN~6 .lut_mask = 64'h085D085D2A7F2A7F;
+defparam \sft_tmp_oN~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X9_Y48_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
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similarity index 90%
rename from Individual_Project/Posit_Adder/Core_Arithmetic/wlfty19qdr
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Binary files a/Individual_Project/Posit_Adder/Core_Arithmetic/wlfty19qdr and b/Individual_Project/Posit_Multiplier/vsim.wlf differ
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/vsim.wlf b/Individual_Project/Posit_Multiplier/wlft4xv32m
similarity index 96%
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similarity index 90%
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similarity index 94%
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diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_vmake b/Individual_Project/Posit_Multiplier/work/_vmake
similarity index 100%
rename from Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/work/_vmake
rename to Individual_Project/Posit_Multiplier/work/_vmake
diff --git a/Individual_Project/tbPositAdder.sv b/Individual_Project/tbPositAdder.sv
deleted file mode 100644
index 86f23f7323825056ac996ba2a352acaff0f75be0..0000000000000000000000000000000000000000
--- a/Individual_Project/tbPositAdder.sv
+++ /dev/null
@@ -1,63 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-// Design unit: tb_Posit_Adder
-//            :
-// File name  : tbPositAdder.sv
-//            :
-// Description: Testbench for Posit Adder
-//            :
-// Limitations: None
-//            : 
-// System     : SystemVerilog IEEE 1800-2005
-//            :
-// Author     : Xiaoan He (Jasper)
-//            : xh2g20@ecs.soton.ac.uk
-//
-// Revision   : Version 1.1 07/12/2022
-/////////////////////////////////////////////////////////////////////
-
-function [31:0] log2;
-input reg [31:0] value;
-	begin
-	value = value-1;
-	for (log2=0; value>0; log2=log2+1)
-        	value = value>>1;
-      	end
-endfunction
-
-module Test_Posit_Adder;
-parameter N = 8, RS = log2(N), ES = 3;
-
-// Input Logic
-logic signed [N-1:0] In1, In2;
-
-// Output Logic
-logic signed [ES+RS:0] LE_O;
-logic [ES-1:0] E_O;
-logic signed [RS:0] R_O;
-
-Posit_Adder #(.N(N), .ES(ES)) PA (.*);
-
-initial
-    begin
-        // initial input is nothing
-        #10ns In1 = 8'b0_0000000;
-              In2 = 8'b0_0000000;
-              
-        #50ns In1 = 8'b0_01_000_01;  // R = -1, E = 000, M = 1.01
-              In2 = 8'b0_001_010_0;  // R = -2, E = 010, M = 1.0
-
-        #50ns In1 = 8'b0_10_001_10;  // R = 0, E = 100, M = 1.1
-              In2 = 8'b0_110_011_1;  // R = 1, E = 100, M = 1.01
-
-        //#50ns In = 8'b0_0001_100;   // R = -3, E = 100, M = 1.00
-        #50ns In1 = 8'b0_1110_101;   // R = 2, E = 101, M = 1.00
-              In2 = 8'b1_01_000_01;  // 10_111_11 R = 0 , E = 111, M = 1.11
-        #50ns In1 = 8'b1_10_001_10;  // 001_110_10 R = -2, E = 110, M = 1.10
-              In2 = 8'b1_001_010_0;  // 01_101_100 R = -1, E = 101, M = 1.10
-        // #50ns In = 8'b1_110_011_1;  // R = -3, E = 100, M = 1.01
-        // #50ns In = 8'b1_0001_100;   // R = -3, E = 100, M = 1.01
-        // #50ns In = 8'b1_1110_101;   // R = -3, E = 100, M = 1.01
-
-
-    end
-endmodule
\ No newline at end of file
diff --git a/Posit_Mult_RTL_View.pdf b/Posit_Mult_RTL_View.pdf
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diff --git a/Reference Code/add/Posit_Adder.done b/Reference Code/add/Posit_Adder.done
new file mode 100644
index 0000000000000000000000000000000000000000..6e23ee06a7505e8a1791ac5da47a7d00067af534
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.done	
@@ -0,0 +1 @@
+Tue Feb 21 16:59:12 2023
diff --git a/Reference Code/add/Posit_Adder.flow.rpt b/Reference Code/add/Posit_Adder.flow.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..96318588cdd74cc092448e85d791e6b8dcc378bd
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.flow.rpt	
@@ -0,0 +1,119 @@
+Flow report for Posit_Adder
+Tue Feb 21 16:59:11 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++---------------------------------+------------------------------------------------+
+; Flow Status                     ; Successful - Tue Feb 21 16:59:11 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Adder                                    ;
+; Top-level Entity Name           ; posit_add                                      ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CGXFC7C7F23C8                                 ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 52                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 0                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/21/2023 16:59:01 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; Posit_Adder         ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                        ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 1099276844422.167699874115208          ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top        ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; posit_add                              ; Posit_Adder   ; --          ; --         ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:11     ; 1.0                     ; 4842 MB             ; 00:00:08                           ;
+; Total                ; 00:00:11     ; --                      ; --                  ; 00:00:08                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder
+
+
+
diff --git a/Reference Code/add/Posit_Adder.map.rpt b/Reference Code/add/Posit_Adder.map.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3b182ed317ee286892f38f9cb01627f585ab2422
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.map.rpt	
@@ -0,0 +1,1409 @@
+Analysis & Synthesis report for Posit_Adder
+Tue Feb 21 16:59:11 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 10. Parameter Settings for User Entity Instance: Top-level Entity: |posit_add
+ 11. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1
+ 12. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k
+ 13. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1
+ 14. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l
+ 15. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+ 16. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+ 17. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+ 18. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+ 19. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+ 20. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+ 21. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h
+ 22. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+ 23. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+ 24. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+ 25. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+ 26. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+ 27. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+ 28. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|DSR_left_N_S:ls
+ 29. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2
+ 30. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k
+ 31. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1
+ 32. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l
+ 33. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+ 34. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+ 35. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+ 36. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+ 37. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+ 38. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+ 39. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h
+ 40. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+ 41. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+ 42. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+ 43. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+ 44. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+ 45. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+ 46. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|DSR_left_N_S:ls
+ 47. Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime1
+ 48. Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime2
+ 49. Parameter Settings for User Entity Instance: sub_N:uut_ediff
+ 50. Parameter Settings for User Entity Instance: sub_N:uut_ediff|sub_N_in:s1
+ 51. Parameter Settings for User Entity Instance: DSR_right_N_S:dsr1
+ 52. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N
+ 53. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11
+ 54. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1
+ 55. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11
+ 56. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1
+ 57. Parameter Settings for User Entity Instance: LOD_N:l2
+ 58. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1
+ 59. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l
+ 60. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l
+ 61. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l
+ 62. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h
+ 63. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h
+ 64. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l
+ 65. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h
+ 66. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h
+ 67. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l
+ 68. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l
+ 69. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h
+ 70. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h
+ 71. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l
+ 72. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h
+ 73. Parameter Settings for User Entity Instance: DSR_left_N_S:dsl1
+ 74. Parameter Settings for User Entity Instance: sub_N:sub3
+ 75. Parameter Settings for User Entity Instance: sub_N:sub3|sub_N_in:s1
+ 76. Parameter Settings for User Entity Instance: add_1:uut_add_mantovf
+ 77. Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro
+ 78. Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1
+ 79. Parameter Settings for User Entity Instance: DSR_right_N_S:dsr2
+ 80. Parameter Settings for User Entity Instance: add_N:uut_add_ulp
+ 81. Parameter Settings for User Entity Instance: add_N:uut_add_ulp|add_N_in:a1
+ 82. Port Connectivity Checks: "add_N:uut_add_ulp"
+ 83. Port Connectivity Checks: "DSR_right_N_S:dsr2"
+ 84. Port Connectivity Checks: "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1"
+ 85. Port Connectivity Checks: "add_1:uut_add_mantovf"
+ 86. Port Connectivity Checks: "sub_N:sub3"
+ 87. Port Connectivity Checks: "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1"
+ 88. Port Connectivity Checks: "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1"
+ 89. Port Connectivity Checks: "add_sub_N:uut_add_sub_N"
+ 90. Port Connectivity Checks: "DSR_right_N_S:dsr1"
+ 91. Port Connectivity Checks: "sub_N:uut_ediff|sub_N_in:s1"
+ 92. Port Connectivity Checks: "sub_N:uut_ediff"
+ 93. Port Connectivity Checks: "data_extract_v1:uut_de1|DSR_left_N_S:ls"
+ 94. Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1"
+ 95. Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k"
+ 96. Post-Synthesis Netlist Statistics for Top Partition
+ 97. Elapsed Time Per Partition
+ 98. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++---------------------------------+------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Feb 21 16:59:11 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; Posit_Adder                                    ;
+; Top-level Entity Name           ; posit_add                                      ;
+; Family                          ; Cyclone V                                      ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 52                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 0                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CGXFC7C7F23C8     ;                    ;
+; Top-level entity name                                                           ; posit_add          ; Posit_Adder        ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                             ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                               ; Library ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+; posit_add.v                      ; yes             ; User Verilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v ;         ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                  ;
++---------------------------------------------+--------------------------------+
+; Resource                                    ; Usage                          ;
++---------------------------------------------+--------------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 337                            ;
+;                                             ;                                ;
+; Combinational ALUT usage for logic          ; 505                            ;
+;     -- 7 input functions                    ; 4                              ;
+;     -- 6 input functions                    ; 165                            ;
+;     -- 5 input functions                    ; 85                             ;
+;     -- 4 input functions                    ; 117                            ;
+;     -- <=3 input functions                  ; 134                            ;
+;                                             ;                                ;
+; Dedicated logic registers                   ; 0                              ;
+;                                             ;                                ;
+; I/O pins                                    ; 52                             ;
+;                                             ;                                ;
+; Total DSP Blocks                            ; 0                              ;
+;                                             ;                                ;
+; Maximum fan-out node                        ; reg_exp_op:uut_reg_ro|r_o[3]~1 ;
+; Maximum fan-out                             ; 59                             ;
+; Total fan-out                               ; 2389                           ;
+; Average fan-out                             ; 3.92                           ;
++---------------------------------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                             ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node      ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                 ; Entity Name     ; Library Name ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; |posit_add                      ; 505 (165)           ; 0 (0)                     ; 0                 ; 0          ; 52   ; 0            ; |posit_add                                                          ; posit_add       ; work         ;
+;    |DSR_left_N_S:dsl1|          ; 25 (25)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_left_N_S:dsl1                                        ; DSR_left_N_S    ; work         ;
+;    |DSR_right_N_S:dsr1|         ; 45 (45)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr1                                       ; DSR_right_N_S   ; work         ;
+;    |DSR_right_N_S:dsr2|         ; 62 (62)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr2                                       ; DSR_right_N_S   ; work         ;
+;    |LOD_N:l2|                   ; 30 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2                                                 ; LOD_N           ; work         ;
+;       |LOD:l1|                  ; 30 (27)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1                                          ; LOD             ; work         ;
+;          |LOD:h|                ; 2 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h                              ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l                        ; LOD             ; work         ;
+;             |LOD:l|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l                              ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h                        ; LOD             ; work         ;
+;          |LOD:l|                ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h                              ; LOD             ; work         ;
+;    |abs_regime:uut_abs_regime1| ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime1                               ; abs_regime      ; work         ;
+;    |abs_regime:uut_abs_regime2| ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime2                               ; abs_regime      ; work         ;
+;    |add_1:uut_add_mantovf|      ; 12 (12)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_1:uut_add_mantovf                                    ; add_1           ; work         ;
+;    |add_N:uut_add_ulp|          ; 16 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp                                        ; add_N           ; work         ;
+;       |add_N_in:a1|             ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp|add_N_in:a1                            ; add_N_in        ; work         ;
+;    |add_sub_N:uut_add_sub_N|    ; 21 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N                                  ; add_sub_N       ; work         ;
+;       |add_N:a11|               ; 21 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11                        ; add_N           ; work         ;
+;          |add_N_in:a1|          ; 21 (21)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1            ; add_N_in        ; work         ;
+;    |data_extract_v1:uut_de1|    ; 51 (4)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 29 (29)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 18 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 18 (15)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 2 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |data_extract_v1:uut_de2|    ; 52 (4)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 30 (30)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 18 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 18 (15)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 2 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |reg_exp_op:uut_reg_ro|      ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|reg_exp_op:uut_reg_ro                                    ; reg_exp_op      ; work         ;
+;    |sub_N:uut_ediff|            ; 8 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff                                          ; sub_N           ; work         ;
+;       |sub_N_in:s1|             ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff|sub_N_in:s1                              ; sub_N_in        ; work         ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                              ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|tmp[1][7]  ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[3]       ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[7]       ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[10]      ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|tmp[1][11] ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[5]       ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[9]       ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[11]      ;
+; 4:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[0][5]                       ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][14]                      ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][12]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][10]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][9]                       ;
+; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|tmp[1][4]                        ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|c[10]                            ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|tmp_o[7]                                           ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[1][23]                      ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[1][19]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[2][29]                      ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[5]                            ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[7]                            ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[34]                           ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[27]                           ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[13]                           ;
+; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[16]                           ;
+; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |posit_add|out                                                ;
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[0][27]                      ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|c[0]                            ;
+; 5:1                ; 6 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|c[3]                            ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[12]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[14]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[12]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[15]      ;
+; 7:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|c[12]                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |posit_add ;
++----------------+----------------------------------+-----------------------+
+; Parameter Name ; Value                            ; Type                  ;
++----------------+----------------------------------+-----------------------+
+; N              ; 16                               ; Signed Integer        ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary       ;
+; es             ; 2                                ; Signed Integer        ;
++----------------+----------------------------------+-----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1 ;
++----------------+----------------------------------+------------------+
+; Parameter Name ; Value                            ; Type             ;
++----------------+----------------------------------+------------------+
+; N              ; 16                               ; Signed Integer   ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary  ;
+; es             ; 2                                ; Signed Integer   ;
++----------------+----------------------------------+------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k ;
++----------------+----------------------------------+--------------------------------+
+; Parameter Name ; Value                            ; Type                           ;
++----------------+----------------------------------+--------------------------------+
+; N              ; 16                               ; Signed Integer                 ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                ;
++----------------+----------------------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1 ;
++----------------+----------------------------------+---------------------------------------+
+; Parameter Name ; Value                            ; Type                                  ;
++----------------+----------------------------------+---------------------------------------+
+; N              ; 16                               ; Signed Integer                        ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                       ;
++----------------+----------------------------------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|DSR_left_N_S:ls ;
++----------------+----------------------------------+----------------------------------+
+; Parameter Name ; Value                            ; Type                             ;
++----------------+----------------------------------+----------------------------------+
+; N              ; 16                               ; Signed Integer                   ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                  ;
++----------------+----------------------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2 ;
++----------------+----------------------------------+------------------+
+; Parameter Name ; Value                            ; Type             ;
++----------------+----------------------------------+------------------+
+; N              ; 16                               ; Signed Integer   ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary  ;
+; es             ; 2                                ; Signed Integer   ;
++----------------+----------------------------------+------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k ;
++----------------+----------------------------------+--------------------------------+
+; Parameter Name ; Value                            ; Type                           ;
++----------------+----------------------------------+--------------------------------+
+; N              ; 16                               ; Signed Integer                 ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                ;
++----------------+----------------------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1 ;
++----------------+----------------------------------+---------------------------------------+
+; Parameter Name ; Value                            ; Type                                  ;
++----------------+----------------------------------+---------------------------------------+
+; N              ; 16                               ; Signed Integer                        ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                       ;
++----------------+----------------------------------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|DSR_left_N_S:ls ;
++----------------+----------------------------------+----------------------------------+
+; Parameter Name ; Value                            ; Type                             ;
++----------------+----------------------------------+----------------------------------+
+; N              ; 16                               ; Signed Integer                   ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                  ;
++----------------+----------------------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime1 ;
++----------------+----------------------------------+---------------------+
+; Parameter Name ; Value                            ; Type                ;
++----------------+----------------------------------+---------------------+
+; N              ; 00000000000000000000000000000100 ; Unsigned Binary     ;
++----------------+----------------------------------+---------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime2 ;
++----------------+----------------------------------+---------------------+
+; Parameter Name ; Value                            ; Type                ;
++----------------+----------------------------------+---------------------+
+; N              ; 00000000000000000000000000000100 ; Unsigned Binary     ;
++----------------+----------------------------------+---------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:uut_ediff        ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:uut_ediff|sub_N_in:s1 ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_right_N_S:dsr1     ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N ;
++----------------+-------+---------------------------------------------+
+; Parameter Name ; Value ; Type                                        ;
++----------------+-------+---------------------------------------------+
+; N              ; 16    ; Signed Integer                              ;
++----------------+-------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11 ;
++----------------+-------+-------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                  ;
++----------------+-------+-------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                        ;
++----------------+-------+-------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1 ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                              ;
++----------------+-------+-------------------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                                    ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11 ;
++----------------+-------+-------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                  ;
++----------------+-------+-------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                        ;
++----------------+-------+-------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1 ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                              ;
++----------------+-------+-------------------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                                    ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2               ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1        ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 8                                ; Signed Integer  ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 8                                ; Signed Integer  ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_left_N_S:dsl1      ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:sub3             ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:sub3|sub_N_in:s1 ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_1:uut_add_mantovf  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; es             ; 2                                ; Signed Integer  ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1 ;
++----------------+----------------------------------+-------------------------------------+
+; Parameter Name ; Value                            ; Type                                ;
++----------------+----------------------------------+-------------------------------------+
+; N              ; 00000000000000000000000000000110 ; Unsigned Binary                     ;
++----------------+----------------------------------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_right_N_S:dsr2     ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 51                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_N:uut_add_ulp ;
++----------------+-------+---------------------------------------+
+; Parameter Name ; Value ; Type                                  ;
++----------------+-------+---------------------------------------+
+; N              ; 16    ; Signed Integer                        ;
++----------------+-------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_N:uut_add_ulp|add_N_in:a1 ;
++----------------+-------+---------------------------------------------------+
+; Parameter Name ; Value ; Type                                              ;
++----------------+-------+---------------------------------------------------+
+; N              ; 16    ; Signed Integer                                    ;
++----------------+-------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_N:uut_add_ulp"                                                                      ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; b[15..1] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; c[16]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DSR_right_N_S:dsr2"                                                                      ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port      ; Type   ; Severity ; Details                                                                             ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+; a[16..0]  ; Input  ; Info     ; Stuck at GND                                                                        ;
+; c[50..35] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1"                                         ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[6] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_1:uut_add_mantovf"                                                              ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------+
+; Port Connectivity Checks: "sub_N:sub3"    ;
++---------+-------+----------+--------------+
+; Port    ; Type  ; Severity ; Details      ;
++---------+-------+----------+--------------+
+; b[6..4] ; Input ; Info     ; Stuck at GND ;
++---------+-------+----------+--------------+
+
+
++---------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1" ;
++-------+-------+----------+------------------------------------------------+
+; Port  ; Type  ; Severity ; Details                                        ;
++-------+-------+----------+------------------------------------------------+
+; a[16] ; Input ; Info     ; Stuck at GND                                   ;
+; b[16] ; Input ; Info     ; Stuck at GND                                   ;
++-------+-------+----------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1" ;
++-------+-------+----------+------------------------------------------------+
+; Port  ; Type  ; Severity ; Details                                        ;
++-------+-------+----------+------------------------------------------------+
+; a[16] ; Input ; Info     ; Stuck at GND                                   ;
+; b[16] ; Input ; Info     ; Stuck at GND                                   ;
++-------+-------+----------+------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N" ;
++------+-------+----------+---------------------------+
+; Port ; Type  ; Severity ; Details                   ;
++------+-------+----------+---------------------------+
+; a[0] ; Input ; Info     ; Stuck at GND              ;
++------+-------+----------+---------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "DSR_right_N_S:dsr1" ;
++------+-------+----------+----------------------+
+; Port ; Type  ; Severity ; Details              ;
++------+-------+----------+----------------------+
+; a[0] ; Input ; Info     ; Stuck at GND         ;
++------+-------+----------+----------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "sub_N:uut_ediff|sub_N_in:s1" ;
++------+-------+----------+-------------------------------+
+; Port ; Type  ; Severity ; Details                       ;
++------+-------+----------+-------------------------------+
+; a[7] ; Input ; Info     ; Stuck at GND                  ;
+; b[7] ; Input ; Info     ; Stuck at GND                  ;
++------+-------+----------+-------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "sub_N:uut_ediff"                                                                    ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|DSR_left_N_S:ls" ;
++---------+-------+----------+----------------------------------------+
+; Port    ; Type  ; Severity ; Details                                ;
++---------+-------+----------+----------------------------------------+
+; a[1..0] ; Input ; Info     ; Stuck at GND                           ;
++---------+-------+----------+----------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1"                                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; vld  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k" ;
++--------+-------+----------+---------------------------------------+
+; Port   ; Type  ; Severity ; Details                               ;
++--------+-------+----------+---------------------------------------+
+; in[15] ; Input ; Info     ; Stuck at GND                          ;
++--------+-------+----------+---------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb     ; 506                         ;
+;     arith             ; 94                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 6                           ;
+;         2 data inputs ; 34                          ;
+;         3 data inputs ; 10                          ;
+;         4 data inputs ; 20                          ;
+;         5 data inputs ; 23                          ;
+;     extend            ; 4                           ;
+;         7 data inputs ; 4                           ;
+;     normal            ; 408                         ;
+;         1 data inputs ; 1                           ;
+;         2 data inputs ; 31                          ;
+;         3 data inputs ; 52                          ;
+;         4 data inputs ; 97                          ;
+;         5 data inputs ; 62                          ;
+;         6 data inputs ; 165                         ;
+; boundary_port         ; 52                          ;
+;                       ;                             ;
+; Max LUT depth         ; 29.80                       ;
+; Average LUT depth     ; 28.49                       ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 21 16:59:00 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (12021): Found 15 design units, including 15 entities, in source file posit_add.v
+    Info (12023): Found entity 1: posit_add File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 2
+    Info (12023): Found entity 2: data_extract_v1 File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 155
+    Info (12023): Found entity 3: sub_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 194
+    Info (12023): Found entity 4: add_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 204
+    Info (12023): Found entity 5: sub_N_in File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 214
+    Info (12023): Found entity 6: add_N_in File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 222
+    Info (12023): Found entity 7: add_sub_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 230
+    Info (12023): Found entity 8: add_1 File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 243
+    Info (12023): Found entity 9: abs_regime File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 252
+    Info (12023): Found entity 10: conv_2c File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 262
+    Info (12023): Found entity 11: reg_exp_op File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 269
+    Info (12023): Found entity 12: DSR_left_N_S File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 285
+    Info (12023): Found entity 13: DSR_right_N_S File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 306
+    Info (12023): Found entity 14: LOD_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 327
+    Info (12023): Found entity 15: LOD File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 348
+Info (12127): Elaborating entity "posit_add" for the top level hierarchy
+Info (12128): Elaborating entity "data_extract_v1" for hierarchy "data_extract_v1:uut_de1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 42
+Warning (10230): Verilog HDL assignment warning at posit_add.v(183): truncated value with size 32 to match size of target (4) File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 183
+Info (12128): Elaborating entity "LOD_N" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 181
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 344
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "DSR_left_N_S" for hierarchy "data_extract_v1:uut_de1|DSR_left_N_S:ls" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 186
+Info (12128): Elaborating entity "abs_regime" for hierarchy "abs_regime:uut_abs_regime1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 70
+Info (12128): Elaborating entity "sub_N" for hierarchy "sub_N:uut_ediff" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 72
+Info (12128): Elaborating entity "sub_N_in" for hierarchy "sub_N:uut_ediff|sub_N_in:s1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 200
+Info (12128): Elaborating entity "DSR_right_N_S" for hierarchy "DSR_right_N_S:dsr1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 86
+Info (12128): Elaborating entity "add_sub_N" for hierarchy "add_sub_N:uut_add_sub_N" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 98
+Info (12128): Elaborating entity "add_N" for hierarchy "add_sub_N:uut_add_sub_N|add_N:a11" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 237
+Info (12128): Elaborating entity "add_N_in" for hierarchy "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 210
+Info (12128): Elaborating entity "sub_N" for hierarchy "add_sub_N:uut_add_sub_N|sub_N:s11" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 238
+Info (12128): Elaborating entity "sub_N_in" for hierarchy "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 200
+Info (12128): Elaborating entity "add_1" for hierarchy "add_1:uut_add_mantovf" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 115
+Info (12128): Elaborating entity "reg_exp_op" for hierarchy "reg_exp_op:uut_reg_ro" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 119
+Warning (10230): Verilog HDL assignment warning at posit_add.v(281): truncated value with size 32 to match size of target (4) File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 281
+Info (12128): Elaborating entity "conv_2c" for hierarchy "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 279
+Info (12128): Elaborating entity "DSR_right_N_S" for hierarchy "DSR_right_N_S:dsr2" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 134
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 557 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 33 input pins
+    Info (21059): Implemented 19 output pins
+    Info (21061): Implemented 505 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 4842 megabytes
+    Info: Processing ended: Tue Feb 21 16:59:11 2023
+    Info: Elapsed time: 00:00:11
+    Info: Total CPU time (on all processors): 00:00:08
+
+
diff --git a/Reference Code/add/Posit_Adder.map.summary b/Reference Code/add/Posit_Adder.map.summary
new file mode 100644
index 0000000000000000000000000000000000000000..959940f063a0452b8cc985f6e9adaf181d8bb223
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.map.summary	
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Feb 21 16:59:11 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : Posit_Adder
+Top-level Entity Name : posit_add
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 52
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/Reference Code/add/Posit_Adder.qpf b/Reference Code/add/Posit_Adder.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..8b3ee3f29bb428ba0a242bcf952b0149f90e4d4f
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.qpf	
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 20:05:15  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "20:05:15  February 14, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "Posit_Adder"
diff --git a/Reference Code/add/Posit_Adder.qsf b/Reference Code/add/Posit_Adder.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..749968cea03060b69c2f87c057deaafdfab6bad0
--- /dev/null
+++ b/Reference Code/add/Posit_Adder.qsf	
@@ -0,0 +1,54 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 16:56:39  February 21, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Posit_Adder_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC7C7F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY posit_add
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:56:39  FEBRUARY 21, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name VERILOG_FILE posit_add.v
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Reference Code/add/Posit_Adder.qws b/Reference Code/add/Posit_Adder.qws
new file mode 100644
index 0000000000000000000000000000000000000000..bf1e54df58bd9f1aa6a3ade70cee4e5a4b948a1e
Binary files /dev/null and b/Reference Code/add/Posit_Adder.qws differ
diff --git a/Reference Code/add/Posit_adder_reference.cr.mti b/Reference Code/add/Posit_adder_reference.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..46c47560bb38436998c676c4fd1524d1662affee
--- /dev/null
+++ b/Reference Code/add/Posit_adder_reference.cr.mti	
@@ -0,0 +1,22 @@
+{H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module posit_add
+-- Compiling module data_extract_v1
+-- Compiling module sub_N
+-- Compiling module add_N
+-- Compiling module sub_N_in
+-- Compiling module add_N_in
+-- Compiling module add_sub_N
+-- Compiling module add_1
+-- Compiling module abs_regime
+-- Compiling module conv_2c
+-- Compiling module reg_exp_op
+-- Compiling module DSR_left_N_S
+-- Compiling module DSR_right_N_S
+-- Compiling module LOD_N
+-- Compiling module LOD
+
+Top level modules:
+	posit_add
+
+} {} {}}
diff --git a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.mpf b/Reference Code/add/Posit_adder_reference.mpf
similarity index 92%
rename from Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.mpf
rename to Reference Code/add/Posit_adder_reference.mpf
index a6977451033a1315add7648f6418f41bedab8ed5..ddec7e39bb71622497c64d97700d0b084578a7e5 100644
--- a/Individual_Project/Posit_Adder/Core_Arithmetic/Alignment/Alignment.mpf
+++ b/Reference Code/add/Posit_adder_reference.mpf	
@@ -220,7 +220,7 @@ Resolution = ps
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 100 ns
+RunLength = 125 ps
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -411,10 +411,10 @@ Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 2
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Alignment/TB_Alignment.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1669818989 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Individual_Project/Core_Arithmetic/Alignment/Posit_Adder_Alignment.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1669819211 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add_8bit_tb.v
+Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1677031432 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v
+Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677022284 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
diff --git a/Reference Code/add/c5_pin_model_dump.txt b/Reference Code/add/c5_pin_model_dump.txt
new file mode 100644
index 0000000000000000000000000000000000000000..31bb72c180c644b5936c76019879f6dabecae944
--- /dev/null
+++ b/Reference Code/add/c5_pin_model_dump.txt	
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/Reference Code/add/db/.cmp.kpt b/Reference Code/add/db/.cmp.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..7ecef3d26b7f14b2b4e7afc1c781185e4330be9a
Binary files /dev/null and b/Reference Code/add/db/.cmp.kpt differ
diff --git a/Reference Code/add/db/Posit_Adder.(0).cnf.cdb b/Reference Code/add/db/Posit_Adder.(0).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..e605d4d7f7bb0bb763274951718455c16a17e1ff
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diff --git a/Reference Code/add/db/Posit_Adder.(0).cnf.hdb b/Reference Code/add/db/Posit_Adder.(0).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..db04f02f1a58db711ef40404101448ad17623f47
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diff --git a/Reference Code/add/db/Posit_Adder.(1).cnf.cdb b/Reference Code/add/db/Posit_Adder.(1).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..b69e526b620513b72c0e5b33368f4265b10d2327
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diff --git a/Reference Code/add/db/Posit_Adder.(1).cnf.hdb b/Reference Code/add/db/Posit_Adder.(1).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..1dbb21d9737e8722bfad74785847f6e7ec26ffdf
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diff --git a/Reference Code/add/db/Posit_Adder.(10).cnf.cdb b/Reference Code/add/db/Posit_Adder.(10).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..cebf5dcb8240d1879e9b29a8454d54fa12c315bd
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diff --git a/Reference Code/add/db/Posit_Adder.(10).cnf.hdb b/Reference Code/add/db/Posit_Adder.(10).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..7c0d7792b3fbba73713bcbe7ddf3405f507d0c46
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diff --git a/Reference Code/add/db/Posit_Adder.(11).cnf.cdb b/Reference Code/add/db/Posit_Adder.(11).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..03bfd074656dfbc9d08f8a64c4d7a74477a81897
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diff --git a/Reference Code/add/db/Posit_Adder.(11).cnf.hdb b/Reference Code/add/db/Posit_Adder.(11).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..758fefb5ad202fd64ebcdb42696db9fba0521dfa
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diff --git a/Reference Code/add/db/Posit_Adder.(12).cnf.cdb b/Reference Code/add/db/Posit_Adder.(12).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..0dc0a2979113bd3d6bc59f0e52f96b896cfb66d2
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diff --git a/Reference Code/add/db/Posit_Adder.(12).cnf.hdb b/Reference Code/add/db/Posit_Adder.(12).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..3adc5a78c3da22e9ec5272526ec79adb23497ddc
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diff --git a/Reference Code/add/db/Posit_Adder.(13).cnf.cdb b/Reference Code/add/db/Posit_Adder.(13).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..568ca7bd059fc43eaf4e30b52524de7372460c4c
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diff --git a/Reference Code/add/db/Posit_Adder.(13).cnf.hdb b/Reference Code/add/db/Posit_Adder.(13).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..ed27c6ce9bfcfebaccb426af25e0dde98a3f4d5a
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diff --git a/Reference Code/add/db/Posit_Adder.(14).cnf.cdb b/Reference Code/add/db/Posit_Adder.(14).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..55e087b801f7b6c16a1916b4cf35caacbbf07e7b
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diff --git a/Reference Code/add/db/Posit_Adder.(14).cnf.hdb b/Reference Code/add/db/Posit_Adder.(14).cnf.hdb
new file mode 100644
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diff --git a/Reference Code/add/db/Posit_Adder.(15).cnf.cdb b/Reference Code/add/db/Posit_Adder.(15).cnf.cdb
new file mode 100644
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diff --git a/Reference Code/add/db/Posit_Adder.(15).cnf.hdb b/Reference Code/add/db/Posit_Adder.(15).cnf.hdb
new file mode 100644
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diff --git a/Reference Code/add/db/Posit_Adder.(16).cnf.cdb b/Reference Code/add/db/Posit_Adder.(16).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..afeffbd67b16a12cd7720b94684ee06fb70ae9f6
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diff --git a/Reference Code/add/db/Posit_Adder.(16).cnf.hdb b/Reference Code/add/db/Posit_Adder.(16).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..269224e4af2bcc411ffc7a0ed2f8c6fef3ce4e7f
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diff --git a/Reference Code/add/db/Posit_Adder.(17).cnf.cdb b/Reference Code/add/db/Posit_Adder.(17).cnf.cdb
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diff --git a/Reference Code/add/db/Posit_Adder.(17).cnf.hdb b/Reference Code/add/db/Posit_Adder.(17).cnf.hdb
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diff --git a/Reference Code/add/db/Posit_Adder.(18).cnf.cdb b/Reference Code/add/db/Posit_Adder.(18).cnf.cdb
new file mode 100644
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diff --git a/Reference Code/add/db/Posit_Adder.(18).cnf.hdb b/Reference Code/add/db/Posit_Adder.(18).cnf.hdb
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diff --git a/Reference Code/add/db/Posit_Adder.(19).cnf.cdb b/Reference Code/add/db/Posit_Adder.(19).cnf.cdb
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index 0000000000000000000000000000000000000000..8ca22a43745a732ee9fb8fb0b420ca2552e612be
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diff --git a/Reference Code/add/db/Posit_Adder.(19).cnf.hdb b/Reference Code/add/db/Posit_Adder.(19).cnf.hdb
new file mode 100644
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diff --git a/Reference Code/add/db/Posit_Adder.(2).cnf.cdb b/Reference Code/add/db/Posit_Adder.(2).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..724ee8cb956b8ead9262a04a74dcbeedda2f4696
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diff --git a/Reference Code/add/db/Posit_Adder.(2).cnf.hdb b/Reference Code/add/db/Posit_Adder.(2).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..13f1ce4265b976b44705020ea807cc7a7abf9fac
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diff --git a/Reference Code/add/db/Posit_Adder.(20).cnf.cdb b/Reference Code/add/db/Posit_Adder.(20).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..423bf7dc00c25ff2f447e2fa8cc72c238b091a71
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diff --git a/Reference Code/add/db/Posit_Adder.(20).cnf.hdb b/Reference Code/add/db/Posit_Adder.(20).cnf.hdb
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index 0000000000000000000000000000000000000000..7c7122439395af00888b5c43879630a064da55a0
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diff --git a/Reference Code/add/db/Posit_Adder.(3).cnf.cdb b/Reference Code/add/db/Posit_Adder.(3).cnf.cdb
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index 0000000000000000000000000000000000000000..e127e60231909463e5f1ddf23df89fae6d33fc47
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diff --git a/Reference Code/add/db/Posit_Adder.(3).cnf.hdb b/Reference Code/add/db/Posit_Adder.(3).cnf.hdb
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index 0000000000000000000000000000000000000000..8c32a1de67a42feed60fb5153afc136715ba12d5
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diff --git a/Reference Code/add/db/Posit_Adder.(4).cnf.cdb b/Reference Code/add/db/Posit_Adder.(4).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..e0b26e8763f2968dba18fa70d7e6a17ca8d29040
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diff --git a/Reference Code/add/db/Posit_Adder.(4).cnf.hdb b/Reference Code/add/db/Posit_Adder.(4).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..5e6f7fa1f2ce868d0869bbefe7ef59251ca3e26f
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diff --git a/Reference Code/add/db/Posit_Adder.(5).cnf.cdb b/Reference Code/add/db/Posit_Adder.(5).cnf.cdb
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index 0000000000000000000000000000000000000000..5684b23f189283bd3e0fedd030dce7766293a6f8
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diff --git a/Reference Code/add/db/Posit_Adder.(5).cnf.hdb b/Reference Code/add/db/Posit_Adder.(5).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..bf3203a41420fce03c39a136601f250b934169a8
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diff --git a/Reference Code/add/db/Posit_Adder.(6).cnf.cdb b/Reference Code/add/db/Posit_Adder.(6).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..470810c622d9594c95cf31287f32b5e11c7d78d9
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diff --git a/Reference Code/add/db/Posit_Adder.(6).cnf.hdb b/Reference Code/add/db/Posit_Adder.(6).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..49220a2ca231feaf40a76545288dab2c66ef8d4a
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diff --git a/Reference Code/add/db/Posit_Adder.(7).cnf.cdb b/Reference Code/add/db/Posit_Adder.(7).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..61c1478f8f7f5f96b4a362141a0098e47c3d4e56
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diff --git a/Reference Code/add/db/Posit_Adder.(7).cnf.hdb b/Reference Code/add/db/Posit_Adder.(7).cnf.hdb
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index 0000000000000000000000000000000000000000..00bd3768af11d1f7c025c14f99cf98d66223c0d4
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diff --git a/Reference Code/add/db/Posit_Adder.(8).cnf.cdb b/Reference Code/add/db/Posit_Adder.(8).cnf.cdb
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index 0000000000000000000000000000000000000000..240ff248a8274996e33a02835f0355f2e6a862dd
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diff --git a/Reference Code/add/db/Posit_Adder.(8).cnf.hdb b/Reference Code/add/db/Posit_Adder.(8).cnf.hdb
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index 0000000000000000000000000000000000000000..8be980c42d5cd08f6349d03bdba7633625b6bfcf
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diff --git a/Reference Code/add/db/Posit_Adder.(9).cnf.cdb b/Reference Code/add/db/Posit_Adder.(9).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..a1dbb9848e0f7b5e72c8c3be50a058c0d50d0b4e
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diff --git a/Reference Code/add/db/Posit_Adder.(9).cnf.hdb b/Reference Code/add/db/Posit_Adder.(9).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..a76f7f6c4bb18a5758ebebf00b1b5e42220cd288
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diff --git a/Reference Code/add/db/Posit_Adder.cbx.xml b/Reference Code/add/db/Posit_Adder.cbx.xml
new file mode 100644
index 0000000000000000000000000000000000000000..d23837fb371589595fa50c652e81d25258ecbff6
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.cbx.xml	
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="Posit_Adder">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Reference Code/add/db/Posit_Adder.cmp.rdb b/Reference Code/add/db/Posit_Adder.cmp.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..2f99007eba29badb0f8b28d0e56d4d00f26c4284
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diff --git a/Reference Code/add/db/Posit_Adder.cmp_merge.kpt b/Reference Code/add/db/Posit_Adder.cmp_merge.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..d7af8c7027a4cb3e9b57215774f88bd6cff47316
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diff --git a/Reference Code/add/db/Posit_Adder.db_info b/Reference Code/add/db/Posit_Adder.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..1ba14374a3d5f2ca4abfe5b29dae44e5bbcf511e
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.db_info	
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 21 16:56:39 2023
diff --git a/Reference Code/add/db/Posit_Adder.hier_info b/Reference Code/add/db/Posit_Adder.hier_info
new file mode 100644
index 0000000000000000000000000000000000000000..9247cb6d792e36bb58fa6bdd71906434bee7d33f
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.hier_info	
@@ -0,0 +1,2218 @@
+|posit_add
+in1[0] => WideOr0.IN0
+in1[0] => comb.DATAA
+in1[0] => Add0.IN17
+in1[1] => WideOr0.IN1
+in1[1] => comb.DATAA
+in1[1] => Add0.IN16
+in1[2] => WideOr0.IN2
+in1[2] => comb.DATAA
+in1[2] => Add0.IN15
+in1[3] => WideOr0.IN3
+in1[3] => comb.DATAA
+in1[3] => Add0.IN14
+in1[4] => WideOr0.IN4
+in1[4] => comb.DATAA
+in1[4] => Add0.IN13
+in1[5] => WideOr0.IN5
+in1[5] => comb.DATAA
+in1[5] => Add0.IN12
+in1[6] => WideOr0.IN6
+in1[6] => comb.DATAA
+in1[6] => Add0.IN11
+in1[7] => WideOr0.IN7
+in1[7] => comb.DATAA
+in1[7] => Add0.IN10
+in1[8] => WideOr0.IN8
+in1[8] => comb.DATAA
+in1[8] => Add0.IN9
+in1[9] => WideOr0.IN9
+in1[9] => comb.DATAA
+in1[9] => Add0.IN8
+in1[10] => WideOr0.IN10
+in1[10] => comb.DATAA
+in1[10] => Add0.IN7
+in1[11] => WideOr0.IN11
+in1[11] => comb.DATAA
+in1[11] => Add0.IN6
+in1[12] => WideOr0.IN12
+in1[12] => comb.DATAA
+in1[12] => Add0.IN5
+in1[13] => WideOr0.IN13
+in1[13] => comb.DATAA
+in1[13] => Add0.IN4
+in1[14] => WideOr0.IN14
+in1[14] => comb.DATAA
+in1[14] => Add0.IN3
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => ls.DATAB
+in1[15] => comb.IN0
+in1[15] => inf1.IN1
+in1[15] => comb.IN1
+in1[15] => Add0.IN2
+in2[0] => WideOr1.IN0
+in2[0] => comb.DATAA
+in2[0] => Add1.IN17
+in2[1] => WideOr1.IN1
+in2[1] => comb.DATAA
+in2[1] => Add1.IN16
+in2[2] => WideOr1.IN2
+in2[2] => comb.DATAA
+in2[2] => Add1.IN15
+in2[3] => WideOr1.IN3
+in2[3] => comb.DATAA
+in2[3] => Add1.IN14
+in2[4] => WideOr1.IN4
+in2[4] => comb.DATAA
+in2[4] => Add1.IN13
+in2[5] => WideOr1.IN5
+in2[5] => comb.DATAA
+in2[5] => Add1.IN12
+in2[6] => WideOr1.IN6
+in2[6] => comb.DATAA
+in2[6] => Add1.IN11
+in2[7] => WideOr1.IN7
+in2[7] => comb.DATAA
+in2[7] => Add1.IN10
+in2[8] => WideOr1.IN8
+in2[8] => comb.DATAA
+in2[8] => Add1.IN9
+in2[9] => WideOr1.IN9
+in2[9] => comb.DATAA
+in2[9] => Add1.IN8
+in2[10] => WideOr1.IN10
+in2[10] => comb.DATAA
+in2[10] => Add1.IN7
+in2[11] => WideOr1.IN11
+in2[11] => comb.DATAA
+in2[11] => Add1.IN6
+in2[12] => WideOr1.IN12
+in2[12] => comb.DATAA
+in2[12] => Add1.IN5
+in2[13] => WideOr1.IN13
+in2[13] => comb.DATAA
+in2[13] => Add1.IN4
+in2[14] => WideOr1.IN14
+in2[14] => comb.DATAA
+in2[14] => Add1.IN3
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => ls.DATAA
+in2[15] => comb.IN1
+in2[15] => inf2.IN1
+in2[15] => comb.IN1
+in2[15] => Add1.IN2
+start => done.DATAIN
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[7] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[8] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[9] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[10] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[11] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[12] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[13] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[14] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[15] <= out.DB_MAX_OUTPUT_PORT_TYPE
+inf <= inf.DB_MAX_OUTPUT_PORT_TYPE
+zero <= zero.DB_MAX_OUTPUT_PORT_TYPE
+done <= start.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1
+in[0] => xin[0].IN1
+in[1] => xin[1].IN1
+in[2] => xin[2].IN1
+in[3] => xin[3].IN1
+in[4] => xin[4].IN1
+in[5] => xin[5].IN1
+in[6] => xin[6].IN1
+in[7] => xin[7].IN1
+in[8] => xin[8].IN1
+in[9] => xin[9].IN1
+in[10] => xin[10].IN1
+in[11] => xin[11].IN1
+in[12] => xin[12].IN1
+in[13] => xin[13].IN1
+in[14] => rc.IN1
+in[15] => ~NO_FANOUT~
+rc <= rc.DB_MAX_OUTPUT_PORT_TYPE
+regime[0] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[1] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[2] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[3] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+exp[0] <= DSR_left_N_S:ls.c
+exp[1] <= DSR_left_N_S:ls.c
+mant[0] <= DSR_left_N_S:ls.c
+mant[1] <= DSR_left_N_S:ls.c
+mant[2] <= DSR_left_N_S:ls.c
+mant[3] <= DSR_left_N_S:ls.c
+mant[4] <= DSR_left_N_S:ls.c
+mant[5] <= DSR_left_N_S:ls.c
+mant[6] <= DSR_left_N_S:ls.c
+mant[7] <= DSR_left_N_S:ls.c
+mant[8] <= DSR_left_N_S:ls.c
+mant[9] <= DSR_left_N_S:ls.c
+mant[10] <= DSR_left_N_S:ls.c
+mant[11] <= DSR_left_N_S:ls.c
+mant[12] <= DSR_left_N_S:ls.c
+mant[13] <= DSR_left_N_S:ls.c
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2
+in[0] => xin[0].IN1
+in[1] => xin[1].IN1
+in[2] => xin[2].IN1
+in[3] => xin[3].IN1
+in[4] => xin[4].IN1
+in[5] => xin[5].IN1
+in[6] => xin[6].IN1
+in[7] => xin[7].IN1
+in[8] => xin[8].IN1
+in[9] => xin[9].IN1
+in[10] => xin[10].IN1
+in[11] => xin[11].IN1
+in[12] => xin[12].IN1
+in[13] => xin[13].IN1
+in[14] => rc.IN1
+in[15] => ~NO_FANOUT~
+rc <= rc.DB_MAX_OUTPUT_PORT_TYPE
+regime[0] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[1] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[2] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[3] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+exp[0] <= DSR_left_N_S:ls.c
+exp[1] <= DSR_left_N_S:ls.c
+mant[0] <= DSR_left_N_S:ls.c
+mant[1] <= DSR_left_N_S:ls.c
+mant[2] <= DSR_left_N_S:ls.c
+mant[3] <= DSR_left_N_S:ls.c
+mant[4] <= DSR_left_N_S:ls.c
+mant[5] <= DSR_left_N_S:ls.c
+mant[6] <= DSR_left_N_S:ls.c
+mant[7] <= DSR_left_N_S:ls.c
+mant[8] <= DSR_left_N_S:ls.c
+mant[9] <= DSR_left_N_S:ls.c
+mant[10] <= DSR_left_N_S:ls.c
+mant[11] <= DSR_left_N_S:ls.c
+mant[12] <= DSR_left_N_S:ls.c
+mant[13] <= DSR_left_N_S:ls.c
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|abs_regime:uut_abs_regime1
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+regime[0] => regime_N.DATAB
+regime[0] => Add0.IN6
+regime[1] => regime_N.DATAB
+regime[1] => Add0.IN5
+regime[2] => regime_N.DATAB
+regime[2] => Add0.IN4
+regime[3] => regime_N.DATAB
+regime[3] => Add0.IN3
+regime_N[0] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[1] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[2] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[3] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[4] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|abs_regime:uut_abs_regime2
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+regime[0] => regime_N.DATAB
+regime[0] => Add0.IN6
+regime[1] => regime_N.DATAB
+regime[1] => Add0.IN5
+regime[2] => regime_N.DATAB
+regime[2] => Add0.IN4
+regime[3] => regime_N.DATAB
+regime[3] => Add0.IN3
+regime_N[0] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[1] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[2] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[3] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[4] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|sub_N:uut_ediff
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+
+
+|posit_add|sub_N:uut_ediff|sub_N_in:s1
+a[0] => Add0.IN16
+a[1] => Add0.IN15
+a[2] => Add0.IN14
+a[3] => Add0.IN13
+a[4] => Add0.IN12
+a[5] => Add0.IN11
+a[6] => Add0.IN10
+a[7] => Add0.IN9
+b[0] => Add0.IN8
+b[1] => Add0.IN7
+b[2] => Add0.IN6
+b[3] => Add0.IN5
+b[4] => Add0.IN4
+b[5] => Add0.IN3
+b[6] => Add0.IN2
+b[7] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_right_N_S:dsr1
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][1].DATAA
+a[1] => tmp[0][0].DATAB
+a[2] => tmp[0][2].DATAA
+a[2] => tmp[0][1].DATAB
+a[3] => tmp[0][3].DATAA
+a[3] => tmp[0][2].DATAB
+a[4] => tmp[0][4].DATAA
+a[4] => tmp[0][3].DATAB
+a[5] => tmp[0][5].DATAA
+a[5] => tmp[0][4].DATAB
+a[6] => tmp[0][6].DATAA
+a[6] => tmp[0][5].DATAB
+a[7] => tmp[0][7].DATAA
+a[7] => tmp[0][6].DATAB
+a[8] => tmp[0][8].DATAA
+a[8] => tmp[0][7].DATAB
+a[9] => tmp[0][9].DATAA
+a[9] => tmp[0][8].DATAB
+a[10] => tmp[0][10].DATAA
+a[10] => tmp[0][9].DATAB
+a[11] => tmp[0][11].DATAA
+a[11] => tmp[0][10].DATAB
+a[12] => tmp[0][12].DATAA
+a[12] => tmp[0][11].DATAB
+a[13] => tmp[0][13].DATAA
+a[13] => tmp[0][12].DATAB
+a[14] => tmp[0][14].DATAA
+a[14] => tmp[0][13].DATAB
+a[15] => tmp[0][15].DATAA
+a[15] => tmp[0][14].DATAB
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+a[0] => a[0].IN2
+a[1] => a[1].IN2
+a[2] => a[2].IN2
+a[3] => a[3].IN2
+a[4] => a[4].IN2
+a[5] => a[5].IN2
+a[6] => a[6].IN2
+a[7] => a[7].IN2
+a[8] => a[8].IN2
+a[9] => a[9].IN2
+a[10] => a[10].IN2
+a[11] => a[11].IN2
+a[12] => a[12].IN2
+a[13] => a[13].IN2
+a[14] => a[14].IN2
+a[15] => a[15].IN2
+b[0] => b[0].IN2
+b[1] => b[1].IN2
+b[2] => b[2].IN2
+b[3] => b[3].IN2
+b[4] => b[4].IN2
+b[5] => b[5].IN2
+b[6] => b[6].IN2
+b[7] => b[7].IN2
+b[8] => b[8].IN2
+b[9] => b[9].IN2
+b[10] => b[10].IN2
+b[11] => b[11].IN2
+b[12] => b[12].IN2
+b[13] => b[13].IN2
+b[14] => b[14].IN2
+b[15] => b[15].IN2
+c[0] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= c.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N|add_N:a11
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= add_N_in:a1.port2
+c[1] <= add_N_in:a1.port2
+c[2] <= add_N_in:a1.port2
+c[3] <= add_N_in:a1.port2
+c[4] <= add_N_in:a1.port2
+c[5] <= add_N_in:a1.port2
+c[6] <= add_N_in:a1.port2
+c[7] <= add_N_in:a1.port2
+c[8] <= add_N_in:a1.port2
+c[9] <= add_N_in:a1.port2
+c[10] <= add_N_in:a1.port2
+c[11] <= add_N_in:a1.port2
+c[12] <= add_N_in:a1.port2
+c[13] <= add_N_in:a1.port2
+c[14] <= add_N_in:a1.port2
+c[15] <= add_N_in:a1.port2
+c[16] <= add_N_in:a1.port2
+
+
+|posit_add|add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1
+a[0] => Add0.IN17
+a[1] => Add0.IN16
+a[2] => Add0.IN15
+a[3] => Add0.IN14
+a[4] => Add0.IN13
+a[5] => Add0.IN12
+a[6] => Add0.IN11
+a[7] => Add0.IN10
+a[8] => Add0.IN9
+a[9] => Add0.IN8
+a[10] => Add0.IN7
+a[11] => Add0.IN6
+a[12] => Add0.IN5
+a[13] => Add0.IN4
+a[14] => Add0.IN3
+a[15] => Add0.IN2
+a[16] => Add0.IN1
+b[0] => Add0.IN34
+b[1] => Add0.IN33
+b[2] => Add0.IN32
+b[3] => Add0.IN31
+b[4] => Add0.IN30
+b[5] => Add0.IN29
+b[6] => Add0.IN28
+b[7] => Add0.IN27
+b[8] => Add0.IN26
+b[9] => Add0.IN25
+b[10] => Add0.IN24
+b[11] => Add0.IN23
+b[12] => Add0.IN22
+b[13] => Add0.IN21
+b[14] => Add0.IN20
+b[15] => Add0.IN19
+b[16] => Add0.IN18
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N|sub_N:s11
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+c[8] <= sub_N_in:s1.port2
+c[9] <= sub_N_in:s1.port2
+c[10] <= sub_N_in:s1.port2
+c[11] <= sub_N_in:s1.port2
+c[12] <= sub_N_in:s1.port2
+c[13] <= sub_N_in:s1.port2
+c[14] <= sub_N_in:s1.port2
+c[15] <= sub_N_in:s1.port2
+c[16] <= sub_N_in:s1.port2
+
+
+|posit_add|add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1
+a[0] => Add0.IN34
+a[1] => Add0.IN33
+a[2] => Add0.IN32
+a[3] => Add0.IN31
+a[4] => Add0.IN30
+a[5] => Add0.IN29
+a[6] => Add0.IN28
+a[7] => Add0.IN27
+a[8] => Add0.IN26
+a[9] => Add0.IN25
+a[10] => Add0.IN24
+a[11] => Add0.IN23
+a[12] => Add0.IN22
+a[13] => Add0.IN21
+a[14] => Add0.IN20
+a[15] => Add0.IN19
+a[16] => Add0.IN18
+b[0] => Add0.IN17
+b[1] => Add0.IN16
+b[2] => Add0.IN15
+b[3] => Add0.IN14
+b[4] => Add0.IN13
+b[5] => Add0.IN12
+b[6] => Add0.IN11
+b[7] => Add0.IN10
+b[8] => Add0.IN9
+b[9] => Add0.IN8
+b[10] => Add0.IN7
+b[11] => Add0.IN6
+b[12] => Add0.IN5
+b[13] => Add0.IN4
+b[14] => Add0.IN3
+b[15] => Add0.IN2
+b[16] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|LOD_N:l2|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_left_N_S:dsl1
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|sub_N:sub3
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+
+
+|posit_add|sub_N:sub3|sub_N_in:s1
+a[0] => Add0.IN16
+a[1] => Add0.IN15
+a[2] => Add0.IN14
+a[3] => Add0.IN13
+a[4] => Add0.IN12
+a[5] => Add0.IN11
+a[6] => Add0.IN10
+a[7] => Add0.IN9
+b[0] => Add0.IN8
+b[1] => Add0.IN7
+b[2] => Add0.IN6
+b[3] => Add0.IN5
+b[4] => Add0.IN4
+b[5] => Add0.IN3
+b[6] => Add0.IN2
+b[7] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_1:uut_add_mantovf
+a[0] => Add0.IN15
+a[1] => Add0.IN14
+a[2] => Add0.IN13
+a[3] => Add0.IN12
+a[4] => Add0.IN11
+a[5] => Add0.IN10
+a[6] => Add0.IN9
+a[7] => Add0.IN8
+mant_ovf => Add0.IN16
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|reg_exp_op:uut_reg_ro
+exp_o[0] => exp_oN[0].DATAA
+exp_o[0] => e_o[0].DATAIN
+exp_o[0] => _.IN1
+exp_o[1] => exp_oN[1].DATAA
+exp_o[1] => e_o[1].DATAIN
+exp_o[1] => _.IN1
+exp_o[2] => exp_oN[2].DATAA
+exp_o[2] => _.IN1
+exp_o[3] => exp_oN[3].DATAA
+exp_o[3] => _.IN1
+exp_o[4] => exp_oN[4].DATAA
+exp_o[4] => _.IN1
+exp_o[5] => exp_oN[5].DATAA
+exp_o[5] => _.IN1
+exp_o[6] => exp_oN[5].OUTPUTSELECT
+exp_o[6] => exp_oN[4].OUTPUTSELECT
+exp_o[6] => exp_oN[3].OUTPUTSELECT
+exp_o[6] => exp_oN[2].OUTPUTSELECT
+exp_o[6] => exp_oN[1].OUTPUTSELECT
+exp_o[6] => exp_oN[0].OUTPUTSELECT
+exp_o[6] => _.IN1
+exp_o[6] => r_o.IN1
+e_o[0] <= exp_o[0].DB_MAX_OUTPUT_PORT_TYPE
+e_o[1] <= exp_o[1].DB_MAX_OUTPUT_PORT_TYPE
+r_o[0] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[1] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[2] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[3] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1
+a[0] => Add0.IN14
+a[1] => Add0.IN13
+a[2] => Add0.IN12
+a[3] => Add0.IN11
+a[4] => Add0.IN10
+a[5] => Add0.IN9
+a[6] => Add0.IN8
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_right_N_S:dsr2
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][1].DATAA
+a[1] => tmp[0][0].DATAB
+a[2] => tmp[0][2].DATAA
+a[2] => tmp[0][1].DATAB
+a[3] => tmp[0][3].DATAA
+a[3] => tmp[0][2].DATAB
+a[4] => tmp[0][4].DATAA
+a[4] => tmp[0][3].DATAB
+a[5] => tmp[0][5].DATAA
+a[5] => tmp[0][4].DATAB
+a[6] => tmp[0][6].DATAA
+a[6] => tmp[0][5].DATAB
+a[7] => tmp[0][7].DATAA
+a[7] => tmp[0][6].DATAB
+a[8] => tmp[0][8].DATAA
+a[8] => tmp[0][7].DATAB
+a[9] => tmp[0][9].DATAA
+a[9] => tmp[0][8].DATAB
+a[10] => tmp[0][10].DATAA
+a[10] => tmp[0][9].DATAB
+a[11] => tmp[0][11].DATAA
+a[11] => tmp[0][10].DATAB
+a[12] => tmp[0][12].DATAA
+a[12] => tmp[0][11].DATAB
+a[13] => tmp[0][13].DATAA
+a[13] => tmp[0][12].DATAB
+a[14] => tmp[0][14].DATAA
+a[14] => tmp[0][13].DATAB
+a[15] => tmp[0][15].DATAA
+a[15] => tmp[0][14].DATAB
+a[16] => tmp[0][16].DATAA
+a[16] => tmp[0][15].DATAB
+a[17] => tmp[0][17].DATAA
+a[17] => tmp[0][16].DATAB
+a[18] => tmp[0][18].DATAA
+a[18] => tmp[0][17].DATAB
+a[19] => tmp[0][19].DATAA
+a[19] => tmp[0][18].DATAB
+a[20] => tmp[0][20].DATAA
+a[20] => tmp[0][19].DATAB
+a[21] => tmp[0][21].DATAA
+a[21] => tmp[0][20].DATAB
+a[22] => tmp[0][22].DATAA
+a[22] => tmp[0][21].DATAB
+a[23] => tmp[0][23].DATAA
+a[23] => tmp[0][22].DATAB
+a[24] => tmp[0][24].DATAA
+a[24] => tmp[0][23].DATAB
+a[25] => tmp[0][25].DATAA
+a[25] => tmp[0][24].DATAB
+a[26] => tmp[0][26].DATAA
+a[26] => tmp[0][25].DATAB
+a[27] => tmp[0][27].DATAA
+a[27] => tmp[0][26].DATAB
+a[28] => tmp[0][28].DATAA
+a[28] => tmp[0][27].DATAB
+a[29] => tmp[0][29].DATAA
+a[29] => tmp[0][28].DATAB
+a[30] => tmp[0][30].DATAA
+a[30] => tmp[0][29].DATAB
+a[31] => tmp[0][31].DATAA
+a[31] => tmp[0][30].DATAB
+a[32] => tmp[0][32].DATAA
+a[32] => tmp[0][31].DATAB
+a[33] => tmp[0][33].DATAA
+a[33] => tmp[0][32].DATAB
+a[34] => tmp[0][34].DATAA
+a[34] => tmp[0][33].DATAB
+a[35] => tmp[0][35].DATAA
+a[35] => tmp[0][34].DATAB
+a[36] => tmp[0][36].DATAA
+a[36] => tmp[0][35].DATAB
+a[37] => tmp[0][37].DATAA
+a[37] => tmp[0][36].DATAB
+a[38] => tmp[0][38].DATAA
+a[38] => tmp[0][37].DATAB
+a[39] => tmp[0][39].DATAA
+a[39] => tmp[0][38].DATAB
+a[40] => tmp[0][40].DATAA
+a[40] => tmp[0][39].DATAB
+a[41] => tmp[0][41].DATAA
+a[41] => tmp[0][40].DATAB
+a[42] => tmp[0][42].DATAA
+a[42] => tmp[0][41].DATAB
+a[43] => tmp[0][43].DATAA
+a[43] => tmp[0][42].DATAB
+a[44] => tmp[0][44].DATAA
+a[44] => tmp[0][43].DATAB
+a[45] => tmp[0][45].DATAA
+a[45] => tmp[0][44].DATAB
+a[46] => tmp[0][46].DATAA
+a[46] => tmp[0][45].DATAB
+a[47] => tmp[0][47].DATAA
+a[47] => tmp[0][46].DATAB
+a[48] => tmp[0][48].DATAA
+a[48] => tmp[0][47].DATAB
+a[49] => tmp[0][49].DATAA
+a[49] => tmp[0][48].DATAB
+a[50] => tmp[0][50].DATAA
+a[50] => tmp[0][49].DATAB
+b[0] => tmp[0][50].OUTPUTSELECT
+b[0] => tmp[0][49].OUTPUTSELECT
+b[0] => tmp[0][48].OUTPUTSELECT
+b[0] => tmp[0][47].OUTPUTSELECT
+b[0] => tmp[0][46].OUTPUTSELECT
+b[0] => tmp[0][45].OUTPUTSELECT
+b[0] => tmp[0][44].OUTPUTSELECT
+b[0] => tmp[0][43].OUTPUTSELECT
+b[0] => tmp[0][42].OUTPUTSELECT
+b[0] => tmp[0][41].OUTPUTSELECT
+b[0] => tmp[0][40].OUTPUTSELECT
+b[0] => tmp[0][39].OUTPUTSELECT
+b[0] => tmp[0][38].OUTPUTSELECT
+b[0] => tmp[0][37].OUTPUTSELECT
+b[0] => tmp[0][36].OUTPUTSELECT
+b[0] => tmp[0][35].OUTPUTSELECT
+b[0] => tmp[0][34].OUTPUTSELECT
+b[0] => tmp[0][33].OUTPUTSELECT
+b[0] => tmp[0][32].OUTPUTSELECT
+b[0] => tmp[0][31].OUTPUTSELECT
+b[0] => tmp[0][30].OUTPUTSELECT
+b[0] => tmp[0][29].OUTPUTSELECT
+b[0] => tmp[0][28].OUTPUTSELECT
+b[0] => tmp[0][27].OUTPUTSELECT
+b[0] => tmp[0][26].OUTPUTSELECT
+b[0] => tmp[0][25].OUTPUTSELECT
+b[0] => tmp[0][24].OUTPUTSELECT
+b[0] => tmp[0][23].OUTPUTSELECT
+b[0] => tmp[0][22].OUTPUTSELECT
+b[0] => tmp[0][21].OUTPUTSELECT
+b[0] => tmp[0][20].OUTPUTSELECT
+b[0] => tmp[0][19].OUTPUTSELECT
+b[0] => tmp[0][18].OUTPUTSELECT
+b[0] => tmp[0][17].OUTPUTSELECT
+b[0] => tmp[0][16].OUTPUTSELECT
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][50].OUTPUTSELECT
+b[1] => tmp[1][49].OUTPUTSELECT
+b[1] => tmp[1][48].OUTPUTSELECT
+b[1] => tmp[1][47].OUTPUTSELECT
+b[1] => tmp[1][46].OUTPUTSELECT
+b[1] => tmp[1][45].OUTPUTSELECT
+b[1] => tmp[1][44].OUTPUTSELECT
+b[1] => tmp[1][43].OUTPUTSELECT
+b[1] => tmp[1][42].OUTPUTSELECT
+b[1] => tmp[1][41].OUTPUTSELECT
+b[1] => tmp[1][40].OUTPUTSELECT
+b[1] => tmp[1][39].OUTPUTSELECT
+b[1] => tmp[1][38].OUTPUTSELECT
+b[1] => tmp[1][37].OUTPUTSELECT
+b[1] => tmp[1][36].OUTPUTSELECT
+b[1] => tmp[1][35].OUTPUTSELECT
+b[1] => tmp[1][34].OUTPUTSELECT
+b[1] => tmp[1][33].OUTPUTSELECT
+b[1] => tmp[1][32].OUTPUTSELECT
+b[1] => tmp[1][31].OUTPUTSELECT
+b[1] => tmp[1][30].OUTPUTSELECT
+b[1] => tmp[1][29].OUTPUTSELECT
+b[1] => tmp[1][28].OUTPUTSELECT
+b[1] => tmp[1][27].OUTPUTSELECT
+b[1] => tmp[1][26].OUTPUTSELECT
+b[1] => tmp[1][25].OUTPUTSELECT
+b[1] => tmp[1][24].OUTPUTSELECT
+b[1] => tmp[1][23].OUTPUTSELECT
+b[1] => tmp[1][22].OUTPUTSELECT
+b[1] => tmp[1][21].OUTPUTSELECT
+b[1] => tmp[1][20].OUTPUTSELECT
+b[1] => tmp[1][19].OUTPUTSELECT
+b[1] => tmp[1][18].OUTPUTSELECT
+b[1] => tmp[1][17].OUTPUTSELECT
+b[1] => tmp[1][16].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][50].OUTPUTSELECT
+b[2] => tmp[2][49].OUTPUTSELECT
+b[2] => tmp[2][48].OUTPUTSELECT
+b[2] => tmp[2][47].OUTPUTSELECT
+b[2] => tmp[2][46].OUTPUTSELECT
+b[2] => tmp[2][45].OUTPUTSELECT
+b[2] => tmp[2][44].OUTPUTSELECT
+b[2] => tmp[2][43].OUTPUTSELECT
+b[2] => tmp[2][42].OUTPUTSELECT
+b[2] => tmp[2][41].OUTPUTSELECT
+b[2] => tmp[2][40].OUTPUTSELECT
+b[2] => tmp[2][39].OUTPUTSELECT
+b[2] => tmp[2][38].OUTPUTSELECT
+b[2] => tmp[2][37].OUTPUTSELECT
+b[2] => tmp[2][36].OUTPUTSELECT
+b[2] => tmp[2][35].OUTPUTSELECT
+b[2] => tmp[2][34].OUTPUTSELECT
+b[2] => tmp[2][33].OUTPUTSELECT
+b[2] => tmp[2][32].OUTPUTSELECT
+b[2] => tmp[2][31].OUTPUTSELECT
+b[2] => tmp[2][30].OUTPUTSELECT
+b[2] => tmp[2][29].OUTPUTSELECT
+b[2] => tmp[2][28].OUTPUTSELECT
+b[2] => tmp[2][27].OUTPUTSELECT
+b[2] => tmp[2][26].OUTPUTSELECT
+b[2] => tmp[2][25].OUTPUTSELECT
+b[2] => tmp[2][24].OUTPUTSELECT
+b[2] => tmp[2][23].OUTPUTSELECT
+b[2] => tmp[2][22].OUTPUTSELECT
+b[2] => tmp[2][21].OUTPUTSELECT
+b[2] => tmp[2][20].OUTPUTSELECT
+b[2] => tmp[2][19].OUTPUTSELECT
+b[2] => tmp[2][18].OUTPUTSELECT
+b[2] => tmp[2][17].OUTPUTSELECT
+b[2] => tmp[2][16].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[17] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[18] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[19] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[20] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[21] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[22] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[23] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[24] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[25] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[26] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[27] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[28] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[29] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[30] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[31] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[32] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[33] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[34] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[35] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[36] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[37] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[38] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[39] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[40] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[41] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[42] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[43] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[44] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[45] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[46] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[47] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[48] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[49] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[50] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_N:uut_add_ulp
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= add_N_in:a1.port2
+c[1] <= add_N_in:a1.port2
+c[2] <= add_N_in:a1.port2
+c[3] <= add_N_in:a1.port2
+c[4] <= add_N_in:a1.port2
+c[5] <= add_N_in:a1.port2
+c[6] <= add_N_in:a1.port2
+c[7] <= add_N_in:a1.port2
+c[8] <= add_N_in:a1.port2
+c[9] <= add_N_in:a1.port2
+c[10] <= add_N_in:a1.port2
+c[11] <= add_N_in:a1.port2
+c[12] <= add_N_in:a1.port2
+c[13] <= add_N_in:a1.port2
+c[14] <= add_N_in:a1.port2
+c[15] <= add_N_in:a1.port2
+c[16] <= add_N_in:a1.port2
+
+
+|posit_add|add_N:uut_add_ulp|add_N_in:a1
+a[0] => Add0.IN17
+a[1] => Add0.IN16
+a[2] => Add0.IN15
+a[3] => Add0.IN14
+a[4] => Add0.IN13
+a[5] => Add0.IN12
+a[6] => Add0.IN11
+a[7] => Add0.IN10
+a[8] => Add0.IN9
+a[9] => Add0.IN8
+a[10] => Add0.IN7
+a[11] => Add0.IN6
+a[12] => Add0.IN5
+a[13] => Add0.IN4
+a[14] => Add0.IN3
+a[15] => Add0.IN2
+a[16] => Add0.IN1
+b[0] => Add0.IN34
+b[1] => Add0.IN33
+b[2] => Add0.IN32
+b[3] => Add0.IN31
+b[4] => Add0.IN30
+b[5] => Add0.IN29
+b[6] => Add0.IN28
+b[7] => Add0.IN27
+b[8] => Add0.IN26
+b[9] => Add0.IN25
+b[10] => Add0.IN24
+b[11] => Add0.IN23
+b[12] => Add0.IN22
+b[13] => Add0.IN21
+b[14] => Add0.IN20
+b[15] => Add0.IN19
+b[16] => Add0.IN18
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Reference Code/add/db/Posit_Adder.hif b/Reference Code/add/db/Posit_Adder.hif
new file mode 100644
index 0000000000000000000000000000000000000000..c5e9f5ba63128e99052d0c0fe95261e911935c71
Binary files /dev/null and b/Reference Code/add/db/Posit_Adder.hif differ
diff --git a/Reference Code/add/db/Posit_Adder.lpc.html b/Reference Code/add/db/Posit_Adder.lpc.html
new file mode 100644
index 0000000000000000000000000000000000000000..4d4ddb8de6cf06813aa7f38f559de2f06340a544
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.lpc.html	
@@ -0,0 +1,1154 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >uut_add_ulp|a1</TD>
+<TD >34</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >17</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_ulp</TD>
+<TD >32</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >15</TD>
+<TD >17</TD>
+<TD >15</TD>
+<TD >15</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dsr2</TD>
+<TD >55</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >51</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_reg_ro|uut_conv_2c1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_reg_ro</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_mantovf</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sub3|s1</TD>
+<TD >16</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >8</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sub3</TD>
+<TD >14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >8</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dsl1</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >3</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2</TD>
+<TD >16</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_sub_N|s11|s1</TD>
+<TD >34</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >17</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_sub_N|s11</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_sub_N|a11|a1</TD>
+<TD >34</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >17</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_sub_N|a11</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_sub_N</TD>
+<TD >33</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >17</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dsr1</TD>
+<TD >20</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >16</TD>
+<TD >1</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_ediff|s1</TD>
+<TD >16</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >8</TD>
+<TD >2</TD>
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+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_ediff</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_abs_regime2</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+</TR>
+<TR >
+<TD >uut_abs_regime1</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
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+</TR>
+<TR >
+<TD >uut_de2|ls</TD>
+<TD >20</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >16</TD>
+<TD >2</TD>
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+<TD >0</TD>
+</TR>
+<TR >
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+<TD >2</TD>
+<TD >0</TD>
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+</TR>
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+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|h|h</TD>
+<TD >4</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|h|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|h|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|h|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|h</TD>
+<TD >8</TD>
+<TD >0</TD>
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+</TR>
+<TR >
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+<TD >2</TD>
+<TD >0</TD>
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+<TR >
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+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|l|h</TD>
+<TD >4</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
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+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|l|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|l|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1|l</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k|l1</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2|xinst_k</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de2</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|ls</TD>
+<TD >20</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >16</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|h</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1|l</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k|l1</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1|xinst_k</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_de1</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/Reference Code/add/db/Posit_Adder.lpc.rdb b/Reference Code/add/db/Posit_Adder.lpc.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..a9c5e73edfb8d35952342dc1661cf9aaa8a029cf
Binary files /dev/null and b/Reference Code/add/db/Posit_Adder.lpc.rdb differ
diff --git a/Reference Code/add/db/Posit_Adder.lpc.txt b/Reference Code/add/db/Posit_Adder.lpc.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9cb1b9834086bfe9ecf4fef655a262ba4fdee3b2
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.lpc.txt	
@@ -0,0 +1,77 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                    ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; uut_add_ulp|a1           ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_ulp              ; 32    ; 15             ; 0            ; 15             ; 17     ; 15              ; 15            ; 15              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsr2                     ; 55    ; 17             ; 0            ; 17             ; 51     ; 17              ; 17            ; 17              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_reg_ro|uut_conv_2c1  ; 7     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_reg_ro               ; 7     ; 0              ; 0            ; 0              ; 6      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_mantovf          ; 9     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; sub3|s1                  ; 16    ; 2              ; 0            ; 2              ; 8      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; sub3                     ; 14    ; 3              ; 0            ; 3              ; 8      ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsl1                     ; 20    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h                  ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l                  ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1                    ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2                       ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|s11|s1     ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|s11        ; 32    ; 0              ; 0            ; 0              ; 17     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|a11|a1     ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|a11        ; 32    ; 0              ; 0            ; 0              ; 17     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N            ; 33    ; 1              ; 0            ; 1              ; 17     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsr1                     ; 20    ; 1              ; 0            ; 1              ; 16     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_ediff|s1             ; 16    ; 2              ; 0            ; 2              ; 8      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_ediff                ; 14    ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_abs_regime2          ; 5     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_abs_regime1          ; 5     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|ls               ; 20    ; 2              ; 0            ; 2              ; 16     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1       ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k          ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2                  ; 16    ; 0              ; 1            ; 0              ; 21     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|ls               ; 20    ; 2              ; 0            ; 2              ; 16     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1       ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k          ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1                  ; 16    ; 0              ; 1            ; 0              ; 21     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Reference Code/add/db/Posit_Adder.map.ammdb b/Reference Code/add/db/Posit_Adder.map.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..abcb3fcadbb7dc2eda53aadaab31a267a693fbe4
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diff --git a/Reference Code/add/db/Posit_Adder.map.bpm b/Reference Code/add/db/Posit_Adder.map.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..75d99048b168abad9cd66f860c8795fd441c714a
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diff --git a/Reference Code/add/db/Posit_Adder.map.cdb b/Reference Code/add/db/Posit_Adder.map.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..2cf8cc23d61fcbf56cea52b2098da55a08484b7e
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diff --git a/Reference Code/add/db/Posit_Adder.map.hdb b/Reference Code/add/db/Posit_Adder.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..5cb81866d82f184b0a05fb60130ef8745c924ce0
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diff --git a/Reference Code/add/db/Posit_Adder.map.kpt b/Reference Code/add/db/Posit_Adder.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..2e31b791873b0b84d263238181519bea624df5ef
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diff --git a/Reference Code/add/db/Posit_Adder.map.logdb b/Reference Code/add/db/Posit_Adder.map.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.map.logdb	
@@ -0,0 +1 @@
+v1
diff --git a/Reference Code/add/db/Posit_Adder.map.qmsg b/Reference Code/add/db/Posit_Adder.map.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..cdb2cca5348cf86542a202707254452658ffe1f3
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.map.qmsg	
@@ -0,0 +1,33 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676998740764 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676998740764 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 21 16:59:00 2023 " "Processing started: Tue Feb 21 16:59:00 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676998740764 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998740764 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998740765 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676998741858 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676998741858 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_add.v 15 15 " "Found 15 design units, including 15 entities, in source file posit_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 posit_add " "Found entity 1: posit_add" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "2 data_extract_v1 " "Found entity 2: data_extract_v1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 155 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "3 sub_N " "Found entity 3: sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "4 add_N " "Found entity 4: add_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 204 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "5 sub_N_in " "Found entity 5: sub_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 214 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "6 add_N_in " "Found entity 6: add_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 222 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "7 add_sub_N " "Found entity 7: add_sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 230 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "8 add_1 " "Found entity 8: add_1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 243 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "9 abs_regime " "Found entity 9: abs_regime" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 252 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "10 conv_2c " "Found entity 10: conv_2c" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 262 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "11 reg_exp_op " "Found entity 11: reg_exp_op" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "12 DSR_left_N_S " "Found entity 12: DSR_left_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 285 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "13 DSR_right_N_S " "Found entity 13: DSR_right_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 306 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "14 LOD_N " "Found entity 14: LOD_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 327 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""} { "Info" "ISGN_ENTITY_NAME" "15 LOD " "Found entity 15: LOD" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 348 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676998749015 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998749015 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "posit_add " "Elaborating entity \"posit_add\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676998749051 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_extract_v1 data_extract_v1:uut_de1 " "Elaborating entity \"data_extract_v1\" for hierarchy \"data_extract_v1:uut_de1\"" {  } { { "posit_add.v" "uut_de1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749096 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(183) " "Verilog HDL assignment warning at posit_add.v(183): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676998749099 "|posit_add|data_extract_v1:uut_de1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD_N data_extract_v1:uut_de1\|LOD_N:xinst_k " "Elaborating entity \"LOD_N\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\"" {  } { { "posit_add.v" "xinst_k" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749106 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1 " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\"" {  } { { "posit_add.v" "l1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 344 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749113 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749119 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749128 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749135 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_left_N_S data_extract_v1:uut_de1\|DSR_left_N_S:ls " "Elaborating entity \"DSR_left_N_S\" for hierarchy \"data_extract_v1:uut_de1\|DSR_left_N_S:ls\"" {  } { { "posit_add.v" "ls" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 186 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749151 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "abs_regime abs_regime:uut_abs_regime1 " "Elaborating entity \"abs_regime\" for hierarchy \"abs_regime:uut_abs_regime1\"" {  } { { "posit_add.v" "uut_abs_regime1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749165 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N sub_N:uut_ediff " "Elaborating entity \"sub_N\" for hierarchy \"sub_N:uut_ediff\"" {  } { { "posit_add.v" "uut_ediff" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749171 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in sub_N:uut_ediff\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"sub_N:uut_ediff\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749177 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr1 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr1\"" {  } { { "posit_add.v" "dsr1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749183 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_N add_sub_N:uut_add_sub_N " "Elaborating entity \"add_sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\"" {  } { { "posit_add.v" "uut_add_sub_N" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 98 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749191 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N add_sub_N:uut_add_sub_N\|add_N:a11 " "Elaborating entity \"add_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\"" {  } { { "posit_add.v" "a11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749197 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N_in add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1 " "Elaborating entity \"add_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1\"" {  } { { "posit_add.v" "a1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749204 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N add_sub_N:uut_add_sub_N\|sub_N:s11 " "Elaborating entity \"sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\"" {  } { { "posit_add.v" "s11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 238 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749209 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749216 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_1 add_1:uut_add_mantovf " "Elaborating entity \"add_1\" for hierarchy \"add_1:uut_add_mantovf\"" {  } { { "posit_add.v" "uut_add_mantovf" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749228 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_exp_op reg_exp_op:uut_reg_ro " "Elaborating entity \"reg_exp_op\" for hierarchy \"reg_exp_op:uut_reg_ro\"" {  } { { "posit_add.v" "uut_reg_ro" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 119 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749233 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(281) " "Verilog HDL assignment warning at posit_add.v(281): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 281 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676998749234 "|posit_add|reg_exp_op:uut_reg_ro"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conv_2c reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1 " "Elaborating entity \"conv_2c\" for hierarchy \"reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1\"" {  } { { "posit_add.v" "uut_conv_2c1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 279 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749240 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr2 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr2\"" {  } { { "posit_add.v" "dsr2" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998749246 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676998750379 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676998751410 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676998751410 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "557 " "Implemented 557 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676998751577 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676998751577 ""} { "Info" "ICUT_CUT_TM_LCELLS" "505 " "Implemented 505 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676998751577 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676998751577 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676998751598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 21 16:59:11 2023 " "Processing ended: Tue Feb 21 16:59:11 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676998751598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676998751598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676998751598 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998751598 ""}
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index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
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+++ b/Reference Code/add/db/Posit_Adder.map_bb.logdb	
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diff --git a/Reference Code/add/db/Posit_Adder.smart_action.txt b/Reference Code/add/db/Posit_Adder.smart_action.txt
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index 0000000000000000000000000000000000000000..e04bbcfecfa47784a5fc67ffb30a5d652da87a98
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.smart_action.txt	
@@ -0,0 +1 @@
+FIT
diff --git a/Reference Code/add/db/Posit_Adder.tis_db_list.ddb b/Reference Code/add/db/Posit_Adder.tis_db_list.ddb
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index 0000000000000000000000000000000000000000..33470436f4bdbdbdc9ee0f97f2abed1c384644ed
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder.tmw_info	
@@ -0,0 +1,2 @@
+start_analysis_synthesis:s:00:00:14
+start_analysis_elaboration:s
diff --git a/Reference Code/add/db/Posit_Adder_partition_pins.json b/Reference Code/add/db/Posit_Adder_partition_pins.json
new file mode 100644
index 0000000000000000000000000000000000000000..270efaf663cc8c9a4b70371bf7010349ff783f37
--- /dev/null
+++ b/Reference Code/add/db/Posit_Adder_partition_pins.json	
@@ -0,0 +1,217 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "out[0]",
+					"strict" : false
+				},
+				{
+					"name" : "out[1]",
+					"strict" : false
+				},
+				{
+					"name" : "out[2]",
+					"strict" : false
+				},
+				{
+					"name" : "out[3]",
+					"strict" : false
+				},
+				{
+					"name" : "out[4]",
+					"strict" : false
+				},
+				{
+					"name" : "out[5]",
+					"strict" : false
+				},
+				{
+					"name" : "out[6]",
+					"strict" : false
+				},
+				{
+					"name" : "out[7]",
+					"strict" : false
+				},
+				{
+					"name" : "out[8]",
+					"strict" : false
+				},
+				{
+					"name" : "out[9]",
+					"strict" : false
+				},
+				{
+					"name" : "out[10]",
+					"strict" : false
+				},
+				{
+					"name" : "out[11]",
+					"strict" : false
+				},
+				{
+					"name" : "out[12]",
+					"strict" : false
+				},
+				{
+					"name" : "out[13]",
+					"strict" : false
+				},
+				{
+					"name" : "out[14]",
+					"strict" : false
+				},
+				{
+					"name" : "out[15]",
+					"strict" : false
+				},
+				{
+					"name" : "inf",
+					"strict" : false
+				},
+				{
+					"name" : "zero",
+					"strict" : false
+				},
+				{
+					"name" : "done",
+					"strict" : false
+				},
+				{
+					"name" : "in1[15]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[12]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[13]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[14]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[10]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[11]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[7]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[8]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[9]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[15]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[12]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[13]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[14]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[10]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[11]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[7]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[8]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[9]",
+					"strict" : false
+				},
+				{
+					"name" : "start",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
\ No newline at end of file
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index 0000000000000000000000000000000000000000..8c32a1de67a42feed60fb5153afc136715ba12d5
Binary files /dev/null and b/Reference Code/add/db/posit-add.(3).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(4).cnf.cdb b/Reference Code/add/db/posit-add.(4).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..e0b26e8763f2968dba18fa70d7e6a17ca8d29040
Binary files /dev/null and b/Reference Code/add/db/posit-add.(4).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(4).cnf.hdb b/Reference Code/add/db/posit-add.(4).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..5e6f7fa1f2ce868d0869bbefe7ef59251ca3e26f
Binary files /dev/null and b/Reference Code/add/db/posit-add.(4).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(5).cnf.cdb b/Reference Code/add/db/posit-add.(5).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..5684b23f189283bd3e0fedd030dce7766293a6f8
Binary files /dev/null and b/Reference Code/add/db/posit-add.(5).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(5).cnf.hdb b/Reference Code/add/db/posit-add.(5).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..bf3203a41420fce03c39a136601f250b934169a8
Binary files /dev/null and b/Reference Code/add/db/posit-add.(5).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(6).cnf.cdb b/Reference Code/add/db/posit-add.(6).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..470810c622d9594c95cf31287f32b5e11c7d78d9
Binary files /dev/null and b/Reference Code/add/db/posit-add.(6).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(6).cnf.hdb b/Reference Code/add/db/posit-add.(6).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..49220a2ca231feaf40a76545288dab2c66ef8d4a
Binary files /dev/null and b/Reference Code/add/db/posit-add.(6).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(7).cnf.cdb b/Reference Code/add/db/posit-add.(7).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..61c1478f8f7f5f96b4a362141a0098e47c3d4e56
Binary files /dev/null and b/Reference Code/add/db/posit-add.(7).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(7).cnf.hdb b/Reference Code/add/db/posit-add.(7).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..00bd3768af11d1f7c025c14f99cf98d66223c0d4
Binary files /dev/null and b/Reference Code/add/db/posit-add.(7).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(8).cnf.cdb b/Reference Code/add/db/posit-add.(8).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..240ff248a8274996e33a02835f0355f2e6a862dd
Binary files /dev/null and b/Reference Code/add/db/posit-add.(8).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(8).cnf.hdb b/Reference Code/add/db/posit-add.(8).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..a1ef53b3749cd5ceee4b2dc90249dee963110ffa
Binary files /dev/null and b/Reference Code/add/db/posit-add.(8).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.(9).cnf.cdb b/Reference Code/add/db/posit-add.(9).cnf.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..a1dbb9848e0f7b5e72c8c3be50a058c0d50d0b4e
Binary files /dev/null and b/Reference Code/add/db/posit-add.(9).cnf.cdb differ
diff --git a/Reference Code/add/db/posit-add.(9).cnf.hdb b/Reference Code/add/db/posit-add.(9).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..f1a94810f9130d7c25f6b5eba70b559881d0057c
Binary files /dev/null and b/Reference Code/add/db/posit-add.(9).cnf.hdb differ
diff --git a/Reference Code/add/db/posit-add.asm.qmsg b/Reference Code/add/db/posit-add.asm.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..7ae1b11f18d85bf678d714a0a72958f1affdab94
--- /dev/null
+++ b/Reference Code/add/db/posit-add.asm.qmsg	
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676405433068 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676405433069 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 20:10:32 2023 " "Processing started: Tue Feb 14 20:10:32 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676405433069 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1676405433069 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off posit-add -c posit-add " "Command: quartus_asm --read_settings_files=off --write_settings_files=off posit-add -c posit-add" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1676405433069 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1676405433839 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1676405437891 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4881 " "Peak virtual memory: 4881 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405438270 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:10:38 2023 " "Processing ended: Tue Feb 14 20:10:38 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405438270 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405438270 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405438270 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1676405438270 ""}
diff --git a/Reference Code/add/db/posit-add.asm.rdb b/Reference Code/add/db/posit-add.asm.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..17dfffe68c29132e82ed5a11ebeb64e9c3bd71f1
Binary files /dev/null and b/Reference Code/add/db/posit-add.asm.rdb differ
diff --git a/Reference Code/add/db/posit-add.cbx.xml b/Reference Code/add/db/posit-add.cbx.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e7737cdc25ee3044d247a27f4818b91afccada1b
--- /dev/null
+++ b/Reference Code/add/db/posit-add.cbx.xml	
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="posit-add">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Reference Code/add/db/posit-add.cmp.bpm b/Reference Code/add/db/posit-add.cmp.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..9607352b10dad5a3cd1f9e58bea73aa1f2a00b39
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp.bpm differ
diff --git a/Reference Code/add/db/posit-add.cmp.cdb b/Reference Code/add/db/posit-add.cmp.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..29be0c48a9b12c7eba00c30c61a733a1fe965a6b
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp.cdb differ
diff --git a/Reference Code/add/db/posit-add.cmp.hdb b/Reference Code/add/db/posit-add.cmp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..e545feacb02224f48e0069933c97e76393ca565e
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp.hdb differ
diff --git a/Reference Code/add/db/posit-add.cmp.idb b/Reference Code/add/db/posit-add.cmp.idb
new file mode 100644
index 0000000000000000000000000000000000000000..45e5de6d80eb20533b100db12f17086e1c95158b
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp.idb differ
diff --git a/Reference Code/add/db/posit-add.cmp.logdb b/Reference Code/add/db/posit-add.cmp.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..ebca17ea5d911a638299ec675d99ec141680dd8c
--- /dev/null
+++ b/Reference Code/add/db/posit-add.cmp.logdb	
@@ -0,0 +1,92 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;52;0;0;52;52;0;19;0;0;0;0;19;0;0;0;0;19;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,52;52;52;52;52;0;52;52;0;0;52;33;52;52;52;52;33;52;52;52;52;33;52;52;52;52;52;52,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,out[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,inf,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,zero,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,done,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in2[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,start,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/Reference Code/add/db/posit-add.cmp.rdb b/Reference Code/add/db/posit-add.cmp.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..bbba38f880186686ac3da7124d9e4a19478cfca1
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp.rdb differ
diff --git a/Reference Code/add/db/posit-add.cmp_merge.kpt b/Reference Code/add/db/posit-add.cmp_merge.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..705aa6a5a53745fe2c3caa1e04c657619bc6a4cd
Binary files /dev/null and b/Reference Code/add/db/posit-add.cmp_merge.kpt differ
diff --git a/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..e0d06c5b2ad7415a435efa5bcb59e2f358e3bd53
Binary files /dev/null and b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_0c_fast.hsd differ
diff --git a/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..3651200a0bf065de37c8578bdb32954144c933d1
Binary files /dev/null and b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.ff_85c_fast.hsd differ
diff --git a/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_0c_slow.hsd b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..6ff63fe34500be6b7f11c866a65d5a8b1abbe12e
Binary files /dev/null and b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_0c_slow.hsd differ
diff --git a/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_85c_slow.hsd b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100644
index 0000000000000000000000000000000000000000..d3df58bc8c9a04b26dfefc7ae758dcf011076d96
Binary files /dev/null and b/Reference Code/add/db/posit-add.cyclonev_io_sim_cache.tt_85c_slow.hsd differ
diff --git a/Reference Code/add/db/posit-add.db_info b/Reference Code/add/db/posit-add.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..32e7f323ce0c7eb84a9a6ae36cbf3afc8181aa35
--- /dev/null
+++ b/Reference Code/add/db/posit-add.db_info	
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 14 20:05:44 2023
diff --git a/Reference Code/add/db/posit-add.eda.qmsg b/Reference Code/add/db/posit-add.eda.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..dda2a6a668dd0f3b2a95fd66da78fcf490300071
--- /dev/null
+++ b/Reference Code/add/db/posit-add.eda.qmsg	
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676405445099 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676405445099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 20:10:45 2023 " "Processing started: Tue Feb 14 20:10:45 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676405445099 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676405445099 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off posit-add -c posit-add " "Command: quartus_eda --read_settings_files=off --write_settings_files=off posit-add -c posit-add" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676405445099 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1676405446105 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "posit-add.vo H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/simulation/questa/ simulation " "Generated file posit-add.vo in folder \"H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1676405446212 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4733 " "Peak virtual memory: 4733 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405446254 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:10:46 2023 " "Processing ended: Tue Feb 14 20:10:46 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405446254 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405446254 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405446254 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1676405446254 ""}
diff --git a/Reference Code/add/db/posit-add.fit.qmsg b/Reference Code/add/db/posit-add.fit.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..7c7da85f540492f17598c23a048169010ac5e7b3
--- /dev/null
+++ b/Reference Code/add/db/posit-add.fit.qmsg	
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1676405375194 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1676405375195 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "posit-add 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"posit-add\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1676405375205 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676405375243 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1676405375243 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1676405375571 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1676405375600 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1676405375821 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "52 52 " "No exact pin location assignment(s) for 52 pins of 52 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1676405376046 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1676405383825 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405383940 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1676405383944 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676405383944 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1676405383945 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1676405383945 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405383968 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "posit-add.sdc " "Synopsys Design Constraints File file not found: 'posit-add.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1676405388453 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1676405388454 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1676405388454 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1676405388457 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1676405388460 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1676405388461 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1676405388461 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1676405388474 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1676405388553 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:19 " "Fitter placement preparation operations ending: elapsed time is 00:00:19" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405407806 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1676405421283 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1676405421753 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405421753 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1676405422689 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X45_Y0 X55_Y10 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X45_Y0 to location X55_Y10" {  } { { "loc" "" { Generic "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X45_Y0 to location X55_Y10"} { { 12 { 0 ""} 45 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1676405426052 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1676405426052 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1676405426373 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1676405426373 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1676405426373 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405426377 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1676405428254 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676405428288 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676405428637 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1676405428637 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1676405428987 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1676405431174 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.fit.smsg " "Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1676405431505 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6740 " "Peak virtual memory: 6740 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405431980 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:10:31 2023 " "Processing ended: Tue Feb 14 20:10:31 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405431980 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:57 " "Elapsed time: 00:00:57" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405431980 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:57 " "Total CPU time (on all processors): 00:00:57" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405431980 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1676405431980 ""}
diff --git a/Reference Code/add/db/posit-add.hier_info b/Reference Code/add/db/posit-add.hier_info
new file mode 100644
index 0000000000000000000000000000000000000000..cb8c304ab50a09375c58f10f64238b4829574510
--- /dev/null
+++ b/Reference Code/add/db/posit-add.hier_info	
@@ -0,0 +1,2218 @@
+|posit_add
+in1[0] => WideOr0.IN0
+in1[0] => comb.DATAA
+in1[0] => Add0.IN17
+in1[1] => WideOr0.IN1
+in1[1] => comb.DATAA
+in1[1] => Add0.IN16
+in1[2] => WideOr0.IN2
+in1[2] => comb.DATAA
+in1[2] => Add0.IN15
+in1[3] => WideOr0.IN3
+in1[3] => comb.DATAA
+in1[3] => Add0.IN14
+in1[4] => WideOr0.IN4
+in1[4] => comb.DATAA
+in1[4] => Add0.IN13
+in1[5] => WideOr0.IN5
+in1[5] => comb.DATAA
+in1[5] => Add0.IN12
+in1[6] => WideOr0.IN6
+in1[6] => comb.DATAA
+in1[6] => Add0.IN11
+in1[7] => WideOr0.IN7
+in1[7] => comb.DATAA
+in1[7] => Add0.IN10
+in1[8] => WideOr0.IN8
+in1[8] => comb.DATAA
+in1[8] => Add0.IN9
+in1[9] => WideOr0.IN9
+in1[9] => comb.DATAA
+in1[9] => Add0.IN8
+in1[10] => WideOr0.IN10
+in1[10] => comb.DATAA
+in1[10] => Add0.IN7
+in1[11] => WideOr0.IN11
+in1[11] => comb.DATAA
+in1[11] => Add0.IN6
+in1[12] => WideOr0.IN12
+in1[12] => comb.DATAA
+in1[12] => Add0.IN5
+in1[13] => WideOr0.IN13
+in1[13] => comb.DATAA
+in1[13] => Add0.IN4
+in1[14] => WideOr0.IN14
+in1[14] => comb.DATAA
+in1[14] => Add0.IN3
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => comb.OUTPUTSELECT
+in1[15] => ls.DATAB
+in1[15] => comb.IN0
+in1[15] => inf1.IN1
+in1[15] => comb.IN1
+in1[15] => Add0.IN2
+in2[0] => WideOr1.IN0
+in2[0] => comb.DATAA
+in2[0] => Add1.IN17
+in2[1] => WideOr1.IN1
+in2[1] => comb.DATAA
+in2[1] => Add1.IN16
+in2[2] => WideOr1.IN2
+in2[2] => comb.DATAA
+in2[2] => Add1.IN15
+in2[3] => WideOr1.IN3
+in2[3] => comb.DATAA
+in2[3] => Add1.IN14
+in2[4] => WideOr1.IN4
+in2[4] => comb.DATAA
+in2[4] => Add1.IN13
+in2[5] => WideOr1.IN5
+in2[5] => comb.DATAA
+in2[5] => Add1.IN12
+in2[6] => WideOr1.IN6
+in2[6] => comb.DATAA
+in2[6] => Add1.IN11
+in2[7] => WideOr1.IN7
+in2[7] => comb.DATAA
+in2[7] => Add1.IN10
+in2[8] => WideOr1.IN8
+in2[8] => comb.DATAA
+in2[8] => Add1.IN9
+in2[9] => WideOr1.IN9
+in2[9] => comb.DATAA
+in2[9] => Add1.IN8
+in2[10] => WideOr1.IN10
+in2[10] => comb.DATAA
+in2[10] => Add1.IN7
+in2[11] => WideOr1.IN11
+in2[11] => comb.DATAA
+in2[11] => Add1.IN6
+in2[12] => WideOr1.IN12
+in2[12] => comb.DATAA
+in2[12] => Add1.IN5
+in2[13] => WideOr1.IN13
+in2[13] => comb.DATAA
+in2[13] => Add1.IN4
+in2[14] => WideOr1.IN14
+in2[14] => comb.DATAA
+in2[14] => Add1.IN3
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => comb.OUTPUTSELECT
+in2[15] => ls.DATAA
+in2[15] => comb.IN1
+in2[15] => inf2.IN1
+in2[15] => comb.IN1
+in2[15] => Add1.IN2
+start => done.DATAIN
+out[0] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[4] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[5] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[6] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[7] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[8] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[9] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[10] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[11] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[12] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[13] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[14] << out.DB_MAX_OUTPUT_PORT_TYPE
+out[15] << out.DB_MAX_OUTPUT_PORT_TYPE
+inf << inf.DB_MAX_OUTPUT_PORT_TYPE
+zero << zero.DB_MAX_OUTPUT_PORT_TYPE
+done << start.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1
+in[0] => xin[0].IN1
+in[1] => xin[1].IN1
+in[2] => xin[2].IN1
+in[3] => xin[3].IN1
+in[4] => xin[4].IN1
+in[5] => xin[5].IN1
+in[6] => xin[6].IN1
+in[7] => xin[7].IN1
+in[8] => xin[8].IN1
+in[9] => xin[9].IN1
+in[10] => xin[10].IN1
+in[11] => xin[11].IN1
+in[12] => xin[12].IN1
+in[13] => xin[13].IN1
+in[14] => rc.IN1
+in[15] => ~NO_FANOUT~
+rc <= rc.DB_MAX_OUTPUT_PORT_TYPE
+regime[0] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[1] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[2] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[3] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+exp[0] <= DSR_left_N_S:ls.c
+exp[1] <= DSR_left_N_S:ls.c
+mant[0] <= DSR_left_N_S:ls.c
+mant[1] <= DSR_left_N_S:ls.c
+mant[2] <= DSR_left_N_S:ls.c
+mant[3] <= DSR_left_N_S:ls.c
+mant[4] <= DSR_left_N_S:ls.c
+mant[5] <= DSR_left_N_S:ls.c
+mant[6] <= DSR_left_N_S:ls.c
+mant[7] <= DSR_left_N_S:ls.c
+mant[8] <= DSR_left_N_S:ls.c
+mant[9] <= DSR_left_N_S:ls.c
+mant[10] <= DSR_left_N_S:ls.c
+mant[11] <= DSR_left_N_S:ls.c
+mant[12] <= DSR_left_N_S:ls.c
+mant[13] <= DSR_left_N_S:ls.c
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2
+in[0] => xin[0].IN1
+in[1] => xin[1].IN1
+in[2] => xin[2].IN1
+in[3] => xin[3].IN1
+in[4] => xin[4].IN1
+in[5] => xin[5].IN1
+in[6] => xin[6].IN1
+in[7] => xin[7].IN1
+in[8] => xin[8].IN1
+in[9] => xin[9].IN1
+in[10] => xin[10].IN1
+in[11] => xin[11].IN1
+in[12] => xin[12].IN1
+in[13] => xin[13].IN1
+in[14] => rc.IN1
+in[15] => ~NO_FANOUT~
+rc <= rc.DB_MAX_OUTPUT_PORT_TYPE
+regime[0] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[1] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[2] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+regime[3] <= regime.DB_MAX_OUTPUT_PORT_TYPE
+exp[0] <= DSR_left_N_S:ls.c
+exp[1] <= DSR_left_N_S:ls.c
+mant[0] <= DSR_left_N_S:ls.c
+mant[1] <= DSR_left_N_S:ls.c
+mant[2] <= DSR_left_N_S:ls.c
+mant[3] <= DSR_left_N_S:ls.c
+mant[4] <= DSR_left_N_S:ls.c
+mant[5] <= DSR_left_N_S:ls.c
+mant[6] <= DSR_left_N_S:ls.c
+mant[7] <= DSR_left_N_S:ls.c
+mant[8] <= DSR_left_N_S:ls.c
+mant[9] <= DSR_left_N_S:ls.c
+mant[10] <= DSR_left_N_S:ls.c
+mant[11] <= DSR_left_N_S:ls.c
+mant[12] <= DSR_left_N_S:ls.c
+mant[13] <= DSR_left_N_S:ls.c
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|abs_regime:uut_abs_regime1
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+regime[0] => regime_N.DATAB
+regime[0] => Add0.IN6
+regime[1] => regime_N.DATAB
+regime[1] => Add0.IN5
+regime[2] => regime_N.DATAB
+regime[2] => Add0.IN4
+regime[3] => regime_N.DATAB
+regime[3] => Add0.IN3
+regime_N[0] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[1] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[2] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[3] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[4] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|abs_regime:uut_abs_regime2
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+rc => regime_N.OUTPUTSELECT
+regime[0] => regime_N.DATAB
+regime[0] => Add0.IN6
+regime[1] => regime_N.DATAB
+regime[1] => Add0.IN5
+regime[2] => regime_N.DATAB
+regime[2] => Add0.IN4
+regime[3] => regime_N.DATAB
+regime[3] => Add0.IN3
+regime_N[0] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[1] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[2] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[3] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+regime_N[4] <= regime_N.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|sub_N:uut_ediff
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+
+
+|posit_add|sub_N:uut_ediff|sub_N_in:s1
+a[0] => Add0.IN16
+a[1] => Add0.IN15
+a[2] => Add0.IN14
+a[3] => Add0.IN13
+a[4] => Add0.IN12
+a[5] => Add0.IN11
+a[6] => Add0.IN10
+a[7] => Add0.IN9
+b[0] => Add0.IN8
+b[1] => Add0.IN7
+b[2] => Add0.IN6
+b[3] => Add0.IN5
+b[4] => Add0.IN4
+b[5] => Add0.IN3
+b[6] => Add0.IN2
+b[7] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_right_N_S:dsr1
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][1].DATAA
+a[1] => tmp[0][0].DATAB
+a[2] => tmp[0][2].DATAA
+a[2] => tmp[0][1].DATAB
+a[3] => tmp[0][3].DATAA
+a[3] => tmp[0][2].DATAB
+a[4] => tmp[0][4].DATAA
+a[4] => tmp[0][3].DATAB
+a[5] => tmp[0][5].DATAA
+a[5] => tmp[0][4].DATAB
+a[6] => tmp[0][6].DATAA
+a[6] => tmp[0][5].DATAB
+a[7] => tmp[0][7].DATAA
+a[7] => tmp[0][6].DATAB
+a[8] => tmp[0][8].DATAA
+a[8] => tmp[0][7].DATAB
+a[9] => tmp[0][9].DATAA
+a[9] => tmp[0][8].DATAB
+a[10] => tmp[0][10].DATAA
+a[10] => tmp[0][9].DATAB
+a[11] => tmp[0][11].DATAA
+a[11] => tmp[0][10].DATAB
+a[12] => tmp[0][12].DATAA
+a[12] => tmp[0][11].DATAB
+a[13] => tmp[0][13].DATAA
+a[13] => tmp[0][12].DATAB
+a[14] => tmp[0][14].DATAA
+a[14] => tmp[0][13].DATAB
+a[15] => tmp[0][15].DATAA
+a[15] => tmp[0][14].DATAB
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+op => c.OUTPUTSELECT
+a[0] => a[0].IN2
+a[1] => a[1].IN2
+a[2] => a[2].IN2
+a[3] => a[3].IN2
+a[4] => a[4].IN2
+a[5] => a[5].IN2
+a[6] => a[6].IN2
+a[7] => a[7].IN2
+a[8] => a[8].IN2
+a[9] => a[9].IN2
+a[10] => a[10].IN2
+a[11] => a[11].IN2
+a[12] => a[12].IN2
+a[13] => a[13].IN2
+a[14] => a[14].IN2
+a[15] => a[15].IN2
+b[0] => b[0].IN2
+b[1] => b[1].IN2
+b[2] => b[2].IN2
+b[3] => b[3].IN2
+b[4] => b[4].IN2
+b[5] => b[5].IN2
+b[6] => b[6].IN2
+b[7] => b[7].IN2
+b[8] => b[8].IN2
+b[9] => b[9].IN2
+b[10] => b[10].IN2
+b[11] => b[11].IN2
+b[12] => b[12].IN2
+b[13] => b[13].IN2
+b[14] => b[14].IN2
+b[15] => b[15].IN2
+c[0] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= c.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= c.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N|add_N:a11
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= add_N_in:a1.port2
+c[1] <= add_N_in:a1.port2
+c[2] <= add_N_in:a1.port2
+c[3] <= add_N_in:a1.port2
+c[4] <= add_N_in:a1.port2
+c[5] <= add_N_in:a1.port2
+c[6] <= add_N_in:a1.port2
+c[7] <= add_N_in:a1.port2
+c[8] <= add_N_in:a1.port2
+c[9] <= add_N_in:a1.port2
+c[10] <= add_N_in:a1.port2
+c[11] <= add_N_in:a1.port2
+c[12] <= add_N_in:a1.port2
+c[13] <= add_N_in:a1.port2
+c[14] <= add_N_in:a1.port2
+c[15] <= add_N_in:a1.port2
+c[16] <= add_N_in:a1.port2
+
+
+|posit_add|add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1
+a[0] => Add0.IN17
+a[1] => Add0.IN16
+a[2] => Add0.IN15
+a[3] => Add0.IN14
+a[4] => Add0.IN13
+a[5] => Add0.IN12
+a[6] => Add0.IN11
+a[7] => Add0.IN10
+a[8] => Add0.IN9
+a[9] => Add0.IN8
+a[10] => Add0.IN7
+a[11] => Add0.IN6
+a[12] => Add0.IN5
+a[13] => Add0.IN4
+a[14] => Add0.IN3
+a[15] => Add0.IN2
+a[16] => Add0.IN1
+b[0] => Add0.IN34
+b[1] => Add0.IN33
+b[2] => Add0.IN32
+b[3] => Add0.IN31
+b[4] => Add0.IN30
+b[5] => Add0.IN29
+b[6] => Add0.IN28
+b[7] => Add0.IN27
+b[8] => Add0.IN26
+b[9] => Add0.IN25
+b[10] => Add0.IN24
+b[11] => Add0.IN23
+b[12] => Add0.IN22
+b[13] => Add0.IN21
+b[14] => Add0.IN20
+b[15] => Add0.IN19
+b[16] => Add0.IN18
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_sub_N:uut_add_sub_N|sub_N:s11
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+c[8] <= sub_N_in:s1.port2
+c[9] <= sub_N_in:s1.port2
+c[10] <= sub_N_in:s1.port2
+c[11] <= sub_N_in:s1.port2
+c[12] <= sub_N_in:s1.port2
+c[13] <= sub_N_in:s1.port2
+c[14] <= sub_N_in:s1.port2
+c[15] <= sub_N_in:s1.port2
+c[16] <= sub_N_in:s1.port2
+
+
+|posit_add|add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1
+a[0] => Add0.IN34
+a[1] => Add0.IN33
+a[2] => Add0.IN32
+a[3] => Add0.IN31
+a[4] => Add0.IN30
+a[5] => Add0.IN29
+a[6] => Add0.IN28
+a[7] => Add0.IN27
+a[8] => Add0.IN26
+a[9] => Add0.IN25
+a[10] => Add0.IN24
+a[11] => Add0.IN23
+a[12] => Add0.IN22
+a[13] => Add0.IN21
+a[14] => Add0.IN20
+a[15] => Add0.IN19
+a[16] => Add0.IN18
+b[0] => Add0.IN17
+b[1] => Add0.IN16
+b[2] => Add0.IN15
+b[3] => Add0.IN14
+b[4] => Add0.IN13
+b[5] => Add0.IN12
+b[6] => Add0.IN11
+b[7] => Add0.IN10
+b[8] => Add0.IN9
+b[9] => Add0.IN8
+b[10] => Add0.IN7
+b[11] => Add0.IN6
+b[12] => Add0.IN5
+b[13] => Add0.IN4
+b[14] => Add0.IN3
+b[15] => Add0.IN2
+b[16] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= LOD:l1.port1
+out[1] <= LOD:l1.port1
+out[2] <= LOD:l1.port1
+out[3] <= LOD:l1.port1
+
+
+|posit_add|LOD_N:l2|LOD:l1
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+in[8] => in[8].IN1
+in[9] => in[9].IN1
+in[10] => in[10].IN1
+in[11] => in[11].IN1
+in[12] => in[12].IN1
+in[13] => in[13].IN1
+in[14] => in[14].IN1
+in[15] => in[15].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+in[4] => in[4].IN1
+in[5] => in[5].IN1
+in[6] => in[6].IN1
+in[7] => in[7].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h
+in[0] => in[0].IN1
+in[1] => in[1].IN1
+in[2] => in[2].IN1
+in[3] => in[3].IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= vld.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h
+in[0] => WideOr0.IN0
+in[0] => out.IN0
+in[1] => WideOr0.IN1
+in[1] => out.IN1
+out[0] <= out.DB_MAX_OUTPUT_PORT_TYPE
+vld <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_left_N_S:dsl1
+a[0] => tmp[0][1].DATAB
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][2].DATAB
+a[1] => tmp[0][1].DATAA
+a[2] => tmp[0][3].DATAB
+a[2] => tmp[0][2].DATAA
+a[3] => tmp[0][4].DATAB
+a[3] => tmp[0][3].DATAA
+a[4] => tmp[0][5].DATAB
+a[4] => tmp[0][4].DATAA
+a[5] => tmp[0][6].DATAB
+a[5] => tmp[0][5].DATAA
+a[6] => tmp[0][7].DATAB
+a[6] => tmp[0][6].DATAA
+a[7] => tmp[0][8].DATAB
+a[7] => tmp[0][7].DATAA
+a[8] => tmp[0][9].DATAB
+a[8] => tmp[0][8].DATAA
+a[9] => tmp[0][10].DATAB
+a[9] => tmp[0][9].DATAA
+a[10] => tmp[0][11].DATAB
+a[10] => tmp[0][10].DATAA
+a[11] => tmp[0][12].DATAB
+a[11] => tmp[0][11].DATAA
+a[12] => tmp[0][13].DATAB
+a[12] => tmp[0][12].DATAA
+a[13] => tmp[0][14].DATAB
+a[13] => tmp[0][13].DATAA
+a[14] => tmp[0][15].DATAB
+a[14] => tmp[0][14].DATAA
+a[15] => tmp[0][15].DATAA
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|sub_N:sub3
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+c[0] <= sub_N_in:s1.port2
+c[1] <= sub_N_in:s1.port2
+c[2] <= sub_N_in:s1.port2
+c[3] <= sub_N_in:s1.port2
+c[4] <= sub_N_in:s1.port2
+c[5] <= sub_N_in:s1.port2
+c[6] <= sub_N_in:s1.port2
+c[7] <= sub_N_in:s1.port2
+
+
+|posit_add|sub_N:sub3|sub_N_in:s1
+a[0] => Add0.IN16
+a[1] => Add0.IN15
+a[2] => Add0.IN14
+a[3] => Add0.IN13
+a[4] => Add0.IN12
+a[5] => Add0.IN11
+a[6] => Add0.IN10
+a[7] => Add0.IN9
+b[0] => Add0.IN8
+b[1] => Add0.IN7
+b[2] => Add0.IN6
+b[3] => Add0.IN5
+b[4] => Add0.IN4
+b[5] => Add0.IN3
+b[6] => Add0.IN2
+b[7] => Add0.IN1
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_1:uut_add_mantovf
+a[0] => Add0.IN15
+a[1] => Add0.IN14
+a[2] => Add0.IN13
+a[3] => Add0.IN12
+a[4] => Add0.IN11
+a[5] => Add0.IN10
+a[6] => Add0.IN9
+a[7] => Add0.IN8
+mant_ovf => Add0.IN16
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|reg_exp_op:uut_reg_ro
+exp_o[0] => exp_oN[0].DATAA
+exp_o[0] => e_o[0].DATAIN
+exp_o[0] => _.IN1
+exp_o[1] => exp_oN[1].DATAA
+exp_o[1] => e_o[1].DATAIN
+exp_o[1] => _.IN1
+exp_o[2] => exp_oN[2].DATAA
+exp_o[2] => _.IN1
+exp_o[3] => exp_oN[3].DATAA
+exp_o[3] => _.IN1
+exp_o[4] => exp_oN[4].DATAA
+exp_o[4] => _.IN1
+exp_o[5] => exp_oN[5].DATAA
+exp_o[5] => _.IN1
+exp_o[6] => exp_oN[5].OUTPUTSELECT
+exp_o[6] => exp_oN[4].OUTPUTSELECT
+exp_o[6] => exp_oN[3].OUTPUTSELECT
+exp_o[6] => exp_oN[2].OUTPUTSELECT
+exp_o[6] => exp_oN[1].OUTPUTSELECT
+exp_o[6] => exp_oN[0].OUTPUTSELECT
+exp_o[6] => _.IN1
+exp_o[6] => r_o.IN1
+e_o[0] <= exp_o[0].DB_MAX_OUTPUT_PORT_TYPE
+e_o[1] <= exp_o[1].DB_MAX_OUTPUT_PORT_TYPE
+r_o[0] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[1] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[2] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+r_o[3] <= r_o.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1
+a[0] => Add0.IN14
+a[1] => Add0.IN13
+a[2] => Add0.IN12
+a[3] => Add0.IN11
+a[4] => Add0.IN10
+a[5] => Add0.IN9
+a[6] => Add0.IN8
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|DSR_right_N_S:dsr2
+a[0] => tmp[0][0].DATAA
+a[1] => tmp[0][1].DATAA
+a[1] => tmp[0][0].DATAB
+a[2] => tmp[0][2].DATAA
+a[2] => tmp[0][1].DATAB
+a[3] => tmp[0][3].DATAA
+a[3] => tmp[0][2].DATAB
+a[4] => tmp[0][4].DATAA
+a[4] => tmp[0][3].DATAB
+a[5] => tmp[0][5].DATAA
+a[5] => tmp[0][4].DATAB
+a[6] => tmp[0][6].DATAA
+a[6] => tmp[0][5].DATAB
+a[7] => tmp[0][7].DATAA
+a[7] => tmp[0][6].DATAB
+a[8] => tmp[0][8].DATAA
+a[8] => tmp[0][7].DATAB
+a[9] => tmp[0][9].DATAA
+a[9] => tmp[0][8].DATAB
+a[10] => tmp[0][10].DATAA
+a[10] => tmp[0][9].DATAB
+a[11] => tmp[0][11].DATAA
+a[11] => tmp[0][10].DATAB
+a[12] => tmp[0][12].DATAA
+a[12] => tmp[0][11].DATAB
+a[13] => tmp[0][13].DATAA
+a[13] => tmp[0][12].DATAB
+a[14] => tmp[0][14].DATAA
+a[14] => tmp[0][13].DATAB
+a[15] => tmp[0][15].DATAA
+a[15] => tmp[0][14].DATAB
+a[16] => tmp[0][16].DATAA
+a[16] => tmp[0][15].DATAB
+a[17] => tmp[0][17].DATAA
+a[17] => tmp[0][16].DATAB
+a[18] => tmp[0][18].DATAA
+a[18] => tmp[0][17].DATAB
+a[19] => tmp[0][19].DATAA
+a[19] => tmp[0][18].DATAB
+a[20] => tmp[0][20].DATAA
+a[20] => tmp[0][19].DATAB
+a[21] => tmp[0][21].DATAA
+a[21] => tmp[0][20].DATAB
+a[22] => tmp[0][22].DATAA
+a[22] => tmp[0][21].DATAB
+a[23] => tmp[0][23].DATAA
+a[23] => tmp[0][22].DATAB
+a[24] => tmp[0][24].DATAA
+a[24] => tmp[0][23].DATAB
+a[25] => tmp[0][25].DATAA
+a[25] => tmp[0][24].DATAB
+a[26] => tmp[0][26].DATAA
+a[26] => tmp[0][25].DATAB
+a[27] => tmp[0][27].DATAA
+a[27] => tmp[0][26].DATAB
+a[28] => tmp[0][28].DATAA
+a[28] => tmp[0][27].DATAB
+a[29] => tmp[0][29].DATAA
+a[29] => tmp[0][28].DATAB
+a[30] => tmp[0][30].DATAA
+a[30] => tmp[0][29].DATAB
+a[31] => tmp[0][31].DATAA
+a[31] => tmp[0][30].DATAB
+a[32] => tmp[0][32].DATAA
+a[32] => tmp[0][31].DATAB
+a[33] => tmp[0][33].DATAA
+a[33] => tmp[0][32].DATAB
+a[34] => tmp[0][34].DATAA
+a[34] => tmp[0][33].DATAB
+a[35] => tmp[0][35].DATAA
+a[35] => tmp[0][34].DATAB
+a[36] => tmp[0][36].DATAA
+a[36] => tmp[0][35].DATAB
+a[37] => tmp[0][37].DATAA
+a[37] => tmp[0][36].DATAB
+a[38] => tmp[0][38].DATAA
+a[38] => tmp[0][37].DATAB
+a[39] => tmp[0][39].DATAA
+a[39] => tmp[0][38].DATAB
+a[40] => tmp[0][40].DATAA
+a[40] => tmp[0][39].DATAB
+a[41] => tmp[0][41].DATAA
+a[41] => tmp[0][40].DATAB
+a[42] => tmp[0][42].DATAA
+a[42] => tmp[0][41].DATAB
+a[43] => tmp[0][43].DATAA
+a[43] => tmp[0][42].DATAB
+a[44] => tmp[0][44].DATAA
+a[44] => tmp[0][43].DATAB
+a[45] => tmp[0][45].DATAA
+a[45] => tmp[0][44].DATAB
+a[46] => tmp[0][46].DATAA
+a[46] => tmp[0][45].DATAB
+a[47] => tmp[0][47].DATAA
+a[47] => tmp[0][46].DATAB
+a[48] => tmp[0][48].DATAA
+a[48] => tmp[0][47].DATAB
+a[49] => tmp[0][49].DATAA
+a[49] => tmp[0][48].DATAB
+a[50] => tmp[0][50].DATAA
+a[50] => tmp[0][49].DATAB
+b[0] => tmp[0][50].OUTPUTSELECT
+b[0] => tmp[0][49].OUTPUTSELECT
+b[0] => tmp[0][48].OUTPUTSELECT
+b[0] => tmp[0][47].OUTPUTSELECT
+b[0] => tmp[0][46].OUTPUTSELECT
+b[0] => tmp[0][45].OUTPUTSELECT
+b[0] => tmp[0][44].OUTPUTSELECT
+b[0] => tmp[0][43].OUTPUTSELECT
+b[0] => tmp[0][42].OUTPUTSELECT
+b[0] => tmp[0][41].OUTPUTSELECT
+b[0] => tmp[0][40].OUTPUTSELECT
+b[0] => tmp[0][39].OUTPUTSELECT
+b[0] => tmp[0][38].OUTPUTSELECT
+b[0] => tmp[0][37].OUTPUTSELECT
+b[0] => tmp[0][36].OUTPUTSELECT
+b[0] => tmp[0][35].OUTPUTSELECT
+b[0] => tmp[0][34].OUTPUTSELECT
+b[0] => tmp[0][33].OUTPUTSELECT
+b[0] => tmp[0][32].OUTPUTSELECT
+b[0] => tmp[0][31].OUTPUTSELECT
+b[0] => tmp[0][30].OUTPUTSELECT
+b[0] => tmp[0][29].OUTPUTSELECT
+b[0] => tmp[0][28].OUTPUTSELECT
+b[0] => tmp[0][27].OUTPUTSELECT
+b[0] => tmp[0][26].OUTPUTSELECT
+b[0] => tmp[0][25].OUTPUTSELECT
+b[0] => tmp[0][24].OUTPUTSELECT
+b[0] => tmp[0][23].OUTPUTSELECT
+b[0] => tmp[0][22].OUTPUTSELECT
+b[0] => tmp[0][21].OUTPUTSELECT
+b[0] => tmp[0][20].OUTPUTSELECT
+b[0] => tmp[0][19].OUTPUTSELECT
+b[0] => tmp[0][18].OUTPUTSELECT
+b[0] => tmp[0][17].OUTPUTSELECT
+b[0] => tmp[0][16].OUTPUTSELECT
+b[0] => tmp[0][15].OUTPUTSELECT
+b[0] => tmp[0][14].OUTPUTSELECT
+b[0] => tmp[0][13].OUTPUTSELECT
+b[0] => tmp[0][12].OUTPUTSELECT
+b[0] => tmp[0][11].OUTPUTSELECT
+b[0] => tmp[0][10].OUTPUTSELECT
+b[0] => tmp[0][9].OUTPUTSELECT
+b[0] => tmp[0][8].OUTPUTSELECT
+b[0] => tmp[0][7].OUTPUTSELECT
+b[0] => tmp[0][6].OUTPUTSELECT
+b[0] => tmp[0][5].OUTPUTSELECT
+b[0] => tmp[0][4].OUTPUTSELECT
+b[0] => tmp[0][3].OUTPUTSELECT
+b[0] => tmp[0][2].OUTPUTSELECT
+b[0] => tmp[0][1].OUTPUTSELECT
+b[0] => tmp[0][0].OUTPUTSELECT
+b[1] => tmp[1][50].OUTPUTSELECT
+b[1] => tmp[1][49].OUTPUTSELECT
+b[1] => tmp[1][48].OUTPUTSELECT
+b[1] => tmp[1][47].OUTPUTSELECT
+b[1] => tmp[1][46].OUTPUTSELECT
+b[1] => tmp[1][45].OUTPUTSELECT
+b[1] => tmp[1][44].OUTPUTSELECT
+b[1] => tmp[1][43].OUTPUTSELECT
+b[1] => tmp[1][42].OUTPUTSELECT
+b[1] => tmp[1][41].OUTPUTSELECT
+b[1] => tmp[1][40].OUTPUTSELECT
+b[1] => tmp[1][39].OUTPUTSELECT
+b[1] => tmp[1][38].OUTPUTSELECT
+b[1] => tmp[1][37].OUTPUTSELECT
+b[1] => tmp[1][36].OUTPUTSELECT
+b[1] => tmp[1][35].OUTPUTSELECT
+b[1] => tmp[1][34].OUTPUTSELECT
+b[1] => tmp[1][33].OUTPUTSELECT
+b[1] => tmp[1][32].OUTPUTSELECT
+b[1] => tmp[1][31].OUTPUTSELECT
+b[1] => tmp[1][30].OUTPUTSELECT
+b[1] => tmp[1][29].OUTPUTSELECT
+b[1] => tmp[1][28].OUTPUTSELECT
+b[1] => tmp[1][27].OUTPUTSELECT
+b[1] => tmp[1][26].OUTPUTSELECT
+b[1] => tmp[1][25].OUTPUTSELECT
+b[1] => tmp[1][24].OUTPUTSELECT
+b[1] => tmp[1][23].OUTPUTSELECT
+b[1] => tmp[1][22].OUTPUTSELECT
+b[1] => tmp[1][21].OUTPUTSELECT
+b[1] => tmp[1][20].OUTPUTSELECT
+b[1] => tmp[1][19].OUTPUTSELECT
+b[1] => tmp[1][18].OUTPUTSELECT
+b[1] => tmp[1][17].OUTPUTSELECT
+b[1] => tmp[1][16].OUTPUTSELECT
+b[1] => tmp[1][15].OUTPUTSELECT
+b[1] => tmp[1][14].OUTPUTSELECT
+b[1] => tmp[1][13].OUTPUTSELECT
+b[1] => tmp[1][12].OUTPUTSELECT
+b[1] => tmp[1][11].OUTPUTSELECT
+b[1] => tmp[1][10].OUTPUTSELECT
+b[1] => tmp[1][9].OUTPUTSELECT
+b[1] => tmp[1][8].OUTPUTSELECT
+b[1] => tmp[1][7].OUTPUTSELECT
+b[1] => tmp[1][6].OUTPUTSELECT
+b[1] => tmp[1][5].OUTPUTSELECT
+b[1] => tmp[1][4].OUTPUTSELECT
+b[1] => tmp[1][3].OUTPUTSELECT
+b[1] => tmp[1][2].OUTPUTSELECT
+b[1] => tmp[1][1].OUTPUTSELECT
+b[1] => tmp[1][0].OUTPUTSELECT
+b[2] => tmp[2][50].OUTPUTSELECT
+b[2] => tmp[2][49].OUTPUTSELECT
+b[2] => tmp[2][48].OUTPUTSELECT
+b[2] => tmp[2][47].OUTPUTSELECT
+b[2] => tmp[2][46].OUTPUTSELECT
+b[2] => tmp[2][45].OUTPUTSELECT
+b[2] => tmp[2][44].OUTPUTSELECT
+b[2] => tmp[2][43].OUTPUTSELECT
+b[2] => tmp[2][42].OUTPUTSELECT
+b[2] => tmp[2][41].OUTPUTSELECT
+b[2] => tmp[2][40].OUTPUTSELECT
+b[2] => tmp[2][39].OUTPUTSELECT
+b[2] => tmp[2][38].OUTPUTSELECT
+b[2] => tmp[2][37].OUTPUTSELECT
+b[2] => tmp[2][36].OUTPUTSELECT
+b[2] => tmp[2][35].OUTPUTSELECT
+b[2] => tmp[2][34].OUTPUTSELECT
+b[2] => tmp[2][33].OUTPUTSELECT
+b[2] => tmp[2][32].OUTPUTSELECT
+b[2] => tmp[2][31].OUTPUTSELECT
+b[2] => tmp[2][30].OUTPUTSELECT
+b[2] => tmp[2][29].OUTPUTSELECT
+b[2] => tmp[2][28].OUTPUTSELECT
+b[2] => tmp[2][27].OUTPUTSELECT
+b[2] => tmp[2][26].OUTPUTSELECT
+b[2] => tmp[2][25].OUTPUTSELECT
+b[2] => tmp[2][24].OUTPUTSELECT
+b[2] => tmp[2][23].OUTPUTSELECT
+b[2] => tmp[2][22].OUTPUTSELECT
+b[2] => tmp[2][21].OUTPUTSELECT
+b[2] => tmp[2][20].OUTPUTSELECT
+b[2] => tmp[2][19].OUTPUTSELECT
+b[2] => tmp[2][18].OUTPUTSELECT
+b[2] => tmp[2][17].OUTPUTSELECT
+b[2] => tmp[2][16].OUTPUTSELECT
+b[2] => tmp[2][15].OUTPUTSELECT
+b[2] => tmp[2][14].OUTPUTSELECT
+b[2] => tmp[2][13].OUTPUTSELECT
+b[2] => tmp[2][12].OUTPUTSELECT
+b[2] => tmp[2][11].OUTPUTSELECT
+b[2] => tmp[2][10].OUTPUTSELECT
+b[2] => tmp[2][9].OUTPUTSELECT
+b[2] => tmp[2][8].OUTPUTSELECT
+b[2] => tmp[2][7].OUTPUTSELECT
+b[2] => tmp[2][6].OUTPUTSELECT
+b[2] => tmp[2][5].OUTPUTSELECT
+b[2] => tmp[2][4].OUTPUTSELECT
+b[2] => tmp[2][3].OUTPUTSELECT
+b[2] => tmp[2][2].OUTPUTSELECT
+b[2] => tmp[2][1].OUTPUTSELECT
+b[2] => tmp[2][0].OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+b[3] => tmp.OUTPUTSELECT
+c[0] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[17] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[18] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[19] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[20] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[21] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[22] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[23] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[24] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[25] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[26] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[27] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[28] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[29] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[30] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[31] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[32] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[33] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[34] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[35] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[36] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[37] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[38] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[39] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[40] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[41] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[42] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[43] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[44] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[45] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[46] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[47] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[48] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[49] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+c[50] <= tmp.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|posit_add|add_N:uut_add_ulp
+a[0] => ain[0].IN1
+a[1] => ain[1].IN1
+a[2] => ain[2].IN1
+a[3] => ain[3].IN1
+a[4] => ain[4].IN1
+a[5] => ain[5].IN1
+a[6] => ain[6].IN1
+a[7] => ain[7].IN1
+a[8] => ain[8].IN1
+a[9] => ain[9].IN1
+a[10] => ain[10].IN1
+a[11] => ain[11].IN1
+a[12] => ain[12].IN1
+a[13] => ain[13].IN1
+a[14] => ain[14].IN1
+a[15] => ain[15].IN1
+b[0] => bin[0].IN1
+b[1] => bin[1].IN1
+b[2] => bin[2].IN1
+b[3] => bin[3].IN1
+b[4] => bin[4].IN1
+b[5] => bin[5].IN1
+b[6] => bin[6].IN1
+b[7] => bin[7].IN1
+b[8] => bin[8].IN1
+b[9] => bin[9].IN1
+b[10] => bin[10].IN1
+b[11] => bin[11].IN1
+b[12] => bin[12].IN1
+b[13] => bin[13].IN1
+b[14] => bin[14].IN1
+b[15] => bin[15].IN1
+c[0] <= add_N_in:a1.port2
+c[1] <= add_N_in:a1.port2
+c[2] <= add_N_in:a1.port2
+c[3] <= add_N_in:a1.port2
+c[4] <= add_N_in:a1.port2
+c[5] <= add_N_in:a1.port2
+c[6] <= add_N_in:a1.port2
+c[7] <= add_N_in:a1.port2
+c[8] <= add_N_in:a1.port2
+c[9] <= add_N_in:a1.port2
+c[10] <= add_N_in:a1.port2
+c[11] <= add_N_in:a1.port2
+c[12] <= add_N_in:a1.port2
+c[13] <= add_N_in:a1.port2
+c[14] <= add_N_in:a1.port2
+c[15] <= add_N_in:a1.port2
+c[16] <= add_N_in:a1.port2
+
+
+|posit_add|add_N:uut_add_ulp|add_N_in:a1
+a[0] => Add0.IN17
+a[1] => Add0.IN16
+a[2] => Add0.IN15
+a[3] => Add0.IN14
+a[4] => Add0.IN13
+a[5] => Add0.IN12
+a[6] => Add0.IN11
+a[7] => Add0.IN10
+a[8] => Add0.IN9
+a[9] => Add0.IN8
+a[10] => Add0.IN7
+a[11] => Add0.IN6
+a[12] => Add0.IN5
+a[13] => Add0.IN4
+a[14] => Add0.IN3
+a[15] => Add0.IN2
+a[16] => Add0.IN1
+b[0] => Add0.IN34
+b[1] => Add0.IN33
+b[2] => Add0.IN32
+b[3] => Add0.IN31
+b[4] => Add0.IN30
+b[5] => Add0.IN29
+b[6] => Add0.IN28
+b[7] => Add0.IN27
+b[8] => Add0.IN26
+b[9] => Add0.IN25
+b[10] => Add0.IN24
+b[11] => Add0.IN23
+b[12] => Add0.IN22
+b[13] => Add0.IN21
+b[14] => Add0.IN20
+b[15] => Add0.IN19
+b[16] => Add0.IN18
+c[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+c[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Reference Code/add/db/posit-add.hif b/Reference Code/add/db/posit-add.hif
new file mode 100644
index 0000000000000000000000000000000000000000..baab1c6cea87ec19a24eb7ea3c63c50aaa78f897
Binary files /dev/null and b/Reference Code/add/db/posit-add.hif differ
diff --git a/Reference Code/add/db/posit-add.lpc.html b/Reference Code/add/db/posit-add.lpc.html
new file mode 100644
index 0000000000000000000000000000000000000000..4d4ddb8de6cf06813aa7f38f559de2f06340a544
--- /dev/null
+++ b/Reference Code/add/db/posit-add.lpc.html	
@@ -0,0 +1,1154 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >uut_add_ulp|a1</TD>
+<TD >34</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >17</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_ulp</TD>
+<TD >32</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >15</TD>
+<TD >17</TD>
+<TD >15</TD>
+<TD >15</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dsr2</TD>
+<TD >55</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >51</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_reg_ro|uut_conv_2c1</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_reg_ro</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >uut_add_mantovf</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sub3|s1</TD>
+<TD >16</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >8</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >sub3</TD>
+<TD >14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >8</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dsl1</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|h</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|h</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l|h</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l|l</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l|l</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >l2|l1|l</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
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diff --git a/Reference Code/add/db/posit-add.lpc.rdb b/Reference Code/add/db/posit-add.lpc.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..a9c5e73edfb8d35952342dc1661cf9aaa8a029cf
Binary files /dev/null and b/Reference Code/add/db/posit-add.lpc.rdb differ
diff --git a/Reference Code/add/db/posit-add.lpc.txt b/Reference Code/add/db/posit-add.lpc.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9cb1b9834086bfe9ecf4fef655a262ba4fdee3b2
--- /dev/null
+++ b/Reference Code/add/db/posit-add.lpc.txt	
@@ -0,0 +1,77 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                    ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; uut_add_ulp|a1           ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_ulp              ; 32    ; 15             ; 0            ; 15             ; 17     ; 15              ; 15            ; 15              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsr2                     ; 55    ; 17             ; 0            ; 17             ; 51     ; 17              ; 17            ; 17              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_reg_ro|uut_conv_2c1  ; 7     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_reg_ro               ; 7     ; 0              ; 0            ; 0              ; 6      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_mantovf          ; 9     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; sub3|s1                  ; 16    ; 2              ; 0            ; 2              ; 8      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; sub3                     ; 14    ; 3              ; 0            ; 3              ; 8      ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsl1                     ; 20    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|h                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h|l                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|h                  ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|h                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l|h              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l|l              ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l|l                ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1|l                  ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2|l1                    ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; l2                       ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|s11|s1     ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|s11        ; 32    ; 0              ; 0            ; 0              ; 17     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|a11|a1     ; 34    ; 2              ; 0            ; 2              ; 17     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N|a11        ; 32    ; 0              ; 0            ; 0              ; 17     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_add_sub_N            ; 33    ; 1              ; 0            ; 1              ; 17     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dsr1                     ; 20    ; 1              ; 0            ; 1              ; 16     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_ediff|s1             ; 16    ; 2              ; 0            ; 2              ; 8      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_ediff                ; 14    ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_abs_regime2          ; 5     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_abs_regime1          ; 5     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|ls               ; 20    ; 2              ; 0            ; 2              ; 16     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|h     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1|l     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k|l1       ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2|xinst_k          ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de2                  ; 16    ; 0              ; 1            ; 0              ; 21     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|ls               ; 20    ; 2              ; 0            ; 2              ; 16     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|h     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|h   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l|h ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l|l ; 2     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l|l   ; 4     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1|l     ; 8     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k|l1       ; 16    ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1|xinst_k          ; 16    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; uut_de1                  ; 16    ; 0              ; 1            ; 0              ; 21     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Reference Code/add/db/posit-add.map.ammdb b/Reference Code/add/db/posit-add.map.ammdb
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diff --git a/Reference Code/add/db/posit-add.map.bpm b/Reference Code/add/db/posit-add.map.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..5c1bac7412d1d9e19f5fc56b6b050b3357742e2b
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diff --git a/Reference Code/add/db/posit-add.map.cdb b/Reference Code/add/db/posit-add.map.cdb
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index 0000000000000000000000000000000000000000..94290fa933541e49a517075e424f238548bf8648
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diff --git a/Reference Code/add/db/posit-add.map.hdb b/Reference Code/add/db/posit-add.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..b3d3149a7109776ad368b97f327c7e738e8ab50f
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diff --git a/Reference Code/add/db/posit-add.map.kpt b/Reference Code/add/db/posit-add.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..28d6bb62943f3ae82f3c9d8e000a135fb0d29311
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diff --git a/Reference Code/add/db/posit-add.map.logdb b/Reference Code/add/db/posit-add.map.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Reference Code/add/db/posit-add.map.logdb	
@@ -0,0 +1 @@
+v1
diff --git a/Reference Code/add/db/posit-add.map.qmsg b/Reference Code/add/db/posit-add.map.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..59411b14f7143a83414f3f6690c93e9d556331be
--- /dev/null
+++ b/Reference Code/add/db/posit-add.map.qmsg	
@@ -0,0 +1,33 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676405364035 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676405364035 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 20:09:23 2023 " "Processing started: Tue Feb 14 20:09:23 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676405364035 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405364035 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add " "Command: quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405364035 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676405364636 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676405364636 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_add.v 15 15 " "Found 15 design units, including 15 entities, in source file posit_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 posit_add " "Found entity 1: posit_add" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "2 data_extract_v1 " "Found entity 2: data_extract_v1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 155 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "3 sub_N " "Found entity 3: sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "4 add_N " "Found entity 4: add_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 204 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "5 sub_N_in " "Found entity 5: sub_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 214 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "6 add_N_in " "Found entity 6: add_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 222 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "7 add_sub_N " "Found entity 7: add_sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 230 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "8 add_1 " "Found entity 8: add_1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 243 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "9 abs_regime " "Found entity 9: abs_regime" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 252 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "10 conv_2c " "Found entity 10: conv_2c" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 262 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "11 reg_exp_op " "Found entity 11: reg_exp_op" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "12 DSR_left_N_S " "Found entity 12: DSR_left_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 285 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "13 DSR_right_N_S " "Found entity 13: DSR_right_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 306 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "14 LOD_N " "Found entity 14: LOD_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 327 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""} { "Info" "ISGN_ENTITY_NAME" "15 LOD " "Found entity 15: LOD" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 348 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405371498 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405371498 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "posit_add " "Elaborating entity \"posit_add\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676405371533 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_extract_v1 data_extract_v1:uut_de1 " "Elaborating entity \"data_extract_v1\" for hierarchy \"data_extract_v1:uut_de1\"" {  } { { "posit_add.v" "uut_de1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371535 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(183) " "Verilog HDL assignment warning at posit_add.v(183): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676405371535 "|posit_add|data_extract_v1:uut_de1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD_N data_extract_v1:uut_de1\|LOD_N:xinst_k " "Elaborating entity \"LOD_N\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\"" {  } { { "posit_add.v" "xinst_k" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371536 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1 " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\"" {  } { { "posit_add.v" "l1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 344 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371536 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371537 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371538 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371538 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_left_N_S data_extract_v1:uut_de1\|DSR_left_N_S:ls " "Elaborating entity \"DSR_left_N_S\" for hierarchy \"data_extract_v1:uut_de1\|DSR_left_N_S:ls\"" {  } { { "posit_add.v" "ls" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 186 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371543 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "abs_regime abs_regime:uut_abs_regime1 " "Elaborating entity \"abs_regime\" for hierarchy \"abs_regime:uut_abs_regime1\"" {  } { { "posit_add.v" "uut_abs_regime1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371548 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N sub_N:uut_ediff " "Elaborating entity \"sub_N\" for hierarchy \"sub_N:uut_ediff\"" {  } { { "posit_add.v" "uut_ediff" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371549 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in sub_N:uut_ediff\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"sub_N:uut_ediff\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371549 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr1 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr1\"" {  } { { "posit_add.v" "dsr1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371550 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_N add_sub_N:uut_add_sub_N " "Elaborating entity \"add_sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\"" {  } { { "posit_add.v" "uut_add_sub_N" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 98 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371551 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N add_sub_N:uut_add_sub_N\|add_N:a11 " "Elaborating entity \"add_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\"" {  } { { "posit_add.v" "a11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371551 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N_in add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1 " "Elaborating entity \"add_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1\"" {  } { { "posit_add.v" "a1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371552 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N add_sub_N:uut_add_sub_N\|sub_N:s11 " "Elaborating entity \"sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\"" {  } { { "posit_add.v" "s11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 238 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371553 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371553 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_1 add_1:uut_add_mantovf " "Elaborating entity \"add_1\" for hierarchy \"add_1:uut_add_mantovf\"" {  } { { "posit_add.v" "uut_add_mantovf" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371559 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_exp_op reg_exp_op:uut_reg_ro " "Elaborating entity \"reg_exp_op\" for hierarchy \"reg_exp_op:uut_reg_ro\"" {  } { { "posit_add.v" "uut_reg_ro" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 119 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371560 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(281) " "Verilog HDL assignment warning at posit_add.v(281): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 281 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676405371560 "|posit_add|reg_exp_op:uut_reg_ro"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conv_2c reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1 " "Elaborating entity \"conv_2c\" for hierarchy \"reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1\"" {  } { { "posit_add.v" "uut_conv_2c1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 279 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371560 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr2 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr2\"" {  } { { "posit_add.v" "dsr2" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405371561 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676405372570 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676405373526 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405373526 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "557 " "Implemented 557 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676405373582 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676405373582 ""} { "Info" "ICUT_CUT_TM_LCELLS" "505 " "Implemented 505 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676405373582 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676405373582 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4838 " "Peak virtual memory: 4838 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405373607 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:09:33 2023 " "Processing ended: Tue Feb 14 20:09:33 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405373607 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405373607 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405373607 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405373607 ""}
diff --git a/Reference Code/add/db/posit-add.map.rdb b/Reference Code/add/db/posit-add.map.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..7f88cd2a70bbeba264a6bfeef457a2f3a72261e1
Binary files /dev/null and b/Reference Code/add/db/posit-add.map.rdb differ
diff --git a/Reference Code/add/db/posit-add.map_bb.cdb b/Reference Code/add/db/posit-add.map_bb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..5fba1bb228f53a94c0c5b7bcaf37f2d7369a0c6a
Binary files /dev/null and b/Reference Code/add/db/posit-add.map_bb.cdb differ
diff --git a/Reference Code/add/db/posit-add.map_bb.hdb b/Reference Code/add/db/posit-add.map_bb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..4eb2fa1f8276770260e171e61d03ac43437195b7
Binary files /dev/null and b/Reference Code/add/db/posit-add.map_bb.hdb differ
diff --git a/Reference Code/add/db/posit-add.map_bb.logdb b/Reference Code/add/db/posit-add.map_bb.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Reference Code/add/db/posit-add.map_bb.logdb	
@@ -0,0 +1 @@
+v1
diff --git a/Reference Code/add/db/posit-add.pre_map.hdb b/Reference Code/add/db/posit-add.pre_map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..ac4f936be463e23c2bd71278862b2b453690c919
Binary files /dev/null and b/Reference Code/add/db/posit-add.pre_map.hdb differ
diff --git a/Reference Code/add/db/posit-add.root_partition.map.reg_db.cdb b/Reference Code/add/db/posit-add.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..1ca300cd71e8f9f28ce9cefbb8bfff14d45dc6fe
Binary files /dev/null and b/Reference Code/add/db/posit-add.root_partition.map.reg_db.cdb differ
diff --git a/Reference Code/add/db/posit-add.routing.rdb b/Reference Code/add/db/posit-add.routing.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..d8fd132347fb3beb3f97e27469cce97bd20fac64
Binary files /dev/null and b/Reference Code/add/db/posit-add.routing.rdb differ
diff --git a/Reference Code/add/db/posit-add.rtlv.hdb b/Reference Code/add/db/posit-add.rtlv.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..b2ce8e4187c2a87cc0694e83c24183cfb5204942
Binary files /dev/null and b/Reference Code/add/db/posit-add.rtlv.hdb differ
diff --git a/Reference Code/add/db/posit-add.rtlv_sg.cdb b/Reference Code/add/db/posit-add.rtlv_sg.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..fd3db7f47c3b626985d9e32eaff7ab069411371d
Binary files /dev/null and b/Reference Code/add/db/posit-add.rtlv_sg.cdb differ
diff --git a/Reference Code/add/db/posit-add.rtlv_sg_swap.cdb b/Reference Code/add/db/posit-add.rtlv_sg_swap.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..ef2e276eeee6678db397b530b33761ae43474a59
Binary files /dev/null and b/Reference Code/add/db/posit-add.rtlv_sg_swap.cdb differ
diff --git a/Reference Code/add/db/posit-add.sld_design_entry.sci b/Reference Code/add/db/posit-add.sld_design_entry.sci
new file mode 100644
index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Reference Code/add/db/posit-add.sld_design_entry.sci differ
diff --git a/Reference Code/add/db/posit-add.sld_design_entry_dsc.sci b/Reference Code/add/db/posit-add.sld_design_entry_dsc.sci
new file mode 100644
index 0000000000000000000000000000000000000000..65c27fe2ea800b795657754ede47ccb86e5ec502
Binary files /dev/null and b/Reference Code/add/db/posit-add.sld_design_entry_dsc.sci differ
diff --git a/Reference Code/add/db/posit-add.smart_action.txt b/Reference Code/add/db/posit-add.smart_action.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c8e8a135c9291129f28f1fcaa018fa29a7cc96fe
--- /dev/null
+++ b/Reference Code/add/db/posit-add.smart_action.txt	
@@ -0,0 +1 @@
+DONE
diff --git a/Reference Code/add/db/posit-add.sta.qmsg b/Reference Code/add/db/posit-add.sta.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..8efbbce39330463dc3ce27cfbd9d0b59f6a46f96
--- /dev/null
+++ b/Reference Code/add/db/posit-add.sta.qmsg	
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676405439571 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676405439571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 20:10:39 2023 " "Processing started: Tue Feb 14 20:10:39 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676405439571 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1676405439571 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta posit-add -c posit-add " "Command: quartus_sta posit-add -c posit-add" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1676405439571 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1676405439745 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1676405440387 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1676405440387 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405440424 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405440425 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "posit-add.sdc " "Synopsys Design Constraints File file not found: 'posit-add.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1676405440845 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405440845 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676405440845 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676405440847 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1676405440847 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676405440848 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1676405440848 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1676405440858 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676405440861 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440863 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440872 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440875 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440878 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440881 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405440883 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676405440887 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676405440914 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676405441643 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405441711 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676405441711 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676405441712 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676405441712 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441715 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441719 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441721 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441725 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441728 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405441730 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676405441734 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676405441874 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676405442462 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405442519 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676405442519 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676405442520 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676405442520 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442523 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442526 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442529 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442532 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442533 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676405442537 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676405442674 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676405442674 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676405442675 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676405442675 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442678 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442681 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442685 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442687 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676405442689 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676405443933 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676405443942 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5176 " "Peak virtual memory: 5176 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405443994 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:10:43 2023 " "Processing ended: Tue Feb 14 20:10:43 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405443994 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405443994 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405443994 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1676405443994 ""}
diff --git a/Reference Code/add/db/posit-add.sta.rdb b/Reference Code/add/db/posit-add.sta.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..1dac7b2658b1d12e3386a6c93b2965f4c9e4791f
Binary files /dev/null and b/Reference Code/add/db/posit-add.sta.rdb differ
diff --git a/Reference Code/add/db/posit-add.sta_cmp.6_slow_1100mv_85c.tdb b/Reference Code/add/db/posit-add.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100644
index 0000000000000000000000000000000000000000..b46bb920f02a0929157baf16a8872d33f131439f
Binary files /dev/null and b/Reference Code/add/db/posit-add.sta_cmp.6_slow_1100mv_85c.tdb differ
diff --git a/Reference Code/add/db/posit-add.tis_db_list.ddb b/Reference Code/add/db/posit-add.tis_db_list.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..1e114b187b8ec41959f4a85d242f119846ab4de9
Binary files /dev/null and b/Reference Code/add/db/posit-add.tis_db_list.ddb differ
diff --git a/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_0c.ddb b/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_0c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..6dac9700662636ec642a637b0bbc3244ed8fb834
Binary files /dev/null and b/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_0c.ddb differ
diff --git a/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_85c.ddb b/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_85c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..4a2d7dd69603fa5fe091e2a434651effa5ea8906
Binary files /dev/null and b/Reference Code/add/db/posit-add.tiscmp.fast_1100mv_85c.ddb differ
diff --git a/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_0c.ddb b/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_0c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..867c0694175c0b6d08e35f8523f3372ebbf8674c
Binary files /dev/null and b/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_0c.ddb differ
diff --git a/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_85c.ddb b/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_85c.ddb
new file mode 100644
index 0000000000000000000000000000000000000000..b27b340c8e6160173c1f3418225fec8884b2f256
Binary files /dev/null and b/Reference Code/add/db/posit-add.tiscmp.slow_1100mv_85c.ddb differ
diff --git a/Reference Code/add/db/posit-add.tmw_info b/Reference Code/add/db/posit-add.tmw_info
new file mode 100644
index 0000000000000000000000000000000000000000..8cbd4a6e805b82785d4432b60f24352b6cd99ebe
--- /dev/null
+++ b/Reference Code/add/db/posit-add.tmw_info	
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:01:23
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:58-start_full_compilation
+start_assembler:s:00:00:06-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/Reference Code/add/db/posit-add.vpr.ammdb b/Reference Code/add/db/posit-add.vpr.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..33df90c51137f155e0a3c815f042cb75332b8d62
Binary files /dev/null and b/Reference Code/add/db/posit-add.vpr.ammdb differ
diff --git a/Reference Code/add/db/posit-add_partition_pins.json b/Reference Code/add/db/posit-add_partition_pins.json
new file mode 100644
index 0000000000000000000000000000000000000000..270efaf663cc8c9a4b70371bf7010349ff783f37
--- /dev/null
+++ b/Reference Code/add/db/posit-add_partition_pins.json	
@@ -0,0 +1,217 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "out[0]",
+					"strict" : false
+				},
+				{
+					"name" : "out[1]",
+					"strict" : false
+				},
+				{
+					"name" : "out[2]",
+					"strict" : false
+				},
+				{
+					"name" : "out[3]",
+					"strict" : false
+				},
+				{
+					"name" : "out[4]",
+					"strict" : false
+				},
+				{
+					"name" : "out[5]",
+					"strict" : false
+				},
+				{
+					"name" : "out[6]",
+					"strict" : false
+				},
+				{
+					"name" : "out[7]",
+					"strict" : false
+				},
+				{
+					"name" : "out[8]",
+					"strict" : false
+				},
+				{
+					"name" : "out[9]",
+					"strict" : false
+				},
+				{
+					"name" : "out[10]",
+					"strict" : false
+				},
+				{
+					"name" : "out[11]",
+					"strict" : false
+				},
+				{
+					"name" : "out[12]",
+					"strict" : false
+				},
+				{
+					"name" : "out[13]",
+					"strict" : false
+				},
+				{
+					"name" : "out[14]",
+					"strict" : false
+				},
+				{
+					"name" : "out[15]",
+					"strict" : false
+				},
+				{
+					"name" : "inf",
+					"strict" : false
+				},
+				{
+					"name" : "zero",
+					"strict" : false
+				},
+				{
+					"name" : "done",
+					"strict" : false
+				},
+				{
+					"name" : "in1[15]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[12]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[13]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[14]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[10]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[11]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[7]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[8]",
+					"strict" : false
+				},
+				{
+					"name" : "in1[9]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[15]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[12]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[13]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[14]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[10]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[11]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[7]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[8]",
+					"strict" : false
+				},
+				{
+					"name" : "in2[9]",
+					"strict" : false
+				},
+				{
+					"name" : "start",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
\ No newline at end of file
diff --git a/Reference Code/add/db/prev_cmp_Posit_Adder.qmsg b/Reference Code/add/db/prev_cmp_Posit_Adder.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..dd3087fa47845b92408a177261fcb305cc589102
--- /dev/null
+++ b/Reference Code/add/db/prev_cmp_Posit_Adder.qmsg	
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676998608135 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676998608135 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 21 16:56:48 2023 " "Processing started: Tue Feb 21 16:56:48 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676998608135 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998608135 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off Posit_Adder -c Posit_Adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998608135 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676998608812 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676998608812 ""}
+{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "Posit_Adder " "Top-level design entity \"Posit_Adder\" is undefined" {  } {  } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1676998620299 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4773 " "Peak virtual memory: 4773 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676998620394 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Feb 21 16:57:00 2023 " "Processing ended: Tue Feb 21 16:57:00 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676998620394 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676998620394 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676998620394 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676998620394 ""}
diff --git a/Reference Code/add/db/prev_cmp_posit-add.qmsg b/Reference Code/add/db/prev_cmp_posit-add.qmsg
new file mode 100644
index 0000000000000000000000000000000000000000..7950e42597c4eee1d828ead1032c5057212fec28
--- /dev/null
+++ b/Reference Code/add/db/prev_cmp_posit-add.qmsg	
@@ -0,0 +1,33 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676405348907 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676405348907 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 14 20:09:08 2023 " "Processing started: Tue Feb 14 20:09:08 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676405348907 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405348907 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add " "Command: quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405348907 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676405349481 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676405349482 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posit_add.v 15 15 " "Found 15 design units, including 15 entities, in source file posit_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 posit_add " "Found entity 1: posit_add" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "2 data_extract_v1 " "Found entity 2: data_extract_v1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 155 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "3 sub_N " "Found entity 3: sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "4 add_N " "Found entity 4: add_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 204 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "5 sub_N_in " "Found entity 5: sub_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 214 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "6 add_N_in " "Found entity 6: add_N_in" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 222 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "7 add_sub_N " "Found entity 7: add_sub_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 230 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "8 add_1 " "Found entity 8: add_1" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 243 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "9 abs_regime " "Found entity 9: abs_regime" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 252 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "10 conv_2c " "Found entity 10: conv_2c" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 262 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "11 reg_exp_op " "Found entity 11: reg_exp_op" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "12 DSR_left_N_S " "Found entity 12: DSR_left_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 285 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "13 DSR_right_N_S " "Found entity 13: DSR_right_N_S" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 306 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "14 LOD_N " "Found entity 14: LOD_N" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 327 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""} { "Info" "ISGN_ENTITY_NAME" "15 LOD " "Found entity 15: LOD" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 348 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676405356342 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405356342 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "posit_add " "Elaborating entity \"posit_add\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676405356368 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_extract_v1 data_extract_v1:uut_de1 " "Elaborating entity \"data_extract_v1\" for hierarchy \"data_extract_v1:uut_de1\"" {  } { { "posit_add.v" "uut_de1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356389 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(183) " "Verilog HDL assignment warning at posit_add.v(183): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676405356391 "|posit_add|data_extract_v1:uut_de1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD_N data_extract_v1:uut_de1\|LOD_N:xinst_k " "Elaborating entity \"LOD_N\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\"" {  } { { "posit_add.v" "xinst_k" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356397 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1 " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\"" {  } { { "posit_add.v" "l1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 344 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356404 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356412 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356420 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LOD data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l " "Elaborating entity \"LOD\" for hierarchy \"data_extract_v1:uut_de1\|LOD_N:xinst_k\|LOD:l1\|LOD:l\|LOD:l\|LOD:l\"" {  } { { "posit_add.v" "l" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356427 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_left_N_S data_extract_v1:uut_de1\|DSR_left_N_S:ls " "Elaborating entity \"DSR_left_N_S\" for hierarchy \"data_extract_v1:uut_de1\|DSR_left_N_S:ls\"" {  } { { "posit_add.v" "ls" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 186 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356438 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "abs_regime abs_regime:uut_abs_regime1 " "Elaborating entity \"abs_regime\" for hierarchy \"abs_regime:uut_abs_regime1\"" {  } { { "posit_add.v" "uut_abs_regime1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356451 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N sub_N:uut_ediff " "Elaborating entity \"sub_N\" for hierarchy \"sub_N:uut_ediff\"" {  } { { "posit_add.v" "uut_ediff" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356458 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in sub_N:uut_ediff\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"sub_N:uut_ediff\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356464 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr1 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr1\"" {  } { { "posit_add.v" "dsr1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356469 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_N add_sub_N:uut_add_sub_N " "Elaborating entity \"add_sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\"" {  } { { "posit_add.v" "uut_add_sub_N" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 98 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356476 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N add_sub_N:uut_add_sub_N\|add_N:a11 " "Elaborating entity \"add_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\"" {  } { { "posit_add.v" "a11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356484 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_N_in add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1 " "Elaborating entity \"add_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|add_N:a11\|add_N_in:a1\"" {  } { { "posit_add.v" "a1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356489 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N add_sub_N:uut_add_sub_N\|sub_N:s11 " "Elaborating entity \"sub_N\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\"" {  } { { "posit_add.v" "s11" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 238 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356496 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub_N_in add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1 " "Elaborating entity \"sub_N_in\" for hierarchy \"add_sub_N:uut_add_sub_N\|sub_N:s11\|sub_N_in:s1\"" {  } { { "posit_add.v" "s1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356501 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_1 add_1:uut_add_mantovf " "Elaborating entity \"add_1\" for hierarchy \"add_1:uut_add_mantovf\"" {  } { { "posit_add.v" "uut_add_mantovf" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356515 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_exp_op reg_exp_op:uut_reg_ro " "Elaborating entity \"reg_exp_op\" for hierarchy \"reg_exp_op:uut_reg_ro\"" {  } { { "posit_add.v" "uut_reg_ro" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 119 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356521 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 posit_add.v(281) " "Verilog HDL assignment warning at posit_add.v(281): truncated value with size 32 to match size of target (4)" {  } { { "posit_add.v" "" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 281 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1676405356522 "|posit_add|reg_exp_op:uut_reg_ro"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conv_2c reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1 " "Elaborating entity \"conv_2c\" for hierarchy \"reg_exp_op:uut_reg_ro\|conv_2c:uut_conv_2c1\"" {  } { { "posit_add.v" "uut_conv_2c1" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 279 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356527 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DSR_right_N_S DSR_right_N_S:dsr2 " "Elaborating entity \"DSR_right_N_S\" for hierarchy \"DSR_right_N_S:dsr2\"" {  } { { "posit_add.v" "dsr2" { Text "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405356534 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676405357620 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676405358504 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676405358504 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "557 " "Implemented 557 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676405358560 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676405358560 ""} { "Info" "ICUT_CUT_TM_LCELLS" "505 " "Implemented 505 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676405358560 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676405358560 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4842 " "Peak virtual memory: 4842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676405358583 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 14 20:09:18 2023 " "Processing ended: Tue Feb 14 20:09:18 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676405358583 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676405358583 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676405358583 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676405358583 ""}
diff --git a/Reference Code/add/error_8bit.txt b/Reference Code/add/error_8bit.txt
index cd2f2623cec2892b8f483ada3e21d0adeb82c75d..5df099f35d3bc59b10006095abdc8d3e901ddbe0 100644
--- a/Reference Code/add/error_8bit.txt	
+++ b/Reference Code/add/error_8bit.txt	
@@ -2054,6 +2054,7 @@
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@@ -3569,6 +3568,7 @@
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@@ -3596,8 +3596,10 @@
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@@ -3821,9 +3823,7 @@
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@@ -4079,6 +4076,9 @@
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@@ -4109,11 +4109,13 @@
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@@ -4364,8 +4364,13 @@
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@@ -4579,6 +4584,33 @@
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@@ -4587,24 +4619,16 @@
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@@ -4625,7 +4649,6 @@
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@@ -4817,6 +4840,14 @@
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@@ -4849,16 +4880,9 @@
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@@ -4880,7 +4904,6 @@
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@@ -5071,6 +5094,17 @@
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@@ -5097,26 +5131,18 @@
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@@ -5139,7 +5165,6 @@
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@@ -5325,6 +5350,15 @@
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@@ -5360,17 +5394,9 @@
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@@ -5394,7 +5420,6 @@
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@@ -5579,6 +5604,19 @@
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@@ -5653,7 +5681,6 @@
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@@ -5833,6 +5860,17 @@
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@@ -5870,19 +5908,9 @@
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@@ -5908,7 +5936,6 @@
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@@ -6087,6 +6114,21 @@
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@@ -6117,30 +6159,18 @@
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@@ -6380,25 +6422,12 @@
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@@ -6627,32 +6673,22 @@
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@@ -7911,30 +7965,19 @@
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@@ -8108,7 +8146,25 @@
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@@ -8164,40 +8219,25 @@
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@@ -8362,7 +8402,24 @@
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@@ -8421,7 +8477,15 @@
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@@ -8430,39 +8494,6 @@
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@@ -8837,7 +8910,28 @@
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-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
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+  0
+  0
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+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
   1
   1
   1
@@ -65295,22 +65295,6 @@
   1
   1
   1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
   0
   0
   0
@@ -65375,22 +65359,38 @@
   0
   0
   0
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
-  1
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
+  0
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+  0
+  0
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+  0
   1
   1
   1
diff --git a/Reference Code/add/ez.v b/Reference Code/add/ez.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/Reference Code/add/incremental_db/README b/Reference Code/add/incremental_db/README
new file mode 100644
index 0000000000000000000000000000000000000000..9f62dcda0512fec7b5b55c11a13d70f91548996f
--- /dev/null
+++ b/Reference Code/add/incremental_db/README	
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.db_info b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..1ba14374a3d5f2ca4abfe5b29dae44e5bbcf511e
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.db_info	
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 21 16:56:39 2023
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.cdb b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..763688a0a4e1d3dd163901a587f05350f80c15fc
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.dpi b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.dpi
new file mode 100644
index 0000000000000000000000000000000000000000..11464e919317c275d354fdfef1c89362aacf2b48
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.dpi differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.cdb b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..703cfbc7e9026905c7eb0dad2181f494ee1b8560
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hb_info b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000000000000000000000000000000000000..8210c55998f9226aeba57897397a9e541102c45e
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hb_info differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hdb b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..053410c099107b5be76cc655e4e2d1ecb7db661e
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.sig b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hbdb.sig	
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hdb b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..6668467debc1502a35830309e05d49dc6b01d453
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.kpt b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d6a78ee628a1be84207b2ad79dcb39f59e865
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/Posit_Adder.root_partition.map.kpt differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.db_info b/Reference Code/add/incremental_db/compiled_partitions/posit-add.db_info
new file mode 100644
index 0000000000000000000000000000000000000000..12f26c49cb3d43265e4490ae36d2f162631aa9f5
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/posit-add.db_info	
@@ -0,0 +1,3 @@
+Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Version_Index = 553882368
+Creation_Time = Tue Feb 14 20:09:16 2023
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.ammdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.ammdb
new file mode 100644
index 0000000000000000000000000000000000000000..b49242e673a78d1681e0e2d3b295d76568c9fff0
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.ammdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.cdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..3250bba71171fd2deb63103acd89bcf680a0b85b
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.dfp b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.dfp
new file mode 100644
index 0000000000000000000000000000000000000000..b1c67d625638bb473b681fa4acb00be38889ece3
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.dfp differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.cdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..2a871177ed36ee7c3ab0d0005d1568fe5f6965f7
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.hdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..f29230bd7bdb54aa0a02088d6caafaf8e921fc6c
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.sig b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hbdb.sig	
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..f74837430c5c54e6b6e2205735b49f2a1cac584f
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.logdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.logdb
new file mode 100644
index 0000000000000000000000000000000000000000..626799f0f85326a8c1fc522db584e86cdfccd51f
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.logdb	
@@ -0,0 +1 @@
+v1
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.rcfdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.rcfdb
new file mode 100644
index 0000000000000000000000000000000000000000..5f65e969e69a2be0f90ef12ec1e9a283da4012b3
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.cmp.rcfdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.cdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..5a3f3f54ba88787cc36bdbef07b5db3a9ee99e3f
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.dpi b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.dpi
new file mode 100644
index 0000000000000000000000000000000000000000..c3f4be7c2b8c0bc54a4143d96081206f8d80f980
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.dpi differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.cdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..3845b2fe27cdfd8be97b3091748fca80d5ee18f2
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.cdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hb_info b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000000000000000000000000000000000000..8210c55998f9226aeba57897397a9e541102c45e
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hb_info differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..8a2cf5498599986ffaf7f6977de539124ca8cd19
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.sig b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.sig
new file mode 100644
index 0000000000000000000000000000000000000000..af9b8e9aa113827749627f5921914b7bff5208a3
--- /dev/null
+++ b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hbdb.sig	
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..84e68e87f693626a1376137c02a8de37bd6adc00
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.kpt b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..84e25b0edb46dd990e6f6bb9183b1d5479c1ba31
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.root_partition.map.kpt differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrp.hdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..d7147fb6bdc835e901cd74775072da78e0d13958
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrp.hdb differ
diff --git a/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrs.cdb b/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrs.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..528d38efb1d87cc85d82fbc1dea4490dac381826
Binary files /dev/null and b/Reference Code/add/incremental_db/compiled_partitions/posit-add.rrs.cdb differ
diff --git a/Reference Code/add/output_files/posit-add.asm.rpt b/Reference Code/add/output_files/posit-add.asm.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5638ea40460bd0e55665e6f935b2868a0dbd6c2a
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.asm.rpt	
@@ -0,0 +1,91 @@
+Assembler report for posit-add
+Tue Feb 14 20:10:38 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Feb 14 20:10:38 2023 ;
+; Revision Name         ; posit-add                             ;
+; Top-level Entity Name ; posit_add                             ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------------------------------------------------------+
+; Assembler Generated Files                                                 ;
++---------------------------------------------------------------------------+
+; File Name                                                                 ;
++---------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.sof ;
++---------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.sof ;
++----------------+------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                            ;
++----------------+------------------------------------------------------------------------------------+
+; JTAG usercode  ; 0x00BA26E0                                                                         ;
+; Checksum       ; 0x00BA26E0                                                                         ;
++----------------+------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 20:10:32 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off posit-add -c posit-add
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4881 megabytes
+    Info: Processing ended: Tue Feb 14 20:10:38 2023
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/Reference Code/add/output_files/posit-add.done b/Reference Code/add/output_files/posit-add.done
new file mode 100644
index 0000000000000000000000000000000000000000..611564cb02511b2bafd5c1430b66f57d54479bda
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.done	
@@ -0,0 +1 @@
+Tue Feb 14 20:10:46 2023
diff --git a/Reference Code/add/output_files/posit-add.eda.rpt b/Reference Code/add/output_files/posit-add.eda.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..2b80a2efe8a141020e8d5fb28cbd10908a5b93a9
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.eda.rpt	
@@ -0,0 +1,94 @@
+EDA Netlist Writer report for posit-add
+Tue Feb 14 20:10:46 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Tue Feb 14 20:10:46 2023 ;
+; Revision Name             ; posit-add                             ;
+; Top-level Entity Name     ; posit_add                             ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                             ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Option                                                                                            ; Setting                     ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+; Tool Name                                                                                         ; Questa Intel FPGA (Verilog) ;
+; Generate functional simulation netlist                                                            ; On                          ;
+; Truncate long hierarchy paths                                                                     ; Off                         ;
+; Map illegal HDL characters                                                                        ; Off                         ;
+; Flatten buses into individual nodes                                                               ; Off                         ;
+; Maintain hierarchy                                                                                ; Off                         ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                         ;
+; Enable glitch filtering                                                                           ; Off                         ;
+; Do not write top level VHDL entity                                                                ; Off                         ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                         ;
+; Architecture name in VHDL output netlist                                                          ; structure                   ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                         ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                         ;
++---------------------------------------------------------------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Simulation Generated Files                                                    ;
++-------------------------------------------------------------------------------+
+; Generated Files                                                               ;
++-------------------------------------------------------------------------------+
+; H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/simulation/questa/posit-add.vo ;
++-------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 20:10:45 2023
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off posit-add -c posit-add
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (204019): Generated file posit-add.vo in folder "H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/simulation/questa/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 4733 megabytes
+    Info: Processing ended: Tue Feb 14 20:10:46 2023
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Reference Code/add/output_files/posit-add.fit.rpt b/Reference Code/add/output_files/posit-add.fit.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..bcc09f88dc29b171a8956dbd48dca5beb6e79243
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.fit.rpt	
@@ -0,0 +1,2075 @@
+Fitter report for posit-add
+Tue Feb 14 20:10:31 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Incremental Compilation Preservation Summary
+  6. Incremental Compilation Partition Settings
+  7. Incremental Compilation Placement Preservation
+  8. Pin-Out File
+  9. Fitter Resource Usage Summary
+ 10. Fitter Partition Statistics
+ 11. Input Pins
+ 12. Output Pins
+ 13. I/O Bank Usage
+ 14. All Package Pins
+ 15. I/O Assignment Warnings
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Routing Usage Summary
+ 20. I/O Rules Summary
+ 21. I/O Rules Details
+ 22. I/O Rules Matrix
+ 23. Fitter Device Options
+ 24. Operating Settings and Conditions
+ 25. Fitter Messages
+ 26. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++---------------------------------+------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Feb 14 20:10:31 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; posit-add                                      ;
+; Top-level Entity Name           ; posit_add                                      ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; 337 / 32,070 ( 1 % )                           ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 52 / 457 ( 11 % )                              ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                          ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                 ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                  ;
++---------------------------------+------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                             ; Setting                               ; Default Value                         ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                             ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                  ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                  ; 85                                    ;                                       ;
+; Use smart compilation                                              ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                                    ; On                                    ;
+; Enable compact report table                                        ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                   ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                  ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                        ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                 ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                               ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                       ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                        ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                   ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                                  ; Care                                  ;
+; Power Optimization During Fitting                                  ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                   ; Off                                   ; Off                                   ;
+; Optimize Timing                                                    ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                           ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                         ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                      ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                      ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization               ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                              ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                          ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                              ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                  ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                              ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                       ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                          ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                             ; Off                                   ; Off                                   ;
+; Fitter Effort                                                      ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                    ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                          ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                  ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                               ; On                                    ; On                                    ;
+; Reserve all unused pins                                            ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                        ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                  ; On                                    ; On                                    ;
+; Active Serial clock source                                         ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
+; Clamping Diode                                                     ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode   ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                     ; On                                    ; On                                    ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.02        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.4%      ;
+;     Processor 3            ;   0.4%      ;
+;     Processor 4            ;   0.4%      ;
+;     Processor 5            ;   0.4%      ;
+;     Processor 6            ;   0.4%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 610 ) ; 0.00 % ( 0 / 610 )         ; 0.00 % ( 0 / 610 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 610 ) ; 0.00 % ( 0 / 610 )         ; 0.00 % ( 0 / 610 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 610 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 337 / 32,070       ; 1 %   ;
+; ALMs needed [=A-B+C]                                        ; 337                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 337 / 32,070       ; 1 %   ;
+;         [a] ALMs used for LUT logic and registers           ; 0                  ;       ;
+;         [b] ALMs used for LUT logic                         ; 337                ;       ;
+;         [c] ALMs used for registers                         ; 0                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 1 / 32,070         ; < 1 % ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 1                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 37 / 3,207         ; 1 %   ;
+;     -- Logic LABs                                           ; 37                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 506                ;       ;
+;     -- 7 input functions                                    ; 4                  ;       ;
+;     -- 6 input functions                                    ; 165                ;       ;
+;     -- 5 input functions                                    ; 85                 ;       ;
+;     -- 4 input functions                                    ; 117                ;       ;
+;     -- <=3 input functions                                  ; 135                ;       ;
+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Dedicated logic registers                                   ; 0                  ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 0 / 64,140         ; 0 %   ;
+;         -- Secondary logic registers                        ; 0 / 64,140         ; 0 %   ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 0                  ;       ;
+;         -- Routing optimization registers                   ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 52 / 457           ; 11 %  ;
+;     -- Clock pins                                           ; 3 / 8              ; 38 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global signals                                              ; 0                  ;       ;
+;     -- Global clocks                                        ; 0 / 16             ; 0 %   ;
+;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
+;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.2% / 0.2% / 0.2% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 5.2% / 5.5% / 4.2% ;       ;
+; Maximum fan-out                                             ; 59                 ;       ;
+; Highest non-global fan-out                                  ; 59                 ;       ;
+; Total fan-out                                               ; 2389               ;       ;
+; Average fan-out                                             ; 3.92               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                        ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Statistic                                                   ; Top                 ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 337 / 32070 ( 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 337                 ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 337 / 32070 ( 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 0                   ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 337                 ; 0                              ;
+;         [c] ALMs used for registers                         ; 0                   ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                   ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 1 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                   ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                   ; 0                              ;
+;         [c] Due to LAB input limits                         ; 1                   ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Difficulty packing design                                   ; Low                 ; Low                            ;
+;                                                             ;                     ;                                ;
+; Total LABs:  partially or completely used                   ; 37 / 3207 ( 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 37                  ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Combinational ALUT usage for logic                          ; 506                 ; 0                              ;
+;     -- 7 input functions                                    ; 4                   ; 0                              ;
+;     -- 6 input functions                                    ; 165                 ; 0                              ;
+;     -- 5 input functions                                    ; 85                  ; 0                              ;
+;     -- 4 input functions                                    ; 117                 ; 0                              ;
+;     -- <=3 input functions                                  ; 135                 ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 0                   ; 0                              ;
+; Memory ALUT usage                                           ; 0                   ; 0                              ;
+;     -- 64-address deep                                      ; 0                   ; 0                              ;
+;     -- 32-address deep                                      ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Dedicated logic registers                                   ; 0                   ; 0                              ;
+;     -- By type:                                             ;                     ;                                ;
+;         -- Primary logic registers                          ; 0 / 64140 ( 0 % )   ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 0 / 64140 ( 0 % )   ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                     ;                                ;
+;         -- Design implementation registers                  ; 0                   ; 0                              ;
+;         -- Routing optimization registers                   ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+;                                                             ;                     ;                                ;
+; Virtual pins                                                ; 0                   ; 0                              ;
+; I/O pins                                                    ; 52                  ; 0                              ;
+; I/O registers                                               ; 0                   ; 0                              ;
+; Total block memory bits                                     ; 0                   ; 0                              ;
+; Total block memory implementation bits                      ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Connections                                                 ;                     ;                                ;
+;     -- Input Connections                                    ; 0                   ; 0                              ;
+;     -- Registered Input Connections                         ; 0                   ; 0                              ;
+;     -- Output Connections                                   ; 0                   ; 0                              ;
+;     -- Registered Output Connections                        ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Internal Connections                                        ;                     ;                                ;
+;     -- Total Connections                                    ; 2391                ; 0                              ;
+;     -- Registered Connections                               ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; External Connections                                        ;                     ;                                ;
+;     -- Top                                                  ; 0                   ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Partition Interface                                         ;                     ;                                ;
+;     -- Input Ports                                          ; 33                  ; 0                              ;
+;     -- Output Ports                                         ; 19                  ; 0                              ;
+;     -- Bidir Ports                                          ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Registered Ports                                            ;                     ;                                ;
+;     -- Registered Input Ports                               ; 0                   ; 0                              ;
+;     -- Registered Output Ports                              ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Port Connectivity                                           ;                     ;                                ;
+;     -- Input Ports driven by GND                            ; 0                   ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                   ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                   ; 0                              ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                             ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; in1[0]  ; AE16  ; 4A       ; 52           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[10] ; AH12  ; 3B       ; 38           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[11] ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[12] ; AK23  ; 4A       ; 72           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[13] ; AJ19  ; 4A       ; 60           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[14] ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[15] ; AH19  ; 4A       ; 58           ; 0            ; 91           ; 35                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[1]  ; AA21  ; 4A       ; 88           ; 0            ; 1            ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[2]  ; AG16  ; 4A       ; 50           ; 0            ; 74           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[3]  ; AE17  ; 4A       ; 50           ; 0            ; 40           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[4]  ; AK11  ; 3B       ; 34           ; 0            ; 57           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[5]  ; AE22  ; 4A       ; 78           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[6]  ; AH24  ; 4A       ; 64           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[7]  ; AH18  ; 4A       ; 56           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[8]  ; AK16  ; 4A       ; 54           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in1[9]  ; AG18  ; 4A       ; 58           ; 0            ; 74           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[0]  ; AJ22  ; 4A       ; 70           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[10] ; AG20  ; 4A       ; 62           ; 0            ; 17           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[11] ; AK22  ; 4A       ; 68           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[12] ; AK18  ; 4A       ; 58           ; 0            ; 57           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[13] ; AE23  ; 4A       ; 78           ; 0            ; 17           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[14] ; AG23  ; 4A       ; 64           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[15] ; AG22  ; 4A       ; 66           ; 0            ; 74           ; 35                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[1]  ; AJ21  ; 4A       ; 62           ; 0            ; 51           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[2]  ; V16   ; 4A       ; 52           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[3]  ; W17   ; 4A       ; 60           ; 0            ; 17           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[4]  ; AD17  ; 4A       ; 64           ; 0            ; 17           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[5]  ; AF19  ; 4A       ; 62           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[6]  ; AH22  ; 4A       ; 66           ; 0            ; 91           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[7]  ; AH17  ; 4A       ; 56           ; 0            ; 34           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[8]  ; AF23  ; 4A       ; 74           ; 0            ; 40           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; in2[9]  ; AJ17  ; 4A       ; 58           ; 0            ; 40           ; 2                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; start   ; AD27  ; 5A       ; 89           ; 8            ; 54           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; done    ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; inf     ; AC18  ; 4A       ; 64           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[0]  ; AJ16  ; 4A       ; 54           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[10] ; AG15  ; 3B       ; 38           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[11] ; AG17  ; 4A       ; 50           ; 0            ; 91           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[12] ; AB17  ; 4A       ; 56           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[13] ; AK19  ; 4A       ; 60           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[14] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[15] ; AG21  ; 4A       ; 54           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[1]  ; AA14  ; 3B       ; 36           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[2]  ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[3]  ; AF16  ; 4A       ; 52           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[4]  ; W15   ; 3B       ; 40           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[5]  ; AF18  ; 4A       ; 50           ; 0            ; 57           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[6]  ; AF21  ; 4A       ; 70           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[7]  ; AK14  ; 3B       ; 40           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[8]  ; AA16  ; 4A       ; 56           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; out[9]  ; AA18  ; 4A       ; 68           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; zero    ; AH20  ; 4A       ; 54           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 7 / 48 ( 15 % )  ; 2.5V          ; --           ; 2.5V          ;
+; 4A       ; 43 / 80 ( 54 % ) ; 2.5V          ; --           ; 2.5V          ;
+; 5A       ; 2 / 32 ( 6 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 5B       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; out[1]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; out[8]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; out[9]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; in1[1]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; out[12]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB23     ; 227        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; inf                             ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC28     ; 245        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC29     ; 247        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC30     ; 259        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; in2[4]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD27     ; 222        ; 5A             ; start                           ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD30     ; 257        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; in1[0]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AE17     ; 135        ; 4A             ; in1[3]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; in1[5]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AE23     ; 189        ; 4A             ; in2[13]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE27     ; 229        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE28     ; 231        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE29     ; 253        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; out[3]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; out[5]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AF19     ; 159        ; 4A             ; in2[5]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; out[6]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; in2[8]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AF29     ; 237        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AF30     ; 239        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; out[10]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG16     ; 134        ; 4A             ; in1[2]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG17     ; 132        ; 4A             ; out[11]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG18     ; 150        ; 4A             ; in1[9]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; in2[10]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG21     ; 143        ; 4A             ; out[15]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG22     ; 166        ; 4A             ; in2[15]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG23     ; 163        ; 4A             ; in2[14]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AG28     ; 233        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; in1[10]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; in2[7]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH18     ; 145        ; 4A             ; in1[7]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH19     ; 148        ; 4A             ; in1[15]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH20     ; 141        ; 4A             ; zero                            ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; in2[6]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; in1[6]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AH29     ; 218        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AH30     ; 241        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; out[0]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ17     ; 151        ; 4A             ; in2[9]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; in1[13]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ20     ; 158        ; 4A             ; in1[14]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; in2[1]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ22     ; 172        ; 4A             ; in2[0]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; in1[4]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; out[7]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; in1[8]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; in2[12]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK19     ; 153        ; 4A             ; out[13]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; in2[11]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK23     ; 179        ; 4A             ; in1[12]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; in2[2]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; V17      ; 154        ; 4A             ; out[14]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; out[4]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; W16      ; 136        ; 4A             ; out[2]                          ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; W17      ; 152        ; 4A             ; in2[3]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; done                            ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; in1[11]                         ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; out[0]   ; Incomplete set of assignments ;
+; out[1]   ; Incomplete set of assignments ;
+; out[2]   ; Incomplete set of assignments ;
+; out[3]   ; Incomplete set of assignments ;
+; out[4]   ; Incomplete set of assignments ;
+; out[5]   ; Incomplete set of assignments ;
+; out[6]   ; Incomplete set of assignments ;
+; out[7]   ; Incomplete set of assignments ;
+; out[8]   ; Incomplete set of assignments ;
+; out[9]   ; Incomplete set of assignments ;
+; out[10]  ; Incomplete set of assignments ;
+; out[11]  ; Incomplete set of assignments ;
+; out[12]  ; Incomplete set of assignments ;
+; out[13]  ; Incomplete set of assignments ;
+; out[14]  ; Incomplete set of assignments ;
+; out[15]  ; Incomplete set of assignments ;
+; inf      ; Incomplete set of assignments ;
+; zero     ; Incomplete set of assignments ;
+; done     ; Incomplete set of assignments ;
+; in1[15]  ; Incomplete set of assignments ;
+; in1[12]  ; Incomplete set of assignments ;
+; in1[13]  ; Incomplete set of assignments ;
+; in1[14]  ; Incomplete set of assignments ;
+; in1[5]   ; Incomplete set of assignments ;
+; in1[10]  ; Incomplete set of assignments ;
+; in1[11]  ; Incomplete set of assignments ;
+; in1[0]   ; Incomplete set of assignments ;
+; in1[1]   ; Incomplete set of assignments ;
+; in1[2]   ; Incomplete set of assignments ;
+; in1[3]   ; Incomplete set of assignments ;
+; in1[4]   ; Incomplete set of assignments ;
+; in1[6]   ; Incomplete set of assignments ;
+; in1[7]   ; Incomplete set of assignments ;
+; in1[8]   ; Incomplete set of assignments ;
+; in1[9]   ; Incomplete set of assignments ;
+; in2[15]  ; Incomplete set of assignments ;
+; in2[12]  ; Incomplete set of assignments ;
+; in2[13]  ; Incomplete set of assignments ;
+; in2[14]  ; Incomplete set of assignments ;
+; in2[5]   ; Incomplete set of assignments ;
+; in2[10]  ; Incomplete set of assignments ;
+; in2[11]  ; Incomplete set of assignments ;
+; in2[0]   ; Incomplete set of assignments ;
+; in2[1]   ; Incomplete set of assignments ;
+; in2[2]   ; Incomplete set of assignments ;
+; in2[3]   ; Incomplete set of assignments ;
+; in2[4]   ; Incomplete set of assignments ;
+; in2[6]   ; Incomplete set of assignments ;
+; in2[7]   ; Incomplete set of assignments ;
+; in2[8]   ; Incomplete set of assignments ;
+; in2[9]   ; Incomplete set of assignments ;
+; start    ; Incomplete set of assignments ;
+; out[0]   ; Missing location assignment   ;
+; out[1]   ; Missing location assignment   ;
+; out[2]   ; Missing location assignment   ;
+; out[3]   ; Missing location assignment   ;
+; out[4]   ; Missing location assignment   ;
+; out[5]   ; Missing location assignment   ;
+; out[6]   ; Missing location assignment   ;
+; out[7]   ; Missing location assignment   ;
+; out[8]   ; Missing location assignment   ;
+; out[9]   ; Missing location assignment   ;
+; out[10]  ; Missing location assignment   ;
+; out[11]  ; Missing location assignment   ;
+; out[12]  ; Missing location assignment   ;
+; out[13]  ; Missing location assignment   ;
+; out[14]  ; Missing location assignment   ;
+; out[15]  ; Missing location assignment   ;
+; inf      ; Missing location assignment   ;
+; zero     ; Missing location assignment   ;
+; done     ; Missing location assignment   ;
+; in1[15]  ; Missing location assignment   ;
+; in1[12]  ; Missing location assignment   ;
+; in1[13]  ; Missing location assignment   ;
+; in1[14]  ; Missing location assignment   ;
+; in1[5]   ; Missing location assignment   ;
+; in1[10]  ; Missing location assignment   ;
+; in1[11]  ; Missing location assignment   ;
+; in1[0]   ; Missing location assignment   ;
+; in1[1]   ; Missing location assignment   ;
+; in1[2]   ; Missing location assignment   ;
+; in1[3]   ; Missing location assignment   ;
+; in1[4]   ; Missing location assignment   ;
+; in1[6]   ; Missing location assignment   ;
+; in1[7]   ; Missing location assignment   ;
+; in1[8]   ; Missing location assignment   ;
+; in1[9]   ; Missing location assignment   ;
+; in2[15]  ; Missing location assignment   ;
+; in2[12]  ; Missing location assignment   ;
+; in2[13]  ; Missing location assignment   ;
+; in2[14]  ; Missing location assignment   ;
+; in2[5]   ; Missing location assignment   ;
+; in2[10]  ; Missing location assignment   ;
+; in2[11]  ; Missing location assignment   ;
+; in2[0]   ; Missing location assignment   ;
+; in2[1]   ; Missing location assignment   ;
+; in2[2]   ; Missing location assignment   ;
+; in2[3]   ; Missing location assignment   ;
+; in2[4]   ; Missing location assignment   ;
+; in2[6]   ; Missing location assignment   ;
+; in2[7]   ; Missing location assignment   ;
+; in2[8]   ; Missing location assignment   ;
+; in2[9]   ; Missing location assignment   ;
+; start    ; Missing location assignment   ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node      ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                 ; Entity Name     ; Library Name ;
++---------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; |posit_add                      ; 336.5 (97.5)         ; 337.0 (97.5)                     ; 1.5 (0.0)                                         ; 1.0 (0.0)                        ; 0.0 (0.0)            ; 506 (166)           ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 52   ; 0            ; |posit_add                                                          ; posit_add       ; work         ;
+;    |DSR_left_N_S:dsl1|          ; 23.0 (23.0)          ; 23.0 (23.0)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|DSR_left_N_S:dsl1                                        ; DSR_left_N_S    ; work         ;
+;    |DSR_right_N_S:dsr1|         ; 36.5 (36.5)          ; 36.5 (36.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (45)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr1                                       ; DSR_right_N_S   ; work         ;
+;    |DSR_right_N_S:dsr2|         ; 44.5 (44.5)          ; 44.5 (44.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 62 (62)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr2                                       ; DSR_right_N_S   ; work         ;
+;    |LOD_N:l2|                   ; 23.0 (0.0)           ; 23.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 30 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2                                                 ; LOD_N           ; work         ;
+;       |LOD:l1|                  ; 23.0 (22.0)          ; 23.0 (22.0)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 30 (27)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1                                          ; LOD             ; work         ;
+;          |LOD:h|                ; 1.0 (0.0)            ; 1.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 0.5 (0.0)            ; 0.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h                              ; LOD             ; work         ;
+;                |LOD:l|          ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l                        ; LOD             ; work         ;
+;             |LOD:l|             ; 0.5 (0.0)            ; 0.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l                              ; LOD             ; work         ;
+;                |LOD:h|          ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h                        ; LOD             ; work         ;
+;          |LOD:l|                ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h                              ; LOD             ; work         ;
+;    |abs_regime:uut_abs_regime1| ; 6.0 (6.0)            ; 6.0 (6.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 8 (8)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime1                               ; abs_regime      ; work         ;
+;    |abs_regime:uut_abs_regime2| ; 4.5 (4.5)            ; 4.5 (4.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 6 (6)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime2                               ; abs_regime      ; work         ;
+;    |add_1:uut_add_mantovf|      ; 6.0 (6.0)            ; 6.0 (6.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (12)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_1:uut_add_mantovf                                    ; add_1           ; work         ;
+;    |add_N:uut_add_ulp|          ; 8.0 (0.0)            ; 8.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp                                        ; add_N           ; work         ;
+;       |add_N_in:a1|             ; 8.0 (8.0)            ; 8.0 (8.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp|add_N_in:a1                            ; add_N_in        ; work         ;
+;    |add_sub_N:uut_add_sub_N|    ; 11.5 (0.0)           ; 10.5 (0.0)                       ; 0.0 (0.0)                                         ; 1.0 (0.0)                        ; 0.0 (0.0)            ; 21 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N                                  ; add_sub_N       ; work         ;
+;       |add_N:a11|               ; 11.5 (0.0)           ; 10.5 (0.0)                       ; 0.0 (0.0)                                         ; 1.0 (0.0)                        ; 0.0 (0.0)            ; 21 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11                        ; add_N           ; work         ;
+;          |add_N_in:a1|          ; 11.5 (11.5)          ; 10.5 (10.5)                      ; 0.0 (0.0)                                         ; 1.0 (1.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1            ; add_N_in        ; work         ;
+;    |data_extract_v1:uut_de1|    ; 34.5 (2.0)           ; 35.5 (2.0)                       ; 1.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 51 (4)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 21.0 (21.0)          ; 21.0 (21.0)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 29 (29)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 11.5 (0.0)           ; 12.5 (0.0)                       ; 1.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 11.5 (9.5)           ; 12.5 (10.5)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (15)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 0.5 (0.0)            ; 0.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 1.5 (0.5)            ; 1.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 1.0 (1.0)            ; 1.0 (1.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |data_extract_v1:uut_de2|    ; 35.0 (2.5)           ; 35.5 (2.5)                       ; 0.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 52 (4)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 21.5 (21.5)          ; 21.5 (21.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 30 (30)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 11.0 (0.0)           ; 11.5 (0.0)                       ; 0.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 11.0 (9.5)           ; 11.5 (10.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (15)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 0.5 (0.0)            ; 0.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 1.0 (0.5)            ; 1.0 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |reg_exp_op:uut_reg_ro|      ; 2.5 (2.5)            ; 2.5 (2.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|reg_exp_op:uut_reg_ro                                    ; reg_exp_op      ; work         ;
+;    |sub_N:uut_ediff|            ; 4.0 (0.0)            ; 4.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 8 (0)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff                                          ; sub_N           ; work         ;
+;       |sub_N_in:s1|             ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 8 (8)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff|sub_N_in:s1                              ; sub_N_in        ; work         ;
++---------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                    ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name    ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; out[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[10] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[11] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[12] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[13] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[14] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; out[15] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; inf     ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; zero    ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; done    ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; in1[15] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[12] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[13] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[14] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[5]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[10] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[11] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[0]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[1]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[2]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[3]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[4]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[6]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[7]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[8]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in1[9]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[15] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[12] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[13] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[14] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[5]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[10] ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[11] ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[0]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[1]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[2]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[3]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[4]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[6]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[7]  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[8]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; in2[9]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; start   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                             ;
++--------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                          ; Pad To Core Index ; Setting ;
++--------------------------------------------------------------+-------------------+---------+
+; in1[15]                                                      ;                   ;         ;
+;      - Add0~45                                               ; 0                 ; 0       ;
+;      - Add0~41                                               ; 0                 ; 0       ;
+;      - Add0~37                                               ; 0                 ; 0       ;
+;      - Add0~29                                               ; 0                 ; 0       ;
+;      - Add0~33                                               ; 0                 ; 0       ;
+;      - Add0~49                                               ; 0                 ; 0       ;
+;      - Add0~53                                               ; 0                 ; 0       ;
+;      - Add0~57                                               ; 0                 ; 0       ;
+;      - Add0~25                                               ; 0                 ; 0       ;
+;      - Add0~21                                               ; 0                 ; 0       ;
+;      - Add0~17                                               ; 0                 ; 0       ;
+;      - Add0~5                                                ; 0                 ; 0       ;
+;      - Add0~9                                                ; 0                 ; 0       ;
+;      - Add0~13                                               ; 0                 ; 0       ;
+;      - Add0~1                                                ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~57 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~61 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~53 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~49 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~29 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~17 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~13 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~9  ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~5  ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~25 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~21 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~65 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~1  ; 0                 ; 0       ;
+;      - inf~0                                                 ; 0                 ; 0       ;
+;      - zero~0                                                ; 0                 ; 0       ;
+;      - ls~0                                                  ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~68 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~69 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~70 ; 0                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~71 ; 0                 ; 0       ;
+; in1[12]                                                      ;                   ;         ;
+;      - Add0~9                                                ; 1                 ; 0       ;
+;      - WideOr0                                               ; 1                 ; 0       ;
+; in1[13]                                                      ;                   ;         ;
+;      - Add0~13                                               ; 1                 ; 0       ;
+;      - WideOr0                                               ; 1                 ; 0       ;
+; in1[14]                                                      ;                   ;         ;
+;      - Add0~1                                                ; 1                 ; 0       ;
+;      - WideOr0                                               ; 1                 ; 0       ;
+; in1[5]                                                       ;                   ;         ;
+;      - Add0~49                                               ; 1                 ; 0       ;
+;      - WideOr0~2                                             ; 1                 ; 0       ;
+; in1[10]                                                      ;                   ;         ;
+;      - Add0~17                                               ; 0                 ; 0       ;
+;      - WideOr0~2                                             ; 0                 ; 0       ;
+; in1[11]                                                      ;                   ;         ;
+;      - Add0~5                                                ; 1                 ; 0       ;
+;      - WideOr0~2                                             ; 1                 ; 0       ;
+; in1[0]                                                       ;                   ;         ;
+;      - Add0~45                                               ; 0                 ; 0       ;
+;      - WideOr0~0                                             ; 0                 ; 0       ;
+; in1[1]                                                       ;                   ;         ;
+;      - Add0~41                                               ; 1                 ; 0       ;
+;      - WideOr0~0                                             ; 1                 ; 0       ;
+; in1[2]                                                       ;                   ;         ;
+;      - Add0~37                                               ; 0                 ; 0       ;
+;      - WideOr0~0                                             ; 0                 ; 0       ;
+; in1[3]                                                       ;                   ;         ;
+;      - Add0~29                                               ; 1                 ; 0       ;
+;      - WideOr0~0                                             ; 1                 ; 0       ;
+; in1[4]                                                       ;                   ;         ;
+;      - Add0~33                                               ; 0                 ; 0       ;
+;      - WideOr0~0                                             ; 0                 ; 0       ;
+; in1[6]                                                       ;                   ;         ;
+;      - Add0~53                                               ; 0                 ; 0       ;
+;      - WideOr0~1                                             ; 0                 ; 0       ;
+; in1[7]                                                       ;                   ;         ;
+;      - Add0~57                                               ; 1                 ; 0       ;
+;      - WideOr0~1                                             ; 1                 ; 0       ;
+; in1[8]                                                       ;                   ;         ;
+;      - Add0~25                                               ; 1                 ; 0       ;
+;      - WideOr0~1                                             ; 1                 ; 0       ;
+; in1[9]                                                       ;                   ;         ;
+;      - Add0~21                                               ; 1                 ; 0       ;
+;      - WideOr0~1                                             ; 1                 ; 0       ;
+; in2[15]                                                      ;                   ;         ;
+;      - Add1~45                                               ; 1                 ; 0       ;
+;      - Add1~41                                               ; 1                 ; 0       ;
+;      - Add1~37                                               ; 1                 ; 0       ;
+;      - Add1~29                                               ; 1                 ; 0       ;
+;      - Add1~33                                               ; 1                 ; 0       ;
+;      - Add1~49                                               ; 1                 ; 0       ;
+;      - Add1~53                                               ; 1                 ; 0       ;
+;      - Add1~57                                               ; 1                 ; 0       ;
+;      - Add1~25                                               ; 1                 ; 0       ;
+;      - Add1~21                                               ; 1                 ; 0       ;
+;      - Add1~17                                               ; 1                 ; 0       ;
+;      - Add1~5                                                ; 1                 ; 0       ;
+;      - Add1~9                                                ; 1                 ; 0       ;
+;      - Add1~13                                               ; 1                 ; 0       ;
+;      - Add1~1                                                ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~57 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~61 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~53 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~49 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~29 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~17 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~13 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~9  ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~5  ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~25 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~21 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~65 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~1  ; 1                 ; 0       ;
+;      - inf~0                                                 ; 1                 ; 0       ;
+;      - zero~0                                                ; 1                 ; 0       ;
+;      - ls~0                                                  ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~68 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~69 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~70 ; 1                 ; 0       ;
+;      - add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1|Add0~71 ; 1                 ; 0       ;
+; in2[12]                                                      ;                   ;         ;
+;      - Add1~9                                                ; 0                 ; 0       ;
+;      - WideOr1                                               ; 0                 ; 0       ;
+; in2[13]                                                      ;                   ;         ;
+;      - Add1~13                                               ; 1                 ; 0       ;
+;      - WideOr1                                               ; 1                 ; 0       ;
+; in2[14]                                                      ;                   ;         ;
+;      - Add1~1                                                ; 0                 ; 0       ;
+;      - WideOr1                                               ; 0                 ; 0       ;
+; in2[5]                                                       ;                   ;         ;
+;      - Add1~49                                               ; 1                 ; 0       ;
+;      - WideOr1~2                                             ; 1                 ; 0       ;
+; in2[10]                                                      ;                   ;         ;
+;      - Add1~17                                               ; 0                 ; 0       ;
+;      - WideOr1~2                                             ; 0                 ; 0       ;
+; in2[11]                                                      ;                   ;         ;
+;      - Add1~5                                                ; 1                 ; 0       ;
+;      - WideOr1~2                                             ; 1                 ; 0       ;
+; in2[0]                                                       ;                   ;         ;
+;      - Add1~45                                               ; 1                 ; 0       ;
+;      - WideOr1~0                                             ; 1                 ; 0       ;
+; in2[1]                                                       ;                   ;         ;
+;      - Add1~41                                               ; 1                 ; 0       ;
+;      - WideOr1~0                                             ; 1                 ; 0       ;
+; in2[2]                                                       ;                   ;         ;
+;      - Add1~37                                               ; 0                 ; 0       ;
+;      - WideOr1~0                                             ; 0                 ; 0       ;
+; in2[3]                                                       ;                   ;         ;
+;      - Add1~29                                               ; 1                 ; 0       ;
+;      - WideOr1~0                                             ; 1                 ; 0       ;
+; in2[4]                                                       ;                   ;         ;
+;      - Add1~33                                               ; 0                 ; 0       ;
+;      - WideOr1~0                                             ; 0                 ; 0       ;
+; in2[6]                                                       ;                   ;         ;
+;      - Add1~53                                               ; 1                 ; 0       ;
+;      - WideOr1~1                                             ; 1                 ; 0       ;
+; in2[7]                                                       ;                   ;         ;
+;      - Add1~57                                               ; 1                 ; 0       ;
+;      - WideOr1~1                                             ; 1                 ; 0       ;
+; in2[8]                                                       ;                   ;         ;
+;      - Add1~25                                               ; 0                 ; 0       ;
+;      - WideOr1~1                                             ; 0                 ; 0       ;
+; in2[9]                                                       ;                   ;         ;
+;      - Add1~21                                               ; 0                 ; 0       ;
+;      - WideOr1~1                                             ; 0                 ; 0       ;
+; start                                                        ;                   ;         ;
+;      - done~output                                           ; 1                 ; 0       ;
++--------------------------------------------------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 819 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 9 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 253 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 132 / 56,300 ( < 1 % )  ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 50 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 0 / 16 ( 0 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 135 / 84,580 ( < 1 % )  ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 14 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 14 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 307 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 410 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 0 / 360 ( 0 % )         ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                 ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 52        ; 0            ; 0            ; 52        ; 52        ; 0            ; 19           ; 0            ; 0            ; 0            ; 0            ; 19           ; 0            ; 0            ; 0            ; 0            ; 19           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 52           ; 52           ; 52           ; 52           ; 52           ; 0         ; 52           ; 52           ; 0         ; 0         ; 52           ; 33           ; 52           ; 52           ; 52           ; 52           ; 33           ; 52           ; 52           ; 52           ; 52           ; 33           ; 52           ; 52           ; 52           ; 52           ; 52           ; 52           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; out[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[8]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[9]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[10]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[11]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[12]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[13]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[14]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; out[15]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; inf                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; zero               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; done               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[15]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[12]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[13]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[14]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[10]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[11]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[8]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1[9]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[15]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[12]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[13]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[14]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[5]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[10]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[11]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[0]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[1]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[2]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[3]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[4]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[6]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[7]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[8]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in2[9]             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; start              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "posit-add"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 52 pins of 52 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'posit-add.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:19
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X45_Y0 to location X55_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Info (144001): Generated suppressed messages file H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 6740 megabytes
+    Info: Processing ended: Tue Feb 14 20:10:31 2023
+    Info: Elapsed time: 00:00:57
+    Info: Total CPU time (on all processors): 00:00:57
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/output_files/posit-add.fit.smsg.
+
+
diff --git a/Reference Code/add/output_files/posit-add.fit.smsg b/Reference Code/add/output_files/posit-add.fit.smsg
new file mode 100644
index 0000000000000000000000000000000000000000..930291945870c27fa8ede0009c58b1d66c8d95a3
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.fit.smsg	
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/Reference Code/add/output_files/posit-add.fit.summary b/Reference Code/add/output_files/posit-add.fit.summary
new file mode 100644
index 0000000000000000000000000000000000000000..d0ee3646426b655d271239bd610025d762e8040d
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.fit.summary	
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Feb 14 20:10:31 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : posit-add
+Top-level Entity Name : posit_add
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 337 / 32,070 ( 1 % )
+Total registers : 0
+Total pins : 52 / 457 ( 11 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/Reference Code/add/output_files/posit-add.flow.rpt b/Reference Code/add/output_files/posit-add.flow.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..1d8afc642077efd591734e92a15cd13221ae9e0b
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.flow.rpt	
@@ -0,0 +1,137 @@
+Flow report for posit-add
+Tue Feb 14 20:10:46 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++---------------------------------+------------------------------------------------+
+; Flow Status                     ; Successful - Tue Feb 14 20:10:46 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; posit-add                                      ;
+; Top-level Entity Name           ; posit_add                                      ;
+; Family                          ; Cyclone V                                      ;
+; Device                          ; 5CSEMA5F31C6                                   ;
+; Timing Models                   ; Final                                          ;
+; Logic utilization (in ALMs)     ; 337 / 32,070 ( 1 % )                           ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 52 / 457 ( 11 % )                              ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                          ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                 ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                  ;
++---------------------------------+------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/14/2023 20:09:24 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; posit-add           ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                               ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID               ; 1099276844422.167640536433692          ; --            ; --          ; --                                ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
+; EDA_SIMULATION_TOOL                 ; Questa Intel FPGA (Verilog)            ; <None>        ; --          ; --                                ;
+; EDA_TIME_SCALE                      ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --                                ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --                                ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top                               ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top                               ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; posit_add   ; Top                               ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --                                ;
+; TOP_LEVEL_ENTITY                    ; posit_add                              ; posit-add     ; --          ; --                                ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10     ; 1.0                     ; 4838 MB             ; 00:00:11                           ;
+; Fitter               ; 00:00:57     ; 1.0                     ; 6740 MB             ; 00:00:57                           ;
+; Assembler            ; 00:00:06     ; 1.0                     ; 4880 MB             ; 00:00:03                           ;
+; Timing Analyzer      ; 00:00:04     ; 1.3                     ; 5176 MB             ; 00:00:04                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 4733 MB             ; 00:00:01                           ;
+; Total                ; 00:01:18     ; --                      ; --                  ; 00:01:16                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
+; Fitter               ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
+; Assembler            ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
+; Timing Analyzer      ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
+; EDA Netlist Writer   ; Jaspers-OMEN     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add
+quartus_fit --read_settings_files=off --write_settings_files=off posit-add -c posit-add
+quartus_asm --read_settings_files=off --write_settings_files=off posit-add -c posit-add
+quartus_sta posit-add -c posit-add
+quartus_eda --read_settings_files=off --write_settings_files=off posit-add -c posit-add
+
+
+
diff --git a/Reference Code/add/output_files/posit-add.jdi b/Reference Code/add/output_files/posit-add.jdi
new file mode 100644
index 0000000000000000000000000000000000000000..713dfdb286343d8e1c5a7edbae975f0552beb0c7
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.jdi	
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="d7b96d5378a42b1c5af4"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="posit-add.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/Reference Code/add/output_files/posit-add.map.rpt b/Reference Code/add/output_files/posit-add.map.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5df554371a057fe92668f2dfd09a28e93b89b8a9
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.map.rpt	
@@ -0,0 +1,1409 @@
+Analysis & Synthesis report for posit-add
+Tue Feb 14 20:09:33 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 10. Parameter Settings for User Entity Instance: Top-level Entity: |posit_add
+ 11. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1
+ 12. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k
+ 13. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1
+ 14. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l
+ 15. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+ 16. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+ 17. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+ 18. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+ 19. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+ 20. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+ 21. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h
+ 22. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+ 23. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+ 24. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+ 25. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+ 26. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+ 27. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+ 28. Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|DSR_left_N_S:ls
+ 29. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2
+ 30. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k
+ 31. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1
+ 32. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l
+ 33. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l
+ 34. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l
+ 35. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h
+ 36. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h
+ 37. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l
+ 38. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h
+ 39. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h
+ 40. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l
+ 41. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l
+ 42. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h
+ 43. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h
+ 44. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l
+ 45. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h
+ 46. Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|DSR_left_N_S:ls
+ 47. Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime1
+ 48. Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime2
+ 49. Parameter Settings for User Entity Instance: sub_N:uut_ediff
+ 50. Parameter Settings for User Entity Instance: sub_N:uut_ediff|sub_N_in:s1
+ 51. Parameter Settings for User Entity Instance: DSR_right_N_S:dsr1
+ 52. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N
+ 53. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11
+ 54. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1
+ 55. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11
+ 56. Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1
+ 57. Parameter Settings for User Entity Instance: LOD_N:l2
+ 58. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1
+ 59. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l
+ 60. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l
+ 61. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l
+ 62. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h
+ 63. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h
+ 64. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l
+ 65. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h
+ 66. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h
+ 67. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l
+ 68. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l
+ 69. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h
+ 70. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h
+ 71. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l
+ 72. Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h
+ 73. Parameter Settings for User Entity Instance: DSR_left_N_S:dsl1
+ 74. Parameter Settings for User Entity Instance: sub_N:sub3
+ 75. Parameter Settings for User Entity Instance: sub_N:sub3|sub_N_in:s1
+ 76. Parameter Settings for User Entity Instance: add_1:uut_add_mantovf
+ 77. Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro
+ 78. Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1
+ 79. Parameter Settings for User Entity Instance: DSR_right_N_S:dsr2
+ 80. Parameter Settings for User Entity Instance: add_N:uut_add_ulp
+ 81. Parameter Settings for User Entity Instance: add_N:uut_add_ulp|add_N_in:a1
+ 82. Port Connectivity Checks: "add_N:uut_add_ulp"
+ 83. Port Connectivity Checks: "DSR_right_N_S:dsr2"
+ 84. Port Connectivity Checks: "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1"
+ 85. Port Connectivity Checks: "add_1:uut_add_mantovf"
+ 86. Port Connectivity Checks: "sub_N:sub3"
+ 87. Port Connectivity Checks: "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1"
+ 88. Port Connectivity Checks: "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1"
+ 89. Port Connectivity Checks: "add_sub_N:uut_add_sub_N"
+ 90. Port Connectivity Checks: "DSR_right_N_S:dsr1"
+ 91. Port Connectivity Checks: "sub_N:uut_ediff|sub_N_in:s1"
+ 92. Port Connectivity Checks: "sub_N:uut_ediff"
+ 93. Port Connectivity Checks: "data_extract_v1:uut_de1|DSR_left_N_S:ls"
+ 94. Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1"
+ 95. Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k"
+ 96. Post-Synthesis Netlist Statistics for Top Partition
+ 97. Elapsed Time Per Partition
+ 98. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++---------------------------------+------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Feb 14 20:09:33 2023          ;
+; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Revision Name                   ; posit-add                                      ;
+; Top-level Entity Name           ; posit_add                                      ;
+; Family                          ; Cyclone V                                      ;
+; Logic utilization (in ALMs)     ; N/A                                            ;
+; Total registers                 ; 0                                              ;
+; Total pins                      ; 52                                             ;
+; Total virtual pins              ; 0                                              ;
+; Total block memory bits         ; 0                                              ;
+; Total DSP Blocks                ; 0                                              ;
+; Total HSSI RX PCSs              ; 0                                              ;
+; Total HSSI PMA RX Deserializers ; 0                                              ;
+; Total HSSI TX PCSs              ; 0                                              ;
+; Total HSSI PMA TX Serializers   ; 0                                              ;
+; Total PLLs                      ; 0                                              ;
+; Total DLLs                      ; 0                                              ;
++---------------------------------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; posit_add          ; posit-add          ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                             ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                               ; Library ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+; posit_add.v                      ; yes             ; User Verilog HDL File  ; H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v ;         ;
++----------------------------------+-----------------+------------------------+------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                  ;
++---------------------------------------------+--------------------------------+
+; Resource                                    ; Usage                          ;
++---------------------------------------------+--------------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 337                            ;
+;                                             ;                                ;
+; Combinational ALUT usage for logic          ; 505                            ;
+;     -- 7 input functions                    ; 4                              ;
+;     -- 6 input functions                    ; 165                            ;
+;     -- 5 input functions                    ; 85                             ;
+;     -- 4 input functions                    ; 117                            ;
+;     -- <=3 input functions                  ; 134                            ;
+;                                             ;                                ;
+; Dedicated logic registers                   ; 0                              ;
+;                                             ;                                ;
+; I/O pins                                    ; 52                             ;
+;                                             ;                                ;
+; Total DSP Blocks                            ; 0                              ;
+;                                             ;                                ;
+; Maximum fan-out node                        ; reg_exp_op:uut_reg_ro|r_o[3]~1 ;
+; Maximum fan-out                             ; 59                             ;
+; Total fan-out                               ; 2389                           ;
+; Average fan-out                             ; 3.92                           ;
++---------------------------------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                             ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node      ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                 ; Entity Name     ; Library Name ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+; |posit_add                      ; 505 (165)           ; 0 (0)                     ; 0                 ; 0          ; 52   ; 0            ; |posit_add                                                          ; posit_add       ; work         ;
+;    |DSR_left_N_S:dsl1|          ; 25 (25)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_left_N_S:dsl1                                        ; DSR_left_N_S    ; work         ;
+;    |DSR_right_N_S:dsr1|         ; 45 (45)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr1                                       ; DSR_right_N_S   ; work         ;
+;    |DSR_right_N_S:dsr2|         ; 62 (62)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|DSR_right_N_S:dsr2                                       ; DSR_right_N_S   ; work         ;
+;    |LOD_N:l2|                   ; 30 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2                                                 ; LOD_N           ; work         ;
+;       |LOD:l1|                  ; 30 (27)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1                                          ; LOD             ; work         ;
+;          |LOD:h|                ; 2 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h                              ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l                        ; LOD             ; work         ;
+;             |LOD:l|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l                              ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h                        ; LOD             ; work         ;
+;          |LOD:l|                ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l                                    ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|LOD_N:l2|LOD:l1|LOD:l|LOD:h                              ; LOD             ; work         ;
+;    |abs_regime:uut_abs_regime1| ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime1                               ; abs_regime      ; work         ;
+;    |abs_regime:uut_abs_regime2| ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|abs_regime:uut_abs_regime2                               ; abs_regime      ; work         ;
+;    |add_1:uut_add_mantovf|      ; 12 (12)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_1:uut_add_mantovf                                    ; add_1           ; work         ;
+;    |add_N:uut_add_ulp|          ; 16 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp                                        ; add_N           ; work         ;
+;       |add_N_in:a1|             ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_N:uut_add_ulp|add_N_in:a1                            ; add_N_in        ; work         ;
+;    |add_sub_N:uut_add_sub_N|    ; 21 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N                                  ; add_sub_N       ; work         ;
+;       |add_N:a11|               ; 21 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11                        ; add_N           ; work         ;
+;          |add_N_in:a1|          ; 21 (21)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1            ; add_N_in        ; work         ;
+;    |data_extract_v1:uut_de1|    ; 51 (4)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 29 (29)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 18 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 18 (15)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 2 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |data_extract_v1:uut_de2|    ; 52 (4)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2                                  ; data_extract_v1 ; work         ;
+;       |DSR_left_N_S:ls|         ; 30 (30)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls                  ; DSR_left_N_S    ; work         ;
+;       |LOD_N:xinst_k|           ; 18 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k                    ; LOD_N           ; work         ;
+;          |LOD:l1|               ; 18 (15)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1             ; LOD             ; work         ;
+;             |LOD:h|             ; 1 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h       ; LOD             ; work         ;
+;                |LOD:l|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ; LOD             ; work         ;
+;             |LOD:l|             ; 2 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l       ; LOD             ; work         ;
+;                |LOD:h|          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ; LOD             ; work         ;
+;    |reg_exp_op:uut_reg_ro|      ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|reg_exp_op:uut_reg_ro                                    ; reg_exp_op      ; work         ;
+;    |sub_N:uut_ediff|            ; 8 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff                                          ; sub_N           ; work         ;
+;       |sub_N_in:s1|             ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |posit_add|sub_N:uut_ediff|sub_N_in:s1                              ; sub_N_in        ; work         ;
++---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                              ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|tmp[1][7]  ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[3]       ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[7]       ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[10]      ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|tmp[1][11] ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[5]       ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[9]       ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[11]      ;
+; 4:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[0][5]                       ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][14]                      ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][12]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][10]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|tmp[2][9]                       ;
+; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|tmp[1][4]                        ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|c[10]                            ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |posit_add|tmp_o[7]                                           ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[1][23]                      ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[1][19]                      ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[2][29]                      ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[5]                            ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[7]                            ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[34]                           ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[27]                           ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[13]                           ;
+; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|c[16]                           ;
+; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |posit_add|out                                                ;
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr2|tmp[0][27]                      ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|c[0]                            ;
+; 5:1                ; 6 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_right_N_S:dsr1|c[3]                            ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[12]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de2|DSR_left_N_S:ls|c[14]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[12]      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |posit_add|data_extract_v1:uut_de1|DSR_left_N_S:ls|c[15]      ;
+; 7:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |posit_add|DSR_left_N_S:dsl1|c[12]                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |posit_add ;
++----------------+----------------------------------+-----------------------+
+; Parameter Name ; Value                            ; Type                  ;
++----------------+----------------------------------+-----------------------+
+; N              ; 16                               ; Signed Integer        ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary       ;
+; es             ; 2                                ; Signed Integer        ;
++----------------+----------------------------------+-----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1 ;
++----------------+----------------------------------+------------------+
+; Parameter Name ; Value                            ; Type             ;
++----------------+----------------------------------+------------------+
+; N              ; 16                               ; Signed Integer   ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary  ;
+; es             ; 2                                ; Signed Integer   ;
++----------------+----------------------------------+------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k ;
++----------------+----------------------------------+--------------------------------+
+; Parameter Name ; Value                            ; Type                           ;
++----------------+----------------------------------+--------------------------------+
+; N              ; 16                               ; Signed Integer                 ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                ;
++----------------+----------------------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1 ;
++----------------+----------------------------------+---------------------------------------+
+; Parameter Name ; Value                            ; Type                                  ;
++----------------+----------------------------------+---------------------------------------+
+; N              ; 16                               ; Signed Integer                        ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                       ;
++----------------+----------------------------------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de1|DSR_left_N_S:ls ;
++----------------+----------------------------------+----------------------------------+
+; Parameter Name ; Value                            ; Type                             ;
++----------------+----------------------------------+----------------------------------+
+; N              ; 16                               ; Signed Integer                   ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                  ;
++----------------+----------------------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2 ;
++----------------+----------------------------------+------------------+
+; Parameter Name ; Value                            ; Type             ;
++----------------+----------------------------------+------------------+
+; N              ; 16                               ; Signed Integer   ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary  ;
+; es             ; 2                                ; Signed Integer   ;
++----------------+----------------------------------+------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k ;
++----------------+----------------------------------+--------------------------------+
+; Parameter Name ; Value                            ; Type                           ;
++----------------+----------------------------------+--------------------------------+
+; N              ; 16                               ; Signed Integer                 ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                ;
++----------------+----------------------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1 ;
++----------------+----------------------------------+---------------------------------------+
+; Parameter Name ; Value                            ; Type                                  ;
++----------------+----------------------------------+---------------------------------------+
+; N              ; 16                               ; Signed Integer                        ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                       ;
++----------------+----------------------------------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h ;
++----------------+----------------------------------+---------------------------------------------+
+; Parameter Name ; Value                            ; Type                                        ;
++----------------+----------------------------------+---------------------------------------------+
+; N              ; 8                                ; Signed Integer                              ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary                             ;
++----------------+----------------------------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                              ;
++----------------+----------------------------------+---------------------------------------------------+
+; N              ; 4                                ; Signed Integer                                    ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary                                   ;
++----------------+----------------------------------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|LOD_N:xinst_k|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+---------------------------------------------------------+
+; Parameter Name ; Value                            ; Type                                                    ;
++----------------+----------------------------------+---------------------------------------------------------+
+; N              ; 2                                ; Signed Integer                                          ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary                                         ;
++----------------+----------------------------------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: data_extract_v1:uut_de2|DSR_left_N_S:ls ;
++----------------+----------------------------------+----------------------------------+
+; Parameter Name ; Value                            ; Type                             ;
++----------------+----------------------------------+----------------------------------+
+; N              ; 16                               ; Signed Integer                   ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary                  ;
++----------------+----------------------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime1 ;
++----------------+----------------------------------+---------------------+
+; Parameter Name ; Value                            ; Type                ;
++----------------+----------------------------------+---------------------+
+; N              ; 00000000000000000000000000000100 ; Unsigned Binary     ;
++----------------+----------------------------------+---------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: abs_regime:uut_abs_regime2 ;
++----------------+----------------------------------+---------------------+
+; Parameter Name ; Value                            ; Type                ;
++----------------+----------------------------------+---------------------+
+; N              ; 00000000000000000000000000000100 ; Unsigned Binary     ;
++----------------+----------------------------------+---------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:uut_ediff        ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:uut_ediff|sub_N_in:s1 ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_right_N_S:dsr1     ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N ;
++----------------+-------+---------------------------------------------+
+; Parameter Name ; Value ; Type                                        ;
++----------------+-------+---------------------------------------------+
+; N              ; 16    ; Signed Integer                              ;
++----------------+-------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11 ;
++----------------+-------+-------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                  ;
++----------------+-------+-------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                        ;
++----------------+-------+-------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1 ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                              ;
++----------------+-------+-------------------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                                    ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11 ;
++----------------+-------+-------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                  ;
++----------------+-------+-------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                        ;
++----------------+-------+-------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1 ;
++----------------+-------+-------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                              ;
++----------------+-------+-------------------------------------------------------------------+
+; N              ; 16    ; Signed Integer                                                    ;
++----------------+-------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2               ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1        ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 8                                ; Signed Integer  ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:l|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 8                                ; Signed Integer  ;
+; S              ; 00000000000000000000000000000011 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:l|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------+
+; Parameter Name ; Value                            ; Type                 ;
++----------------+----------------------------------+----------------------+
+; N              ; 4                                ; Signed Integer       ;
+; S              ; 00000000000000000000000000000010 ; Unsigned Binary      ;
++----------------+----------------------------------+----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:l ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: LOD_N:l2|LOD:l1|LOD:h|LOD:h|LOD:h ;
++----------------+----------------------------------+----------------------------+
+; Parameter Name ; Value                            ; Type                       ;
++----------------+----------------------------------+----------------------------+
+; N              ; 2                                ; Signed Integer             ;
+; S              ; 00000000000000000000000000000001 ; Unsigned Binary            ;
++----------------+----------------------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_left_N_S:dsl1      ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 16                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:sub3             ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sub_N:sub3|sub_N_in:s1 ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_1:uut_add_mantovf  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 00000000000000000000000000000111 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro  ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; es             ; 2                                ; Signed Integer  ;
+; Bs             ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1 ;
++----------------+----------------------------------+-------------------------------------+
+; Parameter Name ; Value                            ; Type                                ;
++----------------+----------------------------------+-------------------------------------+
+; N              ; 00000000000000000000000000000110 ; Unsigned Binary                     ;
++----------------+----------------------------------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DSR_right_N_S:dsr2     ;
++----------------+----------------------------------+-----------------+
+; Parameter Name ; Value                            ; Type            ;
++----------------+----------------------------------+-----------------+
+; N              ; 51                               ; Signed Integer  ;
+; S              ; 00000000000000000000000000000100 ; Unsigned Binary ;
++----------------+----------------------------------+-----------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_N:uut_add_ulp ;
++----------------+-------+---------------------------------------+
+; Parameter Name ; Value ; Type                                  ;
++----------------+-------+---------------------------------------+
+; N              ; 16    ; Signed Integer                        ;
++----------------+-------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: add_N:uut_add_ulp|add_N_in:a1 ;
++----------------+-------+---------------------------------------------------+
+; Parameter Name ; Value ; Type                                              ;
++----------------+-------+---------------------------------------------------+
+; N              ; 16    ; Signed Integer                                    ;
++----------------+-------+---------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_N:uut_add_ulp"                                                                      ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; b[15..1] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; c[16]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DSR_right_N_S:dsr2"                                                                      ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port      ; Type   ; Severity ; Details                                                                             ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+; a[16..0]  ; Input  ; Info     ; Stuck at GND                                                                        ;
+; c[50..35] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1"                                         ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[6] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_1:uut_add_mantovf"                                                              ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------+
+; Port Connectivity Checks: "sub_N:sub3"    ;
++---------+-------+----------+--------------+
+; Port    ; Type  ; Severity ; Details      ;
++---------+-------+----------+--------------+
+; b[6..4] ; Input ; Info     ; Stuck at GND ;
++---------+-------+----------+--------------+
+
+
++---------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1" ;
++-------+-------+----------+------------------------------------------------+
+; Port  ; Type  ; Severity ; Details                                        ;
++-------+-------+----------+------------------------------------------------+
+; a[16] ; Input ; Info     ; Stuck at GND                                   ;
+; b[16] ; Input ; Info     ; Stuck at GND                                   ;
++-------+-------+----------+------------------------------------------------+
+
+
++---------------------------------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1" ;
++-------+-------+----------+------------------------------------------------+
+; Port  ; Type  ; Severity ; Details                                        ;
++-------+-------+----------+------------------------------------------------+
+; a[16] ; Input ; Info     ; Stuck at GND                                   ;
+; b[16] ; Input ; Info     ; Stuck at GND                                   ;
++-------+-------+----------+------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Port Connectivity Checks: "add_sub_N:uut_add_sub_N" ;
++------+-------+----------+---------------------------+
+; Port ; Type  ; Severity ; Details                   ;
++------+-------+----------+---------------------------+
+; a[0] ; Input ; Info     ; Stuck at GND              ;
++------+-------+----------+---------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "DSR_right_N_S:dsr1" ;
++------+-------+----------+----------------------+
+; Port ; Type  ; Severity ; Details              ;
++------+-------+----------+----------------------+
+; a[0] ; Input ; Info     ; Stuck at GND         ;
++------+-------+----------+----------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "sub_N:uut_ediff|sub_N_in:s1" ;
++------+-------+----------+-------------------------------+
+; Port ; Type  ; Severity ; Details                       ;
++------+-------+----------+-------------------------------+
+; a[7] ; Input ; Info     ; Stuck at GND                  ;
+; b[7] ; Input ; Info     ; Stuck at GND                  ;
++------+-------+----------+-------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "sub_N:uut_ediff"                                                                    ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; c[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|DSR_left_N_S:ls" ;
++---------+-------+----------+----------------------------------------+
+; Port    ; Type  ; Severity ; Details                                ;
++---------+-------+----------+----------------------------------------+
+; a[1..0] ; Input ; Info     ; Stuck at GND                           ;
++---------+-------+----------+----------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1"                                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; vld  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Port Connectivity Checks: "data_extract_v1:uut_de1|LOD_N:xinst_k" ;
++--------+-------+----------+---------------------------------------+
+; Port   ; Type  ; Severity ; Details                               ;
++--------+-------+----------+---------------------------------------+
+; in[15] ; Input ; Info     ; Stuck at GND                          ;
++--------+-------+----------+---------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb     ; 506                         ;
+;     arith             ; 94                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 6                           ;
+;         2 data inputs ; 34                          ;
+;         3 data inputs ; 10                          ;
+;         4 data inputs ; 20                          ;
+;         5 data inputs ; 23                          ;
+;     extend            ; 4                           ;
+;         7 data inputs ; 4                           ;
+;     normal            ; 408                         ;
+;         1 data inputs ; 1                           ;
+;         2 data inputs ; 31                          ;
+;         3 data inputs ; 52                          ;
+;         4 data inputs ; 97                          ;
+;         5 data inputs ; 62                          ;
+;         6 data inputs ; 165                         ;
+; boundary_port         ; 52                          ;
+;                       ;                             ;
+; Max LUT depth         ; 29.80                       ;
+; Average LUT depth     ; 28.49                       ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 20:09:23 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off posit-add -c posit-add
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (12021): Found 15 design units, including 15 entities, in source file posit_add.v
+    Info (12023): Found entity 1: posit_add File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 2
+    Info (12023): Found entity 2: data_extract_v1 File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 155
+    Info (12023): Found entity 3: sub_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 194
+    Info (12023): Found entity 4: add_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 204
+    Info (12023): Found entity 5: sub_N_in File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 214
+    Info (12023): Found entity 6: add_N_in File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 222
+    Info (12023): Found entity 7: add_sub_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 230
+    Info (12023): Found entity 8: add_1 File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 243
+    Info (12023): Found entity 9: abs_regime File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 252
+    Info (12023): Found entity 10: conv_2c File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 262
+    Info (12023): Found entity 11: reg_exp_op File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 269
+    Info (12023): Found entity 12: DSR_left_N_S File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 285
+    Info (12023): Found entity 13: DSR_right_N_S File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 306
+    Info (12023): Found entity 14: LOD_N File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 327
+    Info (12023): Found entity 15: LOD File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 348
+Info (12127): Elaborating entity "posit_add" for the top level hierarchy
+Info (12128): Elaborating entity "data_extract_v1" for hierarchy "data_extract_v1:uut_de1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 42
+Warning (10230): Verilog HDL assignment warning at posit_add.v(183): truncated value with size 32 to match size of target (4) File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 183
+Info (12128): Elaborating entity "LOD_N" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 181
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 344
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "LOD" for hierarchy "data_extract_v1:uut_de1|LOD_N:xinst_k|LOD:l1|LOD:l|LOD:l|LOD:l" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 380
+Info (12128): Elaborating entity "DSR_left_N_S" for hierarchy "data_extract_v1:uut_de1|DSR_left_N_S:ls" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 186
+Info (12128): Elaborating entity "abs_regime" for hierarchy "abs_regime:uut_abs_regime1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 70
+Info (12128): Elaborating entity "sub_N" for hierarchy "sub_N:uut_ediff" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 72
+Info (12128): Elaborating entity "sub_N_in" for hierarchy "sub_N:uut_ediff|sub_N_in:s1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 200
+Info (12128): Elaborating entity "DSR_right_N_S" for hierarchy "DSR_right_N_S:dsr1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 86
+Info (12128): Elaborating entity "add_sub_N" for hierarchy "add_sub_N:uut_add_sub_N" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 98
+Info (12128): Elaborating entity "add_N" for hierarchy "add_sub_N:uut_add_sub_N|add_N:a11" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 237
+Info (12128): Elaborating entity "add_N_in" for hierarchy "add_sub_N:uut_add_sub_N|add_N:a11|add_N_in:a1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 210
+Info (12128): Elaborating entity "sub_N" for hierarchy "add_sub_N:uut_add_sub_N|sub_N:s11" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 238
+Info (12128): Elaborating entity "sub_N_in" for hierarchy "add_sub_N:uut_add_sub_N|sub_N:s11|sub_N_in:s1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 200
+Info (12128): Elaborating entity "add_1" for hierarchy "add_1:uut_add_mantovf" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 115
+Info (12128): Elaborating entity "reg_exp_op" for hierarchy "reg_exp_op:uut_reg_ro" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 119
+Warning (10230): Verilog HDL assignment warning at posit_add.v(281): truncated value with size 32 to match size of target (4) File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 281
+Info (12128): Elaborating entity "conv_2c" for hierarchy "reg_exp_op:uut_reg_ro|conv_2c:uut_conv_2c1" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 279
+Info (12128): Elaborating entity "DSR_right_N_S" for hierarchy "DSR_right_N_S:dsr2" File: H:/INDIVIDUAL PROJECT/Posit/Reference Code/add/posit_add.v Line: 134
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 557 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 33 input pins
+    Info (21059): Implemented 19 output pins
+    Info (21061): Implemented 505 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 4838 megabytes
+    Info: Processing ended: Tue Feb 14 20:09:33 2023
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:11
+
+
diff --git a/Reference Code/add/output_files/posit-add.map.summary b/Reference Code/add/output_files/posit-add.map.summary
new file mode 100644
index 0000000000000000000000000000000000000000..41d1f78cc751c5c64c885f636413d1b0eecf3fe0
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.map.summary	
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Feb 14 20:09:33 2023
+Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+Revision Name : posit-add
+Top-level Entity Name : posit_add
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 52
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/Reference Code/add/output_files/posit-add.pin b/Reference Code/add/output_files/posit-add.pin
new file mode 100644
index 0000000000000000000000000000000000000000..ee6ad9adbea70a13ed0a26996b491cf55804e53b
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.pin	
@@ -0,0 +1,977 @@
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       2.5V
+ --                  Bank 4A:       2.5V
+ --                  Bank 5A:       2.5V
+ --                  Bank 5B:       2.5V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+CHIP  "posit-add"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+out[1]                       : AA14      : output : 2.5 V             :         : 3B        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+out[8]                       : AA16      : output : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AA17      : power  :                   : 2.5V    : 4A        :                
+out[9]                       : AA18      : output : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+in1[1]                       : AA21      : input  : 2.5 V             :         : 4A        : N              
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 2.5V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+out[12]                      : AB17      : output : 2.5 V             :         : 4A        : N              
+VCCPD3B4A                    : AB18      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB23      :        :                   :         : 5A        :                
+VCCIO5A                      : AB24      : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 2.5V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 2.5V    : 3B, 4A    :                
+inf                          : AC18      : output : 2.5 V             :         : 4A        : N              
+VCCPD3B4A                    : AC19      : power  :                   : 2.5V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30      :        :                   :         : 5B        :                
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 2.5V    : 3B, 4A    :                
+in2[4]                       : AD17      : input  : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AD18      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
+start                        : AD27      : input  : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : AD28      : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30      :        :                   :         : 5B        :                
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 2.5V    : 3B        :                
+in1[0]                       : AE16      : input  : 2.5 V             :         : 4A        : N              
+in1[3]                       : AE17      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 2.5V    : 3B, 4A    :                
+in1[5]                       : AE22      : input  : 2.5 V             :         : 4A        : N              
+in2[13]                      : AE23      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE27      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE28      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29      :        :                   :         : 5B        :                
+VCCIO5B                      : AE30      : power  :                   : 2.5V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+out[3]                       : AF16      : output : 2.5 V             :         : 4A        : N              
+GND                          : AF17      : gnd    :                   :         :           :                
+out[5]                       : AF18      : output : 2.5 V             :         : 4A        : N              
+in2[5]                       : AF19      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+out[6]                       : AF21      : output : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AF22      : power  :                   : 2.5V    : 4A        :                
+in2[8]                       : AF23      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF28      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF29      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF30      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+out[10]                      : AG15      : output : 2.5 V             :         : 3B        : N              
+in1[2]                       : AG16      : input  : 2.5 V             :         : 4A        : N              
+out[11]                      : AG17      : output : 2.5 V             :         : 4A        : N              
+in1[9]                       : AG18      : input  : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AG19      : power  :                   : 2.5V    : 4A        :                
+in2[10]                      : AG20      : input  : 2.5 V             :         : 4A        : N              
+out[15]                      : AG21      : output : 2.5 V             :         : 4A        : N              
+in2[15]                      : AG22      : input  : 2.5 V             :         : 4A        : N              
+in2[14]                      : AG23      : input  : 2.5 V             :         : 4A        : N              
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG27      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG28      :        :                   :         : 5A        :                
+VCCIO5A                      : AG29      : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG30      :        :                   :         : 5A        :                
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+in1[10]                      : AH12      : input  : 2.5 V             :         : 3B        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 2.5V    : 4A        :                
+in2[7]                       : AH17      : input  : 2.5 V             :         : 4A        : N              
+in1[7]                       : AH18      : input  : 2.5 V             :         : 4A        : N              
+in1[15]                      : AH19      : input  : 2.5 V             :         : 4A        : N              
+zero                         : AH20      : output : 2.5 V             :         : 4A        : N              
+GND                          : AH21      : gnd    :                   :         :           :                
+in2[6]                       : AH22      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+in1[6]                       : AH24      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH28      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH29      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH30      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+out[0]                       : AJ16      : output : 2.5 V             :         : 4A        : N              
+in2[9]                       : AJ17      : input  : 2.5 V             :         : 4A        : N              
+GND                          : AJ18      : gnd    :                   :         :           :                
+in1[13]                      : AJ19      : input  : 2.5 V             :         : 4A        : N              
+in1[14]                      : AJ20      : input  : 2.5 V             :         : 4A        : N              
+in2[1]                       : AJ21      : input  : 2.5 V             :         : 4A        : N              
+in2[0]                       : AJ22      : input  : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AJ23      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29      :        :                   :         : 5A        :                
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 2.5V    : 3B        :                
+in1[4]                       : AK11      : input  : 2.5 V             :         : 3B        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+out[7]                       : AK14      : output : 2.5 V             :         : 3B        : N              
+GND                          : AK15      : gnd    :                   :         :           :                
+in1[8]                       : AK16      : input  : 2.5 V             :         : 4A        : N              
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+in2[12]                      : AK18      : input  : 2.5 V             :         : 4A        : N              
+out[13]                      : AK19      : output : 2.5 V             :         : 4A        : N              
+VCCIO4A                      : AK20      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+in2[11]                      : AK22      : input  : 2.5 V             :         : 4A        : N              
+in1[12]                      : AK23      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 2.5V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+in2[2]                       : V16       : input  : 2.5 V             :         : 4A        : N              
+out[14]                      : V17       : output : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
+VCCPD5A                      : V24       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+out[4]                       : W15       : output : 2.5 V             :         : 3B        : N              
+out[2]                       : W16       : output : 2.5 V             :         : 4A        : N              
+in2[3]                       : W17       : input  : 2.5 V             :         : 4A        : N              
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+done                         : W21       : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
+VCCIO5A                      : W23       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+in1[11]                      : Y16       : input  : 2.5 V             :         : 3B        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/Reference Code/add/output_files/posit-add.sld b/Reference Code/add/output_files/posit-add.sld
new file mode 100644
index 0000000000000000000000000000000000000000..f7d3ed7cc6abd95c50005b31855c0eec845cbeed
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.sld	
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/Reference Code/add/output_files/posit-add.sof b/Reference Code/add/output_files/posit-add.sof
new file mode 100644
index 0000000000000000000000000000000000000000..7ec76f30f293153e93323474f562ae5b89a9448a
Binary files /dev/null and b/Reference Code/add/output_files/posit-add.sof differ
diff --git a/Reference Code/add/output_files/posit-add.sta.rpt b/Reference Code/add/output_files/posit-add.sta.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..411e772c06d911829be73c3f7fa7d515f1870ece
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.sta.rpt	
@@ -0,0 +1,707 @@
+Timing Analyzer report for posit-add
+Tue Feb 14 20:10:44 2023
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++--------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                        ;
++-----------------------+--------------------------------------------------------+
+; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                                 ;
+; Revision Name         ; posit-add                                              ;
+; Device Family         ; Cyclone V                                              ;
+; Device Name           ; 5CSEMA5F31C6                                           ;
+; Timing Models         ; Final                                                  ;
+; Delay Model           ; Combined                                               ;
+; Rise/Fall Delays      ; Enabled                                                ;
++-----------------------+--------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 12          ;
+; Maximum allowed            ; 6           ;
+;                            ;             ;
+; Average used               ; 1.35        ;
+; Maximum used               ; 6           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   7.0%      ;
+;     Processor 3            ;   7.0%      ;
+;     Processor 4            ;   7.0%      ;
+;     Processor 5            ;   7.0%      ;
+;     Processor 6            ;   7.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; out[0]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[1]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[2]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[3]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[4]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[5]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[6]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[7]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[8]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[9]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[10] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[11] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[12] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[13] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[14] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; out[15] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; inf     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; zero    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; done    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++------------------------------------------------------------+
+; Input Transition Times                                     ;
++---------+--------------+-----------------+-----------------+
+; Pin     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++---------+--------------+-----------------+-----------------+
+; in1[15] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[12] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[13] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[14] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[5]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[10] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[11] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[0]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[1]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[2]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[3]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[4]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[6]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[7]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[8]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in1[9]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[15] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[12] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[13] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[14] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[5]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[10] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[11] ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[0]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[1]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[2]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[3]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[4]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[6]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[7]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[8]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; in2[9]  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; start   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++---------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; out[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0568 V           ; 0.173 V                              ; 0.113 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0568 V          ; 0.173 V                             ; 0.113 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; out[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; out[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; out[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; out[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; out[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; out[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; out[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; out[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; out[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; out[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; out[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; out[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; out[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.52e-07 V                   ; 2.42 V              ; -0.0557 V           ; 0.175 V                              ; 0.114 V                              ; 4.5e-10 s                   ; 4.35e-10 s                  ; No                         ; No                         ; 2.32 V                      ; 3.52e-07 V                  ; 2.42 V             ; -0.0557 V          ; 0.175 V                             ; 0.114 V                             ; 4.5e-10 s                  ; 4.35e-10 s                 ; No                        ; No                        ;
+; out[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; out[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; inf     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
+; zero    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.07e-07 V                   ; 2.36 V              ; -0.0231 V           ; 0.14 V                               ; 0.089 V                              ; 4.52e-10 s                  ; 4.35e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.07e-07 V                  ; 2.36 V             ; -0.0231 V          ; 0.14 V                              ; 0.089 V                             ; 4.52e-10 s                 ; 4.35e-10 s                 ; No                        ; Yes                       ;
+; done    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.6e-07 V                    ; 2.41 V              ; -0.0463 V           ; 0.201 V                              ; 0.131 V                              ; 4.61e-10 s                  ; 4.53e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.6e-07 V                   ; 2.41 V             ; -0.0463 V          ; 0.201 V                             ; 0.131 V                             ; 4.61e-10 s                 ; 4.53e-10 s                 ; No                        ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; out[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.0374 V           ; 0.189 V                              ; 0.158 V                              ; 4.66e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.0374 V          ; 0.189 V                             ; 0.158 V                             ; 4.66e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; out[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; out[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; out[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; out[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; out[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; out[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; out[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; out[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; out[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; out[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; out[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; out[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; out[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.88e-05 V                   ; 2.39 V              ; -0.037 V            ; 0.188 V                              ; 0.158 V                              ; 4.67e-10 s                  ; 4.67e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.88e-05 V                  ; 2.39 V             ; -0.037 V           ; 0.188 V                             ; 0.158 V                             ; 4.67e-10 s                 ; 4.67e-10 s                 ; No                        ; Yes                       ;
+; out[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; out[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; inf     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
+; zero    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.49e-05 V                   ; 2.34 V              ; -0.0118 V           ; 0.182 V                              ; 0.051 V                              ; 4.81e-10 s                  ; 4.83e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.49e-05 V                  ; 2.34 V             ; -0.0118 V          ; 0.182 V                             ; 0.051 V                             ; 4.81e-10 s                 ; 4.83e-10 s                 ; Yes                       ; Yes                       ;
+; done    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.96e-05 V                   ; 2.38 V              ; -0.0306 V           ; 0.23 V                               ; 0.206 V                              ; 4.83e-10 s                  ; 5.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 3.96e-05 V                  ; 2.38 V             ; -0.0306 V          ; 0.23 V                              ; 0.206 V                             ; 4.83e-10 s                 ; 5.01e-10 s                 ; No                        ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; out[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; out[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; out[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; out[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; out[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; out[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; out[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; out[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; out[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; out[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; out[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; out[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; out[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; out[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; out[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; out[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; inf     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; zero    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; done    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; out[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; out[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; out[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; out[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; out[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; out[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; out[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; out[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; out[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; out[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; out[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; out[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; out[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; out[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; out[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; out[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; inf     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; zero    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; done    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 33    ; 33   ;
+; Unconstrained Input Port Paths  ; 577   ; 577  ;
+; Unconstrained Output Ports      ; 19    ; 19   ;
+; Unconstrained Output Port Paths ; 577   ; 577  ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; in1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[8]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[9]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[10]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[11]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[12]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[13]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[14]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[15]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[8]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[9]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[10]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[11]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[12]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[13]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[14]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[15]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; start      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; done        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; inf         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[8]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[9]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[10]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[11]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[12]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[13]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[14]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[15]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; zero        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; in1[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[8]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[9]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[10]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[11]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[12]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[13]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[14]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in1[15]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[4]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[5]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[6]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[7]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[8]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[9]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[10]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[11]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[12]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[13]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[14]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; in2[15]    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; start      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; done        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; inf         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[5]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[6]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[7]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[8]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[9]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[10]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[11]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[12]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[13]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[14]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; out[15]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; zero        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+    Info: Processing started: Tue Feb 14 20:10:39 2023
+Info: Command: quartus_sta posit-add -c posit-add
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'posit-add.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 5176 megabytes
+    Info: Processing ended: Tue Feb 14 20:10:43 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:04
+
+
diff --git a/Reference Code/add/output_files/posit-add.sta.summary b/Reference Code/add/output_files/posit-add.sta.summary
new file mode 100644
index 0000000000000000000000000000000000000000..aa5b327ca51ad51bc2474f1a8c822d1c6b0b3acf
--- /dev/null
+++ b/Reference Code/add/output_files/posit-add.sta.summary	
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/Reference Code/add/posit-add.qpf b/Reference Code/add/posit-add.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..135a8af3aea8eb682d5a28a9ec7917150f4c6854
--- /dev/null
+++ b/Reference Code/add/posit-add.qpf	
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 20:05:44  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "20:05:44  February 14, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "posit-add"
diff --git a/Reference Code/add/posit-add.qsf b/Reference Code/add/posit-add.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..98e9f300d79f122f46e28975ea8c198e640e67ff
--- /dev/null
+++ b/Reference Code/add/posit-add.qsf	
@@ -0,0 +1,61 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 20:05:44  February 14, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		posit-add_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY posit_add
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:05:44  FEBRUARY 14, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
+set_global_assignment -name VERILOG_FILE posit_add.v
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Reference Code/add/posit-add.qws b/Reference Code/add/posit-add.qws
new file mode 100644
index 0000000000000000000000000000000000000000..bf1e54df58bd9f1aa6a3ade70cee4e5a4b948a1e
Binary files /dev/null and b/Reference Code/add/posit-add.qws differ
diff --git a/Reference Code/add/posit_add.v b/Reference Code/add/posit_add.v
index e0592d901873adad57b4e87136ef201efbe6eee9..d251989dac7929f0570b14b3371cc84425ce81db 100644
--- a/Reference Code/add/posit_add.v	
+++ b/Reference Code/add/posit_add.v	
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+// `timescale 1ns / 1ps
 module posit_add (in1, in2, start, out, inf, zero, done);
 
 function [31:0] log2;
diff --git a/Reference Code/add/posit_add_8bit_tb.v b/Reference Code/add/posit_add_8bit_tb.v
index 27590f4a6f01d2470a5026ad7a67bcb9f7b55c7e..faa84afdf79e950a4e174f5f8d9b2db7feb55171 100644
--- a/Reference Code/add/posit_add_8bit_tb.v	
+++ b/Reference Code/add/posit_add_8bit_tb.v	
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+// `timescale 1ns / 1ps
 module posit_add_8bit_tb_v;
 
 function [31:0] log2;
@@ -12,7 +12,7 @@ endfunction
 
 parameter N=8;
 parameter Bs=log2(N);
-parameter es=4;
+parameter es=3;
 
 reg [N-1:0] in1, in2;
 reg start; 
@@ -65,16 +65,18 @@ reg [15:0] i;
  end
 
 initial outfile = $fopen("error_8bit.txt", "wb");
-
+reg [N-1:0] show_result;
 reg [N-1:0] result [1:65536];
 initial $readmemb("Pout_8bit_ES4.txt",result);
 reg [N-1:0] diff;
 always @(negedge clk) begin
 	if(start)begin
+		show_result = result[i-1];
      	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];
      	//$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\n",in1, in2, out,result[i-1],diff);
      	$fwrite(outfile, "%d\n",diff);
      	end
 end
+
 endmodule
 
diff --git a/Reference Code/add/result.txt b/Reference Code/add/result.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5df099f35d3bc59b10006095abdc8d3e901ddbe0
--- /dev/null
+++ b/Reference Code/add/result.txt	
@@ -0,0 +1,65534 @@
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diff --git a/Reference Code/add/simulation/questa/posit-add.sft b/Reference Code/add/simulation/questa/posit-add.sft
new file mode 100644
index 0000000000000000000000000000000000000000..9a92a1ec74c2e6108c1769581ffc131af7afc4e6
--- /dev/null
+++ b/Reference Code/add/simulation/questa/posit-add.sft	
@@ -0,0 +1 @@
+set tool_name "Questa Intel FPGA (Verilog)"
diff --git a/Reference Code/add/simulation/questa/posit-add.vo b/Reference Code/add/simulation/questa/posit-add.vo
new file mode 100644
index 0000000000000000000000000000000000000000..81899cf9bbccaab790c785f88f397cb4008368cc
--- /dev/null
+++ b/Reference Code/add/simulation/questa/posit-add.vo	
@@ -0,0 +1,14158 @@
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition"
+
+// DATE "02/14/2023 20:10:46"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for Questa Intel FPGA (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module posit_add (
+	in1,
+	in2,
+	start,
+	out,
+	inf,
+	zero,
+	done);
+input 	[15:0] in1;
+input 	[15:0] in2;
+input 	start;
+output 	[15:0] out;
+output 	inf;
+output 	zero;
+output 	done;
+
+// Design Ports Information
+// out[0]	=>  Location: PIN_AJ16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[1]	=>  Location: PIN_AA14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[2]	=>  Location: PIN_W16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[3]	=>  Location: PIN_AF16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[4]	=>  Location: PIN_W15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[5]	=>  Location: PIN_AF18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[6]	=>  Location: PIN_AF21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[7]	=>  Location: PIN_AK14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[8]	=>  Location: PIN_AA16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[9]	=>  Location: PIN_AA18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[10]	=>  Location: PIN_AG15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[11]	=>  Location: PIN_AG17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[12]	=>  Location: PIN_AB17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[13]	=>  Location: PIN_AK19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[14]	=>  Location: PIN_V17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// out[15]	=>  Location: PIN_AG21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// inf	=>  Location: PIN_AC18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// zero	=>  Location: PIN_AH20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// done	=>  Location: PIN_W21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[15]	=>  Location: PIN_AH19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[12]	=>  Location: PIN_AK23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[13]	=>  Location: PIN_AJ19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[14]	=>  Location: PIN_AJ20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[5]	=>  Location: PIN_AE22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[10]	=>  Location: PIN_AH12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[11]	=>  Location: PIN_Y16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[0]	=>  Location: PIN_AE16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[1]	=>  Location: PIN_AA21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[2]	=>  Location: PIN_AG16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[3]	=>  Location: PIN_AE17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[4]	=>  Location: PIN_AK11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[6]	=>  Location: PIN_AH24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[7]	=>  Location: PIN_AH18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[8]	=>  Location: PIN_AK16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in1[9]	=>  Location: PIN_AG18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[15]	=>  Location: PIN_AG22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[12]	=>  Location: PIN_AK18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[13]	=>  Location: PIN_AE23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[14]	=>  Location: PIN_AG23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[5]	=>  Location: PIN_AF19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[10]	=>  Location: PIN_AG20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[11]	=>  Location: PIN_AK22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[0]	=>  Location: PIN_AJ22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[1]	=>  Location: PIN_AJ21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[2]	=>  Location: PIN_V16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[3]	=>  Location: PIN_W17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[4]	=>  Location: PIN_AD17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[6]	=>  Location: PIN_AH22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[7]	=>  Location: PIN_AH17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[8]	=>  Location: PIN_AF23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// in2[9]	=>  Location: PIN_AJ17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// start	=>  Location: PIN_AD27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \in1[13]~input_o ;
+wire \in1[0]~input_o ;
+wire \in1[2]~input_o ;
+wire \in1[4]~input_o ;
+wire \in1[1]~input_o ;
+wire \in1[3]~input_o ;
+wire \WideOr0~0_combout ;
+wire \in1[11]~input_o ;
+wire \in1[10]~input_o ;
+wire \in1[8]~input_o ;
+wire \in1[9]~input_o ;
+wire \in1[7]~input_o ;
+wire \in1[6]~input_o ;
+wire \WideOr0~1_combout ;
+wire \in1[5]~input_o ;
+wire \WideOr0~2_combout ;
+wire \in1[14]~input_o ;
+wire \in1[12]~input_o ;
+wire \WideOr0~combout ;
+wire \in1[15]~input_o ;
+wire \in2[12]~input_o ;
+wire \in2[4]~input_o ;
+wire \in2[3]~input_o ;
+wire \in2[1]~input_o ;
+wire \in2[2]~input_o ;
+wire \in2[0]~input_o ;
+wire \WideOr1~0_combout ;
+wire \in2[5]~input_o ;
+wire \in2[10]~input_o ;
+wire \in2[7]~input_o ;
+wire \in2[6]~input_o ;
+wire \in2[8]~input_o ;
+wire \in2[9]~input_o ;
+wire \WideOr1~1_combout ;
+wire \in2[11]~input_o ;
+wire \WideOr1~2_combout ;
+wire \in2[13]~input_o ;
+wire \in2[14]~input_o ;
+wire \WideOr1~combout ;
+wire \in2[15]~input_o ;
+wire \zero~0_combout ;
+wire \Add0~46 ;
+wire \Add0~42 ;
+wire \Add0~38 ;
+wire \Add0~30 ;
+wire \Add0~34 ;
+wire \Add0~50 ;
+wire \Add0~54 ;
+wire \Add0~58 ;
+wire \Add0~26 ;
+wire \Add0~22 ;
+wire \Add0~18 ;
+wire \Add0~6 ;
+wire \Add0~10 ;
+wire \Add0~13_sumout ;
+wire \Add1~46 ;
+wire \Add1~42 ;
+wire \Add1~38 ;
+wire \Add1~30 ;
+wire \Add1~34 ;
+wire \Add1~50 ;
+wire \Add1~54 ;
+wire \Add1~58 ;
+wire \Add1~26 ;
+wire \Add1~22 ;
+wire \Add1~18 ;
+wire \Add1~6 ;
+wire \Add1~10 ;
+wire \Add1~13_sumout ;
+wire \Add0~14 ;
+wire \Add0~1_sumout ;
+wire \Add1~9_sumout ;
+wire \Add0~9_sumout ;
+wire \Add1~14 ;
+wire \Add1~1_sumout ;
+wire \LessThan0~1_combout ;
+wire \Add0~25_sumout ;
+wire \Add1~25_sumout ;
+wire \LessThan0~15_combout ;
+wire \Add1~17_sumout ;
+wire \Add0~17_sumout ;
+wire \LessThan0~6_combout ;
+wire \Add0~21_sumout ;
+wire \Add1~21_sumout ;
+wire \Add0~5_sumout ;
+wire \Add1~5_sumout ;
+wire \LessThan0~4_combout ;
+wire \LessThan0~16_combout ;
+wire \Add0~53_sumout ;
+wire \Add0~49_sumout ;
+wire \Add1~57_sumout ;
+wire \Add0~57_sumout ;
+wire \Add1~53_sumout ;
+wire \Add1~49_sumout ;
+wire \LessThan0~12_combout ;
+wire \Add1~29_sumout ;
+wire \Add1~33_sumout ;
+wire \Add0~29_sumout ;
+wire \Add0~37_sumout ;
+wire \Add0~33_sumout ;
+wire \Add1~37_sumout ;
+wire \LessThan0~11_combout ;
+wire \LessThan0~13_combout ;
+wire \LessThan0~9_combout ;
+wire \Add0~41_sumout ;
+wire \Add0~45_sumout ;
+wire \Add1~45_sumout ;
+wire \Add1~41_sumout ;
+wire \LessThan0~10_combout ;
+wire \LessThan0~8_combout ;
+wire \LessThan0~14_combout ;
+wire \LessThan0~5_combout ;
+wire \LessThan0~7_combout ;
+wire \LessThan0~2_combout ;
+wire \LessThan0~3_combout ;
+wire \LessThan0~18_combout ;
+wire \LessThan0~0_combout ;
+wire \uut_de2|xinst_k|l1|l|vld~0_combout ;
+wire \uut_de2|xinst_k|l1|l|h|vld~combout ;
+wire \uut_de2|xinst_k|l1|out[2]~0_combout ;
+wire \uut_de2|xinst_k|l1|h|l|vld~combout ;
+wire \uut_de2|xinst_k|l1|out[2]~1_combout ;
+wire \uut_de2|xinst_k|l1|out[3]~13_combout ;
+wire \uut_de2|xinst_k|l1|out[1]~8_combout ;
+wire \uut_de2|xinst_k|l1|out[1]~11_combout ;
+wire \uut_de2|xinst_k|l1|out[1]~9_combout ;
+wire \uut_de2|xinst_k|l1|out[1]~10_combout ;
+wire \uut_de2|xinst_k|l1|out[1]~12_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~5_combout ;
+wire \uut_de2|xin_r[6]~0_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~3_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~6_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~2_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~4_combout ;
+wire \uut_de2|xinst_k|l1|out[0]~7_combout ;
+wire \uut_de2|ls|tmp[1][6]~8_combout ;
+wire \uut_de2|ls|tmp[1][2]~9_combout ;
+wire \uut_de2|ls|c[6]~10_combout ;
+wire \uut_abs_regime1|regime_N[0]~0_combout ;
+wire \uut_de2|xinst_k|l1|out[2]~14_combout ;
+wire \uut_de2|regime[2]~0_combout ;
+wire \LessThan0~17_combout ;
+wire \uut_de1|xinst_k|l1|out[1]~8_combout ;
+wire \uut_de1|xinst_k|l1|out[1]~11_combout ;
+wire \uut_de1|xinst_k|l1|out[1]~10_combout ;
+wire \uut_de1|xinst_k|l1|out[1]~9_combout ;
+wire \uut_de1|xinst_k|l1|out[1]~12_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~2_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~5_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~4_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~6_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~3_combout ;
+wire \uut_de1|xin_r[6]~0_combout ;
+wire \uut_de1|xinst_k|l1|out[0]~7_combout ;
+wire \uut_de1|xinst_k|l1|l|h|vld~combout ;
+wire \uut_de1|xinst_k|l1|h|l|vld~combout ;
+wire \uut_de1|xinst_k|l1|l|vld~0_combout ;
+wire \uut_de1|xinst_k|l1|out[2]~14_combout ;
+wire \uut_de1|regime[2]~0_combout ;
+wire \lr[2]~6_combout ;
+wire \uut_de2|Add0~1_combout ;
+wire \uut_abs_regime1|regime_N[0]~2_combout ;
+wire \lr[3]~7_combout ;
+wire \uut_de1|xinst_k|l1|out[2]~0_combout ;
+wire \uut_de1|xinst_k|l1|out[2]~1_combout ;
+wire \uut_de1|xinst_k|l1|out[3]~13_combout ;
+wire \uut_de1|Add0~1_combout ;
+wire \lr[3]~8_combout ;
+wire \uut_abs_regime1|regime_N[0]~6_combout ;
+wire \uut_de2|Add0~0_combout ;
+wire \LessThan0~22_combout ;
+wire \LessThan0~23_combout ;
+wire \lr[1]~0_combout ;
+wire \lr[1]~1_combout ;
+wire \lr[1]~2_combout ;
+wire \uut_de1|Add0~0_combout ;
+wire \lr[1]~3_combout ;
+wire \LessThan0~19_combout ;
+wire \LessThan0~20_combout ;
+wire \LessThan0~21_combout ;
+wire \uut_abs_regime1|regime_N[0]~1_combout ;
+wire \uut_abs_regime1|regime_N[3]~3_combout ;
+wire \sr[1]~5_combout ;
+wire \uut_abs_regime2|regime_N[0]~1_combout ;
+wire \sr[3]~6_combout ;
+wire \sr[3]~7_combout ;
+wire \sr[1]~4_combout ;
+wire \uut_abs_regime2|Add0~1_combout ;
+wire \uut_abs_regime2|regime_N[0]~0_combout ;
+wire \uut_abs_regime2|regime_N[3]~2_combout ;
+wire \sr[1]~0_combout ;
+wire \sr[1]~1_combout ;
+wire \uut_abs_regime2|regime_N[0]~3_combout ;
+wire \sr[1]~2_combout ;
+wire \sr[0]~3_combout ;
+wire \sr[2]~8_combout ;
+wire \lr[1]~4_combout ;
+wire \lr[1]~5_combout ;
+wire \uut_abs_regime1|regime_N[2]~5_combout ;
+wire \uut_abs_regime1|regime_N[1]~4_combout ;
+wire \uut_de1|ls|c[15]~15_combout ;
+wire \uut_de1|ls|tmp[1][11]~2_combout ;
+wire \uut_de1|ls|tmp[1][7]~3_combout ;
+wire \uut_de1|ls|tmp[1][3]~4_combout ;
+wire \uut_de1|ls|c[15]~16_combout ;
+wire \uut_de2|ls|tmp[1][3]~4_combout ;
+wire \uut_de2|ls|tmp[1][7]~3_combout ;
+wire \uut_de2|ls|c[15]~16_combout ;
+wire \uut_de2|ls|tmp[1][11]~2_combout ;
+wire \uut_de2|ls|c[15]~17_combout ;
+wire \uut_de1|ls|tmp[1][6]~8_combout ;
+wire \uut_de1|ls|c[14]~17_combout ;
+wire \uut_de1|ls|tmp[1][10]~7_combout ;
+wire \uut_de1|ls|tmp[1][2]~9_combout ;
+wire \uut_de1|ls|c[14]~18_combout ;
+wire \uut_de2|ls|c[14]~18_combout ;
+wire \uut_de2|ls|tmp[1][10]~7_combout ;
+wire \uut_de2|ls|c[14]~19_combout ;
+wire \uut_ediff|s1|Add0~30_cout ;
+wire \uut_ediff|s1|Add0~22 ;
+wire \uut_ediff|s1|Add0~26 ;
+wire \uut_ediff|s1|Add0~18 ;
+wire \uut_ediff|s1|Add0~2 ;
+wire \uut_ediff|s1|Add0~10 ;
+wire \uut_ediff|s1|Add0~13_sumout ;
+wire \uut_ediff|s1|Add0~9_sumout ;
+wire \uut_abs_regime1|Add0~0_combout ;
+wire \uut_abs_regime2|Add0~0_combout ;
+wire \uut_ediff|s1|Add0~14 ;
+wire \uut_ediff|s1|Add0~5_sumout ;
+wire \uut_ediff|s1|Add0~1_sumout ;
+wire \dsr1|c[0]~0_combout ;
+wire \uut_ediff|s1|Add0~25_sumout ;
+wire \dsr1|c[0]~4_combout ;
+wire \uut_ediff|s1|Add0~21_sumout ;
+wire \uut_ediff|s1|Add0~17_sumout ;
+wire \dsr1|tmp[0][15]~3_combout ;
+wire \dsr1|tmp[2][15]~18_combout ;
+wire \uut_de2|ls|c[10]~1_combout ;
+wire \uut_de2|ls|c[11]~3_combout ;
+wire \uut_de1|ls|c[11]~1_combout ;
+wire \uut_de1|ls|c[11]~3_combout ;
+wire \DSR_e_diff[0]~0_combout ;
+wire \uut_de2|ls|c[10]~6_combout ;
+wire \uut_de1|ls|c[10]~6_combout ;
+wire \dsr1|tmp[0][11]~7_combout ;
+wire \dsr1|c[0]~2_combout ;
+wire \dsr1|c[0]~1_combout ;
+wire \dsr1|c[7]~5_combout ;
+wire \uut_de2|ls|tmp[1][4]~5_combout ;
+wire \uut_de2|ls|tmp[1][8]~6_combout ;
+wire \uut_de2|ls|c[8]~8_combout ;
+wire \uut_de1|ls|tmp[1][8]~6_combout ;
+wire \uut_de1|ls|tmp[1][4]~5_combout ;
+wire \uut_de1|ls|c[8]~8_combout ;
+wire \uut_de1|ls|tmp[1][9]~1_combout ;
+wire \uut_de1|ls|tmp[1][5]~0_combout ;
+wire \uut_de1|ls|c[9]~7_combout ;
+wire \uut_de2|ls|tmp[1][9]~1_combout ;
+wire \uut_de2|ls|tmp[1][5]~0_combout ;
+wire \uut_de2|ls|c[9]~7_combout ;
+wire \dsr1|tmp[0][9]~11_combout ;
+wire \uut_de2|ls|c[13]~0_combout ;
+wire \uut_de2|ls|c[13]~2_combout ;
+wire \uut_de2|ls|c[12]~4_combout ;
+wire \uut_de2|ls|c[12]~5_combout ;
+wire \uut_de1|ls|c[13]~0_combout ;
+wire \uut_de1|ls|c[13]~2_combout ;
+wire \uut_de1|ls|c[12]~4_combout ;
+wire \uut_de1|ls|c[12]~5_combout ;
+wire \dsr1|tmp[0][13]~5_combout ;
+wire \uut_de2|ls|c[7]~9_combout ;
+wire \uut_de1|ls|c[6]~10_combout ;
+wire \uut_de1|ls|c[7]~9_combout ;
+wire \dsr1|tmp[0][7]~17_combout ;
+wire \dsr1|c[7]~3_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~68_combout ;
+wire \uut_de2|ls|c[3]~11_combout ;
+wire \uut_de2|ls|c[5]~12_combout ;
+wire \dsr1|tmp[0][8]~15_combout ;
+wire \dsr1|tmp[0][12]~1_combout ;
+wire \uut_de1|ls|c[5]~11_combout ;
+wire \dsr1|tmp[0][6]~19_combout ;
+wire \dsr1|c[6]~6_combout ;
+wire \dsr1|tmp[0][10]~9_combout ;
+wire \dsr1|tmp[0][14]~0_combout ;
+wire \dsr1|c[6]~7_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~69_combout ;
+wire \uut_de1|ls|c[4]~12_combout ;
+wire \uut_de2|ls|c[4]~13_combout ;
+wire \dsr1|tmp[0][5]~20_combout ;
+wire \dsr1|c[5]~9_combout ;
+wire \dsr1|tmp[0][15]~4_combout ;
+wire \dsr1|c[5]~8_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~70_combout ;
+wire \dsr1|c[4]~10_combout ;
+wire \uut_de1|ls|c[3]~13_combout ;
+wire \uut_de2|ls|c[3]~14_combout ;
+wire \dsr1|tmp[0][4]~21_combout ;
+wire \dsr1|c[4]~11_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~71_combout ;
+wire \uut_de2|ls|c[2]~15_combout ;
+wire \uut_de1|ls|c[2]~14_combout ;
+wire \dsr1|tmp[0][3]~22_combout ;
+wire \dsr1|c[3]~12_combout ;
+wire \dsr1|tmp[2][10]~6_combout ;
+wire \dsr1|tmp[2][11]~8_combout ;
+wire \dsr1|c[3]~26_combout ;
+wire \add_m_in1[3]~7_combout ;
+wire \dsr1|tmp[0][2]~23_combout ;
+wire \dsr1|c[2]~13_combout ;
+wire \dsr1|tmp[2][10]~10_combout ;
+wire \dsr1|c[2]~22_combout ;
+wire \dsr1|c[0]~14_combout ;
+wire \dsr1|c[0]~15_combout ;
+wire \dsr1|tmp[2][9]~12_combout ;
+wire \dsr1|c[1]~18_combout ;
+wire \dsr1|tmp[2][8]~16_combout ;
+wire \dsr1|c[0]~16_combout ;
+wire \dsr1|c[0]~17_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~58 ;
+wire \uut_add_sub_N|a11|a1|Add0~62 ;
+wire \uut_add_sub_N|a11|a1|Add0~54 ;
+wire \uut_add_sub_N|a11|a1|Add0~50 ;
+wire \uut_add_sub_N|a11|a1|Add0~46 ;
+wire \uut_add_sub_N|a11|a1|Add0~42 ;
+wire \uut_add_sub_N|a11|a1|Add0~38 ;
+wire \uut_add_sub_N|a11|a1|Add0~33_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~37_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~53_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~61_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~49_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~57_sumout ;
+wire \l2|l1|out[2]~8_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~45_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~41_sumout ;
+wire \l2|l1|out[2]~9_combout ;
+wire \add_m_in1[13]~5_combout ;
+wire \dsr1|tmp[2][13]~14_combout ;
+wire \dsr1|tmp[2][12]~2_combout ;
+wire \add_m_in1[12]~0_combout ;
+wire \add_m_in1[11]~1_combout ;
+wire \add_m_in1[10]~2_combout ;
+wire \add_m_in1[9]~3_combout ;
+wire \add_m_in1[8]~6_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~34 ;
+wire \uut_add_sub_N|a11|a1|Add0~30 ;
+wire \uut_add_sub_N|a11|a1|Add0~18 ;
+wire \uut_add_sub_N|a11|a1|Add0~14 ;
+wire \uut_add_sub_N|a11|a1|Add0~10 ;
+wire \uut_add_sub_N|a11|a1|Add0~6 ;
+wire \uut_add_sub_N|a11|a1|Add0~25_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~5_sumout ;
+wire \l2|l1|h|h|l|WideOr0~combout ;
+wire \add_m_in1[15]~8_combout ;
+wire \dsr1|tmp[2][14]~13_combout ;
+wire \add_m_in1[14]~4_combout ;
+wire \uut_add_sub_N|a11|a1|Add0~26 ;
+wire \uut_add_sub_N|a11|a1|Add0~22 ;
+wire \uut_add_sub_N|a11|a1|Add0~66 ;
+wire \uut_add_sub_N|a11|a1|Add0~1_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~21_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~65_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~13_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~9_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~17_sumout ;
+wire \uut_add_sub_N|a11|a1|Add0~29_sumout ;
+wire \l2|l1|h|l|h|WideOr0~0_combout ;
+wire \l2|l1|out[2]~10_combout ;
+wire \l2|l1|out[1]~6_combout ;
+wire \l2|l1|out[1]~4_combout ;
+wire \l2|l1|out[1]~5_combout ;
+wire \l2|l1|out[1]~7_combout ;
+wire \l2|l1|out[0]~2_combout ;
+wire \l2|l1|out[0]~0_combout ;
+wire \l2|l1|out[0]~1_combout ;
+wire \l2|l1|out[0]~3_combout ;
+wire \dsl1|tmp[1][7]~1_combout ;
+wire \dsl1|tmp[1][3]~2_combout ;
+wire \l2|l1|out[3]~11_combout ;
+wire \l2|l1|out[3]~12_combout ;
+wire \dsl1|tmp[1][11]~0_combout ;
+wire \dsl1|c[15]~0_combout ;
+wire \dsl1|tmp[1][6]~4_combout ;
+wire \l2|l1|out[0]~13_combout ;
+wire \l2|l1|out[0]~14_combout ;
+wire \l2|l1|out[0]~15_combout ;
+wire \dsl1|tmp[1][2]~5_combout ;
+wire \dsl1|c[14]~1_combout ;
+wire \dsl1|tmp[1][10]~3_combout ;
+wire \dsl1|c[14]~2_combout ;
+wire \inf~0_combout ;
+wire \out~0_combout ;
+wire \ls~0_combout ;
+wire \uut_add_mantovf|Add0~28_combout ;
+wire \uut_add_mantovf|Add0~29_combout ;
+wire \l2|l1|l|h|vld~combout ;
+wire \l2|l1|out[2]~26_combout ;
+wire \uut_add_mantovf|Add0~35_combout ;
+wire \l2|l1|out[1]~19_combout ;
+wire \l2|l1|out[1]~25_combout ;
+wire \uut_add_mantovf|Add0~34_combout ;
+wire \uut_add_mantovf|Add0~32_cout ;
+wire \uut_add_mantovf|Add0~6 ;
+wire \uut_add_mantovf|Add0~10 ;
+wire \uut_add_mantovf|Add0~14 ;
+wire \uut_add_mantovf|Add0~18 ;
+wire \uut_add_mantovf|Add0~22 ;
+wire \uut_add_mantovf|Add0~26 ;
+wire \uut_add_mantovf|Add0~1_sumout ;
+wire \uut_add_mantovf|Add0~13_sumout ;
+wire \uut_add_mantovf|Add0~17_sumout ;
+wire \uut_add_mantovf|Add0~25_sumout ;
+wire \uut_add_mantovf|Add0~21_sumout ;
+wire \uut_reg_ro|r_o[3]~1_combout ;
+wire \uut_reg_ro|r_o[2]~0_combout ;
+wire \l2|l1|out[1]~20_combout ;
+wire \l2|l1|out[1]~21_combout ;
+wire \l2|l1|out[0]~16_combout ;
+wire \l2|l1|out[0]~17_combout ;
+wire \l2|l1|out[0]~18_combout ;
+wire \dsl1|tmp[1][0]~6_combout ;
+wire \dsl1|tmp[1][4]~7_combout ;
+wire \tmp_o[6]~2_combout ;
+wire \dsl1|tmp[1][5]~9_combout ;
+wire \l2|l1|out[0]~22_combout ;
+wire \l2|l1|out[0]~23_combout ;
+wire \l2|l1|out[0]~24_combout ;
+wire \dsl1|tmp[1][1]~8_combout ;
+wire \tmp_o[6]~4_combout ;
+wire \tmp_o[6]~5_combout ;
+wire \tmp_o[1]~0_combout ;
+wire \tmp_o[4]~1_combout ;
+wire \uut_reg_ro|r_o[1]~3_combout ;
+wire \tmp_o[7]~6_combout ;
+wire \tmp_o[7]~7_combout ;
+wire \uut_reg_ro|r_o[0]~2_combout ;
+wire \tmp_o[5]~3_combout ;
+wire \dsr2|tmp[1][20]~0_combout ;
+wire \dsl1|c[10]~3_combout ;
+wire \dsl1|c[11]~12_combout ;
+wire \dsl1|c[10]~5_combout ;
+wire \dsl1|tmp[1][8]~11_combout ;
+wire \dsl1|c[12]~10_combout ;
+wire \dsl1|c[12]~11_combout ;
+wire \dsr2|tmp[0][28]~6_combout ;
+wire \dsr2|tmp[0][30]~5_combout ;
+wire \dsl1|tmp[1][9]~10_combout ;
+wire \dsl1|c[13]~8_combout ;
+wire \dsl1|c[13]~9_combout ;
+wire \dsr2|tmp[0][27]~4_combout ;
+wire \dsr2|tmp[1][28]~7_combout ;
+wire \tmp_o[8]~9_combout ;
+wire \tmp_o[8]~10_combout ;
+wire \dsl1|c[8]~6_combout ;
+wire \dsr2|tmp[0][26]~2_combout ;
+wire \dsl1|c[9]~4_combout ;
+wire \dsr2|tmp[0][26]~1_combout ;
+wire \dsl1|c[7]~7_combout ;
+wire \tmp_o[9]~8_combout ;
+wire \dsr2|tmp[1][24]~3_combout ;
+wire \uut_add_mantovf|Add0~9_sumout ;
+wire \uut_add_mantovf|Add0~5_sumout ;
+wire \dsr2|tmp[1][32]~8_combout ;
+wire \dsr2|c[20]~0_combout ;
+wire \dsr2|tmp[1][23]~24_combout ;
+wire \dsr2|tmp[0][25]~23_combout ;
+wire \dsr2|tmp[1][23]~25_combout ;
+wire \dsr2|tmp[0][25]~22_combout ;
+wire \dsr2|tmp[1][23]~26_combout ;
+wire \tmp_o[3]~12_combout ;
+wire \dsr2|tmp[1][19]~34_combout ;
+wire \dsr2|tmp[1][15]~38_combout ;
+wire \dsr2|tmp[0][29]~27_combout ;
+wire \dsr2|tmp[0][27]~14_combout ;
+wire \dsr2|tmp[1][27]~28_combout ;
+wire \dsr2|c[15]~20_combout ;
+wire \tmp_o[2]~13_combout ;
+wire \tmp_o[1]~14_combout ;
+wire \dsr2|tmp[1][16]~39_combout ;
+wire \dsr2|c[16]~21_combout ;
+wire \dsr2|tmp[1][22]~16_combout ;
+wire \dsr2|tmp[0][26]~17_combout ;
+wire \dsr2|tmp[1][26]~18_combout ;
+wire \dsr2|tmp[1][32]~19_combout ;
+wire \dsr2|tmp[1][30]~20_combout ;
+wire \dsr2|tmp[1][18]~35_combout ;
+wire \dsr2|c[18]~18_combout ;
+wire \dsr2|tmp[0][31]~10_combout ;
+wire \dsr2|tmp[0][29]~9_combout ;
+wire \dsr2|tmp[0][27]~31_combout ;
+wire \dsr2|tmp[0][25]~30_combout ;
+wire \dsr2|tmp[2][25]~32_combout ;
+wire \rnd_ulp[0]~5_combout ;
+wire \dsr2|tmp[1][21]~15_combout ;
+wire \rnd_ulp[0]~2_combout ;
+wire \dsr2|tmp[1][17]~37_combout ;
+wire \rnd_ulp[0]~3_combout ;
+wire \dsr2|tmp[0][25]~13_combout ;
+wire \dsr2|c[21]~1_combout ;
+wire \rnd_ulp[0]~1_combout ;
+wire \rnd_ulp[0]~0_combout ;
+wire \dsr2|tmp[1][14]~36_combout ;
+wire \dsr2|c[14]~19_combout ;
+wire \rnd_ulp[0]~4_combout ;
+wire \rnd_ulp[0]~6_combout ;
+wire \tmp_o[15]~11_combout ;
+wire \dsr2|tmp[1][31]~29_combout ;
+wire \dsr2|c[19]~16_combout ;
+wire \uut_add_ulp|a1|Add0~62 ;
+wire \uut_add_ulp|a1|Add0~1_sumout ;
+wire \uut_add_ulp|a1|Add0~61_sumout ;
+wire \tmp1_o_rnd[0]~0_combout ;
+wire \Add2~1_sumout ;
+wire \out~1_combout ;
+wire \out~2_combout ;
+wire \dsr2|tmp[0][33]~11_combout ;
+wire \dsr2|tmp[2][29]~12_combout ;
+wire \dsr2|c[21]~2_combout ;
+wire \dsr2|c[21]~3_combout ;
+wire \uut_add_ulp|a1|Add0~2 ;
+wire \uut_add_ulp|a1|Add0~5_sumout ;
+wire \out~3_combout ;
+wire \Add2~2 ;
+wire \Add2~5_sumout ;
+wire \out~4_combout ;
+wire \out~7_combout ;
+wire \dsr2|tmp[1][34]~21_combout ;
+wire \dsr2|c[22]~4_combout ;
+wire \uut_add_ulp|a1|Add0~6 ;
+wire \uut_add_ulp|a1|Add0~9_sumout ;
+wire \Add2~6 ;
+wire \Add2~9_sumout ;
+wire \out~6_combout ;
+wire \out~5_combout ;
+wire \out~8_combout ;
+wire \dsr2|c[23]~5_combout ;
+wire \uut_add_ulp|a1|Add0~10 ;
+wire \uut_add_ulp|a1|Add0~13_sumout ;
+wire \Add2~10 ;
+wire \Add2~13_sumout ;
+wire \out~9_combout ;
+wire \out~10_combout ;
+wire \dsr2|c[24]~6_combout ;
+wire \uut_add_ulp|a1|Add0~14 ;
+wire \uut_add_ulp|a1|Add0~17_sumout ;
+wire \out~11_combout ;
+wire \Add2~14 ;
+wire \Add2~17_sumout ;
+wire \out~12_combout ;
+wire \dsr2|tmp[2][33]~33_combout ;
+wire \dsr2|c[25]~7_combout ;
+wire \uut_add_ulp|a1|Add0~18 ;
+wire \uut_add_ulp|a1|Add0~21_sumout ;
+wire \Add2~18 ;
+wire \Add2~21_sumout ;
+wire \out~13_combout ;
+wire \out~14_combout ;
+wire \dsr2|c[26]~8_combout ;
+wire \uut_add_ulp|a1|Add0~22 ;
+wire \uut_add_ulp|a1|Add0~25_sumout ;
+wire \out~15_combout ;
+wire \Add2~22 ;
+wire \Add2~25_sumout ;
+wire \out~16_combout ;
+wire \dsr2|c[27]~9_combout ;
+wire \uut_add_ulp|a1|Add0~26 ;
+wire \uut_add_ulp|a1|Add0~29_sumout ;
+wire \dsr2|c[27]~10_combout ;
+wire \out~17_combout ;
+wire \Add2~26 ;
+wire \Add2~29_sumout ;
+wire \out~18_combout ;
+wire \dsr2|c[28]~11_combout ;
+wire \dsr2|c[28]~12_combout ;
+wire \uut_add_ulp|a1|Add0~30 ;
+wire \uut_add_ulp|a1|Add0~33_sumout ;
+wire \out~19_combout ;
+wire \Add2~30 ;
+wire \Add2~33_sumout ;
+wire \out~20_combout ;
+wire \dsr2|c[29]~13_combout ;
+wire \uut_add_ulp|a1|Add0~34 ;
+wire \uut_add_ulp|a1|Add0~37_sumout ;
+wire \out~21_combout ;
+wire \Add2~34 ;
+wire \Add2~37_sumout ;
+wire \out~22_combout ;
+wire \dsr2|c[30]~14_combout ;
+wire \dsr2|c[30]~15_combout ;
+wire \uut_add_ulp|a1|Add0~38 ;
+wire \uut_add_ulp|a1|Add0~41_sumout ;
+wire \Add2~38 ;
+wire \Add2~41_sumout ;
+wire \out~23_combout ;
+wire \out~24_combout ;
+wire \uut_add_ulp|a1|Add0~42 ;
+wire \uut_add_ulp|a1|Add0~45_sumout ;
+wire \out~25_combout ;
+wire \Add2~42 ;
+wire \Add2~45_sumout ;
+wire \out~26_combout ;
+wire \uut_add_ulp|a1|Add0~46 ;
+wire \uut_add_ulp|a1|Add0~49_sumout ;
+wire \out~27_combout ;
+wire \Add2~46 ;
+wire \Add2~49_sumout ;
+wire \out~28_combout ;
+wire \uut_add_ulp|a1|Add0~50 ;
+wire \uut_add_ulp|a1|Add0~53_sumout ;
+wire \Add2~50 ;
+wire \Add2~53_sumout ;
+wire \out~29_combout ;
+wire \out~30_combout ;
+wire \dsr2|c[13]~17_combout ;
+wire \uut_add_ulp|a1|Add0~54 ;
+wire \uut_add_ulp|a1|Add0~57_sumout ;
+wire \Add2~54 ;
+wire \Add2~57_sumout ;
+wire \out~31_combout ;
+wire \out~32_combout ;
+wire \out~33_combout ;
+wire \start~input_o ;
+
+
+// Location: IOOBUF_X54_Y0_N36
+cyclonev_io_obuf \out[0]~output (
+	.i(\out~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[0]),
+	.obar());
+// synopsys translate_off
+defparam \out[0]~output .bus_hold = "false";
+defparam \out[0]~output .open_drain_output = "false";
+defparam \out[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X36_Y0_N2
+cyclonev_io_obuf \out[1]~output (
+	.i(\out~4_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[1]),
+	.obar());
+// synopsys translate_off
+defparam \out[1]~output .bus_hold = "false";
+defparam \out[1]~output .open_drain_output = "false";
+defparam \out[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X52_Y0_N19
+cyclonev_io_obuf \out[2]~output (
+	.i(\out~8_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[2]),
+	.obar());
+// synopsys translate_off
+defparam \out[2]~output .bus_hold = "false";
+defparam \out[2]~output .open_drain_output = "false";
+defparam \out[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X52_Y0_N53
+cyclonev_io_obuf \out[3]~output (
+	.i(\out~10_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[3]),
+	.obar());
+// synopsys translate_off
+defparam \out[3]~output .bus_hold = "false";
+defparam \out[3]~output .open_drain_output = "false";
+defparam \out[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y0_N2
+cyclonev_io_obuf \out[4]~output (
+	.i(\out~12_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[4]),
+	.obar());
+// synopsys translate_off
+defparam \out[4]~output .bus_hold = "false";
+defparam \out[4]~output .open_drain_output = "false";
+defparam \out[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X50_Y0_N59
+cyclonev_io_obuf \out[5]~output (
+	.i(\out~14_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[5]),
+	.obar());
+// synopsys translate_off
+defparam \out[5]~output .bus_hold = "false";
+defparam \out[5]~output .open_drain_output = "false";
+defparam \out[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N19
+cyclonev_io_obuf \out[6]~output (
+	.i(\out~16_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[6]),
+	.obar());
+// synopsys translate_off
+defparam \out[6]~output .bus_hold = "false";
+defparam \out[6]~output .open_drain_output = "false";
+defparam \out[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y0_N53
+cyclonev_io_obuf \out[7]~output (
+	.i(\out~18_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[7]),
+	.obar());
+// synopsys translate_off
+defparam \out[7]~output .bus_hold = "false";
+defparam \out[7]~output .open_drain_output = "false";
+defparam \out[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X56_Y0_N2
+cyclonev_io_obuf \out[8]~output (
+	.i(\out~20_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[8]),
+	.obar());
+// synopsys translate_off
+defparam \out[8]~output .bus_hold = "false";
+defparam \out[8]~output .open_drain_output = "false";
+defparam \out[8]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N19
+cyclonev_io_obuf \out[9]~output (
+	.i(\out~22_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[9]),
+	.obar());
+// synopsys translate_off
+defparam \out[9]~output .bus_hold = "false";
+defparam \out[9]~output .open_drain_output = "false";
+defparam \out[9]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X38_Y0_N2
+cyclonev_io_obuf \out[10]~output (
+	.i(\out~24_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[10]),
+	.obar());
+// synopsys translate_off
+defparam \out[10]~output .bus_hold = "false";
+defparam \out[10]~output .open_drain_output = "false";
+defparam \out[10]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X50_Y0_N93
+cyclonev_io_obuf \out[11]~output (
+	.i(\out~26_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[11]),
+	.obar());
+// synopsys translate_off
+defparam \out[11]~output .bus_hold = "false";
+defparam \out[11]~output .open_drain_output = "false";
+defparam \out[11]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X56_Y0_N19
+cyclonev_io_obuf \out[12]~output (
+	.i(\out~28_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[12]),
+	.obar());
+// synopsys translate_off
+defparam \out[12]~output .bus_hold = "false";
+defparam \out[12]~output .open_drain_output = "false";
+defparam \out[12]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X60_Y0_N53
+cyclonev_io_obuf \out[13]~output (
+	.i(\out~30_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[13]),
+	.obar());
+// synopsys translate_off
+defparam \out[13]~output .bus_hold = "false";
+defparam \out[13]~output .open_drain_output = "false";
+defparam \out[13]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X60_Y0_N2
+cyclonev_io_obuf \out[14]~output (
+	.i(\out~32_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[14]),
+	.obar());
+// synopsys translate_off
+defparam \out[14]~output .bus_hold = "false";
+defparam \out[14]~output .open_drain_output = "false";
+defparam \out[14]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N2
+cyclonev_io_obuf \out[15]~output (
+	.i(\out~33_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(out[15]),
+	.obar());
+// synopsys translate_off
+defparam \out[15]~output .bus_hold = "false";
+defparam \out[15]~output .open_drain_output = "false";
+defparam \out[15]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X64_Y0_N2
+cyclonev_io_obuf \inf~output (
+	.i(\inf~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(inf),
+	.obar());
+// synopsys translate_off
+defparam \inf~output .bus_hold = "false";
+defparam \inf~output .open_drain_output = "false";
+defparam \inf~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N19
+cyclonev_io_obuf \zero~output (
+	.i(!\zero~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(zero),
+	.obar());
+// synopsys translate_off
+defparam \zero~output .bus_hold = "false";
+defparam \zero~output .open_drain_output = "false";
+defparam \zero~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N5
+cyclonev_io_obuf \done~output (
+	.i(\start~input_o ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(done),
+	.obar());
+// synopsys translate_off
+defparam \done~output .bus_hold = "false";
+defparam \done~output .open_drain_output = "false";
+defparam \done~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y0_N35
+cyclonev_io_ibuf \in1[13]~input (
+	.i(in1[13]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[13]~input_o ));
+// synopsys translate_off
+defparam \in1[13]~input .bus_hold = "false";
+defparam \in1[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X52_Y0_N35
+cyclonev_io_ibuf \in1[0]~input (
+	.i(in1[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[0]~input_o ));
+// synopsys translate_off
+defparam \in1[0]~input .bus_hold = "false";
+defparam \in1[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X50_Y0_N75
+cyclonev_io_ibuf \in1[2]~input (
+	.i(in1[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[2]~input_o ));
+// synopsys translate_off
+defparam \in1[2]~input .bus_hold = "false";
+defparam \in1[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X34_Y0_N58
+cyclonev_io_ibuf \in1[4]~input (
+	.i(in1[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[4]~input_o ));
+// synopsys translate_off
+defparam \in1[4]~input .bus_hold = "false";
+defparam \in1[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X88_Y0_N2
+cyclonev_io_ibuf \in1[1]~input (
+	.i(in1[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[1]~input_o ));
+// synopsys translate_off
+defparam \in1[1]~input .bus_hold = "false";
+defparam \in1[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X50_Y0_N41
+cyclonev_io_ibuf \in1[3]~input (
+	.i(in1[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[3]~input_o ));
+// synopsys translate_off
+defparam \in1[3]~input .bus_hold = "false";
+defparam \in1[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N48
+cyclonev_lcell_comb \WideOr0~0 (
+// Equation(s):
+// \WideOr0~0_combout  = ( !\in1[3]~input_o  & ( (!\in1[0]~input_o  & (!\in1[2]~input_o  & (!\in1[4]~input_o  & !\in1[1]~input_o ))) ) )
+
+	.dataa(!\in1[0]~input_o ),
+	.datab(!\in1[2]~input_o ),
+	.datac(!\in1[4]~input_o ),
+	.datad(!\in1[1]~input_o ),
+	.datae(gnd),
+	.dataf(!\in1[3]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr0~0 .extended_lut = "off";
+defparam \WideOr0~0 .lut_mask = 64'h8000800000000000;
+defparam \WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X40_Y0_N18
+cyclonev_io_ibuf \in1[11]~input (
+	.i(in1[11]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[11]~input_o ));
+// synopsys translate_off
+defparam \in1[11]~input .bus_hold = "false";
+defparam \in1[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X38_Y0_N35
+cyclonev_io_ibuf \in1[10]~input (
+	.i(in1[10]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[10]~input_o ));
+// synopsys translate_off
+defparam \in1[10]~input .bus_hold = "false";
+defparam \in1[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X54_Y0_N52
+cyclonev_io_ibuf \in1[8]~input (
+	.i(in1[8]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[8]~input_o ));
+// synopsys translate_off
+defparam \in1[8]~input .bus_hold = "false";
+defparam \in1[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X58_Y0_N75
+cyclonev_io_ibuf \in1[9]~input (
+	.i(in1[9]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[9]~input_o ));
+// synopsys translate_off
+defparam \in1[9]~input .bus_hold = "false";
+defparam \in1[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X56_Y0_N52
+cyclonev_io_ibuf \in1[7]~input (
+	.i(in1[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[7]~input_o ));
+// synopsys translate_off
+defparam \in1[7]~input .bus_hold = "false";
+defparam \in1[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y0_N52
+cyclonev_io_ibuf \in1[6]~input (
+	.i(in1[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[6]~input_o ));
+// synopsys translate_off
+defparam \in1[6]~input .bus_hold = "false";
+defparam \in1[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N54
+cyclonev_lcell_comb \WideOr0~1 (
+// Equation(s):
+// \WideOr0~1_combout  = ( !\in1[6]~input_o  & ( (!\in1[8]~input_o  & (!\in1[9]~input_o  & !\in1[7]~input_o )) ) )
+
+	.dataa(gnd),
+	.datab(!\in1[8]~input_o ),
+	.datac(!\in1[9]~input_o ),
+	.datad(!\in1[7]~input_o ),
+	.datae(gnd),
+	.dataf(!\in1[6]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr0~1 .extended_lut = "off";
+defparam \WideOr0~1 .lut_mask = 64'hC000C00000000000;
+defparam \WideOr0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X78_Y0_N1
+cyclonev_io_ibuf \in1[5]~input (
+	.i(in1[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[5]~input_o ));
+// synopsys translate_off
+defparam \in1[5]~input .bus_hold = "false";
+defparam \in1[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N0
+cyclonev_lcell_comb \WideOr0~2 (
+// Equation(s):
+// \WideOr0~2_combout  = ( !\in1[5]~input_o  & ( (\WideOr0~0_combout  & (!\in1[11]~input_o  & (!\in1[10]~input_o  & \WideOr0~1_combout ))) ) )
+
+	.dataa(!\WideOr0~0_combout ),
+	.datab(!\in1[11]~input_o ),
+	.datac(!\in1[10]~input_o ),
+	.datad(!\WideOr0~1_combout ),
+	.datae(gnd),
+	.dataf(!\in1[5]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr0~2 .extended_lut = "off";
+defparam \WideOr0~2 .lut_mask = 64'h0040004000000000;
+defparam \WideOr0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N35
+cyclonev_io_ibuf \in1[14]~input (
+	.i(in1[14]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[14]~input_o ));
+// synopsys translate_off
+defparam \in1[14]~input .bus_hold = "false";
+defparam \in1[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X72_Y0_N35
+cyclonev_io_ibuf \in1[12]~input (
+	.i(in1[12]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[12]~input_o ));
+// synopsys translate_off
+defparam \in1[12]~input .bus_hold = "false";
+defparam \in1[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N57
+cyclonev_lcell_comb WideOr0(
+// Equation(s):
+// \WideOr0~combout  = ( !\in1[12]~input_o  & ( (!\in1[13]~input_o  & (\WideOr0~2_combout  & !\in1[14]~input_o )) ) )
+
+	.dataa(!\in1[13]~input_o ),
+	.datab(gnd),
+	.datac(!\WideOr0~2_combout ),
+	.datad(!\in1[14]~input_o ),
+	.datae(gnd),
+	.dataf(!\in1[12]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam WideOr0.extended_lut = "off";
+defparam WideOr0.lut_mask = 64'h0A000A0000000000;
+defparam WideOr0.shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X58_Y0_N92
+cyclonev_io_ibuf \in1[15]~input (
+	.i(in1[15]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in1[15]~input_o ));
+// synopsys translate_off
+defparam \in1[15]~input .bus_hold = "false";
+defparam \in1[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X58_Y0_N58
+cyclonev_io_ibuf \in2[12]~input (
+	.i(in2[12]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[12]~input_o ));
+// synopsys translate_off
+defparam \in2[12]~input .bus_hold = "false";
+defparam \in2[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y0_N18
+cyclonev_io_ibuf \in2[4]~input (
+	.i(in2[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[4]~input_o ));
+// synopsys translate_off
+defparam \in2[4]~input .bus_hold = "false";
+defparam \in2[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y0_N18
+cyclonev_io_ibuf \in2[3]~input (
+	.i(in2[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[3]~input_o ));
+// synopsys translate_off
+defparam \in2[3]~input .bus_hold = "false";
+defparam \in2[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N52
+cyclonev_io_ibuf \in2[1]~input (
+	.i(in2[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[1]~input_o ));
+// synopsys translate_off
+defparam \in2[1]~input .bus_hold = "false";
+defparam \in2[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X52_Y0_N1
+cyclonev_io_ibuf \in2[2]~input (
+	.i(in2[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[2]~input_o ));
+// synopsys translate_off
+defparam \in2[2]~input .bus_hold = "false";
+defparam \in2[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X70_Y0_N52
+cyclonev_io_ibuf \in2[0]~input (
+	.i(in2[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[0]~input_o ));
+// synopsys translate_off
+defparam \in2[0]~input .bus_hold = "false";
+defparam \in2[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N45
+cyclonev_lcell_comb \WideOr1~0 (
+// Equation(s):
+// \WideOr1~0_combout  = ( !\in2[0]~input_o  & ( (!\in2[4]~input_o  & (!\in2[3]~input_o  & (!\in2[1]~input_o  & !\in2[2]~input_o ))) ) )
+
+	.dataa(!\in2[4]~input_o ),
+	.datab(!\in2[3]~input_o ),
+	.datac(!\in2[1]~input_o ),
+	.datad(!\in2[2]~input_o ),
+	.datae(gnd),
+	.dataf(!\in2[0]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~0 .extended_lut = "off";
+defparam \WideOr1~0 .lut_mask = 64'h8000800000000000;
+defparam \WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N1
+cyclonev_io_ibuf \in2[5]~input (
+	.i(in2[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[5]~input_o ));
+// synopsys translate_off
+defparam \in2[5]~input .bus_hold = "false";
+defparam \in2[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N18
+cyclonev_io_ibuf \in2[10]~input (
+	.i(in2[10]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[10]~input_o ));
+// synopsys translate_off
+defparam \in2[10]~input .bus_hold = "false";
+defparam \in2[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X56_Y0_N35
+cyclonev_io_ibuf \in2[7]~input (
+	.i(in2[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[7]~input_o ));
+// synopsys translate_off
+defparam \in2[7]~input .bus_hold = "false";
+defparam \in2[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X66_Y0_N92
+cyclonev_io_ibuf \in2[6]~input (
+	.i(in2[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[6]~input_o ));
+// synopsys translate_off
+defparam \in2[6]~input .bus_hold = "false";
+defparam \in2[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X74_Y0_N41
+cyclonev_io_ibuf \in2[8]~input (
+	.i(in2[8]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[8]~input_o ));
+// synopsys translate_off
+defparam \in2[8]~input .bus_hold = "false";
+defparam \in2[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X58_Y0_N41
+cyclonev_io_ibuf \in2[9]~input (
+	.i(in2[9]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[9]~input_o ));
+// synopsys translate_off
+defparam \in2[9]~input .bus_hold = "false";
+defparam \in2[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N48
+cyclonev_lcell_comb \WideOr1~1 (
+// Equation(s):
+// \WideOr1~1_combout  = ( !\in2[9]~input_o  & ( (!\in2[7]~input_o  & (!\in2[6]~input_o  & !\in2[8]~input_o )) ) )
+
+	.dataa(gnd),
+	.datab(!\in2[7]~input_o ),
+	.datac(!\in2[6]~input_o ),
+	.datad(!\in2[8]~input_o ),
+	.datae(gnd),
+	.dataf(!\in2[9]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~1 .extended_lut = "off";
+defparam \WideOr1~1 .lut_mask = 64'hC000C00000000000;
+defparam \WideOr1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X68_Y0_N52
+cyclonev_io_ibuf \in2[11]~input (
+	.i(in2[11]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[11]~input_o ));
+// synopsys translate_off
+defparam \in2[11]~input .bus_hold = "false";
+defparam \in2[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N54
+cyclonev_lcell_comb \WideOr1~2 (
+// Equation(s):
+// \WideOr1~2_combout  = ( !\in2[11]~input_o  & ( (\WideOr1~0_combout  & (!\in2[5]~input_o  & (!\in2[10]~input_o  & \WideOr1~1_combout ))) ) )
+
+	.dataa(!\WideOr1~0_combout ),
+	.datab(!\in2[5]~input_o ),
+	.datac(!\in2[10]~input_o ),
+	.datad(!\WideOr1~1_combout ),
+	.datae(gnd),
+	.dataf(!\in2[11]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \WideOr1~2 .extended_lut = "off";
+defparam \WideOr1~2 .lut_mask = 64'h0040004000000000;
+defparam \WideOr1~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X78_Y0_N18
+cyclonev_io_ibuf \in2[13]~input (
+	.i(in2[13]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[13]~input_o ));
+// synopsys translate_off
+defparam \in2[13]~input .bus_hold = "false";
+defparam \in2[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y0_N35
+cyclonev_io_ibuf \in2[14]~input (
+	.i(in2[14]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[14]~input_o ));
+// synopsys translate_off
+defparam \in2[14]~input .bus_hold = "false";
+defparam \in2[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N51
+cyclonev_lcell_comb WideOr1(
+// Equation(s):
+// \WideOr1~combout  = ( !\in2[14]~input_o  & ( (!\in2[12]~input_o  & (\WideOr1~2_combout  & !\in2[13]~input_o )) ) )
+
+	.dataa(!\in2[12]~input_o ),
+	.datab(gnd),
+	.datac(!\WideOr1~2_combout ),
+	.datad(!\in2[13]~input_o ),
+	.datae(gnd),
+	.dataf(!\in2[14]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\WideOr1~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam WideOr1.extended_lut = "off";
+defparam WideOr1.lut_mask = 64'h0A000A0000000000;
+defparam WideOr1.shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X66_Y0_N75
+cyclonev_io_ibuf \in2[15]~input (
+	.i(in2[15]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\in2[15]~input_o ));
+// synopsys translate_off
+defparam \in2[15]~input .bus_hold = "false";
+defparam \in2[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N30
+cyclonev_lcell_comb \zero~0 (
+// Equation(s):
+// \zero~0_combout  = ( \in2[15]~input_o  ) # ( !\in2[15]~input_o  & ( (!\WideOr0~combout ) # ((!\WideOr1~combout ) # (\in1[15]~input_o )) ) )
+
+	.dataa(!\WideOr0~combout ),
+	.datab(!\in1[15]~input_o ),
+	.datac(gnd),
+	.datad(!\WideOr1~combout ),
+	.datae(gnd),
+	.dataf(!\in2[15]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\zero~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \zero~0 .extended_lut = "off";
+defparam \zero~0 .lut_mask = 64'hFFBBFFBBFFFFFFFF;
+defparam \zero~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N0
+cyclonev_lcell_comb \Add0~45 (
+// Equation(s):
+// \Add0~45_sumout  = SUM(( \in1[15]~input_o  ) + ( !\in1[15]~input_o  $ (!\in1[0]~input_o ) ) + ( !VCC ))
+// \Add0~46  = CARRY(( \in1[15]~input_o  ) + ( !\in1[15]~input_o  $ (!\in1[0]~input_o ) ) + ( !VCC ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[0]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~45_sumout ),
+	.cout(\Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~45 .extended_lut = "off";
+defparam \Add0~45 .lut_mask = 64'h0000AA5500005555;
+defparam \Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N3
+cyclonev_lcell_comb \Add0~41 (
+// Equation(s):
+// \Add0~41_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[1]~input_o ) ) + ( GND ) + ( \Add0~46  ))
+// \Add0~42  = CARRY(( !\in1[15]~input_o  $ (!\in1[1]~input_o ) ) + ( GND ) + ( \Add0~46  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in1[1]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~41_sumout ),
+	.cout(\Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~41 .extended_lut = "off";
+defparam \Add0~41 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N6
+cyclonev_lcell_comb \Add0~37 (
+// Equation(s):
+// \Add0~37_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[2]~input_o ) ) + ( GND ) + ( \Add0~42  ))
+// \Add0~38  = CARRY(( !\in1[15]~input_o  $ (!\in1[2]~input_o ) ) + ( GND ) + ( \Add0~42  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in1[2]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~37_sumout ),
+	.cout(\Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~37 .extended_lut = "off";
+defparam \Add0~37 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N9
+cyclonev_lcell_comb \Add0~29 (
+// Equation(s):
+// \Add0~29_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[3]~input_o ) ) + ( \Add0~38  ))
+// \Add0~30  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[3]~input_o ) ) + ( \Add0~38  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[3]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~29_sumout ),
+	.cout(\Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~29 .extended_lut = "off";
+defparam \Add0~29 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N12
+cyclonev_lcell_comb \Add0~33 (
+// Equation(s):
+// \Add0~33_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[4]~input_o ) ) + ( \Add0~30  ))
+// \Add0~34  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[4]~input_o ) ) + ( \Add0~30  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[4]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~33_sumout ),
+	.cout(\Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~33 .extended_lut = "off";
+defparam \Add0~33 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N15
+cyclonev_lcell_comb \Add0~49 (
+// Equation(s):
+// \Add0~49_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[5]~input_o ) ) + ( \Add0~34  ))
+// \Add0~50  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[5]~input_o ) ) + ( \Add0~34  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[5]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~49_sumout ),
+	.cout(\Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~49 .extended_lut = "off";
+defparam \Add0~49 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N18
+cyclonev_lcell_comb \Add0~53 (
+// Equation(s):
+// \Add0~53_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[6]~input_o ) ) + ( \Add0~50  ))
+// \Add0~54  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[6]~input_o ) ) + ( \Add0~50  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[6]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~53_sumout ),
+	.cout(\Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~53 .extended_lut = "off";
+defparam \Add0~53 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N21
+cyclonev_lcell_comb \Add0~57 (
+// Equation(s):
+// \Add0~57_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[7]~input_o ) ) + ( GND ) + ( \Add0~54  ))
+// \Add0~58  = CARRY(( !\in1[15]~input_o  $ (!\in1[7]~input_o ) ) + ( GND ) + ( \Add0~54  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in1[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~57_sumout ),
+	.cout(\Add0~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~57 .extended_lut = "off";
+defparam \Add0~57 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N24
+cyclonev_lcell_comb \Add0~25 (
+// Equation(s):
+// \Add0~25_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[8]~input_o ) ) + ( \Add0~58  ))
+// \Add0~26  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[8]~input_o ) ) + ( \Add0~58  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[8]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~25_sumout ),
+	.cout(\Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~25 .extended_lut = "off";
+defparam \Add0~25 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N27
+cyclonev_lcell_comb \Add0~21 (
+// Equation(s):
+// \Add0~21_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[9]~input_o ) ) + ( \Add0~26  ))
+// \Add0~22  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[9]~input_o ) ) + ( \Add0~26  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[9]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~21_sumout ),
+	.cout(\Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~21 .extended_lut = "off";
+defparam \Add0~21 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N30
+cyclonev_lcell_comb \Add0~17 (
+// Equation(s):
+// \Add0~17_sumout  = SUM(( GND ) + ( !\in1[15]~input_o  $ (!\in1[10]~input_o ) ) + ( \Add0~22  ))
+// \Add0~18  = CARRY(( GND ) + ( !\in1[15]~input_o  $ (!\in1[10]~input_o ) ) + ( \Add0~22  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[10]~input_o ),
+	.datag(gnd),
+	.cin(\Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~17_sumout ),
+	.cout(\Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~17 .extended_lut = "off";
+defparam \Add0~17 .lut_mask = 64'h0000AA5500000000;
+defparam \Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N33
+cyclonev_lcell_comb \Add0~5 (
+// Equation(s):
+// \Add0~5_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[11]~input_o ) ) + ( GND ) + ( \Add0~18  ))
+// \Add0~6  = CARRY(( !\in1[15]~input_o  $ (!\in1[11]~input_o ) ) + ( GND ) + ( \Add0~18  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in1[11]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~5_sumout ),
+	.cout(\Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~5 .extended_lut = "off";
+defparam \Add0~5 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N36
+cyclonev_lcell_comb \Add0~9 (
+// Equation(s):
+// \Add0~9_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[12]~input_o ) ) + ( GND ) + ( \Add0~6  ))
+// \Add0~10  = CARRY(( !\in1[15]~input_o  $ (!\in1[12]~input_o ) ) + ( GND ) + ( \Add0~6  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in1[12]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~9_sumout ),
+	.cout(\Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~9 .extended_lut = "off";
+defparam \Add0~9 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N39
+cyclonev_lcell_comb \Add0~13 (
+// Equation(s):
+// \Add0~13_sumout  = SUM(( !\in1[15]~input_o  $ (!\in1[13]~input_o ) ) + ( GND ) + ( \Add0~10  ))
+// \Add0~14  = CARRY(( !\in1[15]~input_o  $ (!\in1[13]~input_o ) ) + ( GND ) + ( \Add0~10  ))
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in1[13]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~13_sumout ),
+	.cout(\Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~13 .extended_lut = "off";
+defparam \Add0~13 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N0
+cyclonev_lcell_comb \Add1~45 (
+// Equation(s):
+// \Add1~45_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[0]~input_o ) ) + ( \in2[15]~input_o  ) + ( !VCC ))
+// \Add1~46  = CARRY(( !\in2[15]~input_o  $ (!\in2[0]~input_o ) ) + ( \in2[15]~input_o  ) + ( !VCC ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[0]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~45_sumout ),
+	.cout(\Add1~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~45 .extended_lut = "off";
+defparam \Add1~45 .lut_mask = 64'h0000AAAA000055AA;
+defparam \Add1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N3
+cyclonev_lcell_comb \Add1~41 (
+// Equation(s):
+// \Add1~41_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[1]~input_o ) ) + ( GND ) + ( \Add1~46  ))
+// \Add1~42  = CARRY(( !\in2[15]~input_o  $ (!\in2[1]~input_o ) ) + ( GND ) + ( \Add1~46  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[1]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~41_sumout ),
+	.cout(\Add1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~41 .extended_lut = "off";
+defparam \Add1~41 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N6
+cyclonev_lcell_comb \Add1~37 (
+// Equation(s):
+// \Add1~37_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[2]~input_o ) ) + ( GND ) + ( \Add1~42  ))
+// \Add1~38  = CARRY(( !\in2[15]~input_o  $ (!\in2[2]~input_o ) ) + ( GND ) + ( \Add1~42  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[2]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~37_sumout ),
+	.cout(\Add1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~37 .extended_lut = "off";
+defparam \Add1~37 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N9
+cyclonev_lcell_comb \Add1~29 (
+// Equation(s):
+// \Add1~29_sumout  = SUM(( GND ) + ( !\in2[15]~input_o  $ (!\in2[3]~input_o ) ) + ( \Add1~38  ))
+// \Add1~30  = CARRY(( GND ) + ( !\in2[15]~input_o  $ (!\in2[3]~input_o ) ) + ( \Add1~38  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in2[3]~input_o ),
+	.datag(gnd),
+	.cin(\Add1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~29_sumout ),
+	.cout(\Add1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~29 .extended_lut = "off";
+defparam \Add1~29 .lut_mask = 64'h0000AA5500000000;
+defparam \Add1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N12
+cyclonev_lcell_comb \Add1~33 (
+// Equation(s):
+// \Add1~33_sumout  = SUM(( GND ) + ( !\in2[15]~input_o  $ (!\in2[4]~input_o ) ) + ( \Add1~30  ))
+// \Add1~34  = CARRY(( GND ) + ( !\in2[15]~input_o  $ (!\in2[4]~input_o ) ) + ( \Add1~30  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in2[4]~input_o ),
+	.datag(gnd),
+	.cin(\Add1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~33_sumout ),
+	.cout(\Add1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~33 .extended_lut = "off";
+defparam \Add1~33 .lut_mask = 64'h0000AA5500000000;
+defparam \Add1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N15
+cyclonev_lcell_comb \Add1~49 (
+// Equation(s):
+// \Add1~49_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[5]~input_o ) ) + ( GND ) + ( \Add1~34  ))
+// \Add1~50  = CARRY(( !\in2[15]~input_o  $ (!\in2[5]~input_o ) ) + ( GND ) + ( \Add1~34  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[5]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~49_sumout ),
+	.cout(\Add1~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~49 .extended_lut = "off";
+defparam \Add1~49 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N18
+cyclonev_lcell_comb \Add1~53 (
+// Equation(s):
+// \Add1~53_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[6]~input_o ) ) + ( GND ) + ( \Add1~50  ))
+// \Add1~54  = CARRY(( !\in2[15]~input_o  $ (!\in2[6]~input_o ) ) + ( GND ) + ( \Add1~50  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~53_sumout ),
+	.cout(\Add1~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~53 .extended_lut = "off";
+defparam \Add1~53 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N21
+cyclonev_lcell_comb \Add1~57 (
+// Equation(s):
+// \Add1~57_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[7]~input_o ) ) + ( GND ) + ( \Add1~54  ))
+// \Add1~58  = CARRY(( !\in2[15]~input_o  $ (!\in2[7]~input_o ) ) + ( GND ) + ( \Add1~54  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~57_sumout ),
+	.cout(\Add1~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~57 .extended_lut = "off";
+defparam \Add1~57 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N24
+cyclonev_lcell_comb \Add1~25 (
+// Equation(s):
+// \Add1~25_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[8]~input_o ) ) + ( GND ) + ( \Add1~58  ))
+// \Add1~26  = CARRY(( !\in2[15]~input_o  $ (!\in2[8]~input_o ) ) + ( GND ) + ( \Add1~58  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[8]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~25_sumout ),
+	.cout(\Add1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~25 .extended_lut = "off";
+defparam \Add1~25 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N27
+cyclonev_lcell_comb \Add1~21 (
+// Equation(s):
+// \Add1~21_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[9]~input_o ) ) + ( GND ) + ( \Add1~26  ))
+// \Add1~22  = CARRY(( !\in2[15]~input_o  $ (!\in2[9]~input_o ) ) + ( GND ) + ( \Add1~26  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[9]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~21_sumout ),
+	.cout(\Add1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~21 .extended_lut = "off";
+defparam \Add1~21 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N30
+cyclonev_lcell_comb \Add1~17 (
+// Equation(s):
+// \Add1~17_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[10]~input_o ) ) + ( GND ) + ( \Add1~22  ))
+// \Add1~18  = CARRY(( !\in2[15]~input_o  $ (!\in2[10]~input_o ) ) + ( GND ) + ( \Add1~22  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[10]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~17_sumout ),
+	.cout(\Add1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~17 .extended_lut = "off";
+defparam \Add1~17 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N33
+cyclonev_lcell_comb \Add1~5 (
+// Equation(s):
+// \Add1~5_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[11]~input_o ) ) + ( GND ) + ( \Add1~18  ))
+// \Add1~6  = CARRY(( !\in2[15]~input_o  $ (!\in2[11]~input_o ) ) + ( GND ) + ( \Add1~18  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[11]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~5_sumout ),
+	.cout(\Add1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~5 .extended_lut = "off";
+defparam \Add1~5 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N36
+cyclonev_lcell_comb \Add1~9 (
+// Equation(s):
+// \Add1~9_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[12]~input_o ) ) + ( GND ) + ( \Add1~6  ))
+// \Add1~10  = CARRY(( !\in2[15]~input_o  $ (!\in2[12]~input_o ) ) + ( GND ) + ( \Add1~6  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(!\in2[12]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~9_sumout ),
+	.cout(\Add1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~9 .extended_lut = "off";
+defparam \Add1~9 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N39
+cyclonev_lcell_comb \Add1~13 (
+// Equation(s):
+// \Add1~13_sumout  = SUM(( !\in2[15]~input_o  $ (!\in2[13]~input_o ) ) + ( GND ) + ( \Add1~10  ))
+// \Add1~14  = CARRY(( !\in2[15]~input_o  $ (!\in2[13]~input_o ) ) + ( GND ) + ( \Add1~10  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\in2[13]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~13_sumout ),
+	.cout(\Add1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~13 .extended_lut = "off";
+defparam \Add1~13 .lut_mask = 64'h0000FFFF000055AA;
+defparam \Add1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y4_N42
+cyclonev_lcell_comb \Add0~1 (
+// Equation(s):
+// \Add0~1_sumout  = SUM(( !\in1[14]~input_o  $ (!\in1[15]~input_o ) ) + ( GND ) + ( \Add0~14  ))
+
+	.dataa(!\in1[14]~input_o ),
+	.datab(gnd),
+	.datac(!\in1[15]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add0~1 .extended_lut = "off";
+defparam \Add0~1 .lut_mask = 64'h0000FFFF00005A5A;
+defparam \Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N42
+cyclonev_lcell_comb \Add1~1 (
+// Equation(s):
+// \Add1~1_sumout  = SUM(( !\in2[14]~input_o  $ (!\in2[15]~input_o ) ) + ( GND ) + ( \Add1~14  ))
+
+	.dataa(gnd),
+	.datab(!\in2[14]~input_o ),
+	.datac(!\in2[15]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add1~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add1~1 .extended_lut = "off";
+defparam \Add1~1 .lut_mask = 64'h0000FFFF00003C3C;
+defparam \Add1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N30
+cyclonev_lcell_comb \LessThan0~1 (
+// Equation(s):
+// \LessThan0~1_combout  = ( \Add0~9_sumout  & ( \Add1~1_sumout  & ( (\Add0~1_sumout  & (\Add1~9_sumout  & (!\Add0~13_sumout  $ (\Add1~13_sumout )))) ) ) ) # ( !\Add0~9_sumout  & ( \Add1~1_sumout  & ( (\Add0~1_sumout  & (!\Add1~9_sumout  & (!\Add0~13_sumout  
+// $ (\Add1~13_sumout )))) ) ) ) # ( \Add0~9_sumout  & ( !\Add1~1_sumout  & ( (!\Add0~1_sumout  & (\Add1~9_sumout  & (!\Add0~13_sumout  $ (\Add1~13_sumout )))) ) ) ) # ( !\Add0~9_sumout  & ( !\Add1~1_sumout  & ( (!\Add0~1_sumout  & (!\Add1~9_sumout  & 
+// (!\Add0~13_sumout  $ (\Add1~13_sumout )))) ) ) )
+
+	.dataa(!\Add0~13_sumout ),
+	.datab(!\Add1~13_sumout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add1~9_sumout ),
+	.datae(!\Add0~9_sumout ),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~1 .extended_lut = "off";
+defparam \LessThan0~1 .lut_mask = 64'h9000009009000009;
+defparam \LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N12
+cyclonev_lcell_comb \LessThan0~15 (
+// Equation(s):
+// \LessThan0~15_combout  = ( \Add1~25_sumout  & ( !\Add0~25_sumout  ) )
+
+	.dataa(gnd),
+	.datab(!\Add0~25_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~15 .extended_lut = "off";
+defparam \LessThan0~15 .lut_mask = 64'h00000000CCCCCCCC;
+defparam \LessThan0~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N15
+cyclonev_lcell_comb \LessThan0~6 (
+// Equation(s):
+// \LessThan0~6_combout  = ( \Add0~17_sumout  & ( !\Add1~17_sumout  ) ) # ( !\Add0~17_sumout  & ( \Add1~17_sumout  ) )
+
+	.dataa(!\Add1~17_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~6 .extended_lut = "off";
+defparam \LessThan0~6 .lut_mask = 64'h55555555AAAAAAAA;
+defparam \LessThan0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N6
+cyclonev_lcell_comb \LessThan0~4 (
+// Equation(s):
+// \LessThan0~4_combout  = ( \Add1~5_sumout  & ( !\Add0~5_sumout  ) ) # ( !\Add1~5_sumout  & ( \Add0~5_sumout  ) )
+
+	.dataa(gnd),
+	.datab(!\Add0~5_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~4 .extended_lut = "off";
+defparam \LessThan0~4 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N18
+cyclonev_lcell_comb \LessThan0~16 (
+// Equation(s):
+// \LessThan0~16_combout  = ( \Add1~21_sumout  & ( !\LessThan0~4_combout  & ( (\LessThan0~1_combout  & (!\LessThan0~6_combout  & ((!\Add0~21_sumout ) # (\LessThan0~15_combout )))) ) ) ) # ( !\Add1~21_sumout  & ( !\LessThan0~4_combout  & ( 
+// (\LessThan0~1_combout  & (\LessThan0~15_combout  & (!\LessThan0~6_combout  & !\Add0~21_sumout ))) ) ) )
+
+	.dataa(!\LessThan0~1_combout ),
+	.datab(!\LessThan0~15_combout ),
+	.datac(!\LessThan0~6_combout ),
+	.datad(!\Add0~21_sumout ),
+	.datae(!\Add1~21_sumout ),
+	.dataf(!\LessThan0~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~16 .extended_lut = "off";
+defparam \LessThan0~16 .lut_mask = 64'h1000501000000000;
+defparam \LessThan0~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N0
+cyclonev_lcell_comb \LessThan0~12 (
+// Equation(s):
+// \LessThan0~12_combout  = ( \Add1~53_sumout  & ( \Add1~49_sumout  & ( (\Add0~53_sumout  & (\Add0~49_sumout  & (!\Add1~57_sumout  $ (\Add0~57_sumout )))) ) ) ) # ( !\Add1~53_sumout  & ( \Add1~49_sumout  & ( (!\Add0~53_sumout  & (\Add0~49_sumout  & 
+// (!\Add1~57_sumout  $ (\Add0~57_sumout )))) ) ) ) # ( \Add1~53_sumout  & ( !\Add1~49_sumout  & ( (\Add0~53_sumout  & (!\Add0~49_sumout  & (!\Add1~57_sumout  $ (\Add0~57_sumout )))) ) ) ) # ( !\Add1~53_sumout  & ( !\Add1~49_sumout  & ( (!\Add0~53_sumout  & 
+// (!\Add0~49_sumout  & (!\Add1~57_sumout  $ (\Add0~57_sumout )))) ) ) )
+
+	.dataa(!\Add0~53_sumout ),
+	.datab(!\Add0~49_sumout ),
+	.datac(!\Add1~57_sumout ),
+	.datad(!\Add0~57_sumout ),
+	.datae(!\Add1~53_sumout ),
+	.dataf(!\Add1~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~12 .extended_lut = "off";
+defparam \LessThan0~12 .lut_mask = 64'h8008400420021001;
+defparam \LessThan0~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N6
+cyclonev_lcell_comb \LessThan0~11 (
+// Equation(s):
+// \LessThan0~11_combout  = ( \Add0~33_sumout  & ( \Add1~37_sumout  & ( (\Add1~33_sumout  & ((!\Add1~29_sumout  & (!\Add0~29_sumout  & !\Add0~37_sumout )) # (\Add1~29_sumout  & ((!\Add0~29_sumout ) # (!\Add0~37_sumout ))))) ) ) ) # ( !\Add0~33_sumout  & ( 
+// \Add1~37_sumout  & ( ((!\Add1~29_sumout  & (!\Add0~29_sumout  & !\Add0~37_sumout )) # (\Add1~29_sumout  & ((!\Add0~29_sumout ) # (!\Add0~37_sumout )))) # (\Add1~33_sumout ) ) ) ) # ( \Add0~33_sumout  & ( !\Add1~37_sumout  & ( (\Add1~29_sumout  & 
+// (\Add1~33_sumout  & !\Add0~29_sumout )) ) ) ) # ( !\Add0~33_sumout  & ( !\Add1~37_sumout  & ( ((\Add1~29_sumout  & !\Add0~29_sumout )) # (\Add1~33_sumout ) ) ) )
+
+	.dataa(!\Add1~29_sumout ),
+	.datab(!\Add1~33_sumout ),
+	.datac(!\Add0~29_sumout ),
+	.datad(!\Add0~37_sumout ),
+	.datae(!\Add0~33_sumout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~11 .extended_lut = "off";
+defparam \LessThan0~11 .lut_mask = 64'h73731010F7733110;
+defparam \LessThan0~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N36
+cyclonev_lcell_comb \LessThan0~13 (
+// Equation(s):
+// \LessThan0~13_combout  = ( \Add1~53_sumout  & ( \Add1~49_sumout  & ( (!\Add1~57_sumout  & (!\Add0~57_sumout  & ((!\Add0~53_sumout ) # (!\Add0~49_sumout )))) # (\Add1~57_sumout  & ((!\Add0~53_sumout ) # ((!\Add0~49_sumout ) # (!\Add0~57_sumout )))) ) ) ) # 
+// ( !\Add1~53_sumout  & ( \Add1~49_sumout  & ( (!\Add1~57_sumout  & (!\Add0~53_sumout  & (!\Add0~49_sumout  & !\Add0~57_sumout ))) # (\Add1~57_sumout  & ((!\Add0~57_sumout ) # ((!\Add0~53_sumout  & !\Add0~49_sumout )))) ) ) ) # ( \Add1~53_sumout  & ( 
+// !\Add1~49_sumout  & ( (!\Add0~53_sumout  & ((!\Add0~57_sumout ) # (\Add1~57_sumout ))) # (\Add0~53_sumout  & (\Add1~57_sumout  & !\Add0~57_sumout )) ) ) ) # ( !\Add1~53_sumout  & ( !\Add1~49_sumout  & ( (\Add1~57_sumout  & !\Add0~57_sumout ) ) ) )
+
+	.dataa(!\Add0~53_sumout ),
+	.datab(!\Add0~49_sumout ),
+	.datac(!\Add1~57_sumout ),
+	.datad(!\Add0~57_sumout ),
+	.datae(!\Add1~53_sumout ),
+	.dataf(!\Add1~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~13 .extended_lut = "off";
+defparam \LessThan0~13 .lut_mask = 64'h0F00AF0A8F08EF0E;
+defparam \LessThan0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N3
+cyclonev_lcell_comb \LessThan0~9 (
+// Equation(s):
+// \LessThan0~9_combout  = ( \Add1~33_sumout  & ( (\Add0~33_sumout  & (!\Add0~29_sumout  $ (\Add1~29_sumout ))) ) ) # ( !\Add1~33_sumout  & ( (!\Add0~33_sumout  & (!\Add0~29_sumout  $ (\Add1~29_sumout ))) ) )
+
+	.dataa(!\Add0~29_sumout ),
+	.datab(gnd),
+	.datac(!\Add0~33_sumout ),
+	.datad(!\Add1~29_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~9 .extended_lut = "off";
+defparam \LessThan0~9 .lut_mask = 64'hA050A0500A050A05;
+defparam \LessThan0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N54
+cyclonev_lcell_comb \LessThan0~10 (
+// Equation(s):
+// \LessThan0~10_combout  = ( \Add1~45_sumout  & ( \Add1~41_sumout  & ( (!\Add0~41_sumout  & (!\Add0~37_sumout  $ (((\Add1~37_sumout ))))) # (\Add0~41_sumout  & (!\Add0~45_sumout  & (!\Add0~37_sumout  $ (\Add1~37_sumout )))) ) ) ) # ( !\Add1~45_sumout  & ( 
+// \Add1~41_sumout  & ( (!\Add0~41_sumout  & (!\Add0~37_sumout  $ (\Add1~37_sumout ))) ) ) ) # ( \Add1~45_sumout  & ( !\Add1~41_sumout  & ( (!\Add0~41_sumout  & (!\Add0~45_sumout  & (!\Add0~37_sumout  $ (\Add1~37_sumout )))) ) ) )
+
+	.dataa(!\Add0~37_sumout ),
+	.datab(!\Add0~41_sumout ),
+	.datac(!\Add0~45_sumout ),
+	.datad(!\Add1~37_sumout ),
+	.datae(!\Add1~45_sumout ),
+	.dataf(!\Add1~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~10 .extended_lut = "off";
+defparam \LessThan0~10 .lut_mask = 64'h000080408844A854;
+defparam \LessThan0~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N51
+cyclonev_lcell_comb \LessThan0~8 (
+// Equation(s):
+// \LessThan0~8_combout  = ( \Add1~25_sumout  & ( !\Add0~25_sumout  ) ) # ( !\Add1~25_sumout  & ( \Add0~25_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add0~25_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~8 .extended_lut = "off";
+defparam \LessThan0~8 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \LessThan0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N42
+cyclonev_lcell_comb \LessThan0~14 (
+// Equation(s):
+// \LessThan0~14_combout  = ( \LessThan0~10_combout  & ( !\LessThan0~8_combout  & ( ((\LessThan0~12_combout  & ((\LessThan0~9_combout ) # (\LessThan0~11_combout )))) # (\LessThan0~13_combout ) ) ) ) # ( !\LessThan0~10_combout  & ( !\LessThan0~8_combout  & ( 
+// ((\LessThan0~12_combout  & \LessThan0~11_combout )) # (\LessThan0~13_combout ) ) ) )
+
+	.dataa(!\LessThan0~12_combout ),
+	.datab(!\LessThan0~11_combout ),
+	.datac(!\LessThan0~13_combout ),
+	.datad(!\LessThan0~9_combout ),
+	.datae(!\LessThan0~10_combout ),
+	.dataf(!\LessThan0~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~14 .extended_lut = "off";
+defparam \LessThan0~14 .lut_mask = 64'h1F1F1F5F00000000;
+defparam \LessThan0~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N42
+cyclonev_lcell_comb \LessThan0~5 (
+// Equation(s):
+// \LessThan0~5_combout  = ( \Add0~21_sumout  & ( !\Add1~21_sumout  ) ) # ( !\Add0~21_sumout  & ( \Add1~21_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~5 .extended_lut = "off";
+defparam \LessThan0~5 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N45
+cyclonev_lcell_comb \LessThan0~7 (
+// Equation(s):
+// \LessThan0~7_combout  = ( !\LessThan0~4_combout  & ( (!\LessThan0~6_combout  & (!\LessThan0~5_combout  & \LessThan0~1_combout )) ) )
+
+	.dataa(!\LessThan0~6_combout ),
+	.datab(!\LessThan0~5_combout ),
+	.datac(!\LessThan0~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\LessThan0~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~7 .extended_lut = "off";
+defparam \LessThan0~7 .lut_mask = 64'h0808080800000000;
+defparam \LessThan0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N6
+cyclonev_lcell_comb \LessThan0~2 (
+// Equation(s):
+// \LessThan0~2_combout  = ( \Add0~9_sumout  & ( \Add1~1_sumout  & ( (!\Add0~13_sumout  & (\Add1~13_sumout  & \Add0~1_sumout )) ) ) ) # ( !\Add0~9_sumout  & ( \Add1~1_sumout  & ( (\Add0~1_sumout  & ((!\Add0~13_sumout  & ((\Add1~9_sumout ) # (\Add1~13_sumout 
+// ))) # (\Add0~13_sumout  & (\Add1~13_sumout  & \Add1~9_sumout )))) ) ) ) # ( \Add0~9_sumout  & ( !\Add1~1_sumout  & ( (!\Add0~13_sumout  & (\Add1~13_sumout  & !\Add0~1_sumout )) ) ) ) # ( !\Add0~9_sumout  & ( !\Add1~1_sumout  & ( (!\Add0~1_sumout  & 
+// ((!\Add0~13_sumout  & ((\Add1~9_sumout ) # (\Add1~13_sumout ))) # (\Add0~13_sumout  & (\Add1~13_sumout  & \Add1~9_sumout )))) ) ) )
+
+	.dataa(!\Add0~13_sumout ),
+	.datab(!\Add1~13_sumout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add1~9_sumout ),
+	.datae(!\Add0~9_sumout ),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~2 .extended_lut = "off";
+defparam \LessThan0~2 .lut_mask = 64'h20B02020020B0202;
+defparam \LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N30
+cyclonev_lcell_comb \LessThan0~3 (
+// Equation(s):
+// \LessThan0~3_combout  = ( !\LessThan0~2_combout  & ( \Add1~5_sumout  & ( (!\LessThan0~1_combout ) # ((\Add0~5_sumout  & ((!\Add1~17_sumout ) # (\Add0~17_sumout )))) ) ) ) # ( !\LessThan0~2_combout  & ( !\Add1~5_sumout  & ( (!\Add1~17_sumout ) # 
+// (((!\LessThan0~1_combout ) # (\Add0~17_sumout )) # (\Add0~5_sumout )) ) ) )
+
+	.dataa(!\Add1~17_sumout ),
+	.datab(!\Add0~5_sumout ),
+	.datac(!\LessThan0~1_combout ),
+	.datad(!\Add0~17_sumout ),
+	.datae(!\LessThan0~2_combout ),
+	.dataf(!\Add1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~3 .extended_lut = "off";
+defparam \LessThan0~3 .lut_mask = 64'hFBFF0000F2F30000;
+defparam \LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N15
+cyclonev_lcell_comb \LessThan0~18 (
+// Equation(s):
+// \LessThan0~18_combout  = ( \LessThan0~3_combout  & ( ((\LessThan0~14_combout  & \LessThan0~7_combout )) # (\LessThan0~16_combout ) ) ) # ( !\LessThan0~3_combout  )
+
+	.dataa(!\LessThan0~16_combout ),
+	.datab(gnd),
+	.datac(!\LessThan0~14_combout ),
+	.datad(!\LessThan0~7_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~18 .extended_lut = "off";
+defparam \LessThan0~18 .lut_mask = 64'hFFFFFFFF555F555F;
+defparam \LessThan0~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N30
+cyclonev_lcell_comb \LessThan0~0 (
+// Equation(s):
+// \LessThan0~0_combout  = (!\Add0~1_sumout  & \Add1~1_sumout )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\Add1~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~0 .extended_lut = "off";
+defparam \LessThan0~0 .lut_mask = 64'h00AA00AA00AA00AA;
+defparam \LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N30
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|l|vld~0 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|l|vld~0_combout  = ( !\Add1~1_sumout  & ( (!\Add1~41_sumout  & (!\Add1~37_sumout  & !\Add1~45_sumout )) ) )
+
+	.dataa(gnd),
+	.datab(!\Add1~41_sumout ),
+	.datac(!\Add1~37_sumout ),
+	.datad(!\Add1~45_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|l|vld~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|l|vld~0 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|l|vld~0 .lut_mask = 64'hC000C00000000000;
+defparam \uut_de2|xinst_k|l1|l|vld~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N39
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|l|h|vld (
+// Equation(s):
+// \uut_de2|xinst_k|l1|l|h|vld~combout  = ( \Add1~29_sumout  & ( (\Add1~49_sumout  & (\Add1~53_sumout  & (\Add1~33_sumout  & \Add1~1_sumout ))) ) ) # ( !\Add1~29_sumout  & ( (!\Add1~49_sumout  & (!\Add1~53_sumout  & (!\Add1~33_sumout  & !\Add1~1_sumout ))) ) 
+// )
+
+	.dataa(!\Add1~49_sumout ),
+	.datab(!\Add1~53_sumout ),
+	.datac(!\Add1~33_sumout ),
+	.datad(!\Add1~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|l|h|vld~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|l|h|vld .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|l|h|vld .lut_mask = 64'h8000800000010001;
+defparam \uut_de2|xinst_k|l1|l|h|vld .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N42
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[2]~0 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[2]~0_combout  = ( \Add1~1_sumout  & ( (\Add1~9_sumout  & (\Add1~5_sumout  & \Add1~13_sumout )) ) ) # ( !\Add1~1_sumout  & ( (!\Add1~9_sumout  & (!\Add1~5_sumout  & !\Add1~13_sumout )) ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(!\Add1~5_sumout ),
+	.datac(gnd),
+	.datad(!\Add1~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[2]~0 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[2]~0 .lut_mask = 64'h8800880000110011;
+defparam \uut_de2|xinst_k|l1|out[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N30
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|h|l|vld (
+// Equation(s):
+// \uut_de2|xinst_k|l1|h|l|vld~combout  = ( \Add1~1_sumout  & ( (\Add1~57_sumout  & (\Add1~25_sumout  & (\Add1~17_sumout  & \Add1~21_sumout ))) ) ) # ( !\Add1~1_sumout  & ( (!\Add1~57_sumout  & (!\Add1~25_sumout  & (!\Add1~17_sumout  & !\Add1~21_sumout ))) ) 
+// )
+
+	.dataa(!\Add1~57_sumout ),
+	.datab(!\Add1~25_sumout ),
+	.datac(!\Add1~17_sumout ),
+	.datad(!\Add1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|h|l|vld~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|h|l|vld .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|h|l|vld .lut_mask = 64'h8000800000010001;
+defparam \uut_de2|xinst_k|l1|h|l|vld .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N21
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[2]~1 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[2]~1_combout  = ( \uut_de2|xinst_k|l1|h|l|vld~combout  & ( (!\uut_de2|xinst_k|l1|l|vld~0_combout  & (\uut_de2|xinst_k|l1|l|h|vld~combout  & \uut_de2|xinst_k|l1|out[2]~0_combout )) ) ) # ( !\uut_de2|xinst_k|l1|h|l|vld~combout  & ( 
+// \uut_de2|xinst_k|l1|out[2]~0_combout  ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|l|vld~0_combout ),
+	.datab(!\uut_de2|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[2]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|xinst_k|l1|h|l|vld~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[2]~1 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[2]~1 .lut_mask = 64'h0F0F0F0F02020202;
+defparam \uut_de2|xinst_k|l1|out[2]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N12
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[3]~13 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[3]~13_combout  = ( \uut_de2|xinst_k|l1|h|l|vld~combout  & ( (\uut_de2|xinst_k|l1|out[2]~0_combout  & ((!\uut_de2|xinst_k|l1|l|h|vld~combout ) # (!\uut_de2|xinst_k|l1|l|vld~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de2|xinst_k|l1|l|vld~0_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|xinst_k|l1|h|l|vld~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[3]~13 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[3]~13 .lut_mask = 64'h0000000000FC00FC;
+defparam \uut_de2|xinst_k|l1|out[3]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N42
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[1]~8 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[1]~8_combout  = ( \Add1~33_sumout  & ( \Add1~37_sumout  & ( (\Add1~29_sumout  & (\Add1~1_sumout  & !\Add1~41_sumout )) ) ) ) # ( !\Add1~33_sumout  & ( \Add1~37_sumout  & ( (!\Add1~29_sumout  & !\Add1~1_sumout ) ) ) ) # ( 
+// \Add1~33_sumout  & ( !\Add1~37_sumout  & ( (\Add1~29_sumout  & \Add1~1_sumout ) ) ) ) # ( !\Add1~33_sumout  & ( !\Add1~37_sumout  & ( (!\Add1~29_sumout  & (!\Add1~1_sumout  & ((!\Add1~45_sumout ) # (\Add1~41_sumout )))) ) ) )
+
+	.dataa(!\Add1~45_sumout ),
+	.datab(!\Add1~29_sumout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\Add1~41_sumout ),
+	.datae(!\Add1~33_sumout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[1]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[1]~8 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[1]~8 .lut_mask = 64'h80C00303C0C00300;
+defparam \uut_de2|xinst_k|l1|out[1]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y4_N57
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[1]~11 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[1]~11_combout  = ( \Add1~5_sumout  & ( (\Add1~1_sumout  & \Add1~9_sumout ) ) ) # ( !\Add1~5_sumout  & ( (!\Add1~1_sumout  & !\Add1~9_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\Add1~9_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[1]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[1]~11 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[1]~11 .lut_mask = 64'hF000F000000F000F;
+defparam \uut_de2|xinst_k|l1|out[1]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N36
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[1]~9 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[1]~9_combout  = ( \Add1~1_sumout  & ( (\Add1~49_sumout  & (\Add1~53_sumout  & (\Add1~21_sumout  & \Add1~17_sumout ))) ) ) # ( !\Add1~1_sumout  & ( (!\Add1~49_sumout  & (!\Add1~53_sumout  & (!\Add1~21_sumout  & !\Add1~17_sumout ))) 
+// ) )
+
+	.dataa(!\Add1~49_sumout ),
+	.datab(!\Add1~53_sumout ),
+	.datac(!\Add1~21_sumout ),
+	.datad(!\Add1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[1]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[1]~9 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[1]~9 .lut_mask = 64'h8000800000010001;
+defparam \uut_de2|xinst_k|l1|out[1]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N33
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[1]~10 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[1]~10_combout  = ( \Add1~17_sumout  & ( (\Add1~1_sumout  & (\Add1~21_sumout  & ((!\Add1~57_sumout ) # (!\Add1~25_sumout )))) ) ) # ( !\Add1~17_sumout  & ( (!\Add1~1_sumout  & (!\Add1~21_sumout  & ((\Add1~25_sumout ) # 
+// (\Add1~57_sumout )))) ) )
+
+	.dataa(!\Add1~57_sumout ),
+	.datab(!\Add1~25_sumout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\Add1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[1]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[1]~10 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[1]~10 .lut_mask = 64'h70007000000E000E;
+defparam \uut_de2|xinst_k|l1|out[1]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N48
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[1]~12 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[1]~12_combout  = ( \uut_de2|xinst_k|l1|out[1]~9_combout  & ( \uut_de2|xinst_k|l1|out[1]~10_combout  & ( !\Add1~1_sumout  $ (\Add1~13_sumout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[1]~9_combout  & ( 
+// \uut_de2|xinst_k|l1|out[1]~10_combout  & ( !\Add1~1_sumout  $ (\Add1~13_sumout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[1]~9_combout  & ( !\uut_de2|xinst_k|l1|out[1]~10_combout  & ( (!\uut_de2|xinst_k|l1|out[1]~8_combout  & (!\Add1~1_sumout  $ 
+// ((\Add1~13_sumout )))) # (\uut_de2|xinst_k|l1|out[1]~8_combout  & (!\uut_de2|xinst_k|l1|out[1]~11_combout  & (!\Add1~1_sumout  $ (\Add1~13_sumout )))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[1]~9_combout  & ( !\uut_de2|xinst_k|l1|out[1]~10_combout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~11_combout  & (!\Add1~1_sumout  $ (\Add1~13_sumout ))) ) ) )
+
+	.dataa(!\Add1~1_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~8_combout ),
+	.datac(!\Add1~13_sumout ),
+	.datad(!\uut_de2|xinst_k|l1|out[1]~11_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[1]~9_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[1]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[1]~12 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[1]~12 .lut_mask = 64'hA500A584A5A5A5A5;
+defparam \uut_de2|xinst_k|l1|out[1]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N0
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~5 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~5_combout  = ( \Add1~21_sumout  & ( \Add1~17_sumout  & ( (\Add1~9_sumout  & (\Add1~1_sumout  & (!\Add1~57_sumout  & \Add1~25_sumout ))) ) ) ) # ( !\Add1~21_sumout  & ( \Add1~17_sumout  & ( (\Add1~9_sumout  & \Add1~1_sumout ) ) ) 
+// ) # ( \Add1~21_sumout  & ( !\Add1~17_sumout  & ( (!\Add1~9_sumout  & !\Add1~1_sumout ) ) ) ) # ( !\Add1~21_sumout  & ( !\Add1~17_sumout  & ( (!\Add1~9_sumout  & (!\Add1~1_sumout  & (\Add1~57_sumout  & !\Add1~25_sumout ))) ) ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(!\Add1~1_sumout ),
+	.datac(!\Add1~57_sumout ),
+	.datad(!\Add1~25_sumout ),
+	.datae(!\Add1~21_sumout ),
+	.dataf(!\Add1~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~5 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~5 .lut_mask = 64'h0800888811110010;
+defparam \uut_de2|xinst_k|l1|out[0]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N36
+cyclonev_lcell_comb \uut_de2|xin_r[6]~0 (
+// Equation(s):
+// \uut_de2|xin_r[6]~0_combout  = !\Add1~53_sumout  $ (!\Add1~1_sumout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add1~53_sumout ),
+	.datad(!\Add1~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xin_r[6]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xin_r[6]~0 .extended_lut = "off";
+defparam \uut_de2|xin_r[6]~0 .lut_mask = 64'h0FF00FF00FF00FF0;
+defparam \uut_de2|xin_r[6]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N6
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~3 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~3_combout  = ( \Add1~33_sumout  & ( \Add1~37_sumout  & ( (!\Add1~49_sumout  & (((!\Add1~1_sumout )))) # (\Add1~49_sumout  & (!\Add1~45_sumout  & (\Add1~1_sumout  & \Add1~41_sumout ))) ) ) ) # ( !\Add1~33_sumout  & ( 
+// \Add1~37_sumout  & ( !\Add1~49_sumout  $ (\Add1~1_sumout ) ) ) ) # ( \Add1~33_sumout  & ( !\Add1~37_sumout  & ( !\Add1~49_sumout  $ (\Add1~1_sumout ) ) ) ) # ( !\Add1~33_sumout  & ( !\Add1~37_sumout  & ( (!\Add1~49_sumout  & (!\Add1~1_sumout  & 
+// !\Add1~41_sumout )) # (\Add1~49_sumout  & (\Add1~1_sumout )) ) ) )
+
+	.dataa(!\Add1~45_sumout ),
+	.datab(!\Add1~49_sumout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\Add1~41_sumout ),
+	.datae(!\Add1~33_sumout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~3 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~3 .lut_mask = 64'hC303C3C3C3C3C0C2;
+defparam \uut_de2|xinst_k|l1|out[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N45
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~6 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~6_combout  = ( \Add1~1_sumout  & ( (\Add1~13_sumout  & ((!\Add1~9_sumout ) # (\Add1~5_sumout ))) ) ) # ( !\Add1~1_sumout  & ( (!\Add1~13_sumout  & ((!\Add1~5_sumout ) # (\Add1~9_sumout ))) ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(gnd),
+	.datac(!\Add1~5_sumout ),
+	.datad(!\Add1~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~6 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~6 .lut_mask = 64'hF500F50000AF00AF;
+defparam \uut_de2|xinst_k|l1|out[0]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N45
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~2 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~2_combout  = (!\Add1~1_sumout  & (!\Add1~33_sumout  & \Add1~29_sumout )) # (\Add1~1_sumout  & (\Add1~33_sumout  & !\Add1~29_sumout ))
+
+	.dataa(gnd),
+	.datab(!\Add1~1_sumout ),
+	.datac(!\Add1~33_sumout ),
+	.datad(!\Add1~29_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~2 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~2 .lut_mask = 64'h03C003C003C003C0;
+defparam \uut_de2|xinst_k|l1|out[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N24
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~4 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~4_combout  = ( \Add1~21_sumout  & ( \Add1~17_sumout  & ( (\Add1~9_sumout  & (\Add1~1_sumout  & (\Add1~57_sumout  & \Add1~25_sumout ))) ) ) ) # ( !\Add1~21_sumout  & ( !\Add1~17_sumout  & ( (!\Add1~9_sumout  & (!\Add1~1_sumout  & 
+// (!\Add1~57_sumout  & !\Add1~25_sumout ))) ) ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(!\Add1~1_sumout ),
+	.datac(!\Add1~57_sumout ),
+	.datad(!\Add1~25_sumout ),
+	.datae(!\Add1~21_sumout ),
+	.dataf(!\Add1~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~4 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~4 .lut_mask = 64'h8000000000000001;
+defparam \uut_de2|xinst_k|l1|out[0]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N6
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[0]~7 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[0]~7_combout  = ( \uut_de2|xinst_k|l1|out[0]~2_combout  & ( \uut_de2|xinst_k|l1|out[0]~4_combout  & ( ((!\uut_de2|xin_r[6]~0_combout ) # (!\uut_de2|xinst_k|l1|out[0]~6_combout )) # (\uut_de2|xinst_k|l1|out[0]~5_combout ) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[0]~2_combout  & ( \uut_de2|xinst_k|l1|out[0]~4_combout  & ( ((!\uut_de2|xinst_k|l1|out[0]~6_combout ) # ((!\uut_de2|xin_r[6]~0_combout  & !\uut_de2|xinst_k|l1|out[0]~3_combout ))) # (\uut_de2|xinst_k|l1|out[0]~5_combout ) ) ) ) # 
+// ( \uut_de2|xinst_k|l1|out[0]~2_combout  & ( !\uut_de2|xinst_k|l1|out[0]~4_combout  & ( (!\uut_de2|xinst_k|l1|out[0]~6_combout ) # (\uut_de2|xinst_k|l1|out[0]~5_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~2_combout  & ( 
+// !\uut_de2|xinst_k|l1|out[0]~4_combout  & ( (!\uut_de2|xinst_k|l1|out[0]~6_combout ) # (\uut_de2|xinst_k|l1|out[0]~5_combout ) ) ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|out[0]~5_combout ),
+	.datab(!\uut_de2|xin_r[6]~0_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[0]~3_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[0]~6_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~2_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[0]~7 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[0]~7 .lut_mask = 64'hFF55FF55FFD5FFDD;
+defparam \uut_de2|xinst_k|l1|out[0]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N36
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][6]~8 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][6]~8_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~29_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~41_sumout ))) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~37_sumout  & ( (\Add1~33_sumout ) # (\uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & 
+// (\Add1~29_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~41_sumout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & \Add1~33_sumout ) ) ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datab(!\Add1~29_sumout ),
+	.datac(!\Add1~33_sumout ),
+	.datad(!\Add1~41_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][6]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][6]~8 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][6]~8 .lut_mask = 64'h0A0A22775F5F2277;
+defparam \uut_de2|ls|tmp[1][6]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N18
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][2]~9 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][2]~9_combout  = ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\Add1~45_sumout  & !\uut_de2|xinst_k|l1|out[1]~12_combout ) ) )
+
+	.dataa(!\Add1~45_sumout ),
+	.datab(gnd),
+	.datac(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][2]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][2]~9 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][2]~9 .lut_mask = 64'h5050505000000000;
+defparam \uut_de2|ls|tmp[1][2]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N39
+cyclonev_lcell_comb \uut_de2|ls|c[6]~10 (
+// Equation(s):
+// \uut_de2|ls|c[6]~10_combout  = ( \uut_de2|ls|tmp[1][2]~9_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout  & ((\uut_de2|ls|tmp[1][6]~8_combout ) # (\uut_de2|xinst_k|l1|out[2]~1_combout ))) ) ) # ( !\uut_de2|ls|tmp[1][2]~9_combout  & ( 
+// (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (!\uut_de2|xinst_k|l1|out[3]~13_combout  & \uut_de2|ls|tmp[1][6]~8_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\uut_de2|ls|tmp[1][6]~8_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[6]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[6]~10 .extended_lut = "off";
+defparam \uut_de2|ls|c[6]~10 .lut_mask = 64'h00C000C030F030F0;
+defparam \uut_de2|ls|c[6]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N48
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[0]~0 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[0]~0_combout  = ( \LessThan0~7_combout  & ( \LessThan0~3_combout  & ( ((\Add0~1_sumout  & (!\LessThan0~14_combout  & !\LessThan0~16_combout ))) # (\Add1~1_sumout ) ) ) ) # ( !\LessThan0~7_combout  & ( \LessThan0~3_combout  & ( 
+// ((\Add0~1_sumout  & !\LessThan0~16_combout )) # (\Add1~1_sumout ) ) ) ) # ( \LessThan0~7_combout  & ( !\LessThan0~3_combout  & ( \Add1~1_sumout  ) ) ) # ( !\LessThan0~7_combout  & ( !\LessThan0~3_combout  & ( \Add1~1_sumout  ) ) )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(!\LessThan0~14_combout ),
+	.datac(!\LessThan0~16_combout ),
+	.datad(!\Add1~1_sumout ),
+	.datae(!\LessThan0~7_combout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[0]~0 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[0]~0 .lut_mask = 64'h00FF00FF50FF40FF;
+defparam \uut_abs_regime1|regime_N[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N18
+cyclonev_lcell_comb \uut_de2|xinst_k|l1|out[2]~14 (
+// Equation(s):
+// \uut_de2|xinst_k|l1|out[2]~14_combout  = ( \uut_de2|xinst_k|l1|h|l|vld~combout  & ( (!\uut_de2|xinst_k|l1|l|h|vld~combout ) # (\uut_de2|xinst_k|l1|l|vld~0_combout ) ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|l|vld~0_combout ),
+	.datab(!\uut_de2|xinst_k|l1|l|h|vld~combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|xinst_k|l1|h|l|vld~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|xinst_k|l1|out[2]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|xinst_k|l1|out[2]~14 .extended_lut = "off";
+defparam \uut_de2|xinst_k|l1|out[2]~14 .lut_mask = 64'h00000000DDDDDDDD;
+defparam \uut_de2|xinst_k|l1|out[2]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N18
+cyclonev_lcell_comb \uut_de2|regime[2]~0 (
+// Equation(s):
+// \uut_de2|regime[2]~0_combout  = ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \uut_de2|xinst_k|l1|out[2]~14_combout  & ( (\Add1~1_sumout  & !\uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( 
+// !\uut_de2|xinst_k|l1|out[2]~14_combout  & ( (\uut_de2|xinst_k|l1|out[1]~11_combout  & (!\Add1~13_sumout  $ (\Add1~1_sumout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\uut_de2|xinst_k|l1|out[2]~14_combout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~11_combout  & (((\Add1~1_sumout  & !\uut_de2|xinst_k|l1|out[1]~12_combout )))) # (\uut_de2|xinst_k|l1|out[1]~11_combout  & (!\Add1~13_sumout  $ (((\Add1~1_sumout  & \uut_de2|xinst_k|l1|out[1]~12_combout ))))) ) ) )
+
+	.dataa(!\Add1~13_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~11_combout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[2]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|regime[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|regime[2]~0 .extended_lut = "off";
+defparam \uut_de2|regime[2]~0 .lut_mask = 64'h2E2121210F000000;
+defparam \uut_de2|regime[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N6
+cyclonev_lcell_comb \LessThan0~17 (
+// Equation(s):
+// \LessThan0~17_combout  = ( \LessThan0~0_combout  ) # ( !\LessThan0~0_combout  & ( (!\LessThan0~3_combout ) # (((\LessThan0~7_combout  & \LessThan0~14_combout )) # (\LessThan0~16_combout )) ) )
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\LessThan0~7_combout ),
+	.datac(!\LessThan0~16_combout ),
+	.datad(!\LessThan0~14_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~17 .extended_lut = "off";
+defparam \LessThan0~17 .lut_mask = 64'hAFBFAFBFFFFFFFFF;
+defparam \LessThan0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N30
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[1]~8 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[1]~8_combout  = ( \Add0~41_sumout  & ( \Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~29_sumout  & !\Add0~33_sumout )) ) ) ) # ( !\Add0~41_sumout  & ( \Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~29_sumout  & !\Add0~33_sumout 
+// )) # (\Add0~1_sumout  & (\Add0~29_sumout  & \Add0~33_sumout )) ) ) ) # ( \Add0~41_sumout  & ( !\Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~29_sumout  & !\Add0~33_sumout )) # (\Add0~1_sumout  & (\Add0~29_sumout  & \Add0~33_sumout )) ) ) ) # ( 
+// !\Add0~41_sumout  & ( !\Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~29_sumout  & (!\Add0~45_sumout  & !\Add0~33_sumout ))) # (\Add0~1_sumout  & (\Add0~29_sumout  & ((\Add0~33_sumout )))) ) ) )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(!\Add0~29_sumout ),
+	.datac(!\Add0~45_sumout ),
+	.datad(!\Add0~33_sumout ),
+	.datae(!\Add0~41_sumout ),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[1]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[1]~8 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[1]~8 .lut_mask = 64'h8011881188118800;
+defparam \uut_de1|xinst_k|l1|out[1]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y8_N30
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[1]~11 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[1]~11_combout  = ( \Add0~9_sumout  & ( \Add0~5_sumout  & ( \Add0~1_sumout  ) ) ) # ( !\Add0~9_sumout  & ( !\Add0~5_sumout  & ( !\Add0~1_sumout  ) ) )
+
+	.dataa(gnd),
+	.datab(!\Add0~1_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\Add0~9_sumout ),
+	.dataf(!\Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[1]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[1]~11 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[1]~11 .lut_mask = 64'hCCCC000000003333;
+defparam \uut_de1|xinst_k|l1|out[1]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N33
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[1]~10 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[1]~10_combout  = ( \Add0~21_sumout  & ( (\Add0~17_sumout  & (\Add0~1_sumout  & ((!\Add0~57_sumout ) # (!\Add0~25_sumout )))) ) ) # ( !\Add0~21_sumout  & ( (!\Add0~17_sumout  & (!\Add0~1_sumout  & ((\Add0~25_sumout ) # 
+// (\Add0~57_sumout )))) ) )
+
+	.dataa(!\Add0~57_sumout ),
+	.datab(!\Add0~17_sumout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[1]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[1]~10 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[1]~10 .lut_mask = 64'h40C040C003020302;
+defparam \uut_de1|xinst_k|l1|out[1]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N48
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[1]~9 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[1]~9_combout  = ( \Add0~1_sumout  & ( \Add0~49_sumout  & ( (\Add0~53_sumout  & (\Add0~17_sumout  & \Add0~21_sumout )) ) ) ) # ( !\Add0~1_sumout  & ( !\Add0~49_sumout  & ( (!\Add0~53_sumout  & (!\Add0~17_sumout  & !\Add0~21_sumout 
+// )) ) ) )
+
+	.dataa(!\Add0~53_sumout ),
+	.datab(!\Add0~17_sumout ),
+	.datac(!\Add0~21_sumout ),
+	.datad(gnd),
+	.datae(!\Add0~1_sumout ),
+	.dataf(!\Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[1]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[1]~9 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[1]~9 .lut_mask = 64'h8080000000000101;
+defparam \uut_de1|xinst_k|l1|out[1]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N54
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[1]~12 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[1]~12_combout  = ( \uut_de1|xinst_k|l1|out[1]~9_combout  & ( \Add0~13_sumout  & ( (\Add0~1_sumout  & ((!\uut_de1|xinst_k|l1|out[1]~8_combout ) # ((!\uut_de1|xinst_k|l1|out[1]~11_combout ) # (\uut_de1|xinst_k|l1|out[1]~10_combout 
+// )))) ) ) ) # ( !\uut_de1|xinst_k|l1|out[1]~9_combout  & ( \Add0~13_sumout  & ( (\Add0~1_sumout  & ((!\uut_de1|xinst_k|l1|out[1]~11_combout ) # (\uut_de1|xinst_k|l1|out[1]~10_combout ))) ) ) ) # ( \uut_de1|xinst_k|l1|out[1]~9_combout  & ( !\Add0~13_sumout  
+// & ( (!\Add0~1_sumout  & ((!\uut_de1|xinst_k|l1|out[1]~8_combout ) # ((!\uut_de1|xinst_k|l1|out[1]~11_combout ) # (\uut_de1|xinst_k|l1|out[1]~10_combout )))) ) ) ) # ( !\uut_de1|xinst_k|l1|out[1]~9_combout  & ( !\Add0~13_sumout  & ( (!\Add0~1_sumout  & 
+// ((!\uut_de1|xinst_k|l1|out[1]~11_combout ) # (\uut_de1|xinst_k|l1|out[1]~10_combout ))) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[1]~8_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~11_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[1]~10_combout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[1]~9_combout ),
+	.dataf(!\Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[1]~12 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[1]~12 .lut_mask = 64'hCF00EF0000CF00EF;
+defparam \uut_de1|xinst_k|l1|out[1]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N3
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~2 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~2_combout  = ( \Add0~29_sumout  & ( (!\Add0~33_sumout  & !\Add0~1_sumout ) ) ) # ( !\Add0~29_sumout  & ( (\Add0~33_sumout  & \Add0~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add0~33_sumout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~2 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~2 .lut_mask = 64'h000F000FF000F000;
+defparam \uut_de1|xinst_k|l1|out[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N42
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~5 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~5_combout  = ( \Add0~25_sumout  & ( \Add0~21_sumout  & ( (!\Add0~9_sumout  & (!\Add0~17_sumout  & ((!\Add0~1_sumout )))) # (\Add0~9_sumout  & (\Add0~17_sumout  & (!\Add0~57_sumout  & \Add0~1_sumout ))) ) ) ) # ( !\Add0~25_sumout 
+//  & ( \Add0~21_sumout  & ( (!\Add0~9_sumout  & (!\Add0~17_sumout  & !\Add0~1_sumout )) ) ) ) # ( \Add0~25_sumout  & ( !\Add0~21_sumout  & ( (\Add0~9_sumout  & (\Add0~17_sumout  & \Add0~1_sumout )) ) ) ) # ( !\Add0~25_sumout  & ( !\Add0~21_sumout  & ( 
+// (!\Add0~9_sumout  & (!\Add0~17_sumout  & (\Add0~57_sumout  & !\Add0~1_sumout ))) # (\Add0~9_sumout  & (\Add0~17_sumout  & ((\Add0~1_sumout )))) ) ) )
+
+	.dataa(!\Add0~9_sumout ),
+	.datab(!\Add0~17_sumout ),
+	.datac(!\Add0~57_sumout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\Add0~25_sumout ),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~5 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~5 .lut_mask = 64'h0811001188008810;
+defparam \uut_de1|xinst_k|l1|out[0]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N36
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~4 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~4_combout  = ( \Add0~25_sumout  & ( \Add0~21_sumout  & ( (\Add0~9_sumout  & (\Add0~17_sumout  & (\Add0~57_sumout  & \Add0~1_sumout ))) ) ) ) # ( !\Add0~25_sumout  & ( !\Add0~21_sumout  & ( (!\Add0~9_sumout  & (!\Add0~17_sumout  
+// & (!\Add0~57_sumout  & !\Add0~1_sumout ))) ) ) )
+
+	.dataa(!\Add0~9_sumout ),
+	.datab(!\Add0~17_sumout ),
+	.datac(!\Add0~57_sumout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\Add0~25_sumout ),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~4 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~4 .lut_mask = 64'h8000000000000001;
+defparam \uut_de1|xinst_k|l1|out[0]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y6_N30
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~6 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~6_combout  = ( \Add0~13_sumout  & ( (\Add0~1_sumout  & ((!\Add0~9_sumout ) # (\Add0~5_sumout ))) ) ) # ( !\Add0~13_sumout  & ( (!\Add0~1_sumout  & ((!\Add0~5_sumout ) # (\Add0~9_sumout ))) ) )
+
+	.dataa(!\Add0~5_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~9_sumout ),
+	.datad(gnd),
+	.datae(!\Add0~13_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~6 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~6 .lut_mask = 64'h8C8C31318C8C3131;
+defparam \uut_de1|xinst_k|l1|out[0]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N24
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~3 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~3_combout  = ( \Add0~41_sumout  & ( \Add0~37_sumout  & ( (!\Add0~1_sumout  & (((!\Add0~49_sumout )))) # (\Add0~1_sumout  & (\Add0~49_sumout  & ((!\Add0~45_sumout ) # (!\Add0~33_sumout )))) ) ) ) # ( !\Add0~41_sumout  & ( 
+// \Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~49_sumout )) # (\Add0~1_sumout  & (\Add0~49_sumout  & !\Add0~33_sumout )) ) ) ) # ( \Add0~41_sumout  & ( !\Add0~37_sumout  & ( (!\Add0~1_sumout  & (!\Add0~49_sumout  & \Add0~33_sumout )) # (\Add0~1_sumout  
+// & (\Add0~49_sumout )) ) ) ) # ( !\Add0~41_sumout  & ( !\Add0~37_sumout  & ( !\Add0~1_sumout  $ (\Add0~49_sumout ) ) ) )
+
+	.dataa(!\Add0~45_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~49_sumout ),
+	.datad(!\Add0~33_sumout ),
+	.datae(!\Add0~41_sumout ),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~3 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~3 .lut_mask = 64'hC3C303C3C3C0C3C2;
+defparam \uut_de1|xinst_k|l1|out[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N21
+cyclonev_lcell_comb \uut_de1|xin_r[6]~0 (
+// Equation(s):
+// \uut_de1|xin_r[6]~0_combout  = ( \Add0~53_sumout  & ( !\Add0~1_sumout  ) ) # ( !\Add0~53_sumout  & ( \Add0~1_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add0~53_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xin_r[6]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xin_r[6]~0 .extended_lut = "off";
+defparam \uut_de1|xin_r[6]~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \uut_de1|xin_r[6]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y6_N36
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[0]~7 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[0]~7_combout  = ( \uut_de1|xinst_k|l1|out[0]~3_combout  & ( \uut_de1|xin_r[6]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[0]~6_combout ) # (\uut_de1|xinst_k|l1|out[0]~5_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~3_combout  & ( 
+// \uut_de1|xin_r[6]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[0]~6_combout ) # (\uut_de1|xinst_k|l1|out[0]~5_combout ) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~3_combout  & ( !\uut_de1|xin_r[6]~0_combout  & ( ((!\uut_de1|xinst_k|l1|out[0]~6_combout ) # 
+// ((\uut_de1|xinst_k|l1|out[0]~2_combout  & \uut_de1|xinst_k|l1|out[0]~4_combout ))) # (\uut_de1|xinst_k|l1|out[0]~5_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~3_combout  & ( !\uut_de1|xin_r[6]~0_combout  & ( ((!\uut_de1|xinst_k|l1|out[0]~6_combout ) # 
+// (\uut_de1|xinst_k|l1|out[0]~4_combout )) # (\uut_de1|xinst_k|l1|out[0]~5_combout ) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[0]~2_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[0]~5_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~4_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~6_combout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~3_combout ),
+	.dataf(!\uut_de1|xin_r[6]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[0]~7 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[0]~7 .lut_mask = 64'hFF3FFF37FF33FF33;
+defparam \uut_de1|xinst_k|l1|out[0]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N42
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|l|h|vld (
+// Equation(s):
+// \uut_de1|xinst_k|l1|l|h|vld~combout  = ( \Add0~33_sumout  & ( (\Add0~29_sumout  & (\Add0~1_sumout  & (\Add0~49_sumout  & \Add0~53_sumout ))) ) ) # ( !\Add0~33_sumout  & ( (!\Add0~29_sumout  & (!\Add0~1_sumout  & (!\Add0~49_sumout  & !\Add0~53_sumout ))) ) 
+// )
+
+	.dataa(!\Add0~29_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~49_sumout ),
+	.datad(!\Add0~53_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|l|h|vld~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|l|h|vld .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|l|h|vld .lut_mask = 64'h8000800000010001;
+defparam \uut_de1|xinst_k|l1|l|h|vld .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N30
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|h|l|vld (
+// Equation(s):
+// \uut_de1|xinst_k|l1|h|l|vld~combout  = ( \Add0~21_sumout  & ( (\Add0~57_sumout  & (\Add0~17_sumout  & (\Add0~1_sumout  & \Add0~25_sumout ))) ) ) # ( !\Add0~21_sumout  & ( (!\Add0~57_sumout  & (!\Add0~17_sumout  & (!\Add0~1_sumout  & !\Add0~25_sumout ))) ) 
+// )
+
+	.dataa(!\Add0~57_sumout ),
+	.datab(!\Add0~17_sumout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|h|l|vld~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|h|l|vld .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|h|l|vld .lut_mask = 64'h8000800000010001;
+defparam \uut_de1|xinst_k|l1|h|l|vld .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N21
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|l|vld~0 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|l|vld~0_combout  = ( !\Add0~37_sumout  & ( (!\Add0~41_sumout  & (!\Add0~1_sumout  & !\Add0~45_sumout )) ) )
+
+	.dataa(!\Add0~41_sumout ),
+	.datab(gnd),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add0~45_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|l|vld~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|l|vld~0 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|l|vld~0 .lut_mask = 64'hA000A00000000000;
+defparam \uut_de1|xinst_k|l1|l|vld~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N18
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[2]~14 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[2]~14_combout  = ( \uut_de1|xinst_k|l1|l|vld~0_combout  & ( \uut_de1|xinst_k|l1|h|l|vld~combout  ) ) # ( !\uut_de1|xinst_k|l1|l|vld~0_combout  & ( (!\uut_de1|xinst_k|l1|l|h|vld~combout  & \uut_de1|xinst_k|l1|h|l|vld~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de1|xinst_k|l1|l|h|vld~combout ),
+	.datac(gnd),
+	.datad(!\uut_de1|xinst_k|l1|h|l|vld~combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|l|vld~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[2]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[2]~14 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[2]~14 .lut_mask = 64'h00CC00CC00FF00FF;
+defparam \uut_de1|xinst_k|l1|out[2]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N48
+cyclonev_lcell_comb \uut_de1|regime[2]~0 (
+// Equation(s):
+// \uut_de1|regime[2]~0_combout  = ( \uut_de1|xinst_k|l1|out[2]~14_combout  & ( \Add0~13_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (!\uut_de1|xinst_k|l1|out[0]~7_combout  & \Add0~1_sumout )) ) ) ) # ( !\uut_de1|xinst_k|l1|out[2]~14_combout  & ( 
+// \Add0~13_sumout  & ( (\Add0~1_sumout  & (!\uut_de1|xinst_k|l1|out[1]~11_combout  $ (((\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\uut_de1|xinst_k|l1|out[1]~12_combout ))))) ) ) ) # ( \uut_de1|xinst_k|l1|out[2]~14_combout  & ( !\Add0~13_sumout  & ( 
+// (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (!\uut_de1|xinst_k|l1|out[0]~7_combout  & \Add0~1_sumout )) ) ) ) # ( !\uut_de1|xinst_k|l1|out[2]~14_combout  & ( !\Add0~13_sumout  & ( (!\Add0~1_sumout  & (((\uut_de1|xinst_k|l1|out[1]~11_combout )))) # 
+// (\Add0~1_sumout  & (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((!\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~11_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[2]~14_combout ),
+	.dataf(!\Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|regime[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|regime[2]~0 .extended_lut = "off";
+defparam \uut_de1|regime[2]~0 .lut_mask = 64'h33A000A0009300A0;
+defparam \uut_de1|regime[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N57
+cyclonev_lcell_comb \lr[2]~6 (
+// Equation(s):
+// \lr[2]~6_combout  = ( \uut_de1|regime[2]~0_combout  & ( (!\LessThan0~17_combout ) # (\uut_de2|regime[2]~0_combout ) ) ) # ( !\uut_de1|regime[2]~0_combout  & ( (\uut_de2|regime[2]~0_combout  & \LessThan0~17_combout ) ) )
+
+	.dataa(!\uut_de2|regime[2]~0_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|regime[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[2]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[2]~6 .extended_lut = "off";
+defparam \lr[2]~6 .lut_mask = 64'h11111111DDDDDDDD;
+defparam \lr[2]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N57
+cyclonev_lcell_comb \uut_de2|Add0~1 (
+// Equation(s):
+// \uut_de2|Add0~1_combout  = !\uut_de2|xinst_k|l1|out[3]~13_combout  $ (((!\uut_de2|xinst_k|l1|out[0]~7_combout  & (!\uut_de2|xinst_k|l1|out[1]~12_combout  & !\uut_de2|xinst_k|l1|out[2]~1_combout ))))
+
+	.dataa(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datab(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|Add0~1 .extended_lut = "off";
+defparam \uut_de2|Add0~1 .lut_mask = 64'h6CCC6CCC6CCC6CCC;
+defparam \uut_de2|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N54
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[0]~2 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[0]~2_combout  = ( \LessThan0~16_combout  & ( \Add1~1_sumout  ) ) # ( !\LessThan0~16_combout  & ( \Add1~1_sumout  & ( ((!\LessThan0~3_combout ) # ((\LessThan0~14_combout  & \LessThan0~7_combout ))) # (\LessThan0~0_combout ) ) ) )
+
+	.dataa(!\LessThan0~14_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(!\LessThan0~7_combout ),
+	.datae(!\LessThan0~16_combout ),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[0]~2 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[0]~2 .lut_mask = 64'h00000000F3F7FFFF;
+defparam \uut_abs_regime1|regime_N[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N54
+cyclonev_lcell_comb \lr[3]~7 (
+// Equation(s):
+// \lr[3]~7_combout  = (!\uut_de2|Add0~1_combout  & \uut_abs_regime1|regime_N[0]~2_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_de2|Add0~1_combout ),
+	.datad(!\uut_abs_regime1|regime_N[0]~2_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[3]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[3]~7 .extended_lut = "off";
+defparam \lr[3]~7 .lut_mask = 64'h00F000F000F000F0;
+defparam \lr[3]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N0
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[2]~0 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[2]~0_combout  = ( \Add0~5_sumout  & ( (\Add0~1_sumout  & (\Add0~9_sumout  & \Add0~13_sumout )) ) ) # ( !\Add0~5_sumout  & ( (!\Add0~1_sumout  & (!\Add0~9_sumout  & !\Add0~13_sumout )) ) )
+
+	.dataa(gnd),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add0~9_sumout ),
+	.datad(!\Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[2]~0 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[2]~0 .lut_mask = 64'hC000C00000030003;
+defparam \uut_de1|xinst_k|l1|out[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N21
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[2]~1 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[2]~1_combout  = ( \uut_de1|xinst_k|l1|l|vld~0_combout  & ( (!\uut_de1|xinst_k|l1|h|l|vld~combout  & \uut_de1|xinst_k|l1|out[2]~0_combout ) ) ) # ( !\uut_de1|xinst_k|l1|l|vld~0_combout  & ( (\uut_de1|xinst_k|l1|out[2]~0_combout  & 
+// ((!\uut_de1|xinst_k|l1|h|l|vld~combout ) # (\uut_de1|xinst_k|l1|l|h|vld~combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de1|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de1|xinst_k|l1|h|l|vld~combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|l|vld~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[2]~1 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[2]~1 .lut_mask = 64'h00F300F300F000F0;
+defparam \uut_de1|xinst_k|l1|out[2]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N24
+cyclonev_lcell_comb \uut_de1|xinst_k|l1|out[3]~13 (
+// Equation(s):
+// \uut_de1|xinst_k|l1|out[3]~13_combout  = ( \uut_de1|xinst_k|l1|l|vld~0_combout  & ( (!\uut_de1|xinst_k|l1|l|h|vld~combout  & (\uut_de1|xinst_k|l1|out[2]~0_combout  & \uut_de1|xinst_k|l1|h|l|vld~combout )) ) ) # ( !\uut_de1|xinst_k|l1|l|vld~0_combout  & ( 
+// (\uut_de1|xinst_k|l1|out[2]~0_combout  & \uut_de1|xinst_k|l1|h|l|vld~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de1|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[2]~0_combout ),
+	.datad(!\uut_de1|xinst_k|l1|h|l|vld~combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|l|vld~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|xinst_k|l1|out[3]~13 .extended_lut = "off";
+defparam \uut_de1|xinst_k|l1|out[3]~13 .lut_mask = 64'h000F000F000C000C;
+defparam \uut_de1|xinst_k|l1|out[3]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N54
+cyclonev_lcell_comb \uut_de1|Add0~1 (
+// Equation(s):
+// \uut_de1|Add0~1_combout  = ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( !\uut_de1|xinst_k|l1|out[3]~13_combout  ) ) # ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( !\uut_de1|xinst_k|l1|out[3]~13_combout  $ (((!\uut_de1|xinst_k|l1|out[2]~1_combout  & 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout ))) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datac(gnd),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|Add0~1 .extended_lut = "off";
+defparam \uut_de1|Add0~1 .lut_mask = 64'h66CC66CCCCCCCCCC;
+defparam \uut_de1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N54
+cyclonev_lcell_comb \lr[3]~8 (
+// Equation(s):
+// \lr[3]~8_combout  = ( \uut_de2|xinst_k|l1|out[3]~13_combout  & ( \uut_de1|xinst_k|l1|out[3]~13_combout  & ( (!\LessThan0~17_combout  & ((!\uut_de1|Add0~1_combout ) # ((!\Add0~1_sumout )))) # (\LessThan0~17_combout  & (((!\Add1~1_sumout )))) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( \uut_de1|xinst_k|l1|out[3]~13_combout  & ( (!\LessThan0~17_combout  & ((!\uut_de1|Add0~1_combout ) # (!\Add0~1_sumout ))) ) ) ) # ( \uut_de2|xinst_k|l1|out[3]~13_combout  & ( 
+// !\uut_de1|xinst_k|l1|out[3]~13_combout  & ( (!\LessThan0~17_combout  & (!\uut_de1|Add0~1_combout  & (\Add0~1_sumout ))) # (\LessThan0~17_combout  & (((!\Add1~1_sumout )))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( 
+// !\uut_de1|xinst_k|l1|out[3]~13_combout  & ( (!\uut_de1|Add0~1_combout  & (\Add0~1_sumout  & !\LessThan0~17_combout )) ) ) )
+
+	.dataa(!\uut_de1|Add0~1_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\LessThan0~17_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.dataf(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[3]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[3]~8 .extended_lut = "off";
+defparam \lr[3]~8 .lut_mask = 64'h220022F0EE00EEF0;
+defparam \lr[3]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N12
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[0]~6 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[0]~6_combout  = ( \LessThan0~3_combout  & ( (!\LessThan0~16_combout  & (\Add0~1_sumout  & ((!\LessThan0~14_combout ) # (!\LessThan0~7_combout )))) ) )
+
+	.dataa(!\LessThan0~16_combout ),
+	.datab(!\LessThan0~14_combout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\LessThan0~7_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[0]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[0]~6 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[0]~6 .lut_mask = 64'h000000000A080A08;
+defparam \uut_abs_regime1|regime_N[0]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N12
+cyclonev_lcell_comb \uut_de2|Add0~0 (
+// Equation(s):
+// \uut_de2|Add0~0_combout  = !\uut_de2|xinst_k|l1|out[1]~12_combout  $ (!\uut_de2|xinst_k|l1|out[0]~7_combout )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|Add0~0 .extended_lut = "off";
+defparam \uut_de2|Add0~0 .lut_mask = 64'h3C3C3C3C3C3C3C3C;
+defparam \uut_de2|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N48
+cyclonev_lcell_comb \LessThan0~22 (
+// Equation(s):
+// \LessThan0~22_combout  = ( \LessThan0~9_combout  & ( (!\LessThan0~13_combout  & ((!\LessThan0~12_combout ) # ((!\LessThan0~11_combout  & !\LessThan0~10_combout )))) ) ) # ( !\LessThan0~9_combout  & ( (!\LessThan0~13_combout  & ((!\LessThan0~11_combout ) # 
+// (!\LessThan0~12_combout ))) ) )
+
+	.dataa(!\LessThan0~13_combout ),
+	.datab(!\LessThan0~11_combout ),
+	.datac(!\LessThan0~10_combout ),
+	.datad(!\LessThan0~12_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~22 .extended_lut = "off";
+defparam \LessThan0~22 .lut_mask = 64'hAA88AA88AA80AA80;
+defparam \LessThan0~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N24
+cyclonev_lcell_comb \LessThan0~23 (
+// Equation(s):
+// \LessThan0~23_combout  = ( !\LessThan0~5_combout  & ( !\LessThan0~22_combout  & ( (\LessThan0~1_combout  & (!\LessThan0~6_combout  & (!\LessThan0~8_combout  & !\LessThan0~4_combout ))) ) ) )
+
+	.dataa(!\LessThan0~1_combout ),
+	.datab(!\LessThan0~6_combout ),
+	.datac(!\LessThan0~8_combout ),
+	.datad(!\LessThan0~4_combout ),
+	.datae(!\LessThan0~5_combout ),
+	.dataf(!\LessThan0~22_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~23 .extended_lut = "off";
+defparam \LessThan0~23 .lut_mask = 64'h4000000000000000;
+defparam \LessThan0~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N0
+cyclonev_lcell_comb \lr[1]~0 (
+// Equation(s):
+// \lr[1]~0_combout  = ( !\LessThan0~16_combout  & ( \LessThan0~3_combout  & ( (!\LessThan0~23_combout  & (\uut_de1|xinst_k|l1|out[1]~12_combout  & (!\Add0~1_sumout  & !\LessThan0~0_combout ))) ) ) )
+
+	.dataa(!\LessThan0~23_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\LessThan0~0_combout ),
+	.datae(!\LessThan0~16_combout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~0 .extended_lut = "off";
+defparam \lr[1]~0 .lut_mask = 64'h0000000020000000;
+defparam \lr[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N12
+cyclonev_lcell_comb \lr[1]~1 (
+// Equation(s):
+// \lr[1]~1_combout  = ( \uut_de2|xinst_k|l1|out[1]~9_combout  & ( \uut_de2|xinst_k|l1|out[1]~10_combout  & ( (!\Add1~1_sumout  & !\Add1~13_sumout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[1]~9_combout  & ( \uut_de2|xinst_k|l1|out[1]~10_combout  & ( 
+// (!\Add1~1_sumout  & !\Add1~13_sumout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[1]~9_combout  & ( !\uut_de2|xinst_k|l1|out[1]~10_combout  & ( (!\Add1~1_sumout  & (!\Add1~13_sumout  & ((!\uut_de2|xinst_k|l1|out[1]~8_combout ) # 
+// (!\uut_de2|xinst_k|l1|out[1]~11_combout )))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[1]~9_combout  & ( !\uut_de2|xinst_k|l1|out[1]~10_combout  & ( (!\Add1~1_sumout  & (!\Add1~13_sumout  & !\uut_de2|xinst_k|l1|out[1]~11_combout )) ) ) )
+
+	.dataa(!\Add1~1_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~8_combout ),
+	.datac(!\Add1~13_sumout ),
+	.datad(!\uut_de2|xinst_k|l1|out[1]~11_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[1]~9_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[1]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~1 .extended_lut = "off";
+defparam \lr[1]~1 .lut_mask = 64'hA000A080A0A0A0A0;
+defparam \lr[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N57
+cyclonev_lcell_comb \lr[1]~2 (
+// Equation(s):
+// \lr[1]~2_combout  = ( \LessThan0~16_combout  & ( \lr[1]~1_combout  ) ) # ( !\LessThan0~16_combout  & ( \lr[1]~1_combout  & ( ((!\LessThan0~3_combout ) # ((\LessThan0~14_combout  & \LessThan0~7_combout ))) # (\LessThan0~0_combout ) ) ) )
+
+	.dataa(!\LessThan0~14_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\LessThan0~7_combout ),
+	.datad(!\LessThan0~3_combout ),
+	.datae(!\LessThan0~16_combout ),
+	.dataf(!\lr[1]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~2 .extended_lut = "off";
+defparam \lr[1]~2 .lut_mask = 64'h00000000FF37FFFF;
+defparam \lr[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N9
+cyclonev_lcell_comb \uut_de1|Add0~0 (
+// Equation(s):
+// \uut_de1|Add0~0_combout  = ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( !\uut_de1|xinst_k|l1|out[0]~7_combout  ) ) # ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( \uut_de1|xinst_k|l1|out[0]~7_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|Add0~0 .extended_lut = "off";
+defparam \uut_de1|Add0~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \uut_de1|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N18
+cyclonev_lcell_comb \lr[1]~3 (
+// Equation(s):
+// \lr[1]~3_combout  = ( \uut_abs_regime1|regime_N[0]~2_combout  & ( \uut_de1|Add0~0_combout  & ( (!\uut_de2|Add0~0_combout ) # ((\lr[1]~2_combout ) # (\lr[1]~0_combout )) ) ) ) # ( !\uut_abs_regime1|regime_N[0]~2_combout  & ( \uut_de1|Add0~0_combout  & ( 
+// (\lr[1]~2_combout ) # (\lr[1]~0_combout ) ) ) ) # ( \uut_abs_regime1|regime_N[0]~2_combout  & ( !\uut_de1|Add0~0_combout  & ( ((!\uut_de2|Add0~0_combout ) # ((\lr[1]~2_combout ) # (\lr[1]~0_combout ))) # (\uut_abs_regime1|regime_N[0]~6_combout ) ) ) ) # ( 
+// !\uut_abs_regime1|regime_N[0]~2_combout  & ( !\uut_de1|Add0~0_combout  & ( ((\lr[1]~2_combout ) # (\lr[1]~0_combout )) # (\uut_abs_regime1|regime_N[0]~6_combout ) ) ) )
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~6_combout ),
+	.datab(!\uut_de2|Add0~0_combout ),
+	.datac(!\lr[1]~0_combout ),
+	.datad(!\lr[1]~2_combout ),
+	.datae(!\uut_abs_regime1|regime_N[0]~2_combout ),
+	.dataf(!\uut_de1|Add0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~3 .extended_lut = "off";
+defparam \lr[1]~3 .lut_mask = 64'h5FFFDFFF0FFFCFFF;
+defparam \lr[1]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y6_N15
+cyclonev_lcell_comb \LessThan0~19 (
+// Equation(s):
+// \LessThan0~19_combout  = ( \Add0~9_sumout  & ( !\Add1~9_sumout  ) ) # ( !\Add0~9_sumout  & ( \Add1~9_sumout  ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\Add0~9_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~19 .extended_lut = "off";
+defparam \LessThan0~19 .lut_mask = 64'h5555AAAA5555AAAA;
+defparam \LessThan0~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N0
+cyclonev_lcell_comb \LessThan0~20 (
+// Equation(s):
+// \LessThan0~20_combout  = ( !\LessThan0~19_combout  & ( \Add1~1_sumout  & ( (!\LessThan0~4_combout  & (\Add0~1_sumout  & (!\Add0~13_sumout  $ (\Add1~13_sumout )))) ) ) ) # ( !\LessThan0~19_combout  & ( !\Add1~1_sumout  & ( (!\LessThan0~4_combout  & 
+// (!\Add0~1_sumout  & (!\Add0~13_sumout  $ (\Add1~13_sumout )))) ) ) )
+
+	.dataa(!\Add0~13_sumout ),
+	.datab(!\LessThan0~4_combout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\Add1~13_sumout ),
+	.datae(!\LessThan0~19_combout ),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~20 .extended_lut = "off";
+defparam \LessThan0~20 .lut_mask = 64'h8040000008040000;
+defparam \LessThan0~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N36
+cyclonev_lcell_comb \LessThan0~21 (
+// Equation(s):
+// \LessThan0~21_combout  = ( \Add1~21_sumout  & ( !\LessThan0~6_combout  & ( (\LessThan0~20_combout  & (((!\Add0~21_sumout ) # (\LessThan0~15_combout )) # (\LessThan0~14_combout ))) ) ) ) # ( !\Add1~21_sumout  & ( !\LessThan0~6_combout  & ( 
+// (!\Add0~21_sumout  & (\LessThan0~20_combout  & ((\LessThan0~15_combout ) # (\LessThan0~14_combout )))) ) ) )
+
+	.dataa(!\LessThan0~14_combout ),
+	.datab(!\Add0~21_sumout ),
+	.datac(!\LessThan0~20_combout ),
+	.datad(!\LessThan0~15_combout ),
+	.datae(!\Add1~21_sumout ),
+	.dataf(!\LessThan0~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\LessThan0~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \LessThan0~21 .extended_lut = "off";
+defparam \LessThan0~21 .lut_mask = 64'h040C0D0F00000000;
+defparam \LessThan0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N6
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[0]~1 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[0]~1_combout  = ( \LessThan0~21_combout  & ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add1~1_sumout  $ (!\uut_de2|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( !\LessThan0~21_combout  & ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( 
+// (!\LessThan0~3_combout  & (!\Add1~1_sumout  $ (((!\uut_de2|xinst_k|l1|out[0]~7_combout ))))) # (\LessThan0~3_combout  & (!\Add0~1_sumout  & ((!\Add1~1_sumout ) # (!\uut_de2|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( \LessThan0~21_combout  & ( 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add1~1_sumout  $ (!\uut_de2|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( !\LessThan0~21_combout  & ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( (!\LessThan0~3_combout  & (!\Add1~1_sumout  $ 
+// (((!\uut_de2|xinst_k|l1|out[0]~7_combout ))))) # (\LessThan0~3_combout  & (((\Add1~1_sumout  & !\uut_de2|xinst_k|l1|out[0]~7_combout )) # (\Add0~1_sumout ))) ) ) )
+
+	.dataa(!\Add1~1_sumout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datae(!\LessThan0~21_combout ),
+	.dataf(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[0]~1 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[0]~1 .lut_mask = 64'h57A355AA5CA855AA;
+defparam \uut_abs_regime1|regime_N[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N48
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[3]~3 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[3]~3_combout  = ( \lr[1]~3_combout  & ( \uut_abs_regime1|regime_N[0]~1_combout  & ( !\uut_abs_regime1|regime_N[0]~0_combout  $ (((\lr[3]~8_combout ) # (\lr[3]~7_combout ))) ) ) ) # ( !\lr[1]~3_combout  & ( 
+// \uut_abs_regime1|regime_N[0]~1_combout  & ( !\uut_abs_regime1|regime_N[0]~0_combout  $ (((\lr[3]~8_combout ) # (\lr[3]~7_combout ))) ) ) ) # ( \lr[1]~3_combout  & ( !\uut_abs_regime1|regime_N[0]~1_combout  & ( !\uut_abs_regime1|regime_N[0]~0_combout  $ 
+// (((\lr[3]~8_combout ) # (\lr[3]~7_combout ))) ) ) ) # ( !\lr[1]~3_combout  & ( !\uut_abs_regime1|regime_N[0]~1_combout  & ( (!\uut_abs_regime1|regime_N[0]~0_combout  & (!\lr[2]~6_combout  $ (((!\lr[3]~7_combout  & !\lr[3]~8_combout ))))) # 
+// (\uut_abs_regime1|regime_N[0]~0_combout  & (((\lr[3]~8_combout ) # (\lr[3]~7_combout )))) ) ) )
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datab(!\lr[2]~6_combout ),
+	.datac(!\lr[3]~7_combout ),
+	.datad(!\lr[3]~8_combout ),
+	.datae(!\lr[1]~3_combout ),
+	.dataf(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[3]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[3]~3 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[3]~3 .lut_mask = 64'h2DDDA555A555A555;
+defparam \uut_abs_regime1|regime_N[3]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N36
+cyclonev_lcell_comb \sr[1]~5 (
+// Equation(s):
+// \sr[1]~5_combout  = ( \Add1~1_sumout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\LessThan0~3_combout  & (!\LessThan0~21_combout  & (!\LessThan0~0_combout  & \uut_de2|xinst_k|l1|out[1]~12_combout ))) ) ) ) # ( !\Add1~1_sumout  & ( 
+// \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\LessThan0~3_combout  & (!\LessThan0~21_combout  & (!\LessThan0~0_combout  & \uut_de2|xinst_k|l1|out[1]~12_combout ))) ) ) ) # ( \Add1~1_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( 
+// (\LessThan0~3_combout  & (!\LessThan0~21_combout  & (!\LessThan0~0_combout  & !\uut_de2|xinst_k|l1|out[1]~12_combout ))) ) ) ) # ( !\Add1~1_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\LessThan0~3_combout  & (!\LessThan0~21_combout  & 
+// (!\LessThan0~0_combout  & \uut_de2|xinst_k|l1|out[1]~12_combout ))) ) ) )
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\LessThan0~21_combout ),
+	.datac(!\LessThan0~0_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datae(!\Add1~1_sumout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[1]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[1]~5 .extended_lut = "off";
+defparam \sr[1]~5 .lut_mask = 64'h0040400000400040;
+defparam \sr[1]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N45
+cyclonev_lcell_comb \uut_abs_regime2|regime_N[0]~1 (
+// Equation(s):
+// \uut_abs_regime2|regime_N[0]~1_combout  = ( \Add1~1_sumout  & ( \LessThan0~3_combout  & ( (!\LessThan0~16_combout  & (!\LessThan0~0_combout  & ((!\LessThan0~7_combout ) # (!\LessThan0~14_combout )))) ) ) )
+
+	.dataa(!\LessThan0~16_combout ),
+	.datab(!\LessThan0~7_combout ),
+	.datac(!\LessThan0~0_combout ),
+	.datad(!\LessThan0~14_combout ),
+	.datae(!\Add1~1_sumout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|regime_N[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|regime_N[0]~1 .extended_lut = "off";
+defparam \uut_abs_regime2|regime_N[0]~1 .lut_mask = 64'h000000000000A080;
+defparam \uut_abs_regime2|regime_N[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N15
+cyclonev_lcell_comb \sr[3]~6 (
+// Equation(s):
+// \sr[3]~6_combout  = ( \uut_abs_regime2|regime_N[0]~1_combout  & ( !\uut_de2|Add0~1_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_de2|Add0~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime2|regime_N[0]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[3]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[3]~6 .extended_lut = "off";
+defparam \sr[3]~6 .lut_mask = 64'h00000000F0F0F0F0;
+defparam \sr[3]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N48
+cyclonev_lcell_comb \sr[3]~7 (
+// Equation(s):
+// \sr[3]~7_combout  = ( \uut_de2|xinst_k|l1|out[3]~13_combout  & ( \Add1~1_sumout  & ( (\LessThan0~17_combout  & ((!\Add0~1_sumout  & ((\uut_de1|xinst_k|l1|out[3]~13_combout ))) # (\Add0~1_sumout  & (!\uut_de1|Add0~1_combout )))) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( \Add1~1_sumout  & ( (\LessThan0~17_combout  & ((!\Add0~1_sumout  & ((\uut_de1|xinst_k|l1|out[3]~13_combout ))) # (\Add0~1_sumout  & (!\uut_de1|Add0~1_combout )))) ) ) ) # ( \uut_de2|xinst_k|l1|out[3]~13_combout  
+// & ( !\Add1~1_sumout  & ( (!\LessThan0~17_combout ) # ((!\Add0~1_sumout  & ((\uut_de1|xinst_k|l1|out[3]~13_combout ))) # (\Add0~1_sumout  & (!\uut_de1|Add0~1_combout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( !\Add1~1_sumout  & ( 
+// (\LessThan0~17_combout  & ((!\Add0~1_sumout  & ((\uut_de1|xinst_k|l1|out[3]~13_combout ))) # (\Add0~1_sumout  & (!\uut_de1|Add0~1_combout )))) ) ) )
+
+	.dataa(!\uut_de1|Add0~1_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\LessThan0~17_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.dataf(!\Add1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[3]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[3]~7 .extended_lut = "off";
+defparam \sr[3]~7 .lut_mask = 64'h002EFF2E002E002E;
+defparam \sr[3]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N30
+cyclonev_lcell_comb \sr[1]~4 (
+// Equation(s):
+// \sr[1]~4_combout  = ( \LessThan0~21_combout  & ( \LessThan0~0_combout  & ( !\uut_de1|xinst_k|l1|out[1]~12_combout  $ (((!\Add0~1_sumout ) # (\uut_de1|xinst_k|l1|out[0]~7_combout ))) ) ) ) # ( !\LessThan0~21_combout  & ( \LessThan0~0_combout  & ( 
+// !\uut_de1|xinst_k|l1|out[1]~12_combout  $ (((!\Add0~1_sumout ) # (\uut_de1|xinst_k|l1|out[0]~7_combout ))) ) ) ) # ( \LessThan0~21_combout  & ( !\LessThan0~0_combout  & ( !\uut_de1|xinst_k|l1|out[1]~12_combout  $ (((!\Add0~1_sumout ) # 
+// (\uut_de1|xinst_k|l1|out[0]~7_combout ))) ) ) ) # ( !\LessThan0~21_combout  & ( !\LessThan0~0_combout  & ( (!\LessThan0~3_combout  & (!\uut_de1|xinst_k|l1|out[1]~12_combout  $ (((!\Add0~1_sumout ) # (\uut_de1|xinst_k|l1|out[0]~7_combout ))))) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\LessThan0~21_combout ),
+	.dataf(!\LessThan0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[1]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[1]~4 .extended_lut = "off";
+defparam \sr[1]~4 .lut_mask = 64'h3090339933993399;
+defparam \sr[1]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N0
+cyclonev_lcell_comb \uut_abs_regime2|Add0~1 (
+// Equation(s):
+// \uut_abs_regime2|Add0~1_combout  = ( !\LessThan0~17_combout  & ( (((!\Add1~1_sumout  $ (!\uut_de2|xinst_k|l1|out[0]~7_combout )) # (\uut_de2|regime[2]~0_combout ))) ) ) # ( \LessThan0~17_combout  & ( (!\Add0~1_sumout  $ 
+// ((!\uut_de1|xinst_k|l1|out[0]~7_combout ))) # (\uut_de1|regime[2]~0_combout ) ) )
+
+	.dataa(!\uut_de1|regime[2]~0_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\uut_de2|regime[2]~0_combout ),
+	.datae(!\LessThan0~17_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(!\Add1~1_sumout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|Add0~1 .extended_lut = "on";
+defparam \uut_abs_regime2|Add0~1 .lut_mask = 64'h0FFF7D7DF0FF7D7D;
+defparam \uut_abs_regime2|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N36
+cyclonev_lcell_comb \uut_abs_regime2|regime_N[0]~0 (
+// Equation(s):
+// \uut_abs_regime2|regime_N[0]~0_combout  = ( \LessThan0~7_combout  & ( \LessThan0~3_combout  & ( (\Add0~1_sumout  & (((\Add1~1_sumout ) # (\LessThan0~16_combout )) # (\LessThan0~14_combout ))) ) ) ) # ( !\LessThan0~7_combout  & ( \LessThan0~3_combout  & ( 
+// (\Add0~1_sumout  & ((\Add1~1_sumout ) # (\LessThan0~16_combout ))) ) ) ) # ( \LessThan0~7_combout  & ( !\LessThan0~3_combout  & ( \Add0~1_sumout  ) ) ) # ( !\LessThan0~7_combout  & ( !\LessThan0~3_combout  & ( \Add0~1_sumout  ) ) )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(!\LessThan0~14_combout ),
+	.datac(!\LessThan0~16_combout ),
+	.datad(!\Add1~1_sumout ),
+	.datae(!\LessThan0~7_combout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|regime_N[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|regime_N[0]~0 .extended_lut = "off";
+defparam \uut_abs_regime2|regime_N[0]~0 .lut_mask = 64'h5555555505551555;
+defparam \uut_abs_regime2|regime_N[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N24
+cyclonev_lcell_comb \uut_abs_regime2|regime_N[3]~2 (
+// Equation(s):
+// \uut_abs_regime2|regime_N[3]~2_combout  = ( \uut_abs_regime2|Add0~1_combout  & ( \uut_abs_regime2|regime_N[0]~0_combout  & ( (\sr[3]~7_combout ) # (\sr[3]~6_combout ) ) ) ) # ( !\uut_abs_regime2|Add0~1_combout  & ( \uut_abs_regime2|regime_N[0]~0_combout  
+// & ( (\sr[3]~7_combout ) # (\sr[3]~6_combout ) ) ) ) # ( \uut_abs_regime2|Add0~1_combout  & ( !\uut_abs_regime2|regime_N[0]~0_combout  & ( (!\sr[3]~6_combout  & !\sr[3]~7_combout ) ) ) ) # ( !\uut_abs_regime2|Add0~1_combout  & ( 
+// !\uut_abs_regime2|regime_N[0]~0_combout  & ( (!\sr[1]~5_combout  & (!\sr[1]~4_combout  $ (((!\sr[3]~6_combout  & !\sr[3]~7_combout ))))) # (\sr[1]~5_combout  & (!\sr[3]~6_combout  & (!\sr[3]~7_combout ))) ) ) )
+
+	.dataa(!\sr[1]~5_combout ),
+	.datab(!\sr[3]~6_combout ),
+	.datac(!\sr[3]~7_combout ),
+	.datad(!\sr[1]~4_combout ),
+	.datae(!\uut_abs_regime2|Add0~1_combout ),
+	.dataf(!\uut_abs_regime2|regime_N[0]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|regime_N[3]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|regime_N[3]~2 .extended_lut = "off";
+defparam \uut_abs_regime2|regime_N[3]~2 .lut_mask = 64'h6AC0C0C03F3F3F3F;
+defparam \uut_abs_regime2|regime_N[3]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N18
+cyclonev_lcell_comb \sr[1]~0 (
+// Equation(s):
+// \sr[1]~0_combout  = ( \LessThan0~16_combout  & ( \LessThan0~3_combout  & ( (\uut_de1|xinst_k|l1|out[1]~12_combout  & !\Add0~1_sumout ) ) ) ) # ( !\LessThan0~16_combout  & ( \LessThan0~3_combout  & ( (\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// (!\Add0~1_sumout  & ((\LessThan0~0_combout ) # (\LessThan0~23_combout )))) ) ) ) # ( \LessThan0~16_combout  & ( !\LessThan0~3_combout  & ( (\uut_de1|xinst_k|l1|out[1]~12_combout  & !\Add0~1_sumout ) ) ) ) # ( !\LessThan0~16_combout  & ( 
+// !\LessThan0~3_combout  & ( (\uut_de1|xinst_k|l1|out[1]~12_combout  & !\Add0~1_sumout ) ) ) )
+
+	.dataa(!\LessThan0~23_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~1_sumout ),
+	.datad(!\LessThan0~0_combout ),
+	.datae(!\LessThan0~16_combout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[1]~0 .extended_lut = "off";
+defparam \sr[1]~0 .lut_mask = 64'h3030303010303030;
+defparam \sr[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N42
+cyclonev_lcell_comb \sr[1]~1 (
+// Equation(s):
+// \sr[1]~1_combout  = ( \lr[1]~1_combout  & ( \LessThan0~3_combout  & ( (!\LessThan0~16_combout  & (!\LessThan0~0_combout  & ((!\LessThan0~7_combout ) # (!\LessThan0~14_combout )))) ) ) )
+
+	.dataa(!\LessThan0~16_combout ),
+	.datab(!\LessThan0~7_combout ),
+	.datac(!\LessThan0~14_combout ),
+	.datad(!\LessThan0~0_combout ),
+	.datae(!\lr[1]~1_combout ),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[1]~1 .extended_lut = "off";
+defparam \sr[1]~1 .lut_mask = 64'h000000000000A800;
+defparam \sr[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N33
+cyclonev_lcell_comb \uut_abs_regime2|regime_N[0]~3 (
+// Equation(s):
+// \uut_abs_regime2|regime_N[0]~3_combout  = ( \LessThan0~3_combout  & ( (\Add0~1_sumout  & (((\LessThan0~7_combout  & \LessThan0~14_combout )) # (\LessThan0~16_combout ))) ) ) # ( !\LessThan0~3_combout  & ( \Add0~1_sumout  ) )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(!\LessThan0~7_combout ),
+	.datac(!\LessThan0~14_combout ),
+	.datad(!\LessThan0~16_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|regime_N[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|regime_N[0]~3 .extended_lut = "off";
+defparam \uut_abs_regime2|regime_N[0]~3 .lut_mask = 64'h5555555501550155;
+defparam \uut_abs_regime2|regime_N[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y8_N24
+cyclonev_lcell_comb \sr[1]~2 (
+// Equation(s):
+// \sr[1]~2_combout  = ( \uut_abs_regime2|regime_N[0]~1_combout  & ( \uut_de2|Add0~0_combout  & ( (((\uut_abs_regime2|regime_N[0]~3_combout  & !\uut_de1|Add0~0_combout )) # (\sr[1]~1_combout )) # (\sr[1]~0_combout ) ) ) ) # ( 
+// !\uut_abs_regime2|regime_N[0]~1_combout  & ( \uut_de2|Add0~0_combout  & ( (((\uut_abs_regime2|regime_N[0]~3_combout  & !\uut_de1|Add0~0_combout )) # (\sr[1]~1_combout )) # (\sr[1]~0_combout ) ) ) ) # ( \uut_abs_regime2|regime_N[0]~1_combout  & ( 
+// !\uut_de2|Add0~0_combout  ) ) # ( !\uut_abs_regime2|regime_N[0]~1_combout  & ( !\uut_de2|Add0~0_combout  & ( (((\uut_abs_regime2|regime_N[0]~3_combout  & !\uut_de1|Add0~0_combout )) # (\sr[1]~1_combout )) # (\sr[1]~0_combout ) ) ) )
+
+	.dataa(!\sr[1]~0_combout ),
+	.datab(!\sr[1]~1_combout ),
+	.datac(!\uut_abs_regime2|regime_N[0]~3_combout ),
+	.datad(!\uut_de1|Add0~0_combout ),
+	.datae(!\uut_abs_regime2|regime_N[0]~1_combout ),
+	.dataf(!\uut_de2|Add0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[1]~2 .extended_lut = "off";
+defparam \sr[1]~2 .lut_mask = 64'h7F77FFFF7F777F77;
+defparam \sr[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N24
+cyclonev_lcell_comb \sr[0]~3 (
+// Equation(s):
+// \sr[0]~3_combout  = ( \LessThan0~21_combout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add0~1_sumout  $ (!\uut_de1|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( !\LessThan0~21_combout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\LessThan0~3_combout  
+// & (!\Add0~1_sumout  $ ((!\uut_de1|xinst_k|l1|out[0]~7_combout )))) # (\LessThan0~3_combout  & ((!\Add1~1_sumout ) # ((!\Add0~1_sumout  & \uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( \LessThan0~21_combout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  
+// & ( !\Add0~1_sumout  $ (!\uut_de1|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( !\LessThan0~21_combout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\LessThan0~3_combout  & (!\Add0~1_sumout  $ ((!\uut_de1|xinst_k|l1|out[0]~7_combout )))) # 
+// (\LessThan0~3_combout  & (\Add1~1_sumout  & ((\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~1_sumout )))) ) ) )
+
+	.dataa(!\Add0~1_sumout ),
+	.datab(!\LessThan0~3_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\Add1~1_sumout ),
+	.datae(!\LessThan0~21_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[0]~3 .extended_lut = "off";
+defparam \sr[0]~3 .lut_mask = 64'h485B5A5A7B4A5A5A;
+defparam \sr[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N54
+cyclonev_lcell_comb \sr[2]~8 (
+// Equation(s):
+// \sr[2]~8_combout  = ( \uut_de1|regime[2]~0_combout  & ( (\LessThan0~17_combout ) # (\uut_de2|regime[2]~0_combout ) ) ) # ( !\uut_de1|regime[2]~0_combout  & ( (\uut_de2|regime[2]~0_combout  & !\LessThan0~17_combout ) ) )
+
+	.dataa(!\uut_de2|regime[2]~0_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|regime[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\sr[2]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \sr[2]~8 .extended_lut = "off";
+defparam \sr[2]~8 .lut_mask = 64'h4444444477777777;
+defparam \sr[2]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N42
+cyclonev_lcell_comb \lr[1]~4 (
+// Equation(s):
+// \lr[1]~4_combout  = ( !\LessThan0~21_combout  & ( !\LessThan0~0_combout  & ( (\LessThan0~3_combout  & (!\uut_de1|xinst_k|l1|out[1]~12_combout  $ (((!\Add0~1_sumout ) # (\uut_de1|xinst_k|l1|out[0]~7_combout ))))) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\LessThan0~3_combout ),
+	.datad(!\Add0~1_sumout ),
+	.datae(!\LessThan0~21_combout ),
+	.dataf(!\LessThan0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~4 .extended_lut = "off";
+defparam \lr[1]~4 .lut_mask = 64'h0309000000000000;
+defparam \lr[1]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N18
+cyclonev_lcell_comb \lr[1]~5 (
+// Equation(s):
+// \lr[1]~5_combout  = ( \uut_de2|xinst_k|l1|out[1]~12_combout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\LessThan0~3_combout ) # ((\LessThan0~0_combout ) # (\LessThan0~21_combout )) ) ) ) # ( \uut_de2|xinst_k|l1|out[1]~12_combout  & ( 
+// !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\Add1~1_sumout  & ((!\LessThan0~3_combout ) # ((\LessThan0~0_combout ) # (\LessThan0~21_combout )))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[1]~12_combout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( 
+// (\Add1~1_sumout  & ((!\LessThan0~3_combout ) # ((\LessThan0~0_combout ) # (\LessThan0~21_combout )))) ) ) )
+
+	.dataa(!\LessThan0~3_combout ),
+	.datab(!\LessThan0~21_combout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(!\LessThan0~0_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\lr[1]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \lr[1]~5 .extended_lut = "off";
+defparam \lr[1]~5 .lut_mask = 64'h0B0FB0F00000BBFF;
+defparam \lr[1]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N54
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[2]~5 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[2]~5_combout  = ( \lr[2]~6_combout  & ( ((!\lr[1]~4_combout  & (!\uut_abs_regime1|regime_N[0]~1_combout  & !\lr[1]~5_combout ))) # (\uut_abs_regime1|regime_N[0]~0_combout ) ) ) # ( !\lr[2]~6_combout  & ( 
+// (!\uut_abs_regime1|regime_N[0]~0_combout  & (((\lr[1]~5_combout ) # (\uut_abs_regime1|regime_N[0]~1_combout )) # (\lr[1]~4_combout ))) ) )
+
+	.dataa(!\lr[1]~4_combout ),
+	.datab(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datac(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datad(!\lr[1]~5_combout ),
+	.datae(gnd),
+	.dataf(!\lr[2]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[2]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[2]~5 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[2]~5 .lut_mask = 64'h70F070F08F0F8F0F;
+defparam \uut_abs_regime1|regime_N[2]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N57
+cyclonev_lcell_comb \uut_abs_regime1|regime_N[1]~4 (
+// Equation(s):
+// \uut_abs_regime1|regime_N[1]~4_combout  = ( \uut_abs_regime1|regime_N[0]~0_combout  & ( (\lr[1]~5_combout ) # (\lr[1]~4_combout ) ) ) # ( !\uut_abs_regime1|regime_N[0]~0_combout  & ( !\uut_abs_regime1|regime_N[0]~1_combout  $ (((!\lr[1]~4_combout  & 
+// !\lr[1]~5_combout ))) ) )
+
+	.dataa(!\lr[1]~4_combout ),
+	.datab(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datac(!\lr[1]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|regime_N[1]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|regime_N[1]~4 .extended_lut = "off";
+defparam \uut_abs_regime1|regime_N[1]~4 .lut_mask = 64'h6C6C6C6C5F5F5F5F;
+defparam \uut_abs_regime1|regime_N[1]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y8_N12
+cyclonev_lcell_comb \uut_de1|ls|c[15]~15 (
+// Equation(s):
+// \uut_de1|ls|c[15]~15_combout  = ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( \Add0~17_sumout  & ( (\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~5_sumout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( \Add0~17_sumout  & ( 
+// (!\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~13_sumout )) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~9_sumout ))) ) ) ) # ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( !\Add0~17_sumout  & ( (\Add0~5_sumout  & 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( !\Add0~17_sumout  & ( (!\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~13_sumout )) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~9_sumout ))) ) ) )
+
+	.dataa(!\Add0~13_sumout ),
+	.datab(!\Add0~9_sumout ),
+	.datac(!\Add0~5_sumout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.dataf(!\Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[15]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[15]~15 .extended_lut = "off";
+defparam \uut_de1|ls|c[15]~15 .lut_mask = 64'h55330F0055330FFF;
+defparam \uut_de1|ls|c[15]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N6
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][11]~2 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][11]~2_combout  = ( \Add0~57_sumout  & ( \Add0~53_sumout  & ( ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~21_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~25_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) 
+// ) # ( !\Add0~57_sumout  & ( \Add0~53_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~21_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~25_sumout )))) # 
+// (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( \Add0~57_sumout  & ( !\Add0~53_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~21_sumout ))) # 
+// (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~25_sumout )))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((!\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( !\Add0~57_sumout  & ( !\Add0~53_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~21_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~25_sumout )))) ) ) )
+
+	.dataa(!\Add0~25_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~21_sumout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(!\Add0~57_sumout ),
+	.dataf(!\Add0~53_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][11]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][11]~2 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][11]~2 .lut_mask = 64'h0C443F440C773F77;
+defparam \uut_de1|ls|tmp[1][11]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N30
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][7]~3 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][7]~3_combout  = ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~37_sumout  & ( (\Add0~33_sumout ) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~37_sumout  & ( 
+// (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~49_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~29_sumout )) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// \Add0~33_sumout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~49_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~29_sumout )) ) ) )
+
+	.dataa(!\Add0~29_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~49_sumout ),
+	.datad(!\Add0~33_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][7]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][7]~3 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][7]~3 .lut_mask = 64'h1D1D00CC1D1D33FF;
+defparam \uut_de1|ls|tmp[1][7]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N39
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][3]~4 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][3]~4_combout  = ( \Add0~45_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~41_sumout ))) ) ) # ( !\Add0~45_sumout  & ( (\Add0~41_sumout  & (!\uut_de1|xinst_k|l1|out[0]~7_combout  
+// & !\uut_de1|xinst_k|l1|out[1]~12_combout )) ) )
+
+	.dataa(!\Add0~41_sumout ),
+	.datab(gnd),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datae(gnd),
+	.dataf(!\Add0~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][3]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][3]~4 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][3]~4 .lut_mask = 64'h500050005F005F00;
+defparam \uut_de1|ls|tmp[1][3]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N6
+cyclonev_lcell_comb \uut_de1|ls|c[15]~16 (
+// Equation(s):
+// \uut_de1|ls|c[15]~16_combout  = ( \uut_de1|ls|tmp[1][7]~3_combout  & ( \uut_de1|ls|tmp[1][3]~4_combout  & ( ((!\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|c[15]~15_combout )) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & 
+// ((\uut_de1|ls|tmp[1][11]~2_combout )))) # (\uut_de1|xinst_k|l1|out[3]~13_combout ) ) ) ) # ( !\uut_de1|ls|tmp[1][7]~3_combout  & ( \uut_de1|ls|tmp[1][3]~4_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((!\uut_de1|xinst_k|l1|out[2]~1_combout  & 
+// (\uut_de1|ls|c[15]~15_combout )) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & ((\uut_de1|ls|tmp[1][11]~2_combout ))))) # (\uut_de1|xinst_k|l1|out[3]~13_combout  & (((\uut_de1|xinst_k|l1|out[2]~1_combout )))) ) ) ) # ( \uut_de1|ls|tmp[1][7]~3_combout  & ( 
+// !\uut_de1|ls|tmp[1][3]~4_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((!\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|c[15]~15_combout )) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & ((\uut_de1|ls|tmp[1][11]~2_combout ))))) # 
+// (\uut_de1|xinst_k|l1|out[3]~13_combout  & (((!\uut_de1|xinst_k|l1|out[2]~1_combout )))) ) ) ) # ( !\uut_de1|ls|tmp[1][7]~3_combout  & ( !\uut_de1|ls|tmp[1][3]~4_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & 
+// ((!\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|c[15]~15_combout )) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & ((\uut_de1|ls|tmp[1][11]~2_combout ))))) ) ) )
+
+	.dataa(!\uut_de1|ls|c[15]~15_combout ),
+	.datab(!\uut_de1|ls|tmp[1][11]~2_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datae(!\uut_de1|ls|tmp[1][7]~3_combout ),
+	.dataf(!\uut_de1|ls|tmp[1][3]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[15]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[15]~16 .extended_lut = "off";
+defparam \uut_de1|ls|c[15]~16 .lut_mask = 64'h50305F30503F5F3F;
+defparam \uut_de1|ls|c[15]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y7_N9
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][3]~4 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][3]~4_combout  = ( \Add1~41_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((!\uut_de2|xinst_k|l1|out[0]~7_combout ) # (\Add1~45_sumout ))) ) ) # ( !\Add1~41_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & 
+// (\uut_de2|xinst_k|l1|out[0]~7_combout  & \Add1~45_sumout )) ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datab(gnd),
+	.datac(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\Add1~45_sumout ),
+	.datae(gnd),
+	.dataf(!\Add1~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][3]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][3]~4 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][3]~4 .lut_mask = 64'h000A000AA0AAA0AA;
+defparam \uut_de2|ls|tmp[1][3]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N0
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][7]~3 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][7]~3_combout  = ( \Add1~33_sumout  & ( \Add1~37_sumout  & ( ((!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~49_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~29_sumout )))) # (\uut_de2|xinst_k|l1|out[0]~7_combout ) ) ) 
+// ) # ( !\Add1~33_sumout  & ( \Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[0]~7_combout  & ((!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~49_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~29_sumout ))))) # 
+// (\uut_de2|xinst_k|l1|out[0]~7_combout  & (((\uut_de2|xinst_k|l1|out[1]~12_combout )))) ) ) ) # ( \Add1~33_sumout  & ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[0]~7_combout  & ((!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~49_sumout )) # 
+// (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~29_sumout ))))) # (\uut_de2|xinst_k|l1|out[0]~7_combout  & (((!\uut_de2|xinst_k|l1|out[1]~12_combout )))) ) ) ) # ( !\Add1~33_sumout  & ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[0]~7_combout  & 
+// ((!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~49_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~29_sumout ))))) ) ) )
+
+	.dataa(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datab(!\Add1~49_sumout ),
+	.datac(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datad(!\Add1~29_sumout ),
+	.datae(!\Add1~33_sumout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][7]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][7]~3 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][7]~3 .lut_mask = 64'h202A707A252F757F;
+defparam \uut_de2|ls|tmp[1][7]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N48
+cyclonev_lcell_comb \uut_de2|ls|c[15]~16 (
+// Equation(s):
+// \uut_de2|ls|c[15]~16_combout  = ( \Add1~13_sumout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~9_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~17_sumout )) ) ) ) # ( !\Add1~13_sumout  & 
+// ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~9_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~17_sumout )) ) ) ) # ( \Add1~13_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~5_sumout ) ) ) ) # ( !\Add1~13_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\uut_de2|xinst_k|l1|out[1]~12_combout  & \Add1~5_sumout ) ) ) )
+
+	.dataa(!\Add1~17_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~9_sumout ),
+	.datad(!\Add1~5_sumout ),
+	.datae(!\Add1~13_sumout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[15]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[15]~16 .extended_lut = "off";
+defparam \uut_de2|ls|c[15]~16 .lut_mask = 64'h0033CCFF1D1D1D1D;
+defparam \uut_de2|ls|c[15]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N48
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][11]~2 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][11]~2_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~53_sumout ))) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~57_sumout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & 
+// (\Add1~25_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~53_sumout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (\Add1~57_sumout  & \uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) )
+
+	.dataa(!\Add1~57_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~25_sumout ),
+	.datad(!\Add1~53_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][11]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][11]~2 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][11]~2 .lut_mask = 64'h11110C3FDDDD0C3F;
+defparam \uut_de2|ls|tmp[1][11]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N48
+cyclonev_lcell_comb \uut_de2|ls|c[15]~17 (
+// Equation(s):
+// \uut_de2|ls|c[15]~17_combout  = ( \uut_de2|xinst_k|l1|out[2]~1_combout  & ( \uut_de2|ls|tmp[1][11]~2_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout ) # (\uut_de2|ls|tmp[1][3]~4_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[2]~1_combout  & ( 
+// \uut_de2|ls|tmp[1][11]~2_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout  & ((\uut_de2|ls|c[15]~16_combout ))) # (\uut_de2|xinst_k|l1|out[3]~13_combout  & (\uut_de2|ls|tmp[1][7]~3_combout )) ) ) ) # ( \uut_de2|xinst_k|l1|out[2]~1_combout  & ( 
+// !\uut_de2|ls|tmp[1][11]~2_combout  & ( (\uut_de2|ls|tmp[1][3]~4_combout  & \uut_de2|xinst_k|l1|out[3]~13_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[2]~1_combout  & ( !\uut_de2|ls|tmp[1][11]~2_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout  & 
+// ((\uut_de2|ls|c[15]~16_combout ))) # (\uut_de2|xinst_k|l1|out[3]~13_combout  & (\uut_de2|ls|tmp[1][7]~3_combout )) ) ) )
+
+	.dataa(!\uut_de2|ls|tmp[1][3]~4_combout ),
+	.datab(!\uut_de2|ls|tmp[1][7]~3_combout ),
+	.datac(!\uut_de2|ls|c[15]~16_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.dataf(!\uut_de2|ls|tmp[1][11]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[15]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[15]~17 .extended_lut = "off";
+defparam \uut_de2|ls|c[15]~17 .lut_mask = 64'h0F3300550F33FF55;
+defparam \uut_de2|ls|c[15]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N48
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][6]~8 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][6]~8_combout  = ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~29_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~41_sumout )) ) ) ) # ( 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~37_sumout  & ( (\Add0~33_sumout ) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// ((\Add0~29_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~41_sumout )) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & \Add0~33_sumout ) ) ) )
+
+	.dataa(!\Add0~41_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~29_sumout ),
+	.datad(!\Add0~33_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][6]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][6]~8 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][6]~8 .lut_mask = 64'h00CC1D1D33FF1D1D;
+defparam \uut_de1|ls|tmp[1][6]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N24
+cyclonev_lcell_comb \uut_de1|ls|c[14]~17 (
+// Equation(s):
+// \uut_de1|ls|c[14]~17_combout  = ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~21_sumout  & ( (\Add0~5_sumout ) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~21_sumout  & ( 
+// (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~9_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~17_sumout )) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~21_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// \Add0~5_sumout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~21_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~9_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~17_sumout )) ) ) )
+
+	.dataa(!\Add0~17_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~9_sumout ),
+	.datad(!\Add0~5_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[14]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[14]~17 .extended_lut = "off";
+defparam \uut_de1|ls|c[14]~17 .lut_mask = 64'h1D1D00CC1D1D33FF;
+defparam \uut_de1|ls|c[14]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N18
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][10]~7 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][10]~7_combout  = ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~49_sumout  & ( (\uut_de1|xinst_k|l1|out[1]~12_combout ) # (\Add0~57_sumout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~49_sumout  & ( 
+// (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~25_sumout )) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~53_sumout ))) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~49_sumout  & ( (\Add0~57_sumout  & 
+// !\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~49_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~25_sumout )) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~53_sumout ))) ) ) )
+
+	.dataa(!\Add0~57_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~25_sumout ),
+	.datad(!\Add0~53_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][10]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][10]~7 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][10]~7 .lut_mask = 64'h0C3F44440C3F7777;
+defparam \uut_de1|ls|tmp[1][10]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N45
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][2]~9 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][2]~9_combout  = ( \Add0~45_sumout  & ( (!\uut_de1|xinst_k|l1|out[0]~7_combout  & !\uut_de1|xinst_k|l1|out[1]~12_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datae(gnd),
+	.dataf(!\Add0~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][2]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][2]~9 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][2]~9 .lut_mask = 64'h00000000F000F000;
+defparam \uut_de1|ls|tmp[1][2]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N12
+cyclonev_lcell_comb \uut_de1|ls|c[14]~18 (
+// Equation(s):
+// \uut_de1|ls|c[14]~18_combout  = ( \uut_de1|ls|tmp[1][10]~7_combout  & ( \uut_de1|ls|tmp[1][2]~9_combout  & ( ((!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((\uut_de1|ls|c[14]~17_combout ))) # (\uut_de1|xinst_k|l1|out[3]~13_combout  & 
+// (\uut_de1|ls|tmp[1][6]~8_combout ))) # (\uut_de1|xinst_k|l1|out[2]~1_combout ) ) ) ) # ( !\uut_de1|ls|tmp[1][10]~7_combout  & ( \uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & (((\uut_de1|ls|c[14]~17_combout  & 
+// !\uut_de1|xinst_k|l1|out[2]~1_combout )))) # (\uut_de1|xinst_k|l1|out[3]~13_combout  & (((\uut_de1|xinst_k|l1|out[2]~1_combout )) # (\uut_de1|ls|tmp[1][6]~8_combout ))) ) ) ) # ( \uut_de1|ls|tmp[1][10]~7_combout  & ( !\uut_de1|ls|tmp[1][2]~9_combout  & ( 
+// (!\uut_de1|xinst_k|l1|out[3]~13_combout  & (((\uut_de1|xinst_k|l1|out[2]~1_combout ) # (\uut_de1|ls|c[14]~17_combout )))) # (\uut_de1|xinst_k|l1|out[3]~13_combout  & (\uut_de1|ls|tmp[1][6]~8_combout  & ((!\uut_de1|xinst_k|l1|out[2]~1_combout )))) ) ) ) # 
+// ( !\uut_de1|ls|tmp[1][10]~7_combout  & ( !\uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & ((!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((\uut_de1|ls|c[14]~17_combout ))) # (\uut_de1|xinst_k|l1|out[3]~13_combout  & 
+// (\uut_de1|ls|tmp[1][6]~8_combout )))) ) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][6]~8_combout ),
+	.datab(!\uut_de1|ls|c[14]~17_combout ),
+	.datac(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datae(!\uut_de1|ls|tmp[1][10]~7_combout ),
+	.dataf(!\uut_de1|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[14]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[14]~18 .extended_lut = "off";
+defparam \uut_de1|ls|c[14]~18 .lut_mask = 64'h350035F0350F35FF;
+defparam \uut_de1|ls|c[14]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N54
+cyclonev_lcell_comb \uut_de2|ls|c[14]~18 (
+// Equation(s):
+// \uut_de2|ls|c[14]~18_combout  = ( \Add1~17_sumout  & ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~5_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~21_sumout )) ) ) ) # ( !\Add1~17_sumout  & 
+// ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~5_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~21_sumout )) ) ) ) # ( \Add1~17_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( 
+// (\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~9_sumout ) ) ) ) # ( !\Add1~17_sumout  & ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( (\Add1~9_sumout  & !\uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) )
+
+	.dataa(!\Add1~9_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~21_sumout ),
+	.datad(!\Add1~5_sumout ),
+	.datae(!\Add1~17_sumout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[14]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[14]~18 .extended_lut = "off";
+defparam \uut_de2|ls|c[14]~18 .lut_mask = 64'h4444777703CF03CF;
+defparam \uut_de2|ls|c[14]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N6
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][10]~7 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][10]~7_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~57_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~49_sumout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~57_sumout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~53_sumout ))) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~57_sumout  & ( (\Add1~49_sumout  & 
+// \uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~57_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~53_sumout ))) ) ) )
+
+	.dataa(!\Add1~49_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~25_sumout ),
+	.datad(!\Add1~53_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][10]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][10]~7 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][10]~7 .lut_mask = 64'h0C3F11110C3FDDDD;
+defparam \uut_de2|ls|tmp[1][10]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N54
+cyclonev_lcell_comb \uut_de2|ls|c[14]~19 (
+// Equation(s):
+// \uut_de2|ls|c[14]~19_combout  = ( \uut_de2|xinst_k|l1|out[3]~13_combout  & ( \uut_de2|ls|tmp[1][10]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][6]~8_combout )) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & 
+// ((\uut_de2|ls|tmp[1][2]~9_combout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( \uut_de2|ls|tmp[1][10]~7_combout  & ( (\uut_de2|xinst_k|l1|out[2]~1_combout ) # (\uut_de2|ls|c[14]~18_combout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[3]~13_combout  & 
+// ( !\uut_de2|ls|tmp[1][10]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][6]~8_combout )) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][2]~9_combout ))) ) ) ) # ( !\uut_de2|xinst_k|l1|out[3]~13_combout  & ( 
+// !\uut_de2|ls|tmp[1][10]~7_combout  & ( (\uut_de2|ls|c[14]~18_combout  & !\uut_de2|xinst_k|l1|out[2]~1_combout ) ) ) )
+
+	.dataa(!\uut_de2|ls|tmp[1][6]~8_combout ),
+	.datab(!\uut_de2|ls|c[14]~18_combout ),
+	.datac(!\uut_de2|ls|tmp[1][2]~9_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datae(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.dataf(!\uut_de2|ls|tmp[1][10]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[14]~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[14]~19 .extended_lut = "off";
+defparam \uut_de2|ls|c[14]~19 .lut_mask = 64'h3300550F33FF550F;
+defparam \uut_de2|ls|c[14]~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N30
+cyclonev_lcell_comb \uut_ediff|s1|Add0~30 (
+// Equation(s):
+// \uut_ediff|s1|Add0~30_cout  = CARRY(( VCC ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\uut_ediff|s1|Add0~30_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~30 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~30 .lut_mask = 64'h000000000000FFFF;
+defparam \uut_ediff|s1|Add0~30 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N33
+cyclonev_lcell_comb \uut_ediff|s1|Add0~21 (
+// Equation(s):
+// \uut_ediff|s1|Add0~21_sumout  = SUM(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de2|ls|c[14]~19_combout ))) # (\LessThan0~0_combout  & (!\uut_de1|ls|c[14]~18_combout )))) # (\LessThan0~18_combout  & (!\uut_de1|ls|c[14]~18_combout )) ) 
+// + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & (\uut_de1|ls|c[14]~18_combout )) # (\LessThan0~0_combout  & ((\uut_de2|ls|c[14]~19_combout ))))) # (\LessThan0~18_combout  & (((\uut_de2|ls|c[14]~19_combout )))) ) + ( \uut_ediff|s1|Add0~30_cout  
+// ))
+// \uut_ediff|s1|Add0~22  = CARRY(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de2|ls|c[14]~19_combout ))) # (\LessThan0~0_combout  & (!\uut_de1|ls|c[14]~18_combout )))) # (\LessThan0~18_combout  & (!\uut_de1|ls|c[14]~18_combout )) ) + ( 
+// (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & (\uut_de1|ls|c[14]~18_combout )) # (\LessThan0~0_combout  & ((\uut_de2|ls|c[14]~19_combout ))))) # (\LessThan0~18_combout  & (((\uut_de2|ls|c[14]~19_combout )))) ) + ( \uut_ediff|s1|Add0~30_cout  ))
+
+	.dataa(!\LessThan0~18_combout ),
+	.datab(!\uut_de1|ls|c[14]~18_combout ),
+	.datac(!\LessThan0~0_combout ),
+	.datad(!\uut_de2|ls|c[14]~19_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[14]~19_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~30_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~21_sumout ),
+	.cout(\uut_ediff|s1|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~21 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~21 .lut_mask = 64'h0000DF800000EC4C;
+defparam \uut_ediff|s1|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N36
+cyclonev_lcell_comb \uut_ediff|s1|Add0~25 (
+// Equation(s):
+// \uut_ediff|s1|Add0~25_sumout  = SUM(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & (\uut_de1|ls|c[15]~16_combout )) # (\LessThan0~0_combout  & ((\uut_de2|ls|c[15]~17_combout ))))) # (\LessThan0~18_combout  & (((\uut_de2|ls|c[15]~17_combout )))) ) 
+// + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de2|ls|c[15]~17_combout ))) # (\LessThan0~0_combout  & (!\uut_de1|ls|c[15]~16_combout )))) # (\LessThan0~18_combout  & (((!\uut_de1|ls|c[15]~16_combout )))) ) + ( \uut_ediff|s1|Add0~22  ))
+// \uut_ediff|s1|Add0~26  = CARRY(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & (\uut_de1|ls|c[15]~16_combout )) # (\LessThan0~0_combout  & ((\uut_de2|ls|c[15]~17_combout ))))) # (\LessThan0~18_combout  & (((\uut_de2|ls|c[15]~17_combout )))) ) + ( 
+// (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de2|ls|c[15]~17_combout ))) # (\LessThan0~0_combout  & (!\uut_de1|ls|c[15]~16_combout )))) # (\LessThan0~18_combout  & (((!\uut_de1|ls|c[15]~16_combout )))) ) + ( \uut_ediff|s1|Add0~22  ))
+
+	.dataa(!\LessThan0~18_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\uut_de1|ls|c[15]~16_combout ),
+	.datad(!\uut_de2|ls|c[15]~17_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[15]~17_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~25_sumout ),
+	.cout(\uut_ediff|s1|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~25 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~25 .lut_mask = 64'h0000078F0000087F;
+defparam \uut_ediff|s1|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N39
+cyclonev_lcell_comb \uut_ediff|s1|Add0~17 (
+// Equation(s):
+// \uut_ediff|s1|Add0~17_sumout  = SUM(( \uut_abs_regime1|regime_N[0]~1_combout  ) + ( !\sr[0]~3_combout  ) + ( \uut_ediff|s1|Add0~26  ))
+// \uut_ediff|s1|Add0~18  = CARRY(( \uut_abs_regime1|regime_N[0]~1_combout  ) + ( !\sr[0]~3_combout  ) + ( \uut_ediff|s1|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\sr[0]~3_combout ),
+	.datad(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~17_sumout ),
+	.cout(\uut_ediff|s1|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~17 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~17 .lut_mask = 64'h00000F0F000000FF;
+defparam \uut_ediff|s1|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N42
+cyclonev_lcell_comb \uut_ediff|s1|Add0~1 (
+// Equation(s):
+// \uut_ediff|s1|Add0~1_sumout  = SUM(( !\sr[1]~2_combout  $ (((!\uut_abs_regime2|regime_N[0]~0_combout  & \sr[0]~3_combout ))) ) + ( \uut_abs_regime1|regime_N[1]~4_combout  ) + ( \uut_ediff|s1|Add0~18  ))
+// \uut_ediff|s1|Add0~2  = CARRY(( !\sr[1]~2_combout  $ (((!\uut_abs_regime2|regime_N[0]~0_combout  & \sr[0]~3_combout ))) ) + ( \uut_abs_regime1|regime_N[1]~4_combout  ) + ( \uut_ediff|s1|Add0~18  ))
+
+	.dataa(!\uut_abs_regime2|regime_N[0]~0_combout ),
+	.datab(!\sr[1]~2_combout ),
+	.datac(gnd),
+	.datad(!\sr[0]~3_combout ),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|regime_N[1]~4_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~1_sumout ),
+	.cout(\uut_ediff|s1|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~1 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~1 .lut_mask = 64'h0000FF000000CC66;
+defparam \uut_ediff|s1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N45
+cyclonev_lcell_comb \uut_ediff|s1|Add0~9 (
+// Equation(s):
+// \uut_ediff|s1|Add0~9_sumout  = SUM(( !\sr[2]~8_combout  $ (((!\uut_abs_regime2|regime_N[0]~0_combout  & ((\sr[0]~3_combout ) # (\sr[1]~2_combout ))))) ) + ( \uut_abs_regime1|regime_N[2]~5_combout  ) + ( \uut_ediff|s1|Add0~2  ))
+// \uut_ediff|s1|Add0~10  = CARRY(( !\sr[2]~8_combout  $ (((!\uut_abs_regime2|regime_N[0]~0_combout  & ((\sr[0]~3_combout ) # (\sr[1]~2_combout ))))) ) + ( \uut_abs_regime1|regime_N[2]~5_combout  ) + ( \uut_ediff|s1|Add0~2  ))
+
+	.dataa(!\uut_abs_regime2|regime_N[0]~0_combout ),
+	.datab(!\sr[1]~2_combout ),
+	.datac(!\sr[0]~3_combout ),
+	.datad(!\sr[2]~8_combout ),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|regime_N[2]~5_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~9_sumout ),
+	.cout(\uut_ediff|s1|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~9 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~9 .lut_mask = 64'h0000FF000000D52A;
+defparam \uut_ediff|s1|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N48
+cyclonev_lcell_comb \uut_ediff|s1|Add0~13 (
+// Equation(s):
+// \uut_ediff|s1|Add0~13_sumout  = SUM(( \uut_abs_regime1|regime_N[3]~3_combout  ) + ( !\uut_abs_regime2|regime_N[3]~2_combout  ) + ( \uut_ediff|s1|Add0~10  ))
+// \uut_ediff|s1|Add0~14  = CARRY(( \uut_abs_regime1|regime_N[3]~3_combout  ) + ( !\uut_abs_regime2|regime_N[3]~2_combout  ) + ( \uut_ediff|s1|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_abs_regime1|regime_N[3]~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime2|regime_N[3]~2_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~13_sumout ),
+	.cout(\uut_ediff|s1|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~13 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~13 .lut_mask = 64'h000000FF00000F0F;
+defparam \uut_ediff|s1|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N42
+cyclonev_lcell_comb \uut_abs_regime1|Add0~0 (
+// Equation(s):
+// \uut_abs_regime1|Add0~0_combout  = ( \lr[3]~8_combout  & ( \lr[3]~7_combout  ) ) # ( !\lr[3]~8_combout  & ( \lr[3]~7_combout  ) ) # ( \lr[3]~8_combout  & ( !\lr[3]~7_combout  ) ) # ( !\lr[3]~8_combout  & ( !\lr[3]~7_combout  & ( (((\lr[2]~6_combout ) # 
+// (\lr[1]~5_combout )) # (\uut_abs_regime1|regime_N[0]~1_combout )) # (\lr[1]~4_combout ) ) ) )
+
+	.dataa(!\lr[1]~4_combout ),
+	.datab(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datac(!\lr[1]~5_combout ),
+	.datad(!\lr[2]~6_combout ),
+	.datae(!\lr[3]~8_combout ),
+	.dataf(!\lr[3]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime1|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime1|Add0~0 .extended_lut = "off";
+defparam \uut_abs_regime1|Add0~0 .lut_mask = 64'h7FFFFFFFFFFFFFFF;
+defparam \uut_abs_regime1|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y6_N12
+cyclonev_lcell_comb \uut_abs_regime2|Add0~0 (
+// Equation(s):
+// \uut_abs_regime2|Add0~0_combout  = ( \sr[1]~4_combout  ) # ( !\sr[1]~4_combout  & ( (((\sr[1]~5_combout ) # (\uut_abs_regime2|Add0~1_combout )) # (\sr[3]~6_combout )) # (\sr[3]~7_combout ) ) )
+
+	.dataa(!\sr[3]~7_combout ),
+	.datab(!\sr[3]~6_combout ),
+	.datac(!\uut_abs_regime2|Add0~1_combout ),
+	.datad(!\sr[1]~5_combout ),
+	.datae(gnd),
+	.dataf(!\sr[1]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_abs_regime2|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_abs_regime2|Add0~0 .extended_lut = "off";
+defparam \uut_abs_regime2|Add0~0 .lut_mask = 64'h7FFF7FFFFFFFFFFF;
+defparam \uut_abs_regime2|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N51
+cyclonev_lcell_comb \uut_ediff|s1|Add0~5 (
+// Equation(s):
+// \uut_ediff|s1|Add0~5_sumout  = SUM(( (\uut_abs_regime1|Add0~0_combout  & (!\Add0~1_sumout  & !\Add1~1_sumout )) ) + ( (!\uut_abs_regime2|Add0~0_combout ) # ((\Add0~1_sumout  & \Add1~1_sumout )) ) + ( \uut_ediff|s1|Add0~14  ))
+
+	.dataa(!\uut_abs_regime1|Add0~0_combout ),
+	.datab(!\Add0~1_sumout ),
+	.datac(!\Add1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime2|Add0~0_combout ),
+	.datag(gnd),
+	.cin(\uut_ediff|s1|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_ediff|s1|Add0~5_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_ediff|s1|Add0~5 .extended_lut = "off";
+defparam \uut_ediff|s1|Add0~5 .lut_mask = 64'h000000FC00004040;
+defparam \uut_ediff|s1|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N0
+cyclonev_lcell_comb \dsr1|c[0]~0 (
+// Equation(s):
+// \dsr1|c[0]~0_combout  = ( \uut_ediff|s1|Add0~1_sumout  ) # ( !\uut_ediff|s1|Add0~1_sumout  & ( ((\uut_ediff|s1|Add0~5_sumout ) # (\uut_ediff|s1|Add0~9_sumout )) # (\uut_ediff|s1|Add0~13_sumout ) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(!\uut_ediff|s1|Add0~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~0 .extended_lut = "off";
+defparam \dsr1|c[0]~0 .lut_mask = 64'h7F7F7F7FFFFFFFFF;
+defparam \dsr1|c[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N9
+cyclonev_lcell_comb \dsr1|c[0]~4 (
+// Equation(s):
+// \dsr1|c[0]~4_combout  = (!\uut_ediff|s1|Add0~13_sumout  & !\uut_ediff|s1|Add0~9_sumout )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~4 .extended_lut = "off";
+defparam \dsr1|c[0]~4 .lut_mask = 64'h8888888888888888;
+defparam \dsr1|c[0]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N54
+cyclonev_lcell_comb \dsr1|tmp[0][15]~3 (
+// Equation(s):
+// \dsr1|tmp[0][15]~3_combout  = ( \LessThan0~17_combout  & ( !\WideOr0~combout  ) ) # ( !\LessThan0~17_combout  & ( !\WideOr1~combout  ) )
+
+	.dataa(!\WideOr0~combout ),
+	.datab(!\WideOr1~combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][15]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][15]~3 .extended_lut = "off";
+defparam \dsr1|tmp[0][15]~3 .lut_mask = 64'hCCCCCCCCAAAAAAAA;
+defparam \dsr1|tmp[0][15]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N18
+cyclonev_lcell_comb \dsr1|tmp[2][15]~18 (
+// Equation(s):
+// \dsr1|tmp[2][15]~18_combout  = ( \dsr1|tmp[0][15]~3_combout  & ( !\uut_ediff|s1|Add0~5_sumout  & ( (!\uut_ediff|s1|Add0~25_sumout  & (\dsr1|c[0]~4_combout  & (!\uut_ediff|s1|Add0~21_sumout  & !\uut_ediff|s1|Add0~17_sumout ))) ) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~25_sumout ),
+	.datab(!\dsr1|c[0]~4_combout ),
+	.datac(!\uut_ediff|s1|Add0~21_sumout ),
+	.datad(!\uut_ediff|s1|Add0~17_sumout ),
+	.datae(!\dsr1|tmp[0][15]~3_combout ),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][15]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][15]~18 .extended_lut = "off";
+defparam \dsr1|tmp[2][15]~18 .lut_mask = 64'h0000200000000000;
+defparam \dsr1|tmp[2][15]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y6_N15
+cyclonev_lcell_comb \uut_de2|ls|c[10]~1 (
+// Equation(s):
+// \uut_de2|ls|c[10]~1_combout  = ( \uut_de2|xinst_k|l1|h|l|vld~combout  & ( (!\uut_de2|xinst_k|l1|l|h|vld~combout  & \uut_de2|xinst_k|l1|out[2]~0_combout ) ) ) # ( !\uut_de2|xinst_k|l1|h|l|vld~combout  & ( \uut_de2|xinst_k|l1|out[2]~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[2]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|xinst_k|l1|h|l|vld~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[10]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[10]~1 .extended_lut = "off";
+defparam \uut_de2|ls|c[10]~1 .lut_mask = 64'h0F0F0F0F0C0C0C0C;
+defparam \uut_de2|ls|c[10]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N30
+cyclonev_lcell_comb \uut_de2|ls|c[11]~3 (
+// Equation(s):
+// \uut_de2|ls|c[11]~3_combout  = ( \uut_de2|ls|tmp[1][11]~2_combout  & ( (!\uut_de2|ls|c[10]~1_combout  & (((!\uut_de2|xinst_k|l1|out[2]~1_combout )))) # (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & 
+// (\uut_de2|ls|tmp[1][3]~4_combout )) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][7]~3_combout ))))) ) ) # ( !\uut_de2|ls|tmp[1][11]~2_combout  & ( (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & 
+// (\uut_de2|ls|tmp[1][3]~4_combout )) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][7]~3_combout ))))) ) )
+
+	.dataa(!\uut_de2|ls|tmp[1][3]~4_combout ),
+	.datab(!\uut_de2|ls|tmp[1][7]~3_combout ),
+	.datac(!\uut_de2|ls|c[10]~1_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][11]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[11]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[11]~3 .extended_lut = "off";
+defparam \uut_de2|ls|c[11]~3 .lut_mask = 64'h05030503F503F503;
+defparam \uut_de2|ls|c[11]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N27
+cyclonev_lcell_comb \uut_de1|ls|c[11]~1 (
+// Equation(s):
+// \uut_de1|ls|c[11]~1_combout  = (\uut_de1|xinst_k|l1|out[2]~0_combout  & ((!\uut_de1|xinst_k|l1|l|h|vld~combout ) # (!\uut_de1|xinst_k|l1|h|l|vld~combout )))
+
+	.dataa(!\uut_de1|xinst_k|l1|out[2]~0_combout ),
+	.datab(!\uut_de1|xinst_k|l1|l|h|vld~combout ),
+	.datac(!\uut_de1|xinst_k|l1|h|l|vld~combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[11]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[11]~1 .extended_lut = "off";
+defparam \uut_de1|ls|c[11]~1 .lut_mask = 64'h5454545454545454;
+defparam \uut_de1|ls|c[11]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N39
+cyclonev_lcell_comb \uut_de1|ls|c[11]~3 (
+// Equation(s):
+// \uut_de1|ls|c[11]~3_combout  = ( \uut_de1|xinst_k|l1|out[2]~1_combout  & ( (\uut_de1|ls|c[11]~1_combout  & \uut_de1|ls|tmp[1][7]~3_combout ) ) ) # ( !\uut_de1|xinst_k|l1|out[2]~1_combout  & ( (!\uut_de1|ls|c[11]~1_combout  & 
+// ((\uut_de1|ls|tmp[1][11]~2_combout ))) # (\uut_de1|ls|c[11]~1_combout  & (\uut_de1|ls|tmp[1][3]~4_combout )) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][3]~4_combout ),
+	.datab(!\uut_de1|ls|c[11]~1_combout ),
+	.datac(!\uut_de1|ls|tmp[1][11]~2_combout ),
+	.datad(!\uut_de1|ls|tmp[1][7]~3_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[11]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[11]~3 .extended_lut = "off";
+defparam \uut_de1|ls|c[11]~3 .lut_mask = 64'h1D1D1D1D00330033;
+defparam \uut_de1|ls|c[11]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N3
+cyclonev_lcell_comb \DSR_e_diff[0]~0 (
+// Equation(s):
+// \DSR_e_diff[0]~0_combout  = ( !\uut_ediff|s1|Add0~13_sumout  & ( !\uut_ediff|s1|Add0~5_sumout  & ( (!\uut_ediff|s1|Add0~21_sumout  & !\uut_ediff|s1|Add0~9_sumout ) ) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~21_sumout ),
+	.datab(gnd),
+	.datac(!\uut_ediff|s1|Add0~9_sumout ),
+	.datad(gnd),
+	.datae(!\uut_ediff|s1|Add0~13_sumout ),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\DSR_e_diff[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \DSR_e_diff[0]~0 .extended_lut = "off";
+defparam \DSR_e_diff[0]~0 .lut_mask = 64'hA0A0000000000000;
+defparam \DSR_e_diff[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N36
+cyclonev_lcell_comb \uut_de2|ls|c[10]~6 (
+// Equation(s):
+// \uut_de2|ls|c[10]~6_combout  = ( \uut_de2|ls|tmp[1][10]~7_combout  & ( (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (((!\uut_de2|ls|c[10]~1_combout )) # (\uut_de2|ls|tmp[1][2]~9_combout ))) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & 
+// (((\uut_de2|ls|c[10]~1_combout  & \uut_de2|ls|tmp[1][6]~8_combout )))) ) ) # ( !\uut_de2|ls|tmp[1][10]~7_combout  & ( (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][2]~9_combout )) # 
+// (\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][6]~8_combout ))))) ) )
+
+	.dataa(!\uut_de2|ls|tmp[1][2]~9_combout ),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|ls|c[10]~1_combout ),
+	.datad(!\uut_de2|ls|tmp[1][6]~8_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][10]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[10]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[10]~6 .extended_lut = "off";
+defparam \uut_de2|ls|c[10]~6 .lut_mask = 64'h04070407C4C7C4C7;
+defparam \uut_de2|ls|c[10]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N21
+cyclonev_lcell_comb \uut_de1|ls|c[10]~6 (
+// Equation(s):
+// \uut_de1|ls|c[10]~6_combout  = ( \uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & (((\uut_de1|ls|c[11]~1_combout ) # (\uut_de1|ls|tmp[1][10]~7_combout )))) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & 
+// (\uut_de1|ls|tmp[1][6]~8_combout  & ((\uut_de1|ls|c[11]~1_combout )))) ) ) # ( !\uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & (((\uut_de1|ls|tmp[1][10]~7_combout  & !\uut_de1|ls|c[11]~1_combout )))) # 
+// (\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|tmp[1][6]~8_combout  & ((\uut_de1|ls|c[11]~1_combout )))) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][6]~8_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|tmp[1][10]~7_combout ),
+	.datad(!\uut_de1|ls|c[11]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[10]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[10]~6 .extended_lut = "off";
+defparam \uut_de1|ls|c[10]~6 .lut_mask = 64'h0C110C110CDD0CDD;
+defparam \uut_de1|ls|c[10]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N6
+cyclonev_lcell_comb \dsr1|tmp[0][11]~7 (
+// Equation(s):
+// \dsr1|tmp[0][11]~7_combout  = ( \uut_de1|ls|c[10]~6_combout  & ( \LessThan0~17_combout  & ( (\DSR_e_diff[0]~0_combout ) # (\uut_de1|ls|c[11]~3_combout ) ) ) ) # ( !\uut_de1|ls|c[10]~6_combout  & ( \LessThan0~17_combout  & ( (\uut_de1|ls|c[11]~3_combout  & 
+// !\DSR_e_diff[0]~0_combout ) ) ) ) # ( \uut_de1|ls|c[10]~6_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[11]~3_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[10]~6_combout ))) ) ) ) # ( 
+// !\uut_de1|ls|c[10]~6_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[11]~3_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[10]~6_combout ))) ) ) )
+
+	.dataa(!\uut_de2|ls|c[11]~3_combout ),
+	.datab(!\uut_de1|ls|c[11]~3_combout ),
+	.datac(!\DSR_e_diff[0]~0_combout ),
+	.datad(!\uut_de2|ls|c[10]~6_combout ),
+	.datae(!\uut_de1|ls|c[10]~6_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][11]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][11]~7 .extended_lut = "off";
+defparam \dsr1|tmp[0][11]~7 .lut_mask = 64'h505F505F30303F3F;
+defparam \dsr1|tmp[0][11]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N6
+cyclonev_lcell_comb \dsr1|c[0]~2 (
+// Equation(s):
+// \dsr1|c[0]~2_combout  = ( !\uut_ediff|s1|Add0~5_sumout  & ( (!\uut_ediff|s1|Add0~13_sumout  & (!\uut_ediff|s1|Add0~9_sumout  & !\uut_ediff|s1|Add0~25_sumout )) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(!\uut_ediff|s1|Add0~25_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~2 .extended_lut = "off";
+defparam \dsr1|c[0]~2 .lut_mask = 64'h8080808000000000;
+defparam \dsr1|c[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N3
+cyclonev_lcell_comb \dsr1|c[0]~1 (
+// Equation(s):
+// \dsr1|c[0]~1_combout  = ( !\uut_ediff|s1|Add0~5_sumout  & ( (!\uut_ediff|s1|Add0~13_sumout  & (!\uut_ediff|s1|Add0~9_sumout  & !\uut_ediff|s1|Add0~17_sumout )) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(!\uut_ediff|s1|Add0~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~1 .extended_lut = "off";
+defparam \dsr1|c[0]~1 .lut_mask = 64'h8080808000000000;
+defparam \dsr1|c[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N15
+cyclonev_lcell_comb \dsr1|c[7]~5 (
+// Equation(s):
+// \dsr1|c[7]~5_combout  = ( \dsr1|c[0]~1_combout  & ( (\dsr1|c[0]~0_combout  & \dsr1|tmp[2][15]~18_combout ) ) ) # ( !\dsr1|c[0]~1_combout  & ( (!\dsr1|c[0]~0_combout  & (((\dsr1|tmp[0][11]~7_combout  & \dsr1|c[0]~2_combout )))) # (\dsr1|c[0]~0_combout  & 
+// (\dsr1|tmp[2][15]~18_combout  & ((!\dsr1|c[0]~2_combout )))) ) )
+
+	.dataa(!\dsr1|c[0]~0_combout ),
+	.datab(!\dsr1|tmp[2][15]~18_combout ),
+	.datac(!\dsr1|tmp[0][11]~7_combout ),
+	.datad(!\dsr1|c[0]~2_combout ),
+	.datae(!\dsr1|c[0]~1_combout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[7]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[7]~5 .extended_lut = "off";
+defparam \dsr1|c[7]~5 .lut_mask = 64'h110A1111110A1111;
+defparam \dsr1|c[7]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N33
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][4]~5 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][4]~5_combout  = ( \Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (((!\uut_de2|xinst_k|l1|out[0]~7_combout ) # (\Add1~41_sumout )))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~45_sumout  & 
+// ((!\uut_de2|xinst_k|l1|out[0]~7_combout )))) ) ) # ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (((\Add1~41_sumout  & \uut_de2|xinst_k|l1|out[0]~7_combout )))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~45_sumout  & 
+// ((!\uut_de2|xinst_k|l1|out[0]~7_combout )))) ) )
+
+	.dataa(!\Add1~45_sumout ),
+	.datab(!\Add1~41_sumout ),
+	.datac(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][4]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][4]~5 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][4]~5 .lut_mask = 64'h05300530F530F530;
+defparam \uut_de2|ls|tmp[1][4]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N30
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][8]~6 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][8]~6_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \uut_de2|xinst_k|l1|out[1]~12_combout  & ( \Add1~29_sumout  ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \uut_de2|xinst_k|l1|out[1]~12_combout  & ( \Add1~33_sumout  ) ) 
+// ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\uut_de2|xinst_k|l1|out[1]~12_combout  & ( \Add1~49_sumout  ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\uut_de2|xinst_k|l1|out[1]~12_combout  & ( \Add1~53_sumout  ) ) )
+
+	.dataa(!\Add1~33_sumout ),
+	.datab(!\Add1~53_sumout ),
+	.datac(!\Add1~49_sumout ),
+	.datad(!\Add1~29_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][8]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][8]~6 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][8]~6 .lut_mask = 64'h33330F0F555500FF;
+defparam \uut_de2|ls|tmp[1][8]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N12
+cyclonev_lcell_comb \uut_de2|ls|c[8]~8 (
+// Equation(s):
+// \uut_de2|ls|c[8]~8_combout  = ( \uut_de2|ls|tmp[1][8]~6_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout ) # (\uut_de2|ls|tmp[1][4]~5_combout ))) ) ) # ( !\uut_de2|ls|tmp[1][8]~6_combout  & ( 
+// (\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][4]~5_combout  & !\uut_de2|xinst_k|l1|out[3]~13_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|ls|tmp[1][4]~5_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][8]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[8]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[8]~8 .extended_lut = "off";
+defparam \uut_de2|ls|c[8]~8 .lut_mask = 64'h03000300CF00CF00;
+defparam \uut_de2|ls|c[8]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N12
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][8]~6 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][8]~6_combout  = ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~33_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~49_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~29_sumout )) ) ) ) # ( 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( \Add0~33_sumout  & ( (\Add0~53_sumout ) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( \uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~33_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// ((\Add0~49_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~29_sumout )) ) ) ) # ( !\uut_de1|xinst_k|l1|out[0]~7_combout  & ( !\Add0~33_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & \Add0~53_sumout ) ) ) )
+
+	.dataa(!\Add0~29_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~49_sumout ),
+	.datad(!\Add0~53_sumout ),
+	.datae(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][8]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][8]~6 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][8]~6 .lut_mask = 64'h00CC1D1D33FF1D1D;
+defparam \uut_de1|ls|tmp[1][8]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N36
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][4]~5 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][4]~5_combout  = ( \Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (((!\uut_de1|xinst_k|l1|out[0]~7_combout )) # (\Add0~41_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\Add0~45_sumout  & 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) # ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~41_sumout  & ((\uut_de1|xinst_k|l1|out[0]~7_combout )))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\Add0~45_sumout  & 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) )
+
+	.dataa(!\Add0~41_sumout ),
+	.datab(!\Add0~45_sumout ),
+	.datac(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][4]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][4]~5 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][4]~5 .lut_mask = 64'h03500350F350F350;
+defparam \uut_de1|ls|tmp[1][4]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N27
+cyclonev_lcell_comb \uut_de1|ls|c[8]~8 (
+// Equation(s):
+// \uut_de1|ls|c[8]~8_combout  = ( \uut_de1|ls|tmp[1][4]~5_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((\uut_de1|ls|tmp[1][8]~6_combout ) # (\uut_de1|xinst_k|l1|out[2]~1_combout ))) ) ) # ( !\uut_de1|ls|tmp[1][4]~5_combout  & ( 
+// (!\uut_de1|xinst_k|l1|out[3]~13_combout  & (!\uut_de1|xinst_k|l1|out[2]~1_combout  & \uut_de1|ls|tmp[1][8]~6_combout )) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|tmp[1][8]~6_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][4]~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[8]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[8]~8 .extended_lut = "off";
+defparam \uut_de1|ls|c[8]~8 .lut_mask = 64'h080808082A2A2A2A;
+defparam \uut_de1|ls|c[8]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N0
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][9]~1 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][9]~1_combout  = ( \Add0~33_sumout  & ( \Add0~49_sumout  & ( ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~57_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~53_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout ) ) ) 
+// ) # ( !\Add0~33_sumout  & ( \Add0~49_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~57_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~53_sumout )))) # 
+// (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((!\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( \Add0~33_sumout  & ( !\Add0~49_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~57_sumout ))) # 
+// (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~53_sumout )))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( !\Add0~33_sumout  & ( !\Add0~49_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// ((!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~57_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~53_sumout )))) ) ) )
+
+	.dataa(!\Add0~53_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~57_sumout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(!\Add0~33_sumout ),
+	.dataf(!\Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][9]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][9]~1 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][9]~1 .lut_mask = 64'h0C440C773F443F77;
+defparam \uut_de1|ls|tmp[1][9]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N6
+cyclonev_lcell_comb \uut_de1|ls|tmp[1][5]~0 (
+// Equation(s):
+// \uut_de1|ls|tmp[1][5]~0_combout  = ( \Add0~41_sumout  & ( \Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout )) # (\Add0~29_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// (((!\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~45_sumout )))) ) ) ) # ( !\Add0~41_sumout  & ( \Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout )) # (\Add0~29_sumout ))) # 
+// (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout  & \Add0~45_sumout )))) ) ) ) # ( \Add0~41_sumout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~29_sumout  & 
+// (!\uut_de1|xinst_k|l1|out[0]~7_combout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((!\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~45_sumout )))) ) ) ) # ( !\Add0~41_sumout  & ( !\Add0~37_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// (\Add0~29_sumout  & (!\uut_de1|xinst_k|l1|out[0]~7_combout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\uut_de1|xinst_k|l1|out[0]~7_combout  & \Add0~45_sumout )))) ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datab(!\Add0~29_sumout ),
+	.datac(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datad(!\Add0~45_sumout ),
+	.datae(!\Add0~41_sumout ),
+	.dataf(!\Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|tmp[1][5]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|tmp[1][5]~0 .extended_lut = "off";
+defparam \uut_de1|ls|tmp[1][5]~0 .lut_mask = 64'h202570752A2F7A7F;
+defparam \uut_de1|ls|tmp[1][5]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N33
+cyclonev_lcell_comb \uut_de1|ls|c[9]~7 (
+// Equation(s):
+// \uut_de1|ls|c[9]~7_combout  = ( \uut_de1|ls|tmp[1][5]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((\uut_de1|xinst_k|l1|out[2]~1_combout ) # (\uut_de1|ls|tmp[1][9]~1_combout ))) ) ) # ( !\uut_de1|ls|tmp[1][5]~0_combout  & ( 
+// (\uut_de1|ls|tmp[1][9]~1_combout  & (!\uut_de1|xinst_k|l1|out[2]~1_combout  & !\uut_de1|xinst_k|l1|out[3]~13_combout )) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][9]~1_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(gnd),
+	.datad(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][5]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[9]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[9]~7 .extended_lut = "off";
+defparam \uut_de1|ls|c[9]~7 .lut_mask = 64'h4400440077007700;
+defparam \uut_de1|ls|c[9]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N36
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][9]~1 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][9]~1_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~57_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~53_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~33_sumout )) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~57_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~49_sumout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~57_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & 
+// ((\Add1~53_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~33_sumout )) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~57_sumout  & ( (\uut_de2|xinst_k|l1|out[1]~12_combout  & \Add1~49_sumout ) ) ) )
+
+	.dataa(!\Add1~33_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~49_sumout ),
+	.datad(!\Add1~53_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][9]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][9]~1 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][9]~1 .lut_mask = 64'h030311DDCFCF11DD;
+defparam \uut_de2|ls|tmp[1][9]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y6_N24
+cyclonev_lcell_comb \uut_de2|ls|tmp[1][5]~0 (
+// Equation(s):
+// \uut_de2|ls|tmp[1][5]~0_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~45_sumout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~37_sumout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~29_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~41_sumout ))) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~37_sumout  & ( (\Add1~45_sumout  & 
+// \uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~37_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~29_sumout )) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~41_sumout ))) ) ) )
+
+	.dataa(!\Add1~45_sumout ),
+	.datab(!\Add1~29_sumout ),
+	.datac(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datad(!\Add1~41_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|tmp[1][5]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|tmp[1][5]~0 .extended_lut = "off";
+defparam \uut_de2|ls|tmp[1][5]~0 .lut_mask = 64'h303F0505303FF5F5;
+defparam \uut_de2|ls|tmp[1][5]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N15
+cyclonev_lcell_comb \uut_de2|ls|c[9]~7 (
+// Equation(s):
+// \uut_de2|ls|c[9]~7_combout  = ( \uut_de2|ls|tmp[1][5]~0_combout  & ( (!\uut_de2|xinst_k|l1|out[3]~13_combout  & ((\uut_de2|xinst_k|l1|out[2]~1_combout ) # (\uut_de2|ls|tmp[1][9]~1_combout ))) ) ) # ( !\uut_de2|ls|tmp[1][5]~0_combout  & ( 
+// (\uut_de2|ls|tmp[1][9]~1_combout  & (!\uut_de2|xinst_k|l1|out[3]~13_combout  & !\uut_de2|xinst_k|l1|out[2]~1_combout )) ) )
+
+	.dataa(!\uut_de2|ls|tmp[1][9]~1_combout ),
+	.datab(gnd),
+	.datac(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][5]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[9]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[9]~7 .extended_lut = "off";
+defparam \uut_de2|ls|c[9]~7 .lut_mask = 64'h5000500050F050F0;
+defparam \uut_de2|ls|c[9]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N24
+cyclonev_lcell_comb \dsr1|tmp[0][9]~11 (
+// Equation(s):
+// \dsr1|tmp[0][9]~11_combout  = ( \DSR_e_diff[0]~0_combout  & ( \LessThan0~17_combout  & ( \uut_de1|ls|c[8]~8_combout  ) ) ) # ( !\DSR_e_diff[0]~0_combout  & ( \LessThan0~17_combout  & ( \uut_de1|ls|c[9]~7_combout  ) ) ) # ( \DSR_e_diff[0]~0_combout  & ( 
+// !\LessThan0~17_combout  & ( \uut_de2|ls|c[8]~8_combout  ) ) ) # ( !\DSR_e_diff[0]~0_combout  & ( !\LessThan0~17_combout  & ( \uut_de2|ls|c[9]~7_combout  ) ) )
+
+	.dataa(!\uut_de2|ls|c[8]~8_combout ),
+	.datab(!\uut_de1|ls|c[8]~8_combout ),
+	.datac(!\uut_de1|ls|c[9]~7_combout ),
+	.datad(!\uut_de2|ls|c[9]~7_combout ),
+	.datae(!\DSR_e_diff[0]~0_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][9]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][9]~11 .extended_lut = "off";
+defparam \dsr1|tmp[0][9]~11 .lut_mask = 64'h00FF55550F0F3333;
+defparam \dsr1|tmp[0][9]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N0
+cyclonev_lcell_comb \uut_de2|ls|c[13]~0 (
+// Equation(s):
+// \uut_de2|ls|c[13]~0_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~17_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) ) ) ) # ( 
+// !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( (\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~5_sumout ) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & 
+// ((\Add1~17_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (\Add1~5_sumout  & !\uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) )
+
+	.dataa(!\Add1~5_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~25_sumout ),
+	.datad(!\Add1~17_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[13]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[13]~0 .extended_lut = "off";
+defparam \uut_de2|ls|c[13]~0 .lut_mask = 64'h444403CF777703CF;
+defparam \uut_de2|ls|c[13]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N42
+cyclonev_lcell_comb \uut_de2|ls|c[13]~2 (
+// Equation(s):
+// \uut_de2|ls|c[13]~2_combout  = ( \uut_de2|ls|tmp[1][5]~0_combout  & ( (!\uut_de2|ls|c[10]~1_combout  & (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|c[13]~0_combout ))) # (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout ) # 
+// ((\uut_de2|ls|tmp[1][9]~1_combout )))) ) ) # ( !\uut_de2|ls|tmp[1][5]~0_combout  & ( (!\uut_de2|ls|c[10]~1_combout  & (!\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|c[13]~0_combout ))) # (\uut_de2|ls|c[10]~1_combout  & 
+// (\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][9]~1_combout )))) ) )
+
+	.dataa(!\uut_de2|ls|c[10]~1_combout ),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|ls|c[13]~0_combout ),
+	.datad(!\uut_de2|ls|tmp[1][9]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][5]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[13]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[13]~2 .extended_lut = "off";
+defparam \uut_de2|ls|c[13]~2 .lut_mask = 64'h081908194C5D4C5D;
+defparam \uut_de2|ls|c[13]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N24
+cyclonev_lcell_comb \uut_de2|ls|c[12]~4 (
+// Equation(s):
+// \uut_de2|ls|c[12]~4_combout  = ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout ) # (\Add1~57_sumout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( \Add1~21_sumout  & ( 
+// (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~17_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) ) ) ) # ( \uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (\Add1~57_sumout  & 
+// \uut_de2|xinst_k|l1|out[1]~12_combout ) ) ) ) # ( !\uut_de2|xinst_k|l1|out[0]~7_combout  & ( !\Add1~21_sumout  & ( (!\uut_de2|xinst_k|l1|out[1]~12_combout  & ((\Add1~17_sumout ))) # (\uut_de2|xinst_k|l1|out[1]~12_combout  & (\Add1~25_sumout )) ) ) )
+
+	.dataa(!\Add1~57_sumout ),
+	.datab(!\uut_de2|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add1~25_sumout ),
+	.datad(!\Add1~17_sumout ),
+	.datae(!\uut_de2|xinst_k|l1|out[0]~7_combout ),
+	.dataf(!\Add1~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[12]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[12]~4 .extended_lut = "off";
+defparam \uut_de2|ls|c[12]~4 .lut_mask = 64'h03CF111103CFDDDD;
+defparam \uut_de2|ls|c[12]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y7_N45
+cyclonev_lcell_comb \uut_de2|ls|c[12]~5 (
+// Equation(s):
+// \uut_de2|ls|c[12]~5_combout  = ( \uut_de2|ls|c[12]~4_combout  & ( (!\uut_de2|ls|c[10]~1_combout  & (!\uut_de2|xinst_k|l1|out[2]~1_combout )) # (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][4]~5_combout ))) 
+// # (\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][8]~6_combout )))) ) ) # ( !\uut_de2|ls|c[12]~4_combout  & ( (\uut_de2|ls|c[10]~1_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][4]~5_combout ))) # 
+// (\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][8]~6_combout )))) ) )
+
+	.dataa(!\uut_de2|ls|c[10]~1_combout ),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|ls|tmp[1][8]~6_combout ),
+	.datad(!\uut_de2|ls|tmp[1][4]~5_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[12]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[12]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[12]~5 .extended_lut = "off";
+defparam \uut_de2|ls|c[12]~5 .lut_mask = 64'h0145014589CD89CD;
+defparam \uut_de2|ls|c[12]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N54
+cyclonev_lcell_comb \uut_de1|ls|c[13]~0 (
+// Equation(s):
+// \uut_de1|ls|c[13]~0_combout  = ( \Add0~25_sumout  & ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( (\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~21_sumout ) ) ) ) # ( !\Add0~25_sumout  & ( \uut_de1|xinst_k|l1|out[1]~12_combout  & ( (\Add0~21_sumout  & 
+// !\uut_de1|xinst_k|l1|out[0]~7_combout ) ) ) ) # ( \Add0~25_sumout  & ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( (!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~5_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~17_sumout )) ) ) ) # ( 
+// !\Add0~25_sumout  & ( !\uut_de1|xinst_k|l1|out[1]~12_combout  & ( (!\uut_de1|xinst_k|l1|out[0]~7_combout  & ((\Add0~5_sumout ))) # (\uut_de1|xinst_k|l1|out[0]~7_combout  & (\Add0~17_sumout )) ) ) )
+
+	.dataa(!\Add0~21_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datac(!\Add0~17_sumout ),
+	.datad(!\Add0~5_sumout ),
+	.datae(!\Add0~25_sumout ),
+	.dataf(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[13]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[13]~0 .extended_lut = "off";
+defparam \uut_de1|ls|c[13]~0 .lut_mask = 64'h03CF03CF44447777;
+defparam \uut_de1|ls|c[13]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N30
+cyclonev_lcell_comb \uut_de1|ls|c[13]~2 (
+// Equation(s):
+// \uut_de1|ls|c[13]~2_combout  = ( \uut_de1|ls|tmp[1][5]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & (((\uut_de1|ls|c[11]~1_combout ) # (\uut_de1|ls|c[13]~0_combout )))) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & 
+// (\uut_de1|ls|tmp[1][9]~1_combout  & ((\uut_de1|ls|c[11]~1_combout )))) ) ) # ( !\uut_de1|ls|tmp[1][5]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & (((\uut_de1|ls|c[13]~0_combout  & !\uut_de1|ls|c[11]~1_combout )))) # 
+// (\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|tmp[1][9]~1_combout  & ((\uut_de1|ls|c[11]~1_combout )))) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][9]~1_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|c[13]~0_combout ),
+	.datad(!\uut_de1|ls|c[11]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][5]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[13]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[13]~2 .extended_lut = "off";
+defparam \uut_de1|ls|c[13]~2 .lut_mask = 64'h0C110C110CDD0CDD;
+defparam \uut_de1|ls|c[13]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y5_N12
+cyclonev_lcell_comb \uut_de1|ls|c[12]~4 (
+// Equation(s):
+// \uut_de1|ls|c[12]~4_combout  = ( \Add0~25_sumout  & ( \Add0~17_sumout  & ( (!\uut_de1|xinst_k|l1|out[0]~7_combout ) # ((!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~21_sumout )) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~57_sumout )))) ) ) ) 
+// # ( !\Add0~25_sumout  & ( \Add0~17_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (((!\uut_de1|xinst_k|l1|out[0]~7_combout )) # (\Add0~21_sumout ))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & (((\Add0~57_sumout  & 
+// \uut_de1|xinst_k|l1|out[0]~7_combout )))) ) ) ) # ( \Add0~25_sumout  & ( !\Add0~17_sumout  & ( (!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~21_sumout  & ((\uut_de1|xinst_k|l1|out[0]~7_combout )))) # (\uut_de1|xinst_k|l1|out[1]~12_combout  & 
+// (((!\uut_de1|xinst_k|l1|out[0]~7_combout ) # (\Add0~57_sumout )))) ) ) ) # ( !\Add0~25_sumout  & ( !\Add0~17_sumout  & ( (\uut_de1|xinst_k|l1|out[0]~7_combout  & ((!\uut_de1|xinst_k|l1|out[1]~12_combout  & (\Add0~21_sumout )) # 
+// (\uut_de1|xinst_k|l1|out[1]~12_combout  & ((\Add0~57_sumout ))))) ) ) )
+
+	.dataa(!\Add0~21_sumout ),
+	.datab(!\uut_de1|xinst_k|l1|out[1]~12_combout ),
+	.datac(!\Add0~57_sumout ),
+	.datad(!\uut_de1|xinst_k|l1|out[0]~7_combout ),
+	.datae(!\Add0~25_sumout ),
+	.dataf(!\Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[12]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[12]~4 .extended_lut = "off";
+defparam \uut_de1|ls|c[12]~4 .lut_mask = 64'h00473347CC47FF47;
+defparam \uut_de1|ls|c[12]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N42
+cyclonev_lcell_comb \uut_de1|ls|c[12]~5 (
+// Equation(s):
+// \uut_de1|ls|c[12]~5_combout  = ( \uut_de1|ls|tmp[1][8]~6_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & ((!\uut_de1|ls|c[11]~1_combout  & ((\uut_de1|ls|c[12]~4_combout ))) # (\uut_de1|ls|c[11]~1_combout  & (\uut_de1|ls|tmp[1][4]~5_combout )))) # 
+// (\uut_de1|xinst_k|l1|out[2]~1_combout  & (((\uut_de1|ls|c[11]~1_combout )))) ) ) # ( !\uut_de1|ls|tmp[1][8]~6_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & ((!\uut_de1|ls|c[11]~1_combout  & ((\uut_de1|ls|c[12]~4_combout ))) # 
+// (\uut_de1|ls|c[11]~1_combout  & (\uut_de1|ls|tmp[1][4]~5_combout )))) ) )
+
+	.dataa(!\uut_de1|ls|tmp[1][4]~5_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|c[12]~4_combout ),
+	.datad(!\uut_de1|ls|c[11]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][8]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[12]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[12]~5 .extended_lut = "off";
+defparam \uut_de1|ls|c[12]~5 .lut_mask = 64'h0C440C440C770C77;
+defparam \uut_de1|ls|c[12]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N0
+cyclonev_lcell_comb \dsr1|tmp[0][13]~5 (
+// Equation(s):
+// \dsr1|tmp[0][13]~5_combout  = ( \uut_de1|ls|c[13]~2_combout  & ( \uut_de1|ls|c[12]~5_combout  & ( ((!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[13]~2_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[12]~5_combout )))) # (\LessThan0~17_combout ) ) 
+// ) ) # ( !\uut_de1|ls|c[13]~2_combout  & ( \uut_de1|ls|c[12]~5_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[13]~2_combout  & ((!\LessThan0~17_combout )))) # (\DSR_e_diff[0]~0_combout  & (((\LessThan0~17_combout ) # (\uut_de2|ls|c[12]~5_combout 
+// )))) ) ) ) # ( \uut_de1|ls|c[13]~2_combout  & ( !\uut_de1|ls|c[12]~5_combout  & ( (!\DSR_e_diff[0]~0_combout  & (((\LessThan0~17_combout )) # (\uut_de2|ls|c[13]~2_combout ))) # (\DSR_e_diff[0]~0_combout  & (((\uut_de2|ls|c[12]~5_combout  & 
+// !\LessThan0~17_combout )))) ) ) ) # ( !\uut_de1|ls|c[13]~2_combout  & ( !\uut_de1|ls|c[12]~5_combout  & ( (!\LessThan0~17_combout  & ((!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[13]~2_combout )) # (\DSR_e_diff[0]~0_combout  & 
+// ((\uut_de2|ls|c[12]~5_combout ))))) ) ) )
+
+	.dataa(!\DSR_e_diff[0]~0_combout ),
+	.datab(!\uut_de2|ls|c[13]~2_combout ),
+	.datac(!\uut_de2|ls|c[12]~5_combout ),
+	.datad(!\LessThan0~17_combout ),
+	.datae(!\uut_de1|ls|c[13]~2_combout ),
+	.dataf(!\uut_de1|ls|c[12]~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][13]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][13]~5 .extended_lut = "off";
+defparam \dsr1|tmp[0][13]~5 .lut_mask = 64'h270027AA275527FF;
+defparam \dsr1|tmp[0][13]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N33
+cyclonev_lcell_comb \uut_de2|ls|c[7]~9 (
+// Equation(s):
+// \uut_de2|ls|c[7]~9_combout  = (!\uut_de2|xinst_k|l1|out[3]~13_combout  & ((!\uut_de2|xinst_k|l1|out[2]~1_combout  & ((\uut_de2|ls|tmp[1][7]~3_combout ))) # (\uut_de2|xinst_k|l1|out[2]~1_combout  & (\uut_de2|ls|tmp[1][3]~4_combout ))))
+
+	.dataa(!\uut_de2|ls|tmp[1][3]~4_combout ),
+	.datab(!\uut_de2|ls|tmp[1][7]~3_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datad(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[7]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[7]~9 .extended_lut = "off";
+defparam \uut_de2|ls|c[7]~9 .lut_mask = 64'h3050305030503050;
+defparam \uut_de2|ls|c[7]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N0
+cyclonev_lcell_comb \uut_de1|ls|c[6]~10 (
+// Equation(s):
+// \uut_de1|ls|c[6]~10_combout  = ( \uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & ((\uut_de1|ls|tmp[1][6]~8_combout ) # (\uut_de1|xinst_k|l1|out[2]~1_combout ))) ) ) # ( !\uut_de1|ls|tmp[1][2]~9_combout  & ( 
+// (!\uut_de1|xinst_k|l1|out[3]~13_combout  & (!\uut_de1|xinst_k|l1|out[2]~1_combout  & \uut_de1|ls|tmp[1][6]~8_combout )) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|tmp[1][6]~8_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[6]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[6]~10 .extended_lut = "off";
+defparam \uut_de1|ls|c[6]~10 .lut_mask = 64'h080808082A2A2A2A;
+defparam \uut_de1|ls|c[6]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N18
+cyclonev_lcell_comb \uut_de1|ls|c[7]~9 (
+// Equation(s):
+// \uut_de1|ls|c[7]~9_combout  = ( !\uut_de1|xinst_k|l1|out[3]~13_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & ((\uut_de1|ls|tmp[1][7]~3_combout ))) # (\uut_de1|xinst_k|l1|out[2]~1_combout  & (\uut_de1|ls|tmp[1][3]~4_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de1|ls|tmp[1][3]~4_combout ),
+	.datad(!\uut_de1|ls|tmp[1][7]~3_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[7]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[7]~9 .extended_lut = "off";
+defparam \uut_de1|ls|c[7]~9 .lut_mask = 64'h03CF03CF00000000;
+defparam \uut_de1|ls|c[7]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N0
+cyclonev_lcell_comb \dsr1|tmp[0][7]~17 (
+// Equation(s):
+// \dsr1|tmp[0][7]~17_combout  = ( \uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout ) # (\uut_de1|ls|c[6]~10_combout ) ) ) ) # ( !\uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( (\uut_de1|ls|c[6]~10_combout  & 
+// \DSR_e_diff[0]~0_combout ) ) ) ) # ( \uut_de1|ls|c[7]~9_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[7]~9_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[6]~10_combout ))) ) ) ) # ( 
+// !\uut_de1|ls|c[7]~9_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[7]~9_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[6]~10_combout ))) ) ) )
+
+	.dataa(!\uut_de2|ls|c[7]~9_combout ),
+	.datab(!\uut_de1|ls|c[6]~10_combout ),
+	.datac(!\DSR_e_diff[0]~0_combout ),
+	.datad(!\uut_de2|ls|c[6]~10_combout ),
+	.datae(!\uut_de1|ls|c[7]~9_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][7]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][7]~17 .extended_lut = "off";
+defparam \dsr1|tmp[0][7]~17 .lut_mask = 64'h505F505F0303F3F3;
+defparam \dsr1|tmp[0][7]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N36
+cyclonev_lcell_comb \dsr1|c[7]~3 (
+// Equation(s):
+// \dsr1|c[7]~3_combout  = ( \dsr1|tmp[0][13]~5_combout  & ( \dsr1|tmp[0][7]~17_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~2_combout  & ((!\dsr1|c[0]~1_combout ) # (\dsr1|tmp[0][9]~11_combout ))) # (\dsr1|c[0]~2_combout  & ((\dsr1|c[0]~1_combout 
+// ))))) ) ) ) # ( !\dsr1|tmp[0][13]~5_combout  & ( \dsr1|tmp[0][7]~17_combout  & ( (!\dsr1|c[0]~0_combout  & (\dsr1|c[0]~1_combout  & ((\dsr1|tmp[0][9]~11_combout ) # (\dsr1|c[0]~2_combout )))) ) ) ) # ( \dsr1|tmp[0][13]~5_combout  & ( 
+// !\dsr1|tmp[0][7]~17_combout  & ( (!\dsr1|c[0]~2_combout  & (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout ) # (\dsr1|tmp[0][9]~11_combout )))) ) ) ) # ( !\dsr1|tmp[0][13]~5_combout  & ( !\dsr1|tmp[0][7]~17_combout  & ( (!\dsr1|c[0]~2_combout  & 
+// (\dsr1|tmp[0][9]~11_combout  & (!\dsr1|c[0]~0_combout  & \dsr1|c[0]~1_combout ))) ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][9]~11_combout ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|c[0]~1_combout ),
+	.datae(!\dsr1|tmp[0][13]~5_combout ),
+	.dataf(!\dsr1|tmp[0][7]~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[7]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[7]~3 .extended_lut = "off";
+defparam \dsr1|c[7]~3 .lut_mask = 64'h0020A0200070A070;
+defparam \dsr1|c[7]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N30
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~68 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~68_combout  = ( \in2[15]~input_o  & ( !\in1[15]~input_o  $ (((\dsr1|c[7]~3_combout ) # (\dsr1|c[7]~5_combout ))) ) ) # ( !\in2[15]~input_o  & ( !\in1[15]~input_o  $ (((!\dsr1|c[7]~5_combout  & !\dsr1|c[7]~3_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\dsr1|c[7]~5_combout ),
+	.datac(!\in1[15]~input_o ),
+	.datad(!\dsr1|c[7]~3_combout ),
+	.datae(gnd),
+	.dataf(!\in2[15]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_sub_N|a11|a1|Add0~68_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~68 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~68 .lut_mask = 64'h3CF03CF0C30FC30F;
+defparam \uut_add_sub_N|a11|a1|Add0~68 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N15
+cyclonev_lcell_comb \uut_de2|ls|c[3]~11 (
+// Equation(s):
+// \uut_de2|ls|c[3]~11_combout  = (\uut_de2|xinst_k|l1|out[3]~13_combout ) # (\uut_de2|xinst_k|l1|out[2]~1_combout )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|xinst_k|l1|out[2]~1_combout ),
+	.datac(!\uut_de2|xinst_k|l1|out[3]~13_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[3]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[3]~11 .extended_lut = "off";
+defparam \uut_de2|ls|c[3]~11 .lut_mask = 64'h3F3F3F3F3F3F3F3F;
+defparam \uut_de2|ls|c[3]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N9
+cyclonev_lcell_comb \uut_de2|ls|c[5]~12 (
+// Equation(s):
+// \uut_de2|ls|c[5]~12_combout  = (!\uut_de2|ls|c[3]~11_combout  & \uut_de2|ls|tmp[1][5]~0_combout )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(gnd),
+	.datad(!\uut_de2|ls|tmp[1][5]~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[5]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[5]~12 .extended_lut = "off";
+defparam \uut_de2|ls|c[5]~12 .lut_mask = 64'h00CC00CC00CC00CC;
+defparam \uut_de2|ls|c[5]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N18
+cyclonev_lcell_comb \dsr1|tmp[0][8]~15 (
+// Equation(s):
+// \dsr1|tmp[0][8]~15_combout  = ( \uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( (\DSR_e_diff[0]~0_combout ) # (\uut_de1|ls|c[8]~8_combout ) ) ) ) # ( !\uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( (\uut_de1|ls|c[8]~8_combout  & 
+// !\DSR_e_diff[0]~0_combout ) ) ) ) # ( \uut_de1|ls|c[7]~9_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[8]~8_combout ))) # (\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[7]~9_combout )) ) ) ) # ( 
+// !\uut_de1|ls|c[7]~9_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[8]~8_combout ))) # (\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[7]~9_combout )) ) ) )
+
+	.dataa(!\uut_de2|ls|c[7]~9_combout ),
+	.datab(!\uut_de1|ls|c[8]~8_combout ),
+	.datac(!\DSR_e_diff[0]~0_combout ),
+	.datad(!\uut_de2|ls|c[8]~8_combout ),
+	.datae(!\uut_de1|ls|c[7]~9_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][8]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][8]~15 .extended_lut = "off";
+defparam \dsr1|tmp[0][8]~15 .lut_mask = 64'h05F505F530303F3F;
+defparam \dsr1|tmp[0][8]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N42
+cyclonev_lcell_comb \dsr1|tmp[0][12]~1 (
+// Equation(s):
+// \dsr1|tmp[0][12]~1_combout  = ( \DSR_e_diff[0]~0_combout  & ( \uut_de2|ls|c[12]~5_combout  & ( (!\LessThan0~17_combout  & (\uut_de2|ls|c[11]~3_combout )) # (\LessThan0~17_combout  & ((\uut_de1|ls|c[11]~3_combout ))) ) ) ) # ( !\DSR_e_diff[0]~0_combout  & 
+// ( \uut_de2|ls|c[12]~5_combout  & ( (!\LessThan0~17_combout ) # (\uut_de1|ls|c[12]~5_combout ) ) ) ) # ( \DSR_e_diff[0]~0_combout  & ( !\uut_de2|ls|c[12]~5_combout  & ( (!\LessThan0~17_combout  & (\uut_de2|ls|c[11]~3_combout )) # (\LessThan0~17_combout  & 
+// ((\uut_de1|ls|c[11]~3_combout ))) ) ) ) # ( !\DSR_e_diff[0]~0_combout  & ( !\uut_de2|ls|c[12]~5_combout  & ( (\uut_de1|ls|c[12]~5_combout  & \LessThan0~17_combout ) ) ) )
+
+	.dataa(!\uut_de1|ls|c[12]~5_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de2|ls|c[11]~3_combout ),
+	.datad(!\uut_de1|ls|c[11]~3_combout ),
+	.datae(!\DSR_e_diff[0]~0_combout ),
+	.dataf(!\uut_de2|ls|c[12]~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][12]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][12]~1 .extended_lut = "off";
+defparam \dsr1|tmp[0][12]~1 .lut_mask = 64'h11110C3FDDDD0C3F;
+defparam \dsr1|tmp[0][12]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N45
+cyclonev_lcell_comb \uut_de1|ls|c[5]~11 (
+// Equation(s):
+// \uut_de1|ls|c[5]~11_combout  = ( \uut_de1|ls|tmp[1][5]~0_combout  & ( (!\uut_de1|xinst_k|l1|out[2]~1_combout  & !\uut_de1|xinst_k|l1|out[3]~13_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(gnd),
+	.datad(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][5]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[5]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[5]~11 .extended_lut = "off";
+defparam \uut_de1|ls|c[5]~11 .lut_mask = 64'h00000000CC00CC00;
+defparam \uut_de1|ls|c[5]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N42
+cyclonev_lcell_comb \dsr1|tmp[0][6]~19 (
+// Equation(s):
+// \dsr1|tmp[0][6]~19_combout  = ( \uut_de2|ls|c[5]~12_combout  & ( \uut_de1|ls|c[5]~11_combout  & ( ((!\LessThan0~17_combout  & (\uut_de2|ls|c[6]~10_combout )) # (\LessThan0~17_combout  & ((\uut_de1|ls|c[6]~10_combout )))) # (\DSR_e_diff[0]~0_combout ) ) ) 
+// ) # ( !\uut_de2|ls|c[5]~12_combout  & ( \uut_de1|ls|c[5]~11_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((!\LessThan0~17_combout  & (\uut_de2|ls|c[6]~10_combout )) # (\LessThan0~17_combout  & ((\uut_de1|ls|c[6]~10_combout ))))) # (\DSR_e_diff[0]~0_combout  
+// & (((\LessThan0~17_combout )))) ) ) ) # ( \uut_de2|ls|c[5]~12_combout  & ( !\uut_de1|ls|c[5]~11_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((!\LessThan0~17_combout  & (\uut_de2|ls|c[6]~10_combout )) # (\LessThan0~17_combout  & 
+// ((\uut_de1|ls|c[6]~10_combout ))))) # (\DSR_e_diff[0]~0_combout  & (((!\LessThan0~17_combout )))) ) ) ) # ( !\uut_de2|ls|c[5]~12_combout  & ( !\uut_de1|ls|c[5]~11_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((!\LessThan0~17_combout  & 
+// (\uut_de2|ls|c[6]~10_combout )) # (\LessThan0~17_combout  & ((\uut_de1|ls|c[6]~10_combout ))))) ) ) )
+
+	.dataa(!\DSR_e_diff[0]~0_combout ),
+	.datab(!\uut_de2|ls|c[6]~10_combout ),
+	.datac(!\LessThan0~17_combout ),
+	.datad(!\uut_de1|ls|c[6]~10_combout ),
+	.datae(!\uut_de2|ls|c[5]~12_combout ),
+	.dataf(!\uut_de1|ls|c[5]~11_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][6]~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][6]~19 .extended_lut = "off";
+defparam \dsr1|tmp[0][6]~19 .lut_mask = 64'h202A707A252F757F;
+defparam \dsr1|tmp[0][6]~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N0
+cyclonev_lcell_comb \dsr1|c[6]~6 (
+// Equation(s):
+// \dsr1|c[6]~6_combout  = ( \dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & (!\dsr1|c[0]~2_combout )) # (\dsr1|c[0]~1_combout  & ((\dsr1|tmp[0][8]~15_combout ) # (\dsr1|c[0]~2_combout 
+// ))))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( (\dsr1|c[0]~1_combout  & (!\dsr1|c[0]~0_combout  & ((\dsr1|tmp[0][8]~15_combout ) # (\dsr1|c[0]~2_combout )))) ) ) ) # ( \dsr1|tmp[0][12]~1_combout  & ( 
+// !\dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~0_combout  & (!\dsr1|c[0]~2_combout  & ((!\dsr1|c[0]~1_combout ) # (\dsr1|tmp[0][8]~15_combout )))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( !\dsr1|tmp[0][6]~19_combout  & ( (\dsr1|c[0]~1_combout  & 
+// (!\dsr1|c[0]~0_combout  & (!\dsr1|c[0]~2_combout  & \dsr1|tmp[0][8]~15_combout ))) ) ) )
+
+	.dataa(!\dsr1|c[0]~1_combout ),
+	.datab(!\dsr1|c[0]~0_combout ),
+	.datac(!\dsr1|c[0]~2_combout ),
+	.datad(!\dsr1|tmp[0][8]~15_combout ),
+	.datae(!\dsr1|tmp[0][12]~1_combout ),
+	.dataf(!\dsr1|tmp[0][6]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[6]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[6]~6 .extended_lut = "off";
+defparam \dsr1|c[6]~6 .lut_mask = 64'h004080C0044484C4;
+defparam \dsr1|c[6]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N12
+cyclonev_lcell_comb \dsr1|tmp[0][10]~9 (
+// Equation(s):
+// \dsr1|tmp[0][10]~9_combout  = ( \uut_de1|ls|c[10]~6_combout  & ( \LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout ) # (\uut_de1|ls|c[9]~7_combout ) ) ) ) # ( !\uut_de1|ls|c[10]~6_combout  & ( \LessThan0~17_combout  & ( (\DSR_e_diff[0]~0_combout  & 
+// \uut_de1|ls|c[9]~7_combout ) ) ) ) # ( \uut_de1|ls|c[10]~6_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[10]~6_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[9]~7_combout ))) ) ) ) # ( 
+// !\uut_de1|ls|c[10]~6_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[10]~6_combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[9]~7_combout ))) ) ) )
+
+	.dataa(!\DSR_e_diff[0]~0_combout ),
+	.datab(!\uut_de2|ls|c[10]~6_combout ),
+	.datac(!\uut_de1|ls|c[9]~7_combout ),
+	.datad(!\uut_de2|ls|c[9]~7_combout ),
+	.datae(!\uut_de1|ls|c[10]~6_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][10]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][10]~9 .extended_lut = "off";
+defparam \dsr1|tmp[0][10]~9 .lut_mask = 64'h227722770505AFAF;
+defparam \dsr1|tmp[0][10]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N36
+cyclonev_lcell_comb \dsr1|tmp[0][14]~0 (
+// Equation(s):
+// \dsr1|tmp[0][14]~0_combout  = ( \uut_de1|ls|c[13]~2_combout  & ( \LessThan0~17_combout  & ( (!\WideOr0~combout ) # (\DSR_e_diff[0]~0_combout ) ) ) ) # ( !\uut_de1|ls|c[13]~2_combout  & ( \LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & 
+// !\WideOr0~combout ) ) ) ) # ( \uut_de1|ls|c[13]~2_combout  & ( !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (!\WideOr1~combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[13]~2_combout ))) ) ) ) # ( !\uut_de1|ls|c[13]~2_combout  & ( 
+// !\LessThan0~17_combout  & ( (!\DSR_e_diff[0]~0_combout  & (!\WideOr1~combout )) # (\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[13]~2_combout ))) ) ) )
+
+	.dataa(!\DSR_e_diff[0]~0_combout ),
+	.datab(!\WideOr1~combout ),
+	.datac(!\WideOr0~combout ),
+	.datad(!\uut_de2|ls|c[13]~2_combout ),
+	.datae(!\uut_de1|ls|c[13]~2_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][14]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][14]~0 .extended_lut = "off";
+defparam \dsr1|tmp[0][14]~0 .lut_mask = 64'h88DD88DDA0A0F5F5;
+defparam \dsr1|tmp[0][14]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N6
+cyclonev_lcell_comb \dsr1|c[6]~7 (
+// Equation(s):
+// \dsr1|c[6]~7_combout  = ( !\dsr1|c[0]~1_combout  & ( \uut_ediff|s1|Add0~25_sumout  & ( (\dsr1|c[0]~2_combout  & (!\dsr1|c[0]~0_combout  & \dsr1|tmp[0][10]~9_combout )) ) ) ) # ( \dsr1|c[0]~1_combout  & ( !\uut_ediff|s1|Add0~25_sumout  & ( 
+// (\dsr1|c[0]~0_combout  & \dsr1|tmp[0][14]~0_combout ) ) ) ) # ( !\dsr1|c[0]~1_combout  & ( !\uut_ediff|s1|Add0~25_sumout  & ( (\dsr1|c[0]~2_combout  & (!\dsr1|c[0]~0_combout  & \dsr1|tmp[0][10]~9_combout )) ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|c[0]~0_combout ),
+	.datac(!\dsr1|tmp[0][10]~9_combout ),
+	.datad(!\dsr1|tmp[0][14]~0_combout ),
+	.datae(!\dsr1|c[0]~1_combout ),
+	.dataf(!\uut_ediff|s1|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[6]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[6]~7 .extended_lut = "off";
+defparam \dsr1|c[6]~7 .lut_mask = 64'h0404003304040000;
+defparam \dsr1|c[6]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N12
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~69 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~69_combout  = ( \dsr1|c[6]~7_combout  & ( !\in1[15]~input_o  $ (\in2[15]~input_o ) ) ) # ( !\dsr1|c[6]~7_combout  & ( !\in1[15]~input_o  $ (!\in2[15]~input_o  $ (\dsr1|c[6]~6_combout )) ) )
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(!\in2[15]~input_o ),
+	.datac(!\dsr1|c[6]~6_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr1|c[6]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_sub_N|a11|a1|Add0~69_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~69 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~69 .lut_mask = 64'h6969696999999999;
+defparam \uut_add_sub_N|a11|a1|Add0~69 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y5_N57
+cyclonev_lcell_comb \uut_de1|ls|c[4]~12 (
+// Equation(s):
+// \uut_de1|ls|c[4]~12_combout  = (!\uut_de1|xinst_k|l1|out[2]~1_combout  & (!\uut_de1|xinst_k|l1|out[3]~13_combout  & \uut_de1|ls|tmp[1][4]~5_combout ))
+
+	.dataa(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datac(!\uut_de1|ls|tmp[1][4]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[4]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[4]~12 .extended_lut = "off";
+defparam \uut_de1|ls|c[4]~12 .lut_mask = 64'h0808080808080808;
+defparam \uut_de1|ls|c[4]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N6
+cyclonev_lcell_comb \uut_de2|ls|c[4]~13 (
+// Equation(s):
+// \uut_de2|ls|c[4]~13_combout  = (!\uut_de2|ls|c[3]~11_combout  & \uut_de2|ls|tmp[1][4]~5_combout )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(!\uut_de2|ls|tmp[1][4]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[4]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[4]~13 .extended_lut = "off";
+defparam \uut_de2|ls|c[4]~13 .lut_mask = 64'h0C0C0C0C0C0C0C0C;
+defparam \uut_de2|ls|c[4]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N18
+cyclonev_lcell_comb \dsr1|tmp[0][5]~20 (
+// Equation(s):
+// \dsr1|tmp[0][5]~20_combout  = ( \DSR_e_diff[0]~0_combout  & ( \uut_de1|ls|c[5]~11_combout  & ( (!\LessThan0~17_combout  & ((\uut_de2|ls|c[4]~13_combout ))) # (\LessThan0~17_combout  & (\uut_de1|ls|c[4]~12_combout )) ) ) ) # ( !\DSR_e_diff[0]~0_combout  & 
+// ( \uut_de1|ls|c[5]~11_combout  & ( (\LessThan0~17_combout ) # (\uut_de2|ls|c[5]~12_combout ) ) ) ) # ( \DSR_e_diff[0]~0_combout  & ( !\uut_de1|ls|c[5]~11_combout  & ( (!\LessThan0~17_combout  & ((\uut_de2|ls|c[4]~13_combout ))) # (\LessThan0~17_combout  & 
+// (\uut_de1|ls|c[4]~12_combout )) ) ) ) # ( !\DSR_e_diff[0]~0_combout  & ( !\uut_de1|ls|c[5]~11_combout  & ( (\uut_de2|ls|c[5]~12_combout  & !\LessThan0~17_combout ) ) ) )
+
+	.dataa(!\uut_de2|ls|c[5]~12_combout ),
+	.datab(!\uut_de1|ls|c[4]~12_combout ),
+	.datac(!\LessThan0~17_combout ),
+	.datad(!\uut_de2|ls|c[4]~13_combout ),
+	.datae(!\DSR_e_diff[0]~0_combout ),
+	.dataf(!\uut_de1|ls|c[5]~11_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][5]~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][5]~20 .extended_lut = "off";
+defparam \dsr1|tmp[0][5]~20 .lut_mask = 64'h505003F35F5F03F3;
+defparam \dsr1|tmp[0][5]~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N54
+cyclonev_lcell_comb \dsr1|c[5]~9 (
+// Equation(s):
+// \dsr1|c[5]~9_combout  = ( \dsr1|c[0]~1_combout  & ( \dsr1|tmp[0][5]~20_combout  & ( (!\dsr1|c[0]~0_combout  & ((\dsr1|tmp[0][7]~17_combout ) # (\dsr1|c[0]~2_combout ))) ) ) ) # ( !\dsr1|c[0]~1_combout  & ( \dsr1|tmp[0][5]~20_combout  & ( 
+// (\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][9]~11_combout  & !\dsr1|c[0]~0_combout )) ) ) ) # ( \dsr1|c[0]~1_combout  & ( !\dsr1|tmp[0][5]~20_combout  & ( (!\dsr1|c[0]~2_combout  & (!\dsr1|c[0]~0_combout  & \dsr1|tmp[0][7]~17_combout )) ) ) ) # ( 
+// !\dsr1|c[0]~1_combout  & ( !\dsr1|tmp[0][5]~20_combout  & ( (\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][9]~11_combout  & !\dsr1|c[0]~0_combout )) ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][9]~11_combout ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[0][7]~17_combout ),
+	.datae(!\dsr1|c[0]~1_combout ),
+	.dataf(!\dsr1|tmp[0][5]~20_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[5]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[5]~9 .extended_lut = "off";
+defparam \dsr1|c[5]~9 .lut_mask = 64'h101000A0101050F0;
+defparam \dsr1|c[5]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N15
+cyclonev_lcell_comb \dsr1|tmp[0][15]~4 (
+// Equation(s):
+// \dsr1|tmp[0][15]~4_combout  = ( !\uut_ediff|s1|Add0~21_sumout  & ( (!\uut_ediff|s1|Add0~5_sumout  & (!\uut_ediff|s1|Add0~9_sumout  & (\dsr1|tmp[0][15]~3_combout  & !\uut_ediff|s1|Add0~13_sumout ))) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~5_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(!\dsr1|tmp[0][15]~3_combout ),
+	.datad(!\uut_ediff|s1|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][15]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][15]~4 .extended_lut = "off";
+defparam \dsr1|tmp[0][15]~4 .lut_mask = 64'h0800080000000000;
+defparam \dsr1|tmp[0][15]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N18
+cyclonev_lcell_comb \dsr1|c[5]~8 (
+// Equation(s):
+// \dsr1|c[5]~8_combout  = ( \dsr1|tmp[0][13]~5_combout  & ( \dsr1|c[0]~2_combout  & ( (\dsr1|c[0]~0_combout  & \dsr1|c[0]~1_combout ) ) ) ) # ( \dsr1|tmp[0][13]~5_combout  & ( !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & 
+// (((\dsr1|tmp[0][11]~7_combout  & !\dsr1|c[0]~1_combout )))) # (\dsr1|c[0]~0_combout  & (\dsr1|tmp[0][15]~4_combout  & ((\dsr1|c[0]~1_combout )))) ) ) ) # ( !\dsr1|tmp[0][13]~5_combout  & ( !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & 
+// (((\dsr1|tmp[0][11]~7_combout  & !\dsr1|c[0]~1_combout )))) # (\dsr1|c[0]~0_combout  & (\dsr1|tmp[0][15]~4_combout  & ((\dsr1|c[0]~1_combout )))) ) ) )
+
+	.dataa(!\dsr1|tmp[0][15]~4_combout ),
+	.datab(!\dsr1|tmp[0][11]~7_combout ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|c[0]~1_combout ),
+	.datae(!\dsr1|tmp[0][13]~5_combout ),
+	.dataf(!\dsr1|c[0]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[5]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[5]~8 .extended_lut = "off";
+defparam \dsr1|c[5]~8 .lut_mask = 64'h300530050000000F;
+defparam \dsr1|c[5]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N15
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~70 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~70_combout  = ( \dsr1|c[5]~8_combout  & ( !\in1[15]~input_o  $ (\in2[15]~input_o ) ) ) # ( !\dsr1|c[5]~8_combout  & ( !\in1[15]~input_o  $ (!\in2[15]~input_o  $ (\dsr1|c[5]~9_combout )) ) )
+
+	.dataa(!\in1[15]~input_o ),
+	.datab(!\in2[15]~input_o ),
+	.datac(!\dsr1|c[5]~9_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr1|c[5]~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_sub_N|a11|a1|Add0~70_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~70 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~70 .lut_mask = 64'h6969696999999999;
+defparam \uut_add_sub_N|a11|a1|Add0~70 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N18
+cyclonev_lcell_comb \dsr1|c[4]~10 (
+// Equation(s):
+// \dsr1|c[4]~10_combout  = ( \dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~1_combout  & (!\dsr1|c[0]~2_combout  & ((!\dsr1|c[0]~0_combout )))) # (\dsr1|c[0]~1_combout  & (\dsr1|c[0]~0_combout  & ((\dsr1|tmp[0][14]~0_combout ) 
+// # (\dsr1|c[0]~2_combout )))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & ((!\dsr1|c[0]~1_combout  & ((!\dsr1|c[0]~0_combout ))) # (\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][14]~0_combout  & 
+// \dsr1|c[0]~0_combout )))) ) ) ) # ( \dsr1|tmp[0][12]~1_combout  & ( !\dsr1|tmp[0][10]~9_combout  & ( (\dsr1|c[0]~1_combout  & (\dsr1|c[0]~0_combout  & ((\dsr1|tmp[0][14]~0_combout ) # (\dsr1|c[0]~2_combout )))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( 
+// !\dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][14]~0_combout  & (\dsr1|c[0]~1_combout  & \dsr1|c[0]~0_combout ))) ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][14]~0_combout ),
+	.datac(!\dsr1|c[0]~1_combout ),
+	.datad(!\dsr1|c[0]~0_combout ),
+	.datae(!\dsr1|tmp[0][12]~1_combout ),
+	.dataf(!\dsr1|tmp[0][10]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[4]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[4]~10 .extended_lut = "off";
+defparam \dsr1|c[4]~10 .lut_mask = 64'h00020007A002A007;
+defparam \dsr1|c[4]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N3
+cyclonev_lcell_comb \uut_de1|ls|c[3]~13 (
+// Equation(s):
+// \uut_de1|ls|c[3]~13_combout  = ( \uut_de1|ls|tmp[1][3]~4_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & !\uut_de1|xinst_k|l1|out[2]~1_combout ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][3]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[3]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[3]~13 .extended_lut = "off";
+defparam \uut_de1|ls|c[3]~13 .lut_mask = 64'h0000000088888888;
+defparam \uut_de1|ls|c[3]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N45
+cyclonev_lcell_comb \uut_de2|ls|c[3]~14 (
+// Equation(s):
+// \uut_de2|ls|c[3]~14_combout  = (!\uut_de2|ls|c[3]~11_combout  & \uut_de2|ls|tmp[1][3]~4_combout )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(gnd),
+	.datad(!\uut_de2|ls|tmp[1][3]~4_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[3]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[3]~14 .extended_lut = "off";
+defparam \uut_de2|ls|c[3]~14 .lut_mask = 64'h00CC00CC00CC00CC;
+defparam \uut_de2|ls|c[3]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N24
+cyclonev_lcell_comb \dsr1|tmp[0][4]~21 (
+// Equation(s):
+// \dsr1|tmp[0][4]~21_combout  = ( \LessThan0~17_combout  & ( \uut_de2|ls|c[4]~13_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((\uut_de1|ls|c[4]~12_combout ))) # (\DSR_e_diff[0]~0_combout  & (\uut_de1|ls|c[3]~13_combout )) ) ) ) # ( !\LessThan0~17_combout  & 
+// ( \uut_de2|ls|c[4]~13_combout  & ( (!\DSR_e_diff[0]~0_combout ) # (\uut_de2|ls|c[3]~14_combout ) ) ) ) # ( \LessThan0~17_combout  & ( !\uut_de2|ls|c[4]~13_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((\uut_de1|ls|c[4]~12_combout ))) # 
+// (\DSR_e_diff[0]~0_combout  & (\uut_de1|ls|c[3]~13_combout )) ) ) ) # ( !\LessThan0~17_combout  & ( !\uut_de2|ls|c[4]~13_combout  & ( (\DSR_e_diff[0]~0_combout  & \uut_de2|ls|c[3]~14_combout ) ) ) )
+
+	.dataa(!\uut_de1|ls|c[3]~13_combout ),
+	.datab(!\uut_de1|ls|c[4]~12_combout ),
+	.datac(!\DSR_e_diff[0]~0_combout ),
+	.datad(!\uut_de2|ls|c[3]~14_combout ),
+	.datae(!\LessThan0~17_combout ),
+	.dataf(!\uut_de2|ls|c[4]~13_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][4]~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][4]~21 .extended_lut = "off";
+defparam \dsr1|tmp[0][4]~21 .lut_mask = 64'h000F3535F0FF3535;
+defparam \dsr1|tmp[0][4]~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N24
+cyclonev_lcell_comb \dsr1|c[4]~11 (
+// Equation(s):
+// \dsr1|c[4]~11_combout  = ( \dsr1|c[0]~2_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & ((\dsr1|tmp[0][8]~15_combout ))) # (\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][4]~21_combout )))) ) ) ) # ( 
+// !\dsr1|c[0]~2_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~0_combout  & \dsr1|c[0]~1_combout ) ) ) ) # ( \dsr1|c[0]~2_combout  & ( !\dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & 
+// ((\dsr1|tmp[0][8]~15_combout ))) # (\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][4]~21_combout )))) ) ) )
+
+	.dataa(!\dsr1|tmp[0][4]~21_combout ),
+	.datab(!\dsr1|c[0]~0_combout ),
+	.datac(!\dsr1|c[0]~1_combout ),
+	.datad(!\dsr1|tmp[0][8]~15_combout ),
+	.datae(!\dsr1|c[0]~2_combout ),
+	.dataf(!\dsr1|tmp[0][6]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[4]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[4]~11 .extended_lut = "off";
+defparam \dsr1|c[4]~11 .lut_mask = 64'h000004C40C0C04C4;
+defparam \dsr1|c[4]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N42
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~71 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~71_combout  = ( \in1[15]~input_o  & ( !\in2[15]~input_o  $ (((\dsr1|c[4]~11_combout ) # (\dsr1|c[4]~10_combout ))) ) ) # ( !\in1[15]~input_o  & ( !\in2[15]~input_o  $ (((!\dsr1|c[4]~10_combout  & !\dsr1|c[4]~11_combout ))) ) )
+
+	.dataa(!\dsr1|c[4]~10_combout ),
+	.datab(gnd),
+	.datac(!\dsr1|c[4]~11_combout ),
+	.datad(!\in2[15]~input_o ),
+	.datae(gnd),
+	.dataf(!\in1[15]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_sub_N|a11|a1|Add0~71_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~71 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~71 .lut_mask = 64'h5FA05FA0A05FA05F;
+defparam \uut_add_sub_N|a11|a1|Add0~71 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N42
+cyclonev_lcell_comb \uut_de2|ls|c[2]~15 (
+// Equation(s):
+// \uut_de2|ls|c[2]~15_combout  = ( \uut_de2|ls|tmp[1][2]~9_combout  & ( !\uut_de2|ls|c[3]~11_combout  ) )
+
+	.dataa(gnd),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de2|ls|c[2]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de2|ls|c[2]~15 .extended_lut = "off";
+defparam \uut_de2|ls|c[2]~15 .lut_mask = 64'h00000000CCCCCCCC;
+defparam \uut_de2|ls|c[2]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N24
+cyclonev_lcell_comb \uut_de1|ls|c[2]~14 (
+// Equation(s):
+// \uut_de1|ls|c[2]~14_combout  = ( \uut_de1|ls|tmp[1][2]~9_combout  & ( (!\uut_de1|xinst_k|l1|out[3]~13_combout  & !\uut_de1|xinst_k|l1|out[2]~1_combout ) ) )
+
+	.dataa(!\uut_de1|xinst_k|l1|out[3]~13_combout ),
+	.datab(!\uut_de1|xinst_k|l1|out[2]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|tmp[1][2]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_de1|ls|c[2]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_de1|ls|c[2]~14 .extended_lut = "off";
+defparam \uut_de1|ls|c[2]~14 .lut_mask = 64'h0000000088888888;
+defparam \uut_de1|ls|c[2]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N30
+cyclonev_lcell_comb \dsr1|tmp[0][3]~22 (
+// Equation(s):
+// \dsr1|tmp[0][3]~22_combout  = ( \LessThan0~17_combout  & ( \uut_de1|ls|c[2]~14_combout  & ( (\uut_de1|ls|c[3]~13_combout ) # (\DSR_e_diff[0]~0_combout ) ) ) ) # ( !\LessThan0~17_combout  & ( \uut_de1|ls|c[2]~14_combout  & ( (!\DSR_e_diff[0]~0_combout  & 
+// ((\uut_de2|ls|c[3]~14_combout ))) # (\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[2]~15_combout )) ) ) ) # ( \LessThan0~17_combout  & ( !\uut_de1|ls|c[2]~14_combout  & ( (!\DSR_e_diff[0]~0_combout  & \uut_de1|ls|c[3]~13_combout ) ) ) ) # ( 
+// !\LessThan0~17_combout  & ( !\uut_de1|ls|c[2]~14_combout  & ( (!\DSR_e_diff[0]~0_combout  & ((\uut_de2|ls|c[3]~14_combout ))) # (\DSR_e_diff[0]~0_combout  & (\uut_de2|ls|c[2]~15_combout )) ) ) )
+
+	.dataa(!\DSR_e_diff[0]~0_combout ),
+	.datab(!\uut_de2|ls|c[2]~15_combout ),
+	.datac(!\uut_de1|ls|c[3]~13_combout ),
+	.datad(!\uut_de2|ls|c[3]~14_combout ),
+	.datae(!\LessThan0~17_combout ),
+	.dataf(!\uut_de1|ls|c[2]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][3]~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][3]~22 .extended_lut = "off";
+defparam \dsr1|tmp[0][3]~22 .lut_mask = 64'h11BB0A0A11BB5F5F;
+defparam \dsr1|tmp[0][3]~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N51
+cyclonev_lcell_comb \dsr1|c[3]~12 (
+// Equation(s):
+// \dsr1|c[3]~12_combout  = ( \dsr1|tmp[0][5]~20_combout  & ( (!\dsr1|c[0]~2_combout ) # (\dsr1|tmp[0][3]~22_combout ) ) ) # ( !\dsr1|tmp[0][5]~20_combout  & ( (\dsr1|c[0]~2_combout  & \dsr1|tmp[0][3]~22_combout ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(gnd),
+	.datac(!\dsr1|tmp[0][3]~22_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[0][5]~20_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[3]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[3]~12 .extended_lut = "off";
+defparam \dsr1|c[3]~12 .lut_mask = 64'h05050505AFAFAFAF;
+defparam \dsr1|c[3]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N12
+cyclonev_lcell_comb \dsr1|tmp[2][10]~6 (
+// Equation(s):
+// \dsr1|tmp[2][10]~6_combout  = ( \uut_ediff|s1|Add0~17_sumout  & ( (!\uut_ediff|s1|Add0~5_sumout  & (!\uut_ediff|s1|Add0~9_sumout  & (!\uut_ediff|s1|Add0~25_sumout  & !\uut_ediff|s1|Add0~13_sumout ))) ) ) # ( !\uut_ediff|s1|Add0~17_sumout  & ( 
+// (!\uut_ediff|s1|Add0~5_sumout  & (!\uut_ediff|s1|Add0~9_sumout  & (\uut_ediff|s1|Add0~25_sumout  & !\uut_ediff|s1|Add0~13_sumout ))) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~5_sumout ),
+	.datab(!\uut_ediff|s1|Add0~9_sumout ),
+	.datac(!\uut_ediff|s1|Add0~25_sumout ),
+	.datad(!\uut_ediff|s1|Add0~13_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][10]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][10]~6 .extended_lut = "off";
+defparam \dsr1|tmp[2][10]~6 .lut_mask = 64'h0800080080008000;
+defparam \dsr1|tmp[2][10]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N48
+cyclonev_lcell_comb \dsr1|tmp[2][11]~8 (
+// Equation(s):
+// \dsr1|tmp[2][11]~8_combout  = ( \dsr1|tmp[2][10]~6_combout  & ( (!\dsr1|c[0]~2_combout  & ((\dsr1|tmp[0][13]~5_combout ))) # (\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][15]~4_combout )) ) ) # ( !\dsr1|tmp[2][10]~6_combout  & ( (\dsr1|c[0]~2_combout  & 
+// \dsr1|tmp[0][11]~7_combout ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][11]~7_combout ),
+	.datac(!\dsr1|tmp[0][15]~4_combout ),
+	.datad(!\dsr1|tmp[0][13]~5_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[2][10]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][11]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][11]~8 .extended_lut = "off";
+defparam \dsr1|tmp[2][11]~8 .lut_mask = 64'h1111111105AF05AF;
+defparam \dsr1|tmp[2][11]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N6
+cyclonev_lcell_comb \dsr1|c[3]~26 (
+// Equation(s):
+// \dsr1|c[3]~26_combout  = ( !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & (((\dsr1|tmp[0][9]~11_combout )))) # (\dsr1|c[0]~1_combout  & (\dsr1|c[3]~12_combout )))) # (\dsr1|c[0]~0_combout  & ((((\dsr1|tmp[2][11]~8_combout 
+// ))))) ) ) # ( \dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & (((\dsr1|tmp[0][7]~17_combout )))) # (\dsr1|c[0]~1_combout  & (\dsr1|c[3]~12_combout )))) # (\dsr1|c[0]~0_combout  & ((((\dsr1|tmp[2][11]~8_combout ))))) ) )
+
+	.dataa(!\dsr1|c[3]~12_combout ),
+	.datab(!\dsr1|c[0]~1_combout ),
+	.datac(!\dsr1|tmp[0][7]~17_combout ),
+	.datad(!\dsr1|tmp[2][11]~8_combout ),
+	.datae(!\dsr1|c[0]~2_combout ),
+	.dataf(!\dsr1|c[0]~0_combout ),
+	.datag(!\dsr1|tmp[0][9]~11_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[3]~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[3]~26 .extended_lut = "on";
+defparam \dsr1|c[3]~26 .lut_mask = 64'h1D1D1D1D00FF00FF;
+defparam \dsr1|c[3]~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N39
+cyclonev_lcell_comb \add_m_in1[3]~7 (
+// Equation(s):
+// \add_m_in1[3]~7_combout  = ( \uut_de2|ls|c[2]~15_combout  & ( (\LessThan0~17_combout ) # (\uut_de1|ls|c[2]~14_combout ) ) ) # ( !\uut_de2|ls|c[2]~15_combout  & ( (\uut_de1|ls|c[2]~14_combout  & !\LessThan0~17_combout ) ) )
+
+	.dataa(!\uut_de1|ls|c[2]~14_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\LessThan0~17_combout ),
+	.datae(!\uut_de2|ls|c[2]~15_combout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[3]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[3]~7 .extended_lut = "off";
+defparam \add_m_in1[3]~7 .lut_mask = 64'h550055FF550055FF;
+defparam \add_m_in1[3]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N12
+cyclonev_lcell_comb \dsr1|tmp[0][2]~23 (
+// Equation(s):
+// \dsr1|tmp[0][2]~23_combout  = (!\LessThan0~17_combout  & (\uut_de2|ls|c[2]~15_combout )) # (\LessThan0~17_combout  & ((\uut_de1|ls|c[2]~14_combout )))
+
+	.dataa(gnd),
+	.datab(!\uut_de2|ls|c[2]~15_combout ),
+	.datac(!\uut_de1|ls|c[2]~14_combout ),
+	.datad(!\LessThan0~17_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[0][2]~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[0][2]~23 .extended_lut = "off";
+defparam \dsr1|tmp[0][2]~23 .lut_mask = 64'h330F330F330F330F;
+defparam \dsr1|tmp[0][2]~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N15
+cyclonev_lcell_comb \dsr1|c[2]~13 (
+// Equation(s):
+// \dsr1|c[2]~13_combout  = ( \dsr1|tmp[0][4]~21_combout  & ( (!\dsr1|c[0]~2_combout ) # ((\dsr1|tmp[0][2]~23_combout  & !\DSR_e_diff[0]~0_combout )) ) ) # ( !\dsr1|tmp[0][4]~21_combout  & ( (\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][2]~23_combout  & 
+// !\DSR_e_diff[0]~0_combout )) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(gnd),
+	.datac(!\dsr1|tmp[0][2]~23_combout ),
+	.datad(!\DSR_e_diff[0]~0_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[0][4]~21_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[2]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[2]~13 .extended_lut = "off";
+defparam \dsr1|c[2]~13 .lut_mask = 64'h05000500AFAAAFAA;
+defparam \dsr1|c[2]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N39
+cyclonev_lcell_comb \dsr1|tmp[2][10]~10 (
+// Equation(s):
+// \dsr1|tmp[2][10]~10_combout  = ( \dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (((\dsr1|tmp[0][12]~1_combout  & \dsr1|tmp[2][10]~6_combout )))) # (\dsr1|c[0]~2_combout  & (((!\dsr1|tmp[2][10]~6_combout )) # (\dsr1|tmp[0][14]~0_combout ))) ) ) 
+// # ( !\dsr1|tmp[0][10]~9_combout  & ( (\dsr1|tmp[2][10]~6_combout  & ((!\dsr1|c[0]~2_combout  & ((\dsr1|tmp[0][12]~1_combout ))) # (\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][14]~0_combout )))) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][14]~0_combout ),
+	.datac(!\dsr1|tmp[0][12]~1_combout ),
+	.datad(!\dsr1|tmp[2][10]~6_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[0][10]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][10]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][10]~10 .extended_lut = "off";
+defparam \dsr1|tmp[2][10]~10 .lut_mask = 64'h001B001B551B551B;
+defparam \dsr1|tmp[2][10]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N30
+cyclonev_lcell_comb \dsr1|c[2]~22 (
+// Equation(s):
+// \dsr1|c[2]~22_combout  = ( !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][8]~15_combout )) # (\dsr1|c[0]~1_combout  & (((\dsr1|c[2]~13_combout )))))) # (\dsr1|c[0]~0_combout  & ((((\dsr1|tmp[2][10]~10_combout 
+// ))))) ) ) # ( \dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][6]~19_combout )) # (\dsr1|c[0]~1_combout  & (((\dsr1|c[2]~13_combout )))))) # (\dsr1|c[0]~0_combout  & ((((\dsr1|tmp[2][10]~10_combout ))))) ) )
+
+	.dataa(!\dsr1|c[0]~1_combout ),
+	.datab(!\dsr1|c[0]~0_combout ),
+	.datac(!\dsr1|tmp[0][6]~19_combout ),
+	.datad(!\dsr1|c[2]~13_combout ),
+	.datae(!\dsr1|c[0]~2_combout ),
+	.dataf(!\dsr1|tmp[2][10]~10_combout ),
+	.datag(!\dsr1|tmp[0][8]~15_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[2]~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[2]~22 .extended_lut = "on";
+defparam \dsr1|c[2]~22 .lut_mask = 64'h084C084C3B7F3B7F;
+defparam \dsr1|c[2]~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N24
+cyclonev_lcell_comb \dsr1|c[0]~14 (
+// Equation(s):
+// \dsr1|c[0]~14_combout  = ( \uut_ediff|s1|Add0~9_sumout  & ( \uut_ediff|s1|Add0~5_sumout  ) ) # ( !\uut_ediff|s1|Add0~9_sumout  & ( \uut_ediff|s1|Add0~5_sumout  ) ) # ( \uut_ediff|s1|Add0~9_sumout  & ( !\uut_ediff|s1|Add0~5_sumout  ) ) # ( 
+// !\uut_ediff|s1|Add0~9_sumout  & ( !\uut_ediff|s1|Add0~5_sumout  & ( ((!\uut_ediff|s1|Add0~17_sumout  & (!\uut_ediff|s1|Add0~25_sumout  & !\uut_ediff|s1|Add0~1_sumout )) # (\uut_ediff|s1|Add0~17_sumout  & (\uut_ediff|s1|Add0~25_sumout ))) # 
+// (\uut_ediff|s1|Add0~13_sumout ) ) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~17_sumout ),
+	.datac(!\uut_ediff|s1|Add0~25_sumout ),
+	.datad(!\uut_ediff|s1|Add0~1_sumout ),
+	.datae(!\uut_ediff|s1|Add0~9_sumout ),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~14 .extended_lut = "off";
+defparam \dsr1|c[0]~14 .lut_mask = 64'hD757FFFFFFFFFFFF;
+defparam \dsr1|c[0]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y6_N54
+cyclonev_lcell_comb \dsr1|c[0]~15 (
+// Equation(s):
+// \dsr1|c[0]~15_combout  = ( !\uut_ediff|s1|Add0~9_sumout  & ( !\uut_ediff|s1|Add0~5_sumout  & ( (!\uut_ediff|s1|Add0~13_sumout  & (!\uut_ediff|s1|Add0~25_sumout  & ((!\uut_ediff|s1|Add0~1_sumout ) # (\uut_ediff|s1|Add0~17_sumout )))) ) ) )
+
+	.dataa(!\uut_ediff|s1|Add0~13_sumout ),
+	.datab(!\uut_ediff|s1|Add0~17_sumout ),
+	.datac(!\uut_ediff|s1|Add0~25_sumout ),
+	.datad(!\uut_ediff|s1|Add0~1_sumout ),
+	.datae(!\uut_ediff|s1|Add0~9_sumout ),
+	.dataf(!\uut_ediff|s1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~15 .extended_lut = "off";
+defparam \dsr1|c[0]~15 .lut_mask = 64'hA020000000000000;
+defparam \dsr1|c[0]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N24
+cyclonev_lcell_comb \dsr1|tmp[2][9]~12 (
+// Equation(s):
+// \dsr1|tmp[2][9]~12_combout  = ( \dsr1|tmp[0][13]~5_combout  & ( \dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~1_combout ) # (\dsr1|tmp[0][9]~11_combout ) ) ) ) # ( !\dsr1|tmp[0][13]~5_combout  & ( \dsr1|c[0]~2_combout  & ( (\dsr1|tmp[0][9]~11_combout  & 
+// \dsr1|c[0]~1_combout ) ) ) ) # ( \dsr1|tmp[0][13]~5_combout  & ( !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][15]~4_combout )) # (\dsr1|c[0]~1_combout  & ((\dsr1|tmp[0][11]~7_combout ))) ) ) ) # ( !\dsr1|tmp[0][13]~5_combout  & ( 
+// !\dsr1|c[0]~2_combout  & ( (!\dsr1|c[0]~1_combout  & (\dsr1|tmp[0][15]~4_combout )) # (\dsr1|c[0]~1_combout  & ((\dsr1|tmp[0][11]~7_combout ))) ) ) )
+
+	.dataa(!\dsr1|tmp[0][15]~4_combout ),
+	.datab(!\dsr1|tmp[0][11]~7_combout ),
+	.datac(!\dsr1|tmp[0][9]~11_combout ),
+	.datad(!\dsr1|c[0]~1_combout ),
+	.datae(!\dsr1|tmp[0][13]~5_combout ),
+	.dataf(!\dsr1|c[0]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][9]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][9]~12 .extended_lut = "off";
+defparam \dsr1|tmp[2][9]~12 .lut_mask = 64'h55335533000FFF0F;
+defparam \dsr1|tmp[2][9]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N0
+cyclonev_lcell_comb \dsr1|c[1]~18 (
+// Equation(s):
+// \dsr1|c[1]~18_combout  = ( !\dsr1|c[0]~15_combout  & ( (!\dsr1|c[0]~0_combout  & ((!\dsr1|c[0]~14_combout  & (((\dsr1|tmp[0][3]~22_combout )))) # (\dsr1|c[0]~14_combout  & (\dsr1|tmp[0][7]~17_combout )))) # (\dsr1|c[0]~0_combout  & 
+// ((((\dsr1|tmp[2][9]~12_combout ))))) ) ) # ( \dsr1|c[0]~15_combout  & ( (!\dsr1|c[0]~0_combout  & (!\dsr1|c[0]~14_combout  & (\dsr1|tmp[0][5]~20_combout ))) # (\dsr1|c[0]~0_combout  & ((((\dsr1|tmp[2][9]~12_combout ))))) ) )
+
+	.dataa(!\dsr1|c[0]~0_combout ),
+	.datab(!\dsr1|c[0]~14_combout ),
+	.datac(!\dsr1|tmp[0][5]~20_combout ),
+	.datad(!\dsr1|tmp[0][3]~22_combout ),
+	.datae(!\dsr1|c[0]~15_combout ),
+	.dataf(!\dsr1|tmp[2][9]~12_combout ),
+	.datag(!\dsr1|tmp[0][7]~17_combout ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[1]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[1]~18 .extended_lut = "on";
+defparam \dsr1|c[1]~18 .lut_mask = 64'h028A080857DF5D5D;
+defparam \dsr1|c[1]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N54
+cyclonev_lcell_comb \dsr1|tmp[2][8]~16 (
+// Equation(s):
+// \dsr1|tmp[2][8]~16_combout  = ( \dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (((\dsr1|c[0]~1_combout )) # (\dsr1|tmp[0][14]~0_combout ))) # (\dsr1|c[0]~2_combout  & (((!\dsr1|c[0]~1_combout ) # 
+// (\dsr1|tmp[0][8]~15_combout )))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( \dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (((\dsr1|c[0]~1_combout )) # (\dsr1|tmp[0][14]~0_combout ))) # (\dsr1|c[0]~2_combout  & (((\dsr1|c[0]~1_combout  & 
+// \dsr1|tmp[0][8]~15_combout )))) ) ) ) # ( \dsr1|tmp[0][12]~1_combout  & ( !\dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][14]~0_combout  & (!\dsr1|c[0]~1_combout ))) # (\dsr1|c[0]~2_combout  & (((!\dsr1|c[0]~1_combout ) # 
+// (\dsr1|tmp[0][8]~15_combout )))) ) ) ) # ( !\dsr1|tmp[0][12]~1_combout  & ( !\dsr1|tmp[0][10]~9_combout  & ( (!\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][14]~0_combout  & (!\dsr1|c[0]~1_combout ))) # (\dsr1|c[0]~2_combout  & (((\dsr1|c[0]~1_combout  & 
+// \dsr1|tmp[0][8]~15_combout )))) ) ) )
+
+	.dataa(!\dsr1|c[0]~2_combout ),
+	.datab(!\dsr1|tmp[0][14]~0_combout ),
+	.datac(!\dsr1|c[0]~1_combout ),
+	.datad(!\dsr1|tmp[0][8]~15_combout ),
+	.datae(!\dsr1|tmp[0][12]~1_combout ),
+	.dataf(!\dsr1|tmp[0][10]~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][8]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][8]~16 .extended_lut = "off";
+defparam \dsr1|tmp[2][8]~16 .lut_mask = 64'h202570752A2F7A7F;
+defparam \dsr1|tmp[2][8]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N48
+cyclonev_lcell_comb \dsr1|c[0]~16 (
+// Equation(s):
+// \dsr1|c[0]~16_combout  = ( \dsr1|c[0]~14_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( !\dsr1|c[0]~15_combout  ) ) ) # ( !\dsr1|c[0]~14_combout  & ( \dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~15_combout  & (((!\DSR_e_diff[0]~0_combout  & 
+// \dsr1|tmp[0][2]~23_combout )))) # (\dsr1|c[0]~15_combout  & (\dsr1|tmp[0][4]~21_combout )) ) ) ) # ( !\dsr1|c[0]~14_combout  & ( !\dsr1|tmp[0][6]~19_combout  & ( (!\dsr1|c[0]~15_combout  & (((!\DSR_e_diff[0]~0_combout  & \dsr1|tmp[0][2]~23_combout )))) # 
+// (\dsr1|c[0]~15_combout  & (\dsr1|tmp[0][4]~21_combout )) ) ) )
+
+	.dataa(!\dsr1|tmp[0][4]~21_combout ),
+	.datab(!\dsr1|c[0]~15_combout ),
+	.datac(!\DSR_e_diff[0]~0_combout ),
+	.datad(!\dsr1|tmp[0][2]~23_combout ),
+	.datae(!\dsr1|c[0]~14_combout ),
+	.dataf(!\dsr1|tmp[0][6]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~16 .extended_lut = "off";
+defparam \dsr1|c[0]~16 .lut_mask = 64'h11D1000011D1CCCC;
+defparam \dsr1|c[0]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N42
+cyclonev_lcell_comb \dsr1|c[0]~17 (
+// Equation(s):
+// \dsr1|c[0]~17_combout  = ( \dsr1|c[0]~16_combout  & ( (!\dsr1|c[0]~0_combout ) # (\dsr1|tmp[2][8]~16_combout ) ) ) # ( !\dsr1|c[0]~16_combout  & ( (\dsr1|c[0]~0_combout  & \dsr1|tmp[2][8]~16_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][8]~16_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|c[0]~16_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|c[0]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|c[0]~17 .extended_lut = "off";
+defparam \dsr1|c[0]~17 .lut_mask = 64'h000F000FF0FFF0FF;
+defparam \dsr1|c[0]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N0
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~57 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~57_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[0]~17_combout )) ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o ) ) + ( !VCC ))
+// \uut_add_sub_N|a11|a1|Add0~58  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[0]~17_combout )) ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o ) ) + ( !VCC ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~17_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~57 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~57 .lut_mask = 64'h0000999900006969;
+defparam \uut_add_sub_N|a11|a1|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N3
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~61 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~61_sumout  = SUM(( GND ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[1]~18_combout )) ) + ( \uut_add_sub_N|a11|a1|Add0~58  ))
+// \uut_add_sub_N|a11|a1|Add0~62  = CARRY(( GND ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[1]~18_combout )) ) + ( \uut_add_sub_N|a11|a1|Add0~58  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr1|c[1]~18_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~62 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~61 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~61 .lut_mask = 64'h0000996600000000;
+defparam \uut_add_sub_N|a11|a1|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N6
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~53 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~53_sumout  = SUM(( GND ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[2]~22_combout )) ) + ( \uut_add_sub_N|a11|a1|Add0~62  ))
+// \uut_add_sub_N|a11|a1|Add0~54  = CARRY(( GND ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[2]~22_combout )) ) + ( \uut_add_sub_N|a11|a1|Add0~62  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr1|c[2]~22_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~62 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~53 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~53 .lut_mask = 64'h0000996600000000;
+defparam \uut_add_sub_N|a11|a1|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N9
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~49 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~49_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[3]~26_combout )) ) + ( \add_m_in1[3]~7_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~54  ))
+// \uut_add_sub_N|a11|a1|Add0~50  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (\dsr1|c[3]~26_combout )) ) + ( \add_m_in1[3]~7_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~54  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(gnd),
+	.datad(!\dsr1|c[3]~26_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[3]~7_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~49 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~49 .lut_mask = 64'h0000FF0000006699;
+defparam \uut_add_sub_N|a11|a1|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N12
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~45 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~45_sumout  = SUM(( \uut_add_sub_N|a11|a1|Add0~71_combout  ) + ( (!\LessThan0~17_combout  & (((\uut_de1|ls|c[3]~13_combout )))) # (\LessThan0~17_combout  & (!\uut_de2|ls|c[3]~11_combout  & (\uut_de2|ls|tmp[1][3]~4_combout ))) ) + 
+// ( \uut_add_sub_N|a11|a1|Add0~50  ))
+// \uut_add_sub_N|a11|a1|Add0~46  = CARRY(( \uut_add_sub_N|a11|a1|Add0~71_combout  ) + ( (!\LessThan0~17_combout  & (((\uut_de1|ls|c[3]~13_combout )))) # (\LessThan0~17_combout  & (!\uut_de2|ls|c[3]~11_combout  & (\uut_de2|ls|tmp[1][3]~4_combout ))) ) + ( 
+// \uut_add_sub_N|a11|a1|Add0~50  ))
+
+	.dataa(!\LessThan0~17_combout ),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(!\uut_de2|ls|tmp[1][3]~4_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~71_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|c[3]~13_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~45 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~45 .lut_mask = 64'h0000FB51000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N15
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~41 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~41_sumout  = SUM(( (!\LessThan0~17_combout  & (((\uut_de1|ls|c[4]~12_combout )))) # (\LessThan0~17_combout  & (!\uut_de2|ls|c[3]~11_combout  & (\uut_de2|ls|tmp[1][4]~5_combout ))) ) + ( \uut_add_sub_N|a11|a1|Add0~70_combout  ) + 
+// ( \uut_add_sub_N|a11|a1|Add0~46  ))
+// \uut_add_sub_N|a11|a1|Add0~42  = CARRY(( (!\LessThan0~17_combout  & (((\uut_de1|ls|c[4]~12_combout )))) # (\LessThan0~17_combout  & (!\uut_de2|ls|c[3]~11_combout  & (\uut_de2|ls|tmp[1][4]~5_combout ))) ) + ( \uut_add_sub_N|a11|a1|Add0~70_combout  ) + ( 
+// \uut_add_sub_N|a11|a1|Add0~46  ))
+
+	.dataa(!\LessThan0~17_combout ),
+	.datab(!\uut_de2|ls|c[3]~11_combout ),
+	.datac(!\uut_de2|ls|tmp[1][4]~5_combout ),
+	.datad(!\uut_de1|ls|c[4]~12_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~70_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~41 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~41 .lut_mask = 64'h0000FF00000004AE;
+defparam \uut_add_sub_N|a11|a1|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N18
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~37 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~37_sumout  = SUM(( \uut_add_sub_N|a11|a1|Add0~69_combout  ) + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((\uut_de1|ls|c[5]~11_combout ))) # (\LessThan0~0_combout  & (\uut_de2|ls|c[5]~12_combout )))) # 
+// (\LessThan0~18_combout  & (((\uut_de2|ls|c[5]~12_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~42  ))
+// \uut_add_sub_N|a11|a1|Add0~38  = CARRY(( \uut_add_sub_N|a11|a1|Add0~69_combout  ) + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((\uut_de1|ls|c[5]~11_combout ))) # (\LessThan0~0_combout  & (\uut_de2|ls|c[5]~12_combout )))) # 
+// (\LessThan0~18_combout  & (((\uut_de2|ls|c[5]~12_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~42  ))
+
+	.dataa(!\LessThan0~18_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\uut_de2|ls|c[5]~12_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~69_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|c[5]~11_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~37 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~37 .lut_mask = 64'h0000F870000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N21
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~33 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~33_sumout  = SUM(( \uut_add_sub_N|a11|a1|Add0~68_combout  ) + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((\uut_de1|ls|c[6]~10_combout ))) # (\LessThan0~0_combout  & (\uut_de2|ls|c[6]~10_combout )))) # 
+// (\LessThan0~18_combout  & (((\uut_de2|ls|c[6]~10_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~38  ))
+// \uut_add_sub_N|a11|a1|Add0~34  = CARRY(( \uut_add_sub_N|a11|a1|Add0~68_combout  ) + ( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((\uut_de1|ls|c[6]~10_combout ))) # (\LessThan0~0_combout  & (\uut_de2|ls|c[6]~10_combout )))) # 
+// (\LessThan0~18_combout  & (((\uut_de2|ls|c[6]~10_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~38  ))
+
+	.dataa(!\LessThan0~18_combout ),
+	.datab(!\LessThan0~0_combout ),
+	.datac(!\uut_de2|ls|c[6]~10_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~68_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|c[6]~10_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~33 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~33 .lut_mask = 64'h0000F870000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N51
+cyclonev_lcell_comb \l2|l1|out[2]~8 (
+// Equation(s):
+// \l2|l1|out[2]~8_combout  = ( !\uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~53_sumout  & (!\uut_add_sub_N|a11|a1|Add0~61_sumout  & !\uut_add_sub_N|a11|a1|Add0~49_sumout )) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[2]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[2]~8 .extended_lut = "off";
+defparam \l2|l1|out[2]~8 .lut_mask = 64'hA000A00000000000;
+defparam \l2|l1|out[2]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N9
+cyclonev_lcell_comb \l2|l1|out[2]~9 (
+// Equation(s):
+// \l2|l1|out[2]~9_combout  = ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~33_sumout  & (!\uut_add_sub_N|a11|a1|Add0~37_sumout  & (!\l2|l1|out[2]~8_combout  & !\uut_add_sub_N|a11|a1|Add0~45_sumout ))) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datac(!\l2|l1|out[2]~8_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[2]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[2]~9 .extended_lut = "off";
+defparam \l2|l1|out[2]~9 .lut_mask = 64'h8000800000000000;
+defparam \l2|l1|out[2]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N51
+cyclonev_lcell_comb \add_m_in1[13]~5 (
+// Equation(s):
+// \add_m_in1[13]~5_combout  = ( \uut_de2|ls|c[12]~5_combout  & ( (\LessThan0~17_combout ) # (\uut_de1|ls|c[12]~5_combout ) ) ) # ( !\uut_de2|ls|c[12]~5_combout  & ( (\uut_de1|ls|c[12]~5_combout  & !\LessThan0~17_combout ) ) )
+
+	.dataa(!\uut_de1|ls|c[12]~5_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[12]~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[13]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[13]~5 .extended_lut = "off";
+defparam \add_m_in1[13]~5 .lut_mask = 64'h4444444477777777;
+defparam \add_m_in1[13]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y5_N33
+cyclonev_lcell_comb \dsr1|tmp[2][13]~14 (
+// Equation(s):
+// \dsr1|tmp[2][13]~14_combout  = ( \dsr1|c[0]~2_combout  & ( (\dsr1|c[0]~1_combout  & \dsr1|tmp[0][13]~5_combout ) ) ) # ( !\dsr1|c[0]~2_combout  & ( (\dsr1|tmp[0][15]~4_combout  & \dsr1|c[0]~1_combout ) ) )
+
+	.dataa(!\dsr1|tmp[0][15]~4_combout ),
+	.datab(gnd),
+	.datac(!\dsr1|c[0]~1_combout ),
+	.datad(!\dsr1|tmp[0][13]~5_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|c[0]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][13]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][13]~14 .extended_lut = "off";
+defparam \dsr1|tmp[2][13]~14 .lut_mask = 64'h05050505000F000F;
+defparam \dsr1|tmp[2][13]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N51
+cyclonev_lcell_comb \dsr1|tmp[2][12]~2 (
+// Equation(s):
+// \dsr1|tmp[2][12]~2_combout  = (\dsr1|c[0]~1_combout  & ((!\dsr1|c[0]~2_combout  & (\dsr1|tmp[0][14]~0_combout )) # (\dsr1|c[0]~2_combout  & ((\dsr1|tmp[0][12]~1_combout )))))
+
+	.dataa(!\dsr1|c[0]~1_combout ),
+	.datab(!\dsr1|tmp[0][14]~0_combout ),
+	.datac(!\dsr1|tmp[0][12]~1_combout ),
+	.datad(!\dsr1|c[0]~2_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][12]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][12]~2 .extended_lut = "off";
+defparam \dsr1|tmp[2][12]~2 .lut_mask = 64'h1105110511051105;
+defparam \dsr1|tmp[2][12]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N18
+cyclonev_lcell_comb \add_m_in1[12]~0 (
+// Equation(s):
+// \add_m_in1[12]~0_combout  = (!\LessThan0~17_combout  & ((\uut_de1|ls|c[11]~3_combout ))) # (\LessThan0~17_combout  & (\uut_de2|ls|c[11]~3_combout ))
+
+	.dataa(gnd),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de2|ls|c[11]~3_combout ),
+	.datad(!\uut_de1|ls|c[11]~3_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[12]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[12]~0 .extended_lut = "off";
+defparam \add_m_in1[12]~0 .lut_mask = 64'h03CF03CF03CF03CF;
+defparam \add_m_in1[12]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N21
+cyclonev_lcell_comb \add_m_in1[11]~1 (
+// Equation(s):
+// \add_m_in1[11]~1_combout  = (!\LessThan0~17_combout  & ((\uut_de1|ls|c[10]~6_combout ))) # (\LessThan0~17_combout  & (\uut_de2|ls|c[10]~6_combout ))
+
+	.dataa(gnd),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de2|ls|c[10]~6_combout ),
+	.datad(!\uut_de1|ls|c[10]~6_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[11]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[11]~1 .extended_lut = "off";
+defparam \add_m_in1[11]~1 .lut_mask = 64'h03CF03CF03CF03CF;
+defparam \add_m_in1[11]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N48
+cyclonev_lcell_comb \add_m_in1[10]~2 (
+// Equation(s):
+// \add_m_in1[10]~2_combout  = ( \uut_de2|ls|c[9]~7_combout  & ( (\uut_de1|ls|c[9]~7_combout ) # (\LessThan0~17_combout ) ) ) # ( !\uut_de2|ls|c[9]~7_combout  & ( (!\LessThan0~17_combout  & \uut_de1|ls|c[9]~7_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de1|ls|c[9]~7_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[9]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[10]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[10]~2 .extended_lut = "off";
+defparam \add_m_in1[10]~2 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
+defparam \add_m_in1[10]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N36
+cyclonev_lcell_comb \add_m_in1[9]~3 (
+// Equation(s):
+// \add_m_in1[9]~3_combout  = ( \LessThan0~17_combout  & ( \uut_de2|ls|c[8]~8_combout  ) ) # ( !\LessThan0~17_combout  & ( \uut_de1|ls|c[8]~8_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_de1|ls|c[8]~8_combout ),
+	.datad(!\uut_de2|ls|c[8]~8_combout ),
+	.datae(gnd),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[9]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[9]~3 .extended_lut = "off";
+defparam \add_m_in1[9]~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
+defparam \add_m_in1[9]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y5_N27
+cyclonev_lcell_comb \add_m_in1[8]~6 (
+// Equation(s):
+// \add_m_in1[8]~6_combout  = ( \uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( \uut_de2|ls|c[7]~9_combout  ) ) ) # ( !\uut_de1|ls|c[7]~9_combout  & ( \LessThan0~17_combout  & ( \uut_de2|ls|c[7]~9_combout  ) ) ) # ( \uut_de1|ls|c[7]~9_combout  & ( 
+// !\LessThan0~17_combout  ) )
+
+	.dataa(!\uut_de2|ls|c[7]~9_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\uut_de1|ls|c[7]~9_combout ),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[8]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[8]~6 .extended_lut = "off";
+defparam \add_m_in1[8]~6 .lut_mask = 64'h0000FFFF55555555;
+defparam \add_m_in1[8]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N24
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~29 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~29_sumout  = SUM(( \add_m_in1[8]~6_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][8]~16_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~34  ))
+// \uut_add_sub_N|a11|a1|Add0~30  = CARRY(( \add_m_in1[8]~6_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][8]~16_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~34  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\add_m_in1[8]~6_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[2][8]~16_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~29 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~29 .lut_mask = 64'h00009969000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N27
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~17 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~17_sumout  = SUM(( \add_m_in1[9]~3_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][9]~12_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~30  ))
+// \uut_add_sub_N|a11|a1|Add0~18  = CARRY(( \add_m_in1[9]~3_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][9]~12_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~30  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\add_m_in1[9]~3_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[2][9]~12_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~17 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~17 .lut_mask = 64'h00009969000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N30
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~13 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~13_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][10]~10_combout )))) ) + ( \add_m_in1[10]~2_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~18  ))
+// \uut_add_sub_N|a11|a1|Add0~14  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][10]~10_combout )))) ) + ( \add_m_in1[10]~2_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~18  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][10]~10_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[10]~2_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~13 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~13 .lut_mask = 64'h0000FF0000006696;
+defparam \uut_add_sub_N|a11|a1|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N33
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~9 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~9_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][11]~8_combout )))) ) + ( \add_m_in1[11]~1_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~14  ))
+// \uut_add_sub_N|a11|a1|Add0~10  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][11]~8_combout )))) ) + ( \add_m_in1[11]~1_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~14  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][11]~8_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[11]~1_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~9 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~9 .lut_mask = 64'h0000FF0000006696;
+defparam \uut_add_sub_N|a11|a1|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N36
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~5 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~5_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][12]~2_combout )))) ) + ( \add_m_in1[12]~0_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~10  ))
+// \uut_add_sub_N|a11|a1|Add0~6  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][12]~2_combout )))) ) + ( \add_m_in1[12]~0_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~10  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][12]~2_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[12]~0_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~5 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~5 .lut_mask = 64'h0000FF0000006696;
+defparam \uut_add_sub_N|a11|a1|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N39
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~25 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~25_sumout  = SUM(( \add_m_in1[13]~5_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][13]~14_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~6  ))
+// \uut_add_sub_N|a11|a1|Add0~26  = CARRY(( \add_m_in1[13]~5_combout  ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][13]~14_combout )))) ) + ( \uut_add_sub_N|a11|a1|Add0~6  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\add_m_in1[13]~5_combout ),
+	.datae(gnd),
+	.dataf(!\dsr1|tmp[2][13]~14_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~25 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~25 .lut_mask = 64'h00009969000000FF;
+defparam \uut_add_sub_N|a11|a1|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N12
+cyclonev_lcell_comb \l2|l1|h|h|l|WideOr0 (
+// Equation(s):
+// \l2|l1|h|h|l|WideOr0~combout  = (\uut_add_sub_N|a11|a1|Add0~5_sumout ) # (\uut_add_sub_N|a11|a1|Add0~25_sumout )
+
+	.dataa(gnd),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datac(gnd),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|h|h|l|WideOr0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|h|h|l|WideOr0 .extended_lut = "off";
+defparam \l2|l1|h|h|l|WideOr0 .lut_mask = 64'h33FF33FF33FF33FF;
+defparam \l2|l1|h|h|l|WideOr0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N57
+cyclonev_lcell_comb \add_m_in1[15]~8 (
+// Equation(s):
+// \add_m_in1[15]~8_combout  = ( \LessThan0~17_combout  & ( !\WideOr1~combout  ) ) # ( !\LessThan0~17_combout  & ( !\WideOr0~combout  ) )
+
+	.dataa(!\WideOr0~combout ),
+	.datab(!\WideOr1~combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\LessThan0~17_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[15]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[15]~8 .extended_lut = "off";
+defparam \add_m_in1[15]~8 .lut_mask = 64'hAAAAAAAACCCCCCCC;
+defparam \add_m_in1[15]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y4_N48
+cyclonev_lcell_comb \dsr1|tmp[2][14]~13 (
+// Equation(s):
+// \dsr1|tmp[2][14]~13_combout  = ( !\uut_ediff|s1|Add0~25_sumout  & ( (\dsr1|c[0]~1_combout  & \dsr1|tmp[0][14]~0_combout ) ) )
+
+	.dataa(!\dsr1|c[0]~1_combout ),
+	.datab(!\dsr1|tmp[0][14]~0_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_ediff|s1|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr1|tmp[2][14]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr1|tmp[2][14]~13 .extended_lut = "off";
+defparam \dsr1|tmp[2][14]~13 .lut_mask = 64'h1111111100000000;
+defparam \dsr1|tmp[2][14]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y5_N6
+cyclonev_lcell_comb \add_m_in1[14]~4 (
+// Equation(s):
+// \add_m_in1[14]~4_combout  = ( \LessThan0~17_combout  & ( \uut_de2|ls|c[13]~2_combout  ) ) # ( !\LessThan0~17_combout  & ( \uut_de1|ls|c[13]~2_combout  ) )
+
+	.dataa(!\uut_de2|ls|c[13]~2_combout ),
+	.datab(gnd),
+	.datac(!\uut_de1|ls|c[13]~2_combout ),
+	.datad(gnd),
+	.datae(!\LessThan0~17_combout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\add_m_in1[14]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \add_m_in1[14]~4 .extended_lut = "off";
+defparam \add_m_in1[14]~4 .lut_mask = 64'h0F0F55550F0F5555;
+defparam \add_m_in1[14]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N42
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~21 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~21_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][14]~13_combout )))) ) + ( \add_m_in1[14]~4_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~26  ))
+// \uut_add_sub_N|a11|a1|Add0~22  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][14]~13_combout )))) ) + ( \add_m_in1[14]~4_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~26  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][14]~13_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[14]~4_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~21 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~21 .lut_mask = 64'h0000FF0000006696;
+defparam \uut_add_sub_N|a11|a1|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N45
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~65 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~65_sumout  = SUM(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][15]~18_combout )))) ) + ( \add_m_in1[15]~8_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~22  ))
+// \uut_add_sub_N|a11|a1|Add0~66  = CARRY(( !\in2[15]~input_o  $ (!\in1[15]~input_o  $ (((!\dsr1|c[0]~0_combout  & \dsr1|tmp[2][15]~18_combout )))) ) + ( \add_m_in1[15]~8_combout  ) + ( \uut_add_sub_N|a11|a1|Add0~22  ))
+
+	.dataa(!\in2[15]~input_o ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\dsr1|c[0]~0_combout ),
+	.datad(!\dsr1|tmp[2][15]~18_combout ),
+	.datae(gnd),
+	.dataf(!\add_m_in1[15]~8_combout ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.cout(\uut_add_sub_N|a11|a1|Add0~66 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~65 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~65 .lut_mask = 64'h0000FF0000006696;
+defparam \uut_add_sub_N|a11|a1|Add0~65 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y5_N48
+cyclonev_lcell_comb \uut_add_sub_N|a11|a1|Add0~1 (
+// Equation(s):
+// \uut_add_sub_N|a11|a1|Add0~1_sumout  = SUM(( GND ) + ( !\in2[15]~input_o  $ (!\in1[15]~input_o ) ) + ( \uut_add_sub_N|a11|a1|Add0~66  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\in2[15]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in1[15]~input_o ),
+	.datag(gnd),
+	.cin(\uut_add_sub_N|a11|a1|Add0~66 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_sub_N|a11|a1|Add0~1 .extended_lut = "off";
+defparam \uut_add_sub_N|a11|a1|Add0~1 .lut_mask = 64'h0000F00F00000000;
+defparam \uut_add_sub_N|a11|a1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N12
+cyclonev_lcell_comb \l2|l1|h|l|h|WideOr0~0 (
+// Equation(s):
+// \l2|l1|h|l|h|WideOr0~0_combout  = ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & (!\uut_add_sub_N|a11|a1|Add0~9_sumout  & !\uut_add_sub_N|a11|a1|Add0~17_sumout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|h|l|h|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|h|l|h|WideOr0~0 .extended_lut = "off";
+defparam \l2|l1|h|l|h|WideOr0~0 .lut_mask = 64'hC000C00000000000;
+defparam \l2|l1|h|l|h|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N54
+cyclonev_lcell_comb \l2|l1|out[2]~10 (
+// Equation(s):
+// \l2|l1|out[2]~10_combout  = ( !\uut_add_sub_N|a11|a1|Add0~65_sumout  & ( \l2|l1|h|l|h|WideOr0~0_combout  & ( (\l2|l1|out[2]~9_combout  & (!\l2|l1|h|h|l|WideOr0~combout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & !\uut_add_sub_N|a11|a1|Add0~21_sumout ))) ) 
+// ) ) # ( !\uut_add_sub_N|a11|a1|Add0~65_sumout  & ( !\l2|l1|h|l|h|WideOr0~0_combout  & ( (!\l2|l1|h|h|l|WideOr0~combout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & !\uut_add_sub_N|a11|a1|Add0~21_sumout )) ) ) )
+
+	.dataa(!\l2|l1|out[2]~9_combout ),
+	.datab(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.dataf(!\l2|l1|h|l|h|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[2]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[2]~10 .extended_lut = "off";
+defparam \l2|l1|out[2]~10 .lut_mask = 64'hC000000040000000;
+defparam \l2|l1|out[2]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N15
+cyclonev_lcell_comb \l2|l1|out[1]~6 (
+// Equation(s):
+// \l2|l1|out[1]~6_combout  = (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & !\uut_add_sub_N|a11|a1|Add0~9_sumout )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~6 .extended_lut = "off";
+defparam \l2|l1|out[1]~6 .lut_mask = 64'hA0A0A0A0A0A0A0A0;
+defparam \l2|l1|out[1]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N36
+cyclonev_lcell_comb \l2|l1|out[1]~4 (
+// Equation(s):
+// \l2|l1|out[1]~4_combout  = ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( \uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~41_sumout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ) # (\uut_add_sub_N|a11|a1|Add0~49_sumout ))) ) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~41_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~61_sumout ) # (\uut_add_sub_N|a11|a1|Add0~53_sumout )) # (\uut_add_sub_N|a11|a1|Add0~49_sumout 
+// ))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~4 .extended_lut = "off";
+defparam \l2|l1|out[1]~4 .lut_mask = 64'hF070000070700000;
+defparam \l2|l1|out[1]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N6
+cyclonev_lcell_comb \l2|l1|out[1]~5 (
+// Equation(s):
+// \l2|l1|out[1]~5_combout  = ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & (((\l2|l1|out[1]~4_combout ) # (\uut_add_sub_N|a11|a1|Add0~37_sumout )) # (\uut_add_sub_N|a11|a1|Add0~33_sumout ))) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datac(!\l2|l1|out[1]~4_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~5 .extended_lut = "off";
+defparam \l2|l1|out[1]~5 .lut_mask = 64'h7F007F0000000000;
+defparam \l2|l1|out[1]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N18
+cyclonev_lcell_comb \l2|l1|out[1]~7 (
+// Equation(s):
+// \l2|l1|out[1]~7_combout  = ( \l2|l1|out[1]~5_combout  & ( !\uut_add_sub_N|a11|a1|Add0~21_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~65_sumout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & \l2|l1|h|h|l|WideOr0~combout )) ) ) ) # ( !\l2|l1|out[1]~5_combout  & ( 
+// !\uut_add_sub_N|a11|a1|Add0~21_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~65_sumout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & ((\l2|l1|h|h|l|WideOr0~combout ) # (\l2|l1|out[1]~6_combout )))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.datab(!\l2|l1|out[1]~6_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datae(!\l2|l1|out[1]~5_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~7 .extended_lut = "off";
+defparam \l2|l1|out[1]~7 .lut_mask = 64'h20A000A000000000;
+defparam \l2|l1|out[1]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N0
+cyclonev_lcell_comb \l2|l1|out[0]~2 (
+// Equation(s):
+// \l2|l1|out[0]~2_combout  = (!\uut_add_sub_N|a11|a1|Add0~65_sumout  & !\uut_add_sub_N|a11|a1|Add0~1_sumout )
+
+	.dataa(gnd),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~2 .extended_lut = "off";
+defparam \l2|l1|out[0]~2 .lut_mask = 64'hC0C0C0C0C0C0C0C0;
+defparam \l2|l1|out[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N30
+cyclonev_lcell_comb \l2|l1|out[0]~0 (
+// Equation(s):
+// \l2|l1|out[0]~0_combout  = ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( \uut_add_sub_N|a11|a1|Add0~57_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( \uut_add_sub_N|a11|a1|Add0~57_sumout  & ( 
+// (!\uut_add_sub_N|a11|a1|Add0~49_sumout  & (!\uut_add_sub_N|a11|a1|Add0~41_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~61_sumout ) # (\uut_add_sub_N|a11|a1|Add0~53_sumout )))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( 
+// !\uut_add_sub_N|a11|a1|Add0~57_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~49_sumout  & 
+// (\uut_add_sub_N|a11|a1|Add0~53_sumout  & !\uut_add_sub_N|a11|a1|Add0~41_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~0 .extended_lut = "off";
+defparam \l2|l1|out[0]~0 .lut_mask = 64'h2020F0F0A020F0F0;
+defparam \l2|l1|out[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N30
+cyclonev_lcell_comb \l2|l1|out[0]~1 (
+// Equation(s):
+// \l2|l1|out[0]~1_combout  = ( !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( \uut_add_sub_N|a11|a1|Add0~37_sumout  & ( ((!\uut_add_sub_N|a11|a1|Add0~29_sumout  & \uut_add_sub_N|a11|a1|Add0~33_sumout )) # (\uut_add_sub_N|a11|a1|Add0~17_sumout ) ) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  & ( ((!\uut_add_sub_N|a11|a1|Add0~29_sumout  & ((!\l2|l1|out[0]~0_combout ) # (\uut_add_sub_N|a11|a1|Add0~33_sumout )))) # (\uut_add_sub_N|a11|a1|Add0~17_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datab(!\l2|l1|out[0]~0_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~1 .extended_lut = "off";
+defparam \l2|l1|out[0]~1 .lut_mask = 64'hD5F5000055F50000;
+defparam \l2|l1|out[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N6
+cyclonev_lcell_comb \l2|l1|out[0]~3 (
+// Equation(s):
+// \l2|l1|out[0]~3_combout  = ( \l2|l1|out[0]~2_combout  & ( \l2|l1|out[0]~1_combout  & ( ((!\uut_add_sub_N|a11|a1|Add0~25_sumout  & \uut_add_sub_N|a11|a1|Add0~5_sumout )) # (\uut_add_sub_N|a11|a1|Add0~21_sumout ) ) ) ) # ( \l2|l1|out[0]~2_combout  & ( 
+// !\l2|l1|out[0]~1_combout  & ( ((!\uut_add_sub_N|a11|a1|Add0~25_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~9_sumout ) # (\uut_add_sub_N|a11|a1|Add0~5_sumout )))) # (\uut_add_sub_N|a11|a1|Add0~21_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datae(!\l2|l1|out[0]~2_combout ),
+	.dataf(!\l2|l1|out[0]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~3 .extended_lut = "off";
+defparam \l2|l1|out[0]~3 .lut_mask = 64'h00008FCF00000FCF;
+defparam \l2|l1|out[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N36
+cyclonev_lcell_comb \dsl1|tmp[1][7]~1 (
+// Equation(s):
+// \dsl1|tmp[1][7]~1_combout  = ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( \l2|l1|out[0]~3_combout  & ( (\uut_add_sub_N|a11|a1|Add0~33_sumout ) # (\l2|l1|out[1]~7_combout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( \l2|l1|out[0]~3_combout  & ( 
+// (!\l2|l1|out[1]~7_combout  & \uut_add_sub_N|a11|a1|Add0~33_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~29_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~37_sumout )) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~29_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~37_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.dataf(!\l2|l1|out[0]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][7]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][7]~1 .extended_lut = "off";
+defparam \dsl1|tmp[1][7]~1 .lut_mask = 64'h11DD11DD0C0C3F3F;
+defparam \dsl1|tmp[1][7]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N42
+cyclonev_lcell_comb \dsl1|tmp[1][3]~2 (
+// Equation(s):
+// \dsl1|tmp[1][3]~2_combout  = ( \uut_add_sub_N|a11|a1|Add0~61_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( ((!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout 
+// )))) # (\l2|l1|out[0]~3_combout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~61_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & ((!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout 
+//  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))))) # (\l2|l1|out[0]~3_combout  & (!\l2|l1|out[1]~7_combout )) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~61_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & 
+// ((!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))))) # (\l2|l1|out[0]~3_combout  & (\l2|l1|out[1]~7_combout )) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~61_sumout  & 
+// ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & ((!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))))) ) ) )
+
+	.dataa(!\l2|l1|out[0]~3_combout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][3]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][3]~2 .extended_lut = "off";
+defparam \dsl1|tmp[1][3]~2 .lut_mask = 64'h082A193B4C6E5D7F;
+defparam \dsl1|tmp[1][3]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N18
+cyclonev_lcell_comb \l2|l1|out[3]~11 (
+// Equation(s):
+// \l2|l1|out[3]~11_combout  = ( !\uut_add_sub_N|a11|a1|Add0~33_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~41_sumout  & (!\uut_add_sub_N|a11|a1|Add0~37_sumout  & (\l2|l1|out[2]~8_combout  & !\uut_add_sub_N|a11|a1|Add0~45_sumout ))) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datac(!\l2|l1|out[2]~8_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[3]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[3]~11 .extended_lut = "off";
+defparam \l2|l1|out[3]~11 .lut_mask = 64'h0800080000000000;
+defparam \l2|l1|out[3]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N30
+cyclonev_lcell_comb \l2|l1|out[3]~12 (
+// Equation(s):
+// \l2|l1|out[3]~12_combout  = ( !\uut_add_sub_N|a11|a1|Add0~65_sumout  & ( \l2|l1|h|l|h|WideOr0~0_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (!\l2|l1|h|h|l|WideOr0~combout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & !\l2|l1|out[3]~11_combout ))) 
+// ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datab(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(!\l2|l1|out[3]~11_combout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.dataf(!\l2|l1|h|l|h|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[3]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[3]~12 .extended_lut = "off";
+defparam \l2|l1|out[3]~12 .lut_mask = 64'h0000000080000000;
+defparam \l2|l1|out[3]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N30
+cyclonev_lcell_comb \dsl1|tmp[1][11]~0 (
+// Equation(s):
+// \dsl1|tmp[1][11]~0_combout  = ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((!\l2|l1|out[1]~7_combout ) # (\uut_add_sub_N|a11|a1|Add0~13_sumout )))) # (\l2|l1|out[0]~3_combout  & 
+// (((\l2|l1|out[1]~7_combout )) # (\uut_add_sub_N|a11|a1|Add0~9_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\uut_add_sub_N|a11|a1|Add0~13_sumout  & 
+// \l2|l1|out[1]~7_combout )))) # (\l2|l1|out[0]~3_combout  & (((\l2|l1|out[1]~7_combout )) # (\uut_add_sub_N|a11|a1|Add0~9_sumout ))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout  & 
+// (((!\l2|l1|out[1]~7_combout ) # (\uut_add_sub_N|a11|a1|Add0~13_sumout )))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~9_sumout  & ((!\l2|l1|out[1]~7_combout )))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( 
+// !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\uut_add_sub_N|a11|a1|Add0~13_sumout  & \l2|l1|out[1]~7_combout )))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~9_sumout  & ((!\l2|l1|out[1]~7_combout )))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datad(!\l2|l1|out[1]~7_combout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][11]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][11]~0 .extended_lut = "off";
+defparam \dsl1|tmp[1][11]~0 .lut_mask = 64'h110CDD0C113FDD3F;
+defparam \dsl1|tmp[1][11]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N0
+cyclonev_lcell_comb \dsl1|c[15]~0 (
+// Equation(s):
+// \dsl1|c[15]~0_combout  = ( \dsl1|tmp[1][11]~0_combout  & ( \uut_add_sub_N|a11|a1|Add0~1_sumout  & ( (!\l2|l1|out[3]~12_combout ) # ((!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][7]~1_combout )) # (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][3]~2_combout )))) 
+// ) ) ) # ( !\dsl1|tmp[1][11]~0_combout  & ( \uut_add_sub_N|a11|a1|Add0~1_sumout  & ( (!\l2|l1|out[2]~10_combout  & (((!\l2|l1|out[3]~12_combout )) # (\dsl1|tmp[1][7]~1_combout ))) # (\l2|l1|out[2]~10_combout  & (((\dsl1|tmp[1][3]~2_combout  & 
+// \l2|l1|out[3]~12_combout )))) ) ) ) # ( \dsl1|tmp[1][11]~0_combout  & ( !\uut_add_sub_N|a11|a1|Add0~1_sumout  & ( (!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][7]~1_combout  & ((\l2|l1|out[3]~12_combout )))) # (\l2|l1|out[2]~10_combout  & 
+// (((!\l2|l1|out[3]~12_combout ) # (\dsl1|tmp[1][3]~2_combout )))) ) ) ) # ( !\dsl1|tmp[1][11]~0_combout  & ( !\uut_add_sub_N|a11|a1|Add0~1_sumout  & ( (\l2|l1|out[3]~12_combout  & ((!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][7]~1_combout )) # 
+// (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][3]~2_combout ))))) ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][7]~1_combout ),
+	.datac(!\dsl1|tmp[1][3]~2_combout ),
+	.datad(!\l2|l1|out[3]~12_combout ),
+	.datae(!\dsl1|tmp[1][11]~0_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[15]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[15]~0 .extended_lut = "off";
+defparam \dsl1|c[15]~0 .lut_mask = 64'h00275527AA27FF27;
+defparam \dsl1|c[15]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N54
+cyclonev_lcell_comb \dsl1|tmp[1][6]~4 (
+// Equation(s):
+// \dsl1|tmp[1][6]~4_combout  = ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( ((!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~33_sumout ))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~37_sumout 
+// ))) # (\l2|l1|out[1]~7_combout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\uut_add_sub_N|a11|a1|Add0~33_sumout  & !\l2|l1|out[1]~7_combout )))) # 
+// (\l2|l1|out[0]~3_combout  & (((\l2|l1|out[1]~7_combout )) # (\uut_add_sub_N|a11|a1|Add0~37_sumout ))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\l2|l1|out[1]~7_combout ) 
+// # (\uut_add_sub_N|a11|a1|Add0~33_sumout )))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~37_sumout  & ((!\l2|l1|out[1]~7_combout )))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( 
+// (!\l2|l1|out[1]~7_combout  & ((!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~33_sumout ))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~37_sumout )))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datad(!\l2|l1|out[1]~7_combout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][6]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][6]~4 .extended_lut = "off";
+defparam \dsl1|tmp[1][6]~4 .lut_mask = 64'h1D001DCC1D331DFF;
+defparam \dsl1|tmp[1][6]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N48
+cyclonev_lcell_comb \l2|l1|out[0]~13 (
+// Equation(s):
+// \l2|l1|out[0]~13_combout  = ( \uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~45_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~53_sumout  & \uut_add_sub_N|a11|a1|Add0~61_sumout )) # (\uut_add_sub_N|a11|a1|Add0~49_sumout ))) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~57_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~45_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~53_sumout ) # (\uut_add_sub_N|a11|a1|Add0~49_sumout ))) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~13 .extended_lut = "off";
+defparam \l2|l1|out[0]~13 .lut_mask = 64'hA0F0A0F020F020F0;
+defparam \l2|l1|out[0]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N24
+cyclonev_lcell_comb \l2|l1|out[0]~14 (
+// Equation(s):
+// \l2|l1|out[0]~14_combout  = ( \l2|l1|out[0]~13_combout  & ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~33_sumout  & \uut_add_sub_N|a11|a1|Add0~37_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) ) ) # ( !\l2|l1|out[0]~13_combout  & ( \uut_add_sub_N|a11|a1|Add0~41_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~33_sumout  & \uut_add_sub_N|a11|a1|Add0~37_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) ) ) # ( \l2|l1|out[0]~13_combout  & ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~33_sumout  & \uut_add_sub_N|a11|a1|Add0~37_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) ) ) # ( !\l2|l1|out[0]~13_combout  & ( !\uut_add_sub_N|a11|a1|Add0~41_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~33_sumout ) # (\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) 
+// ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(!\l2|l1|out[0]~13_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~14 .extended_lut = "off";
+defparam \l2|l1|out[0]~14 .lut_mask = 64'hA0F020F020F020F0;
+defparam \l2|l1|out[0]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N36
+cyclonev_lcell_comb \l2|l1|out[0]~15 (
+// Equation(s):
+// \l2|l1|out[0]~15_combout  = ( \uut_add_sub_N|a11|a1|Add0~13_sumout  & ( \l2|l1|out[0]~14_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (((\uut_add_sub_N|a11|a1|Add0~9_sumout  & !\uut_add_sub_N|a11|a1|Add0~5_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( \l2|l1|out[0]~14_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (((\uut_add_sub_N|a11|a1|Add0~9_sumout  & !\uut_add_sub_N|a11|a1|Add0~5_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout ))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~13_sumout  & ( !\l2|l1|out[0]~14_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (((\uut_add_sub_N|a11|a1|Add0~9_sumout  & !\uut_add_sub_N|a11|a1|Add0~5_sumout )) # 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( !\l2|l1|out[0]~14_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~5_sumout ) # (\uut_add_sub_N|a11|a1|Add0~25_sumout ))) ) 
+// ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.dataf(!\l2|l1|out[0]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~15 .extended_lut = "off";
+defparam \l2|l1|out[0]~15 .lut_mask = 64'hF030703070307030;
+defparam \l2|l1|out[0]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N54
+cyclonev_lcell_comb \dsl1|tmp[1][2]~5 (
+// Equation(s):
+// \dsl1|tmp[1][2]~5_combout  = ( \uut_add_sub_N|a11|a1|Add0~61_sumout  & ( \l2|l1|out[1]~7_combout  & ( (!\l2|l1|out[0]~2_combout ) # (\l2|l1|out[0]~15_combout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~61_sumout  & ( !\l2|l1|out[1]~7_combout  & ( 
+// (!\l2|l1|out[0]~15_combout  & ((!\l2|l1|out[0]~2_combout  & (\uut_add_sub_N|a11|a1|Add0~49_sumout )) # (\l2|l1|out[0]~2_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))))) # (\l2|l1|out[0]~15_combout  & (\uut_add_sub_N|a11|a1|Add0~49_sumout )) ) ) ) # 
+// ( !\uut_add_sub_N|a11|a1|Add0~61_sumout  & ( !\l2|l1|out[1]~7_combout  & ( (!\l2|l1|out[0]~15_combout  & ((!\l2|l1|out[0]~2_combout  & (\uut_add_sub_N|a11|a1|Add0~49_sumout )) # (\l2|l1|out[0]~2_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))))) # 
+// (\l2|l1|out[0]~15_combout  & (\uut_add_sub_N|a11|a1|Add0~49_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datab(!\l2|l1|out[0]~15_combout ),
+	.datac(!\l2|l1|out[0]~2_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.dataf(!\l2|l1|out[1]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][2]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][2]~5 .extended_lut = "off";
+defparam \dsl1|tmp[1][2]~5 .lut_mask = 64'h515D515D0000F3F3;
+defparam \dsl1|tmp[1][2]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N12
+cyclonev_lcell_comb \dsl1|c[14]~1 (
+// Equation(s):
+// \dsl1|c[14]~1_combout  = ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( \l2|l1|out[0]~3_combout  & ( (\uut_add_sub_N|a11|a1|Add0~21_sumout ) # (\l2|l1|out[1]~7_combout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( \l2|l1|out[0]~3_combout  & ( 
+// (!\l2|l1|out[1]~7_combout  & \uut_add_sub_N|a11|a1|Add0~21_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~65_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout )) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~65_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.dataf(!\l2|l1|out[0]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[14]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[14]~1 .extended_lut = "off";
+defparam \dsl1|c[14]~1 .lut_mask = 64'h1D1D1D1D00CC33FF;
+defparam \dsl1|c[14]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N18
+cyclonev_lcell_comb \dsl1|tmp[1][10]~3 (
+// Equation(s):
+// \dsl1|tmp[1][10]~3_combout  = ( \l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout ) # (\uut_add_sub_N|a11|a1|Add0~29_sumout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( 
+// (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~9_sumout ))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~13_sumout )) ) ) ) # ( \l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (\l2|l1|out[0]~3_combout  & 
+// \uut_add_sub_N|a11|a1|Add0~29_sumout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~9_sumout ))) # (\l2|l1|out[0]~3_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~13_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(!\l2|l1|out[1]~7_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][10]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][10]~3 .extended_lut = "off";
+defparam \dsl1|tmp[1][10]~3 .lut_mask = 64'h1D1D00331D1DCCFF;
+defparam \dsl1|tmp[1][10]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N6
+cyclonev_lcell_comb \dsl1|c[14]~2 (
+// Equation(s):
+// \dsl1|c[14]~2_combout  = ( \dsl1|tmp[1][10]~3_combout  & ( \l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout ) # (\dsl1|tmp[1][2]~5_combout ) ) ) ) # ( !\dsl1|tmp[1][10]~3_combout  & ( \l2|l1|out[2]~10_combout  & ( (\dsl1|tmp[1][2]~5_combout  & 
+// \l2|l1|out[3]~12_combout ) ) ) ) # ( \dsl1|tmp[1][10]~3_combout  & ( !\l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout  & ((\dsl1|c[14]~1_combout ))) # (\l2|l1|out[3]~12_combout  & (\dsl1|tmp[1][6]~4_combout )) ) ) ) # ( 
+// !\dsl1|tmp[1][10]~3_combout  & ( !\l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout  & ((\dsl1|c[14]~1_combout ))) # (\l2|l1|out[3]~12_combout  & (\dsl1|tmp[1][6]~4_combout )) ) ) )
+
+	.dataa(!\dsl1|tmp[1][6]~4_combout ),
+	.datab(!\dsl1|tmp[1][2]~5_combout ),
+	.datac(!\dsl1|c[14]~1_combout ),
+	.datad(!\l2|l1|out[3]~12_combout ),
+	.datae(!\dsl1|tmp[1][10]~3_combout ),
+	.dataf(!\l2|l1|out[2]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[14]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[14]~2 .extended_lut = "off";
+defparam \dsl1|c[14]~2 .lut_mask = 64'h0F550F550033FF33;
+defparam \dsl1|c[14]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y5_N33
+cyclonev_lcell_comb \inf~0 (
+// Equation(s):
+// \inf~0_combout  = ( \in2[15]~input_o  & ( ((\WideOr0~combout  & \in1[15]~input_o )) # (\WideOr1~combout ) ) ) # ( !\in2[15]~input_o  & ( (\WideOr0~combout  & \in1[15]~input_o ) ) )
+
+	.dataa(!\WideOr0~combout ),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\WideOr1~combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in2[15]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\inf~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \inf~0 .extended_lut = "off";
+defparam \inf~0 .lut_mask = 64'h111111111F1F1F1F;
+defparam \inf~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N0
+cyclonev_lcell_comb \out~0 (
+// Equation(s):
+// \out~0_combout  = ( !\inf~0_combout  & ( (\zero~0_combout  & ((\dsl1|c[14]~2_combout ) # (\dsl1|c[15]~0_combout ))) ) )
+
+	.dataa(!\zero~0_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\dsl1|c[14]~2_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\inf~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~0 .extended_lut = "off";
+defparam \out~0 .lut_mask = 64'h1515151500000000;
+defparam \out~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N30
+cyclonev_lcell_comb \ls~0 (
+// Equation(s):
+// \ls~0_combout  = ( \in2[15]~input_o  & ( (\LessThan0~17_combout ) # (\in1[15]~input_o ) ) ) # ( !\in2[15]~input_o  & ( (\in1[15]~input_o  & !\LessThan0~17_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\in1[15]~input_o ),
+	.datac(!\LessThan0~17_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\in2[15]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ls~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ls~0 .extended_lut = "off";
+defparam \ls~0 .lut_mask = 64'h303030303F3F3F3F;
+defparam \ls~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N48
+cyclonev_lcell_comb \uut_add_mantovf|Add0~28 (
+// Equation(s):
+// \uut_add_mantovf|Add0~28_combout  = ( \uut_de1|ls|c[14]~18_combout  & ( (!\LessThan0~17_combout  & (((\uut_de1|ls|c[15]~16_combout )))) # (\LessThan0~17_combout  & (\uut_de2|ls|c[15]~17_combout  & (\uut_de2|ls|c[14]~19_combout ))) ) ) # ( 
+// !\uut_de1|ls|c[14]~18_combout  & ( (\uut_de2|ls|c[15]~17_combout  & (\LessThan0~17_combout  & \uut_de2|ls|c[14]~19_combout )) ) )
+
+	.dataa(!\uut_de2|ls|c[15]~17_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de2|ls|c[14]~19_combout ),
+	.datad(!\uut_de1|ls|c[15]~16_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de1|ls|c[14]~18_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_mantovf|Add0~28_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~28 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~28 .lut_mask = 64'h0101010101CD01CD;
+defparam \uut_add_mantovf|Add0~28 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N57
+cyclonev_lcell_comb \uut_add_mantovf|Add0~29 (
+// Equation(s):
+// \uut_add_mantovf|Add0~29_combout  = (\uut_add_mantovf|Add0~28_combout  & \uut_abs_regime1|regime_N[0]~1_combout )
+
+	.dataa(!\uut_add_mantovf|Add0~28_combout ),
+	.datab(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_mantovf|Add0~29_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~29 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~29 .lut_mask = 64'h1111111111111111;
+defparam \uut_add_mantovf|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N21
+cyclonev_lcell_comb \l2|l1|l|h|vld (
+// Equation(s):
+// \l2|l1|l|h|vld~combout  = ( !\uut_add_sub_N|a11|a1|Add0~33_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~41_sumout  & (!\uut_add_sub_N|a11|a1|Add0~37_sumout  & !\uut_add_sub_N|a11|a1|Add0~45_sumout )) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|l|h|vld~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|l|h|vld .extended_lut = "off";
+defparam \l2|l1|l|h|vld .lut_mask = 64'hA000A00000000000;
+defparam \l2|l1|l|h|vld .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N54
+cyclonev_lcell_comb \l2|l1|out[2]~26 (
+// Equation(s):
+// \l2|l1|out[2]~26_combout  = ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \l2|l1|out[2]~8_combout  ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \l2|l1|out[2]~8_combout  & ( ((\uut_add_sub_N|a11|a1|Add0~9_sumout ) # 
+// (\uut_add_sub_N|a11|a1|Add0~13_sumout )) # (\uut_add_sub_N|a11|a1|Add0~29_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\l2|l1|out[2]~8_combout  ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\l2|l1|out[2]~8_combout  & ( 
+// (((\uut_add_sub_N|a11|a1|Add0~9_sumout ) # (\l2|l1|l|h|vld~combout )) # (\uut_add_sub_N|a11|a1|Add0~13_sumout )) # (\uut_add_sub_N|a11|a1|Add0~29_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datac(!\l2|l1|l|h|vld~combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.dataf(!\l2|l1|out[2]~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[2]~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[2]~26 .extended_lut = "off";
+defparam \l2|l1|out[2]~26 .lut_mask = 64'h7FFFFFFF77FFFFFF;
+defparam \l2|l1|out[2]~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N54
+cyclonev_lcell_comb \uut_add_mantovf|Add0~35 (
+// Equation(s):
+// \uut_add_mantovf|Add0~35_combout  = !\uut_add_mantovf|Add0~28_combout  $ (!\uut_abs_regime1|regime_N[0]~1_combout )
+
+	.dataa(!\uut_add_mantovf|Add0~28_combout ),
+	.datab(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_mantovf|Add0~35_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~35 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~35 .lut_mask = 64'h6666666666666666;
+defparam \uut_add_mantovf|Add0~35 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N15
+cyclonev_lcell_comb \l2|l1|out[1]~19 (
+// Equation(s):
+// \l2|l1|out[1]~19_combout  = ( !\uut_add_sub_N|a11|a1|Add0~33_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~19 .extended_lut = "off";
+defparam \l2|l1|out[1]~19 .lut_mask = 64'hF0F0F0F000000000;
+defparam \l2|l1|out[1]~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N48
+cyclonev_lcell_comb \l2|l1|out[1]~25 (
+// Equation(s):
+// \l2|l1|out[1]~25_combout  = ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \l2|l1|out[1]~19_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & !\uut_add_sub_N|a11|a1|Add0~9_sumout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( 
+// \l2|l1|out[1]~19_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & (!\uut_add_sub_N|a11|a1|Add0~9_sumout  & ((!\l2|l1|out[1]~4_combout ) # (\uut_add_sub_N|a11|a1|Add0~29_sumout )))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( 
+// !\l2|l1|out[1]~19_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & !\uut_add_sub_N|a11|a1|Add0~9_sumout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\l2|l1|out[1]~19_combout  & ( (\uut_add_sub_N|a11|a1|Add0~29_sumout  & 
+// (!\uut_add_sub_N|a11|a1|Add0~13_sumout  & !\uut_add_sub_N|a11|a1|Add0~9_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datac(!\l2|l1|out[1]~4_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.dataf(!\l2|l1|out[1]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~25_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~25 .extended_lut = "off";
+defparam \l2|l1|out[1]~25 .lut_mask = 64'h4400CC00C400CC00;
+defparam \l2|l1|out[1]~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y5_N51
+cyclonev_lcell_comb \uut_add_mantovf|Add0~34 (
+// Equation(s):
+// \uut_add_mantovf|Add0~34_combout  = ( \uut_de2|ls|c[14]~19_combout  & ( (!\LessThan0~17_combout  & ((!\uut_de1|ls|c[14]~18_combout  $ (!\uut_de1|ls|c[15]~16_combout )))) # (\LessThan0~17_combout  & (!\uut_de2|ls|c[15]~17_combout )) ) ) # ( 
+// !\uut_de2|ls|c[14]~19_combout  & ( (!\LessThan0~17_combout  & ((!\uut_de1|ls|c[14]~18_combout  $ (!\uut_de1|ls|c[15]~16_combout )))) # (\LessThan0~17_combout  & (\uut_de2|ls|c[15]~17_combout )) ) )
+
+	.dataa(!\uut_de2|ls|c[15]~17_combout ),
+	.datab(!\LessThan0~17_combout ),
+	.datac(!\uut_de1|ls|c[14]~18_combout ),
+	.datad(!\uut_de1|ls|c[15]~16_combout ),
+	.datae(gnd),
+	.dataf(!\uut_de2|ls|c[14]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_add_mantovf|Add0~34_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~34 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~34 .lut_mask = 64'h1DD11DD12EE22EE2;
+defparam \uut_add_mantovf|Add0~34 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N0
+cyclonev_lcell_comb \uut_add_mantovf|Add0~32 (
+// Equation(s):
+// \uut_add_mantovf|Add0~32_cout  = CARRY(( \uut_add_sub_N|a11|a1|Add0~1_sumout  ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\uut_add_mantovf|Add0~32_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~32 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~32 .lut_mask = 64'h0000000000000F0F;
+defparam \uut_add_mantovf|Add0~32 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N3
+cyclonev_lcell_comb \uut_add_mantovf|Add0~5 (
+// Equation(s):
+// \uut_add_mantovf|Add0~5_sumout  = SUM(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de1|ls|c[14]~18_combout ))) # (\LessThan0~0_combout  & (!\uut_de2|ls|c[14]~19_combout )))) # (\LessThan0~18_combout  & (!\uut_de2|ls|c[14]~19_combout )) 
+// ) + ( !\l2|l1|out[0]~3_combout  ) + ( \uut_add_mantovf|Add0~32_cout  ))
+// \uut_add_mantovf|Add0~6  = CARRY(( (!\LessThan0~18_combout  & ((!\LessThan0~0_combout  & ((!\uut_de1|ls|c[14]~18_combout ))) # (\LessThan0~0_combout  & (!\uut_de2|ls|c[14]~19_combout )))) # (\LessThan0~18_combout  & (!\uut_de2|ls|c[14]~19_combout )) ) + ( 
+// !\l2|l1|out[0]~3_combout  ) + ( \uut_add_mantovf|Add0~32_cout  ))
+
+	.dataa(!\LessThan0~18_combout ),
+	.datab(!\uut_de2|ls|c[14]~19_combout ),
+	.datac(!\LessThan0~0_combout ),
+	.datad(!\uut_de1|ls|c[14]~18_combout ),
+	.datae(gnd),
+	.dataf(!\l2|l1|out[0]~3_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~32_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~5_sumout ),
+	.cout(\uut_add_mantovf|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~5 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~5 .lut_mask = 64'h000000FF0000EC4C;
+defparam \uut_add_mantovf|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N6
+cyclonev_lcell_comb \uut_add_mantovf|Add0~9 (
+// Equation(s):
+// \uut_add_mantovf|Add0~9_sumout  = SUM(( ((!\l2|l1|out[0]~2_combout ) # ((!\l2|l1|h|h|l|WideOr0~combout  & !\l2|l1|out[1]~25_combout ))) # (\uut_add_sub_N|a11|a1|Add0~21_sumout ) ) + ( \uut_add_mantovf|Add0~34_combout  ) + ( \uut_add_mantovf|Add0~6  ))
+// \uut_add_mantovf|Add0~10  = CARRY(( ((!\l2|l1|out[0]~2_combout ) # ((!\l2|l1|h|h|l|WideOr0~combout  & !\l2|l1|out[1]~25_combout ))) # (\uut_add_sub_N|a11|a1|Add0~21_sumout ) ) + ( \uut_add_mantovf|Add0~34_combout  ) + ( \uut_add_mantovf|Add0~6  ))
+
+	.dataa(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datac(!\l2|l1|out[1]~25_combout ),
+	.datad(!\l2|l1|out[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~34_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~9_sumout ),
+	.cout(\uut_add_mantovf|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~9 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~9 .lut_mask = 64'h0000FF000000FFB3;
+defparam \uut_add_mantovf|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N9
+cyclonev_lcell_comb \uut_add_mantovf|Add0~13 (
+// Equation(s):
+// \uut_add_mantovf|Add0~13_sumout  = SUM(( (((!\l2|l1|out[2]~26_combout ) # (!\l2|l1|out[0]~2_combout )) # (\uut_add_sub_N|a11|a1|Add0~21_sumout )) # (\l2|l1|h|h|l|WideOr0~combout ) ) + ( \uut_add_mantovf|Add0~35_combout  ) + ( \uut_add_mantovf|Add0~10  ))
+// \uut_add_mantovf|Add0~14  = CARRY(( (((!\l2|l1|out[2]~26_combout ) # (!\l2|l1|out[0]~2_combout )) # (\uut_add_sub_N|a11|a1|Add0~21_sumout )) # (\l2|l1|h|h|l|WideOr0~combout ) ) + ( \uut_add_mantovf|Add0~35_combout  ) + ( \uut_add_mantovf|Add0~10  ))
+
+	.dataa(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datac(!\l2|l1|out[2]~26_combout ),
+	.datad(!\l2|l1|out[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~35_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~13_sumout ),
+	.cout(\uut_add_mantovf|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~13 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~13 .lut_mask = 64'h0000FF000000FFF7;
+defparam \uut_add_mantovf|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N12
+cyclonev_lcell_comb \uut_add_mantovf|Add0~17 (
+// Equation(s):
+// \uut_add_mantovf|Add0~17_sumout  = SUM(( !\l2|l1|out[3]~12_combout  ) + ( !\lr[1]~3_combout  $ (!\uut_add_mantovf|Add0~29_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( \uut_add_mantovf|Add0~14  
+// ))
+// \uut_add_mantovf|Add0~18  = CARRY(( !\l2|l1|out[3]~12_combout  ) + ( !\lr[1]~3_combout  $ (!\uut_add_mantovf|Add0~29_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( \uut_add_mantovf|Add0~14  ))
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datab(!\lr[1]~3_combout ),
+	.datac(!\uut_add_mantovf|Add0~29_combout ),
+	.datad(!\l2|l1|out[3]~12_combout ),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~17_sumout ),
+	.cout(\uut_add_mantovf|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~17 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~17 .lut_mask = 64'h0000C3690000FF00;
+defparam \uut_add_mantovf|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N15
+cyclonev_lcell_comb \uut_add_mantovf|Add0~21 (
+// Equation(s):
+// \uut_add_mantovf|Add0~21_sumout  = SUM(( (!\uut_add_mantovf|Add0~29_combout ) # (!\lr[1]~3_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( !\lr[2]~6_combout  $ ((((!\lr[1]~3_combout  & 
+// !\uut_abs_regime1|regime_N[0]~1_combout )) # (\uut_abs_regime1|regime_N[0]~0_combout ))) ) + ( \uut_add_mantovf|Add0~18  ))
+// \uut_add_mantovf|Add0~22  = CARRY(( (!\uut_add_mantovf|Add0~29_combout ) # (!\lr[1]~3_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( !\lr[2]~6_combout  $ ((((!\lr[1]~3_combout  & 
+// !\uut_abs_regime1|regime_N[0]~1_combout )) # (\uut_abs_regime1|regime_N[0]~0_combout ))) ) + ( \uut_add_mantovf|Add0~18  ))
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datab(!\lr[1]~3_combout ),
+	.datac(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datad(!\uut_add_mantovf|Add0~29_combout ),
+	.datae(gnd),
+	.dataf(!\lr[2]~6_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~21_sumout ),
+	.cout(\uut_add_mantovf|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~21 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~21 .lut_mask = 64'h0000D52A0000FFC6;
+defparam \uut_add_mantovf|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N18
+cyclonev_lcell_comb \uut_add_mantovf|Add0~25 (
+// Equation(s):
+// \uut_add_mantovf|Add0~25_sumout  = SUM(( \uut_abs_regime1|regime_N[3]~3_combout  ) + ( (!\uut_add_mantovf|Add0~29_combout ) # (!\lr[1]~3_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( 
+// \uut_add_mantovf|Add0~22  ))
+// \uut_add_mantovf|Add0~26  = CARRY(( \uut_abs_regime1|regime_N[3]~3_combout  ) + ( (!\uut_add_mantovf|Add0~29_combout ) # (!\lr[1]~3_combout  $ (((!\uut_abs_regime1|regime_N[0]~0_combout  & \uut_abs_regime1|regime_N[0]~1_combout )))) ) + ( 
+// \uut_add_mantovf|Add0~22  ))
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datab(!\lr[1]~3_combout ),
+	.datac(!\uut_add_mantovf|Add0~29_combout ),
+	.datad(!\uut_abs_regime1|regime_N[3]~3_combout ),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~25_sumout ),
+	.cout(\uut_add_mantovf|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~25 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~25 .lut_mask = 64'h00000309000000FF;
+defparam \uut_add_mantovf|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N21
+cyclonev_lcell_comb \uut_add_mantovf|Add0~1 (
+// Equation(s):
+// \uut_add_mantovf|Add0~1_sumout  = SUM(( (\uut_add_mantovf|Add0~29_combout  & (!\lr[1]~3_combout  $ (((!\uut_abs_regime1|regime_N[0]~1_combout ) # (\uut_abs_regime1|regime_N[0]~0_combout ))))) ) + ( (!\uut_abs_regime1|regime_N[0]~0_combout  & 
+// \uut_abs_regime1|Add0~0_combout ) ) + ( \uut_add_mantovf|Add0~26  ))
+
+	.dataa(!\uut_abs_regime1|regime_N[0]~0_combout ),
+	.datab(!\lr[1]~3_combout ),
+	.datac(!\uut_add_mantovf|Add0~29_combout ),
+	.datad(!\uut_abs_regime1|regime_N[0]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_abs_regime1|Add0~0_combout ),
+	.datag(gnd),
+	.cin(\uut_add_mantovf|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_mantovf|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_mantovf|Add0~1 .extended_lut = "off";
+defparam \uut_add_mantovf|Add0~1 .lut_mask = 64'h0000FF5500000309;
+defparam \uut_add_mantovf|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N27
+cyclonev_lcell_comb \uut_reg_ro|r_o[3]~1 (
+// Equation(s):
+// \uut_reg_ro|r_o[3]~1_combout  = ( \uut_add_mantovf|Add0~21_sumout  & ( !\uut_add_mantovf|Add0~25_sumout  $ (((\uut_add_mantovf|Add0~1_sumout  & ((!\uut_add_mantovf|Add0~13_sumout ) # (!\uut_add_mantovf|Add0~17_sumout ))))) ) ) # ( 
+// !\uut_add_mantovf|Add0~21_sumout  & ( !\uut_add_mantovf|Add0~25_sumout  $ ((((!\uut_add_mantovf|Add0~13_sumout  & !\uut_add_mantovf|Add0~17_sumout )) # (\uut_add_mantovf|Add0~1_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\uut_add_mantovf|Add0~17_sumout ),
+	.datad(!\uut_add_mantovf|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_reg_ro|r_o[3]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_reg_ro|r_o[3]~1 .extended_lut = "off";
+defparam \uut_reg_ro|r_o[3]~1 .lut_mask = 64'h2AD52AD5AB54AB54;
+defparam \uut_reg_ro|r_o[3]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N39
+cyclonev_lcell_comb \uut_reg_ro|r_o[2]~0 (
+// Equation(s):
+// \uut_reg_ro|r_o[2]~0_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( !\uut_add_mantovf|Add0~21_sumout  $ (((\uut_add_mantovf|Add0~1_sumout  & !\uut_add_mantovf|Add0~17_sumout ))) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( 
+// !\uut_add_mantovf|Add0~21_sumout  $ (((!\uut_add_mantovf|Add0~17_sumout ) # (\uut_add_mantovf|Add0~1_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~21_sumout ),
+	.datab(gnd),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(!\uut_add_mantovf|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_reg_ro|r_o[2]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_reg_ro|r_o[2]~0 .extended_lut = "off";
+defparam \uut_reg_ro|r_o[2]~0 .lut_mask = 64'h55A555A5A5AAA5AA;
+defparam \uut_reg_ro|r_o[2]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N3
+cyclonev_lcell_comb \l2|l1|out[1]~20 (
+// Equation(s):
+// \l2|l1|out[1]~20_combout  = (!\uut_add_sub_N|a11|a1|Add0~17_sumout  & !\uut_add_sub_N|a11|a1|Add0~29_sumout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~20 .extended_lut = "off";
+defparam \l2|l1|out[1]~20 .lut_mask = 64'hF000F000F000F000;
+defparam \l2|l1|out[1]~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N48
+cyclonev_lcell_comb \l2|l1|out[1]~21 (
+// Equation(s):
+// \l2|l1|out[1]~21_combout  = ( \l2|l1|out[1]~19_combout  & ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~25_sumout  & ((!\l2|l1|out[1]~6_combout ) # ((\l2|l1|out[1]~20_combout  & \l2|l1|out[1]~4_combout )))) ) ) ) # ( 
+// !\l2|l1|out[1]~19_combout  & ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~25_sumout  & ((!\l2|l1|out[1]~6_combout ) # (\l2|l1|out[1]~20_combout ))) ) ) )
+
+	.dataa(!\l2|l1|out[1]~20_combout ),
+	.datab(!\l2|l1|out[1]~6_combout ),
+	.datac(!\l2|l1|out[1]~4_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datae(!\l2|l1|out[1]~19_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[1]~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[1]~21 .extended_lut = "off";
+defparam \l2|l1|out[1]~21 .lut_mask = 64'hDD00CD0000000000;
+defparam \l2|l1|out[1]~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N3
+cyclonev_lcell_comb \l2|l1|out[0]~16 (
+// Equation(s):
+// \l2|l1|out[0]~16_combout  = ( !\uut_add_sub_N|a11|a1|Add0~53_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~57_sumout ) # (\uut_add_sub_N|a11|a1|Add0~61_sumout ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~16 .extended_lut = "off";
+defparam \l2|l1|out[0]~16 .lut_mask = 64'hBBBBBBBB00000000;
+defparam \l2|l1|out[0]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N6
+cyclonev_lcell_comb \l2|l1|out[0]~17 (
+// Equation(s):
+// \l2|l1|out[0]~17_combout  = ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~33_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~41_sumout ) # (\uut_add_sub_N|a11|a1|Add0~37_sumout ))) ) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~33_sumout  & \uut_add_sub_N|a11|a1|Add0~37_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout 
+//  & ( (!\uut_add_sub_N|a11|a1|Add0~33_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~41_sumout ) # (\uut_add_sub_N|a11|a1|Add0~37_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( 
+// (!\uut_add_sub_N|a11|a1|Add0~33_sumout  & (((!\uut_add_sub_N|a11|a1|Add0~41_sumout  & !\l2|l1|out[0]~16_combout )) # (\uut_add_sub_N|a11|a1|Add0~37_sumout ))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datad(!\l2|l1|out[0]~16_combout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~17 .extended_lut = "off";
+defparam \l2|l1|out[0]~17 .lut_mask = 64'h8C0C8C8C0C0C8C8C;
+defparam \l2|l1|out[0]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N0
+cyclonev_lcell_comb \l2|l1|out[0]~18 (
+// Equation(s):
+// \l2|l1|out[0]~18_combout  = ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \uut_add_sub_N|a11|a1|Add0~29_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~5_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~13_sumout ) # (\uut_add_sub_N|a11|a1|Add0~9_sumout ))) ) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \uut_add_sub_N|a11|a1|Add0~29_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~5_sumout  & \uut_add_sub_N|a11|a1|Add0~9_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  
+// & ( (!\uut_add_sub_N|a11|a1|Add0~5_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~13_sumout ) # (\uut_add_sub_N|a11|a1|Add0~9_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  & ( 
+// (!\uut_add_sub_N|a11|a1|Add0~5_sumout  & (((!\l2|l1|out[0]~17_combout  & !\uut_add_sub_N|a11|a1|Add0~13_sumout )) # (\uut_add_sub_N|a11|a1|Add0~9_sumout ))) ) ) )
+
+	.dataa(!\l2|l1|out[0]~17_combout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~18 .extended_lut = "off";
+defparam \l2|l1|out[0]~18 .lut_mask = 64'h80F0C0F000F0C0F0;
+defparam \l2|l1|out[0]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N12
+cyclonev_lcell_comb \dsl1|tmp[1][0]~6 (
+// Equation(s):
+// \dsl1|tmp[1][0]~6_combout  = ( \l2|l1|out[1]~21_combout  & ( \l2|l1|out[0]~18_combout  & ( (\uut_add_sub_N|a11|a1|Add0~61_sumout  & ((!\uut_add_sub_N|a11|a1|Add0~21_sumout ) # (!\l2|l1|out[0]~2_combout ))) ) ) ) # ( !\l2|l1|out[1]~21_combout  & ( 
+// \l2|l1|out[0]~18_combout  & ( (!\l2|l1|out[0]~2_combout  & \uut_add_sub_N|a11|a1|Add0~61_sumout ) ) ) ) # ( \l2|l1|out[1]~21_combout  & ( !\l2|l1|out[0]~18_combout  & ( (\uut_add_sub_N|a11|a1|Add0~61_sumout  & ((!\l2|l1|out[0]~2_combout ) # 
+// ((!\uut_add_sub_N|a11|a1|Add0~21_sumout  & \uut_add_sub_N|a11|a1|Add0~25_sumout )))) ) ) ) # ( !\l2|l1|out[1]~21_combout  & ( !\l2|l1|out[0]~18_combout  & ( (!\l2|l1|out[0]~2_combout  & \uut_add_sub_N|a11|a1|Add0~61_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datac(!\l2|l1|out[0]~2_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datae(!\l2|l1|out[1]~21_combout ),
+	.dataf(!\l2|l1|out[0]~18_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][0]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][0]~6 .extended_lut = "off";
+defparam \dsl1|tmp[1][0]~6 .lut_mask = 64'h00F000F200F000FA;
+defparam \dsl1|tmp[1][0]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N18
+cyclonev_lcell_comb \dsl1|tmp[1][4]~7 (
+// Equation(s):
+// \dsl1|tmp[1][4]~7_combout  = ( \l2|l1|out[0]~3_combout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))) ) ) ) # ( 
+// !\l2|l1|out[0]~3_combout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (\uut_add_sub_N|a11|a1|Add0~41_sumout ) # (\l2|l1|out[1]~7_combout ) ) ) ) # ( \l2|l1|out[0]~3_combout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~45_sumout )) # (\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~53_sumout ))) ) ) ) # ( !\l2|l1|out[0]~3_combout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[1]~7_combout  & 
+// \uut_add_sub_N|a11|a1|Add0~41_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datae(!\l2|l1|out[0]~3_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][4]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][4]~7 .extended_lut = "off";
+defparam \dsl1|tmp[1][4]~7 .lut_mask = 64'h0C0C44773F3F4477;
+defparam \dsl1|tmp[1][4]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N15
+cyclonev_lcell_comb \tmp_o[6]~2 (
+// Equation(s):
+// \tmp_o[6]~2_combout  = ( \dsl1|tmp[1][4]~7_combout  & ( (!\l2|l1|out[2]~10_combout ) # (\dsl1|tmp[1][0]~6_combout ) ) ) # ( !\dsl1|tmp[1][4]~7_combout  & ( (\l2|l1|out[2]~10_combout  & \dsl1|tmp[1][0]~6_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][0]~6_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsl1|tmp[1][4]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[6]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[6]~2 .extended_lut = "off";
+defparam \tmp_o[6]~2 .lut_mask = 64'h11111111BBBBBBBB;
+defparam \tmp_o[6]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N0
+cyclonev_lcell_comb \dsl1|tmp[1][5]~9 (
+// Equation(s):
+// \dsl1|tmp[1][5]~9_combout  = ( \uut_add_sub_N|a11|a1|Add0~37_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((!\l2|l1|out[1]~7_combout ) # (\uut_add_sub_N|a11|a1|Add0~45_sumout )))) # (\l2|l1|out[0]~3_combout  & 
+// (((\l2|l1|out[1]~7_combout )) # (\uut_add_sub_N|a11|a1|Add0~41_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  & ( \uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\uut_add_sub_N|a11|a1|Add0~45_sumout  & 
+// \l2|l1|out[1]~7_combout )))) # (\l2|l1|out[0]~3_combout  & (((\l2|l1|out[1]~7_combout )) # (\uut_add_sub_N|a11|a1|Add0~41_sumout ))) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~37_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  
+// & (((!\l2|l1|out[1]~7_combout ) # (\uut_add_sub_N|a11|a1|Add0~45_sumout )))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~41_sumout  & ((!\l2|l1|out[1]~7_combout )))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  & ( 
+// !\uut_add_sub_N|a11|a1|Add0~49_sumout  & ( (!\l2|l1|out[0]~3_combout  & (((\uut_add_sub_N|a11|a1|Add0~45_sumout  & \l2|l1|out[1]~7_combout )))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~41_sumout  & ((!\l2|l1|out[1]~7_combout )))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.datad(!\l2|l1|out[1]~7_combout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][5]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][5]~9 .extended_lut = "off";
+defparam \dsl1|tmp[1][5]~9 .lut_mask = 64'h110CDD0C113FDD3F;
+defparam \dsl1|tmp[1][5]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N0
+cyclonev_lcell_comb \l2|l1|out[0]~22 (
+// Equation(s):
+// \l2|l1|out[0]~22_combout  = ( \uut_add_sub_N|a11|a1|Add0~53_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~49_sumout  ) ) # ( !\uut_add_sub_N|a11|a1|Add0~53_sumout  & ( (\uut_add_sub_N|a11|a1|Add0~57_sumout  & (!\uut_add_sub_N|a11|a1|Add0~61_sumout  & 
+// !\uut_add_sub_N|a11|a1|Add0~49_sumout )) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~57_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~49_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~22 .extended_lut = "off";
+defparam \l2|l1|out[0]~22 .lut_mask = 64'h40404040F0F0F0F0;
+defparam \l2|l1|out[0]~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N36
+cyclonev_lcell_comb \l2|l1|out[0]~23 (
+// Equation(s):
+// \l2|l1|out[0]~23_combout  = ( \uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  & ( ((\uut_add_sub_N|a11|a1|Add0~41_sumout  & !\uut_add_sub_N|a11|a1|Add0~37_sumout )) # (\uut_add_sub_N|a11|a1|Add0~33_sumout ) ) ) ) # ( 
+// !\uut_add_sub_N|a11|a1|Add0~45_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~29_sumout  & ( ((!\uut_add_sub_N|a11|a1|Add0~37_sumout  & ((!\l2|l1|out[0]~22_combout ) # (\uut_add_sub_N|a11|a1|Add0~41_sumout )))) # (\uut_add_sub_N|a11|a1|Add0~33_sumout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~41_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.datac(!\l2|l1|out[0]~22_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~45_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~23 .extended_lut = "off";
+defparam \l2|l1|out[0]~23 .lut_mask = 64'hC4FF44FF00000000;
+defparam \l2|l1|out[0]~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X57_Y8_N42
+cyclonev_lcell_comb \l2|l1|out[0]~24 (
+// Equation(s):
+// \l2|l1|out[0]~24_combout  = ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~25_sumout  ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( \uut_add_sub_N|a11|a1|Add0~5_sumout  & ( 
+// !\uut_add_sub_N|a11|a1|Add0~25_sumout  ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~25_sumout  & (!\uut_add_sub_N|a11|a1|Add0~9_sumout  & \uut_add_sub_N|a11|a1|Add0~13_sumout )) 
+// ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~17_sumout  & ( !\uut_add_sub_N|a11|a1|Add0~5_sumout  & ( (!\uut_add_sub_N|a11|a1|Add0~25_sumout  & (!\uut_add_sub_N|a11|a1|Add0~9_sumout  & ((!\l2|l1|out[0]~23_combout ) # (\uut_add_sub_N|a11|a1|Add0~13_sumout )))) ) 
+// ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datac(!\l2|l1|out[0]~23_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\l2|l1|out[0]~24_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \l2|l1|out[0]~24 .extended_lut = "off";
+defparam \l2|l1|out[0]~24 .lut_mask = 64'h80880088AAAAAAAA;
+defparam \l2|l1|out[0]~24 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y8_N24
+cyclonev_lcell_comb \dsl1|tmp[1][1]~8 (
+// Equation(s):
+// \dsl1|tmp[1][1]~8_combout  = ( \l2|l1|out[1]~21_combout  & ( \l2|l1|out[0]~24_combout  & ( (!\l2|l1|out[0]~2_combout  & (\uut_add_sub_N|a11|a1|Add0~53_sumout )) # (\l2|l1|out[0]~2_combout  & ((\uut_add_sub_N|a11|a1|Add0~61_sumout ))) ) ) ) # ( 
+// !\l2|l1|out[1]~21_combout  & ( \l2|l1|out[0]~24_combout  & ( (!\l2|l1|out[0]~2_combout  & (((\uut_add_sub_N|a11|a1|Add0~53_sumout )))) # (\l2|l1|out[0]~2_combout  & (\uut_add_sub_N|a11|a1|Add0~21_sumout  & ((\uut_add_sub_N|a11|a1|Add0~61_sumout )))) ) ) ) 
+// # ( \l2|l1|out[1]~21_combout  & ( !\l2|l1|out[0]~24_combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (\uut_add_sub_N|a11|a1|Add0~53_sumout )) # (\uut_add_sub_N|a11|a1|Add0~21_sumout  & ((!\l2|l1|out[0]~2_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~53_sumout )) # (\l2|l1|out[0]~2_combout  & ((\uut_add_sub_N|a11|a1|Add0~61_sumout ))))) ) ) ) # ( !\l2|l1|out[1]~21_combout  & ( !\l2|l1|out[0]~24_combout  & ( (!\l2|l1|out[0]~2_combout  & 
+// (((\uut_add_sub_N|a11|a1|Add0~53_sumout )))) # (\l2|l1|out[0]~2_combout  & (\uut_add_sub_N|a11|a1|Add0~21_sumout  & ((\uut_add_sub_N|a11|a1|Add0~61_sumout )))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~53_sumout ),
+	.datac(!\l2|l1|out[0]~2_combout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~61_sumout ),
+	.datae(!\l2|l1|out[1]~21_combout ),
+	.dataf(!\l2|l1|out[0]~24_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][1]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][1]~8 .extended_lut = "off";
+defparam \dsl1|tmp[1][1]~8 .lut_mask = 64'h303532373035303F;
+defparam \dsl1|tmp[1][1]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N48
+cyclonev_lcell_comb \tmp_o[6]~4 (
+// Equation(s):
+// \tmp_o[6]~4_combout  = ( \l2|l1|out[2]~10_combout  & ( \dsl1|tmp[1][1]~8_combout  ) ) # ( !\l2|l1|out[2]~10_combout  & ( \dsl1|tmp[1][5]~9_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsl1|tmp[1][5]~9_combout ),
+	.datad(!\dsl1|tmp[1][1]~8_combout ),
+	.datae(gnd),
+	.dataf(!\l2|l1|out[2]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[6]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[6]~4 .extended_lut = "off";
+defparam \tmp_o[6]~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
+defparam \tmp_o[6]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N54
+cyclonev_lcell_comb \tmp_o[6]~5 (
+// Equation(s):
+// \tmp_o[6]~5_combout  = ( !\l2|l1|out[3]~12_combout  & ( (!\dsl1|c[15]~0_combout  & (\tmp_o[6]~2_combout )) # (\dsl1|c[15]~0_combout  & ((\tmp_o[6]~4_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\tmp_o[6]~2_combout ),
+	.datac(!\tmp_o[6]~4_combout ),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[6]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[6]~5 .extended_lut = "off";
+defparam \tmp_o[6]~5 .lut_mask = 64'h330F330F00000000;
+defparam \tmp_o[6]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N42
+cyclonev_lcell_comb \tmp_o[1]~0 (
+// Equation(s):
+// \tmp_o[1]~0_combout  = ( \l2|l1|l|h|vld~combout  & ( !\l2|l1|h|h|l|WideOr0~combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (\l2|l1|out[0]~2_combout  & ((!\l2|l1|out[2]~8_combout ) # (!\l2|l1|h|l|h|WideOr0~0_combout )))) ) ) ) # ( 
+// !\l2|l1|l|h|vld~combout  & ( !\l2|l1|h|h|l|WideOr0~combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & \l2|l1|out[0]~2_combout ) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datab(!\l2|l1|out[2]~8_combout ),
+	.datac(!\l2|l1|out[0]~2_combout ),
+	.datad(!\l2|l1|h|l|h|WideOr0~0_combout ),
+	.datae(!\l2|l1|l|h|vld~combout ),
+	.dataf(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[1]~0 .extended_lut = "off";
+defparam \tmp_o[1]~0 .lut_mask = 64'h0A0A0A0800000000;
+defparam \tmp_o[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N30
+cyclonev_lcell_comb \tmp_o[4]~1 (
+// Equation(s):
+// \tmp_o[4]~1_combout  = ( !\tmp_o[1]~0_combout  & ( (!\dsl1|c[15]~0_combout  & (\dsl1|tmp[1][2]~5_combout )) # (\dsl1|c[15]~0_combout  & ((\dsl1|tmp[1][3]~2_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\dsl1|tmp[1][2]~5_combout ),
+	.datad(!\dsl1|tmp[1][3]~2_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[4]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[4]~1 .extended_lut = "off";
+defparam \tmp_o[4]~1 .lut_mask = 64'h0C3F0C3F00000000;
+defparam \tmp_o[4]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N42
+cyclonev_lcell_comb \uut_reg_ro|r_o[1]~3 (
+// Equation(s):
+// \uut_reg_ro|r_o[1]~3_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( !\uut_add_mantovf|Add0~17_sumout  ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( \uut_add_mantovf|Add0~17_sumout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\uut_add_mantovf|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_reg_ro|r_o[1]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_reg_ro|r_o[1]~3 .extended_lut = "off";
+defparam \uut_reg_ro|r_o[1]~3 .lut_mask = 64'h00FF00FFFF00FF00;
+defparam \uut_reg_ro|r_o[1]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N33
+cyclonev_lcell_comb \tmp_o[7]~6 (
+// Equation(s):
+// \tmp_o[7]~6_combout  = ( \dsl1|tmp[1][6]~4_combout  & ( (!\l2|l1|out[2]~10_combout ) # (\dsl1|tmp[1][2]~5_combout ) ) ) # ( !\dsl1|tmp[1][6]~4_combout  & ( (\l2|l1|out[2]~10_combout  & \dsl1|tmp[1][2]~5_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][2]~5_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsl1|tmp[1][6]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[7]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[7]~6 .extended_lut = "off";
+defparam \tmp_o[7]~6 .lut_mask = 64'h11111111BBBBBBBB;
+defparam \tmp_o[7]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N57
+cyclonev_lcell_comb \tmp_o[7]~7 (
+// Equation(s):
+// \tmp_o[7]~7_combout  = ( \tmp_o[7]~6_combout  & ( (!\l2|l1|out[3]~12_combout  & ((\dsl1|c[15]~0_combout ) # (\tmp_o[6]~4_combout ))) ) ) # ( !\tmp_o[7]~6_combout  & ( (\tmp_o[6]~4_combout  & (!\l2|l1|out[3]~12_combout  & !\dsl1|c[15]~0_combout )) ) )
+
+	.dataa(!\tmp_o[6]~4_combout ),
+	.datab(gnd),
+	.datac(!\l2|l1|out[3]~12_combout ),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[7]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[7]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[7]~7 .extended_lut = "off";
+defparam \tmp_o[7]~7 .lut_mask = 64'h5000500050F050F0;
+defparam \tmp_o[7]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N9
+cyclonev_lcell_comb \uut_reg_ro|r_o[0]~2 (
+// Equation(s):
+// \uut_reg_ro|r_o[0]~2_combout  = !\uut_add_mantovf|Add0~13_sumout  $ (!\uut_add_mantovf|Add0~1_sumout )
+
+	.dataa(!\uut_add_mantovf|Add0~13_sumout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\uut_reg_ro|r_o[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_reg_ro|r_o[0]~2 .extended_lut = "off";
+defparam \uut_reg_ro|r_o[0]~2 .lut_mask = 64'h6666666666666666;
+defparam \uut_reg_ro|r_o[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N51
+cyclonev_lcell_comb \tmp_o[5]~3 (
+// Equation(s):
+// \tmp_o[5]~3_combout  = ( \dsl1|tmp[1][3]~2_combout  & ( (!\l2|l1|out[3]~12_combout  & ((!\dsl1|c[15]~0_combout  & (!\l2|l1|out[2]~10_combout )) # (\dsl1|c[15]~0_combout  & ((\tmp_o[6]~2_combout ))))) ) ) # ( !\dsl1|tmp[1][3]~2_combout  & ( 
+// (!\l2|l1|out[3]~12_combout  & (\tmp_o[6]~2_combout  & \dsl1|c[15]~0_combout )) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\l2|l1|out[3]~12_combout ),
+	.datac(!\tmp_o[6]~2_combout ),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|tmp[1][3]~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[5]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[5]~3 .extended_lut = "off";
+defparam \tmp_o[5]~3 .lut_mask = 64'h000C000C880C880C;
+defparam \tmp_o[5]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N36
+cyclonev_lcell_comb \dsr2|tmp[1][20]~0 (
+// Equation(s):
+// \dsr2|tmp[1][20]~0_combout  = ( \uut_reg_ro|r_o[0]~2_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # (\tmp_o[7]~7_combout ) ) ) ) # ( !\uut_reg_ro|r_o[0]~2_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & 
+// ((\tmp_o[4]~1_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[6]~5_combout )) ) ) ) # ( \uut_reg_ro|r_o[0]~2_combout  & ( !\tmp_o[5]~3_combout  & ( (\uut_reg_ro|r_o[1]~3_combout  & \tmp_o[7]~7_combout ) ) ) ) # ( !\uut_reg_ro|r_o[0]~2_combout  & ( 
+// !\tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((\tmp_o[4]~1_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[6]~5_combout )) ) ) )
+
+	.dataa(!\tmp_o[6]~5_combout ),
+	.datab(!\tmp_o[4]~1_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\tmp_o[7]~7_combout ),
+	.datae(!\uut_reg_ro|r_o[0]~2_combout ),
+	.dataf(!\tmp_o[5]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][20]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][20]~0 .extended_lut = "off";
+defparam \dsr2|tmp[1][20]~0 .lut_mask = 64'h3535000F3535F0FF;
+defparam \dsr2|tmp[1][20]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X56_Y8_N24
+cyclonev_lcell_comb \dsl1|c[10]~3 (
+// Equation(s):
+// \dsl1|c[10]~3_combout  = ( \l2|l1|l|h|vld~combout  & ( !\l2|l1|h|h|l|WideOr0~combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (!\uut_add_sub_N|a11|a1|Add0~65_sumout  & (!\uut_add_sub_N|a11|a1|Add0~1_sumout  & !\l2|l1|h|l|h|WideOr0~0_combout ))) ) ) 
+// ) # ( !\l2|l1|l|h|vld~combout  & ( !\l2|l1|h|h|l|WideOr0~combout  & ( (!\uut_add_sub_N|a11|a1|Add0~21_sumout  & (!\uut_add_sub_N|a11|a1|Add0~65_sumout  & !\uut_add_sub_N|a11|a1|Add0~1_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datab(!\uut_add_sub_N|a11|a1|Add0~65_sumout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~1_sumout ),
+	.datad(!\l2|l1|h|l|h|WideOr0~0_combout ),
+	.datae(!\l2|l1|l|h|vld~combout ),
+	.dataf(!\l2|l1|h|h|l|WideOr0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[10]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[10]~3 .extended_lut = "off";
+defparam \dsl1|c[10]~3 .lut_mask = 64'h8080800000000000;
+defparam \dsl1|c[10]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N42
+cyclonev_lcell_comb \dsl1|c[11]~12 (
+// Equation(s):
+// \dsl1|c[11]~12_combout  = ( \dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][3]~2_combout ))) # (\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][7]~1_combout )) ) ) # ( !\dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & 
+// \dsl1|tmp[1][11]~0_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][7]~1_combout ),
+	.datac(!\dsl1|tmp[1][3]~2_combout ),
+	.datad(!\dsl1|tmp[1][11]~0_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[10]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[11]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[11]~12 .extended_lut = "off";
+defparam \dsl1|c[11]~12 .lut_mask = 64'h00AA00AA1B1B1B1B;
+defparam \dsl1|c[11]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N30
+cyclonev_lcell_comb \dsl1|c[10]~5 (
+// Equation(s):
+// \dsl1|c[10]~5_combout  = ( \dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][2]~5_combout )) # (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][6]~4_combout ))) ) ) # ( !\dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & 
+// \dsl1|tmp[1][10]~3_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][2]~5_combout ),
+	.datac(!\dsl1|tmp[1][10]~3_combout ),
+	.datad(!\dsl1|tmp[1][6]~4_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[10]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[10]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[10]~5 .extended_lut = "off";
+defparam \dsl1|c[10]~5 .lut_mask = 64'h0A0A0A0A22772277;
+defparam \dsl1|c[10]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N42
+cyclonev_lcell_comb \dsl1|tmp[1][8]~11 (
+// Equation(s):
+// \dsl1|tmp[1][8]~11_combout  = ( \uut_add_sub_N|a11|a1|Add0~37_sumout  & ( \l2|l1|out[0]~3_combout  & ( (\uut_add_sub_N|a11|a1|Add0~29_sumout ) # (\l2|l1|out[1]~7_combout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  & ( \l2|l1|out[0]~3_combout  & ( 
+// (!\l2|l1|out[1]~7_combout  & \uut_add_sub_N|a11|a1|Add0~29_sumout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~37_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~17_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~33_sumout )) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~37_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & ((\uut_add_sub_N|a11|a1|Add0~17_sumout ))) # (\l2|l1|out[1]~7_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~33_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~37_sumout ),
+	.dataf(!\l2|l1|out[0]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][8]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][8]~11 .extended_lut = "off";
+defparam \dsl1|tmp[1][8]~11 .lut_mask = 64'h1D1D1D1D00CC33FF;
+defparam \dsl1|tmp[1][8]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N24
+cyclonev_lcell_comb \dsl1|c[12]~10 (
+// Equation(s):
+// \dsl1|c[12]~10_combout  = ( \l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~13_sumout  & ( (\uut_add_sub_N|a11|a1|Add0~9_sumout ) # (\l2|l1|out[0]~3_combout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~13_sumout  & ( 
+// (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~25_sumout ))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~5_sumout )) ) ) ) # ( \l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( (!\l2|l1|out[0]~3_combout  & 
+// \uut_add_sub_N|a11|a1|Add0~9_sumout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~13_sumout  & ( (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~25_sumout ))) # (\l2|l1|out[0]~3_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~5_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datae(!\l2|l1|out[1]~7_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[12]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[12]~10 .extended_lut = "off";
+defparam \dsl1|c[12]~10 .lut_mask = 64'h11DD0C0C11DD3F3F;
+defparam \dsl1|c[12]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N24
+cyclonev_lcell_comb \dsl1|c[12]~11 (
+// Equation(s):
+// \dsl1|c[12]~11_combout  = ( \dsl1|c[12]~10_combout  & ( \l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout  & ((\dsl1|tmp[1][8]~11_combout ))) # (\l2|l1|out[3]~12_combout  & (\dsl1|tmp[1][0]~6_combout )) ) ) ) # ( !\dsl1|c[12]~10_combout  & ( 
+// \l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout  & ((\dsl1|tmp[1][8]~11_combout ))) # (\l2|l1|out[3]~12_combout  & (\dsl1|tmp[1][0]~6_combout )) ) ) ) # ( \dsl1|c[12]~10_combout  & ( !\l2|l1|out[2]~10_combout  & ( (!\l2|l1|out[3]~12_combout ) # 
+// (\dsl1|tmp[1][4]~7_combout ) ) ) ) # ( !\dsl1|c[12]~10_combout  & ( !\l2|l1|out[2]~10_combout  & ( (\dsl1|tmp[1][4]~7_combout  & \l2|l1|out[3]~12_combout ) ) ) )
+
+	.dataa(!\dsl1|tmp[1][4]~7_combout ),
+	.datab(!\dsl1|tmp[1][0]~6_combout ),
+	.datac(!\dsl1|tmp[1][8]~11_combout ),
+	.datad(!\l2|l1|out[3]~12_combout ),
+	.datae(!\dsl1|c[12]~10_combout ),
+	.dataf(!\l2|l1|out[2]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[12]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[12]~11 .extended_lut = "off";
+defparam \dsl1|c[12]~11 .lut_mask = 64'h0055FF550F330F33;
+defparam \dsl1|c[12]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N15
+cyclonev_lcell_comb \dsr2|tmp[0][28]~6 (
+// Equation(s):
+// \dsr2|tmp[0][28]~6_combout  = (!\uut_add_mantovf|Add0~13_sumout  & ((!\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[10]~5_combout )) # (\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[12]~11_combout ))))) # (\uut_add_mantovf|Add0~13_sumout  & 
+// ((!\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[12]~11_combout ))) # (\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[10]~5_combout ))))
+
+	.dataa(!\uut_add_mantovf|Add0~13_sumout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\dsl1|c[10]~5_combout ),
+	.datad(!\dsl1|c[12]~11_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][28]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][28]~6 .extended_lut = "off";
+defparam \dsr2|tmp[0][28]~6 .lut_mask = 64'h096F096F096F096F;
+defparam \dsr2|tmp[0][28]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N12
+cyclonev_lcell_comb \dsr2|tmp[0][30]~5 (
+// Equation(s):
+// \dsr2|tmp[0][30]~5_combout  = (!\uut_add_mantovf|Add0~13_sumout  & ((!\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[12]~11_combout ))) # (\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[14]~2_combout )))) # (\uut_add_mantovf|Add0~13_sumout  & 
+// ((!\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[14]~2_combout )) # (\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[12]~11_combout )))))
+
+	.dataa(!\uut_add_mantovf|Add0~13_sumout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\dsl1|c[14]~2_combout ),
+	.datad(!\dsl1|c[12]~11_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][30]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][30]~5 .extended_lut = "off";
+defparam \dsr2|tmp[0][30]~5 .lut_mask = 64'h069F069F069F069F;
+defparam \dsr2|tmp[0][30]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N6
+cyclonev_lcell_comb \dsl1|tmp[1][9]~10 (
+// Equation(s):
+// \dsl1|tmp[1][9]~10_combout  = ( \uut_add_sub_N|a11|a1|Add0~33_sumout  & ( \l2|l1|out[0]~3_combout  & ( (\l2|l1|out[1]~7_combout ) # (\uut_add_sub_N|a11|a1|Add0~17_sumout ) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~33_sumout  & ( \l2|l1|out[0]~3_combout  & ( 
+// (\uut_add_sub_N|a11|a1|Add0~17_sumout  & !\l2|l1|out[1]~7_combout ) ) ) ) # ( \uut_add_sub_N|a11|a1|Add0~33_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~13_sumout )) # (\l2|l1|out[1]~7_combout  & 
+// ((\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) ) ) # ( !\uut_add_sub_N|a11|a1|Add0~33_sumout  & ( !\l2|l1|out[0]~3_combout  & ( (!\l2|l1|out[1]~7_combout  & (\uut_add_sub_N|a11|a1|Add0~13_sumout )) # (\l2|l1|out[1]~7_combout  & 
+// ((\uut_add_sub_N|a11|a1|Add0~29_sumout ))) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~17_sumout ),
+	.datab(!\l2|l1|out[1]~7_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~13_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~29_sumout ),
+	.datae(!\uut_add_sub_N|a11|a1|Add0~33_sumout ),
+	.dataf(!\l2|l1|out[0]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|tmp[1][9]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|tmp[1][9]~10 .extended_lut = "off";
+defparam \dsl1|tmp[1][9]~10 .lut_mask = 64'h0C3F0C3F44447777;
+defparam \dsl1|tmp[1][9]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y7_N48
+cyclonev_lcell_comb \dsl1|c[13]~8 (
+// Equation(s):
+// \dsl1|c[13]~8_combout  = ( \l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~9_sumout  & ( (\l2|l1|out[0]~3_combout ) # (\uut_add_sub_N|a11|a1|Add0~5_sumout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( \uut_add_sub_N|a11|a1|Add0~9_sumout  & ( 
+// (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~21_sumout ))) # (\l2|l1|out[0]~3_combout  & (\uut_add_sub_N|a11|a1|Add0~25_sumout )) ) ) ) # ( \l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~9_sumout  & ( 
+// (\uut_add_sub_N|a11|a1|Add0~5_sumout  & !\l2|l1|out[0]~3_combout ) ) ) ) # ( !\l2|l1|out[1]~7_combout  & ( !\uut_add_sub_N|a11|a1|Add0~9_sumout  & ( (!\l2|l1|out[0]~3_combout  & ((\uut_add_sub_N|a11|a1|Add0~21_sumout ))) # (\l2|l1|out[0]~3_combout  & 
+// (\uut_add_sub_N|a11|a1|Add0~25_sumout )) ) ) )
+
+	.dataa(!\uut_add_sub_N|a11|a1|Add0~5_sumout ),
+	.datab(!\l2|l1|out[0]~3_combout ),
+	.datac(!\uut_add_sub_N|a11|a1|Add0~25_sumout ),
+	.datad(!\uut_add_sub_N|a11|a1|Add0~21_sumout ),
+	.datae(!\l2|l1|out[1]~7_combout ),
+	.dataf(!\uut_add_sub_N|a11|a1|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[13]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[13]~8 .extended_lut = "off";
+defparam \dsl1|c[13]~8 .lut_mask = 64'h03CF444403CF7777;
+defparam \dsl1|c[13]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N18
+cyclonev_lcell_comb \dsl1|c[13]~9 (
+// Equation(s):
+// \dsl1|c[13]~9_combout  = ( \dsl1|tmp[1][5]~9_combout  & ( \l2|l1|out[3]~12_combout  & ( (!\l2|l1|out[2]~10_combout ) # (\dsl1|tmp[1][1]~8_combout ) ) ) ) # ( !\dsl1|tmp[1][5]~9_combout  & ( \l2|l1|out[3]~12_combout  & ( (\l2|l1|out[2]~10_combout  & 
+// \dsl1|tmp[1][1]~8_combout ) ) ) ) # ( \dsl1|tmp[1][5]~9_combout  & ( !\l2|l1|out[3]~12_combout  & ( (!\l2|l1|out[2]~10_combout  & ((\dsl1|c[13]~8_combout ))) # (\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][9]~10_combout )) ) ) ) # ( 
+// !\dsl1|tmp[1][5]~9_combout  & ( !\l2|l1|out[3]~12_combout  & ( (!\l2|l1|out[2]~10_combout  & ((\dsl1|c[13]~8_combout ))) # (\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][9]~10_combout )) ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][9]~10_combout ),
+	.datac(!\dsl1|c[13]~8_combout ),
+	.datad(!\dsl1|tmp[1][1]~8_combout ),
+	.datae(!\dsl1|tmp[1][5]~9_combout ),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[13]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[13]~9 .extended_lut = "off";
+defparam \dsl1|c[13]~9 .lut_mask = 64'h1B1B1B1B0055AAFF;
+defparam \dsl1|c[13]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N33
+cyclonev_lcell_comb \dsr2|tmp[0][27]~4 (
+// Equation(s):
+// \dsr2|tmp[0][27]~4_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( !\dsl1|c[15]~0_combout  $ (\uut_add_mantovf|Add0~1_sumout ) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( !\dsl1|c[15]~0_combout  $ (!\uut_add_mantovf|Add0~1_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(gnd),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][27]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][27]~4 .extended_lut = "off";
+defparam \dsr2|tmp[0][27]~4 .lut_mask = 64'h33CC33CCCC33CC33;
+defparam \dsr2|tmp[0][27]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N18
+cyclonev_lcell_comb \dsr2|tmp[1][28]~7 (
+// Equation(s):
+// \dsr2|tmp[1][28]~7_combout  = ( \dsl1|c[13]~9_combout  & ( \dsr2|tmp[0][27]~4_combout  & ( (\uut_reg_ro|r_o[1]~3_combout ) # (\dsl1|c[11]~12_combout ) ) ) ) # ( !\dsl1|c[13]~9_combout  & ( \dsr2|tmp[0][27]~4_combout  & ( (\dsl1|c[11]~12_combout  & 
+// !\uut_reg_ro|r_o[1]~3_combout ) ) ) ) # ( \dsl1|c[13]~9_combout  & ( !\dsr2|tmp[0][27]~4_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][28]~6_combout )) # (\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][30]~5_combout ))) ) ) ) # ( 
+// !\dsl1|c[13]~9_combout  & ( !\dsr2|tmp[0][27]~4_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][28]~6_combout )) # (\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][30]~5_combout ))) ) ) )
+
+	.dataa(!\dsl1|c[11]~12_combout ),
+	.datab(!\dsr2|tmp[0][28]~6_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\dsr2|tmp[0][30]~5_combout ),
+	.datae(!\dsl1|c[13]~9_combout ),
+	.dataf(!\dsr2|tmp[0][27]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][28]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][28]~7 .extended_lut = "off";
+defparam \dsr2|tmp[1][28]~7 .lut_mask = 64'h303F303F50505F5F;
+defparam \dsr2|tmp[1][28]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N36
+cyclonev_lcell_comb \tmp_o[8]~9 (
+// Equation(s):
+// \tmp_o[8]~9_combout  = ( \dsl1|tmp[1][7]~1_combout  & ( (!\l2|l1|out[2]~10_combout ) # (\dsl1|tmp[1][3]~2_combout ) ) ) # ( !\dsl1|tmp[1][7]~1_combout  & ( (\l2|l1|out[2]~10_combout  & \dsl1|tmp[1][3]~2_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(gnd),
+	.datac(!\dsl1|tmp[1][3]~2_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsl1|tmp[1][7]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[8]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[8]~9 .extended_lut = "off";
+defparam \tmp_o[8]~9 .lut_mask = 64'h05050505AFAFAFAF;
+defparam \tmp_o[8]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N45
+cyclonev_lcell_comb \tmp_o[8]~10 (
+// Equation(s):
+// \tmp_o[8]~10_combout  = ( !\l2|l1|out[3]~12_combout  & ( (!\dsl1|c[15]~0_combout  & ((\tmp_o[7]~6_combout ))) # (\dsl1|c[15]~0_combout  & (\tmp_o[8]~9_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\tmp_o[8]~9_combout ),
+	.datac(!\tmp_o[7]~6_combout ),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[8]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[8]~10 .extended_lut = "off";
+defparam \tmp_o[8]~10 .lut_mask = 64'h0F330F3300000000;
+defparam \tmp_o[8]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N12
+cyclonev_lcell_comb \dsl1|c[8]~6 (
+// Equation(s):
+// \dsl1|c[8]~6_combout  = ( \dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][0]~6_combout )) # (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][4]~7_combout ))) ) ) # ( !\dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & 
+// \dsl1|tmp[1][8]~11_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][0]~6_combout ),
+	.datac(!\dsl1|tmp[1][8]~11_combout ),
+	.datad(!\dsl1|tmp[1][4]~7_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[10]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[8]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[8]~6 .extended_lut = "off";
+defparam \dsl1|c[8]~6 .lut_mask = 64'h0A0A0A0A22772277;
+defparam \dsl1|c[8]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N6
+cyclonev_lcell_comb \dsr2|tmp[0][26]~2 (
+// Equation(s):
+// \dsr2|tmp[0][26]~2_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( (!\dsl1|c[15]~0_combout  & (\dsl1|c[8]~6_combout  & ((\uut_add_mantovf|Add0~1_sumout )))) # (\dsl1|c[15]~0_combout  & (((\dsl1|c[10]~5_combout  & !\uut_add_mantovf|Add0~1_sumout )))) ) ) 
+// # ( !\uut_add_mantovf|Add0~13_sumout  & ( (!\dsl1|c[15]~0_combout  & (\dsl1|c[8]~6_combout  & ((!\uut_add_mantovf|Add0~1_sumout )))) # (\dsl1|c[15]~0_combout  & (((\dsl1|c[10]~5_combout  & \uut_add_mantovf|Add0~1_sumout )))) ) )
+
+	.dataa(!\dsl1|c[8]~6_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\dsl1|c[10]~5_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][26]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][26]~2 .extended_lut = "off";
+defparam \dsr2|tmp[0][26]~2 .lut_mask = 64'h4403440303440344;
+defparam \dsr2|tmp[0][26]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N39
+cyclonev_lcell_comb \dsl1|c[9]~4 (
+// Equation(s):
+// \dsl1|c[9]~4_combout  = ( \dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][1]~8_combout )) # (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][5]~9_combout ))) ) ) # ( !\dsl1|c[10]~3_combout  & ( (!\l2|l1|out[2]~10_combout  & 
+// \dsl1|tmp[1][9]~10_combout ) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][9]~10_combout ),
+	.datac(!\dsl1|tmp[1][1]~8_combout ),
+	.datad(!\dsl1|tmp[1][5]~9_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[10]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[9]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[9]~4 .extended_lut = "off";
+defparam \dsl1|c[9]~4 .lut_mask = 64'h222222220A5F0A5F;
+defparam \dsl1|c[9]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N30
+cyclonev_lcell_comb \dsr2|tmp[0][26]~1 (
+// Equation(s):
+// \dsr2|tmp[0][26]~1_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( (\dsl1|c[9]~4_combout  & (!\dsl1|c[15]~0_combout  $ (\uut_add_mantovf|Add0~1_sumout ))) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( (\dsl1|c[9]~4_combout  & (!\dsl1|c[15]~0_combout  $ 
+// (!\uut_add_mantovf|Add0~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[9]~4_combout ),
+	.datac(!\dsl1|c[15]~0_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][26]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][26]~1 .extended_lut = "off";
+defparam \dsr2|tmp[0][26]~1 .lut_mask = 64'h0330033030033003;
+defparam \dsr2|tmp[0][26]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y7_N45
+cyclonev_lcell_comb \dsl1|c[7]~7 (
+// Equation(s):
+// \dsl1|c[7]~7_combout  = ( !\l2|l1|out[3]~12_combout  & ( (!\l2|l1|out[2]~10_combout  & (\dsl1|tmp[1][7]~1_combout )) # (\l2|l1|out[2]~10_combout  & ((\dsl1|tmp[1][3]~2_combout ))) ) )
+
+	.dataa(!\l2|l1|out[2]~10_combout ),
+	.datab(!\dsl1|tmp[1][7]~1_combout ),
+	.datac(!\dsl1|tmp[1][3]~2_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsl1|c[7]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsl1|c[7]~7 .extended_lut = "off";
+defparam \dsl1|c[7]~7 .lut_mask = 64'h2727272700000000;
+defparam \dsl1|c[7]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N9
+cyclonev_lcell_comb \tmp_o[9]~8 (
+// Equation(s):
+// \tmp_o[9]~8_combout  = ( \dsl1|c[7]~7_combout  & ( (!\dsl1|c[15]~0_combout ) # (\dsl1|c[8]~6_combout ) ) ) # ( !\dsl1|c[7]~7_combout  & ( (\dsl1|c[8]~6_combout  & \dsl1|c[15]~0_combout ) ) )
+
+	.dataa(!\dsl1|c[8]~6_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[7]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[9]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[9]~8 .extended_lut = "off";
+defparam \tmp_o[9]~8 .lut_mask = 64'h00550055FF55FF55;
+defparam \tmp_o[9]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N48
+cyclonev_lcell_comb \dsr2|tmp[1][24]~3 (
+// Equation(s):
+// \dsr2|tmp[1][24]~3_combout  = ( \uut_reg_ro|r_o[1]~3_combout  & ( \tmp_o[9]~8_combout  & ( (!\dsr2|tmp[0][26]~2_combout  & !\dsr2|tmp[0][26]~1_combout ) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & ( \tmp_o[9]~8_combout  & ( (!\tmp_o[8]~10_combout  & 
+// !\uut_reg_ro|r_o[0]~2_combout ) ) ) ) # ( \uut_reg_ro|r_o[1]~3_combout  & ( !\tmp_o[9]~8_combout  & ( (!\dsr2|tmp[0][26]~2_combout  & !\dsr2|tmp[0][26]~1_combout ) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & ( !\tmp_o[9]~8_combout  & ( 
+// (!\tmp_o[8]~10_combout ) # (\uut_reg_ro|r_o[0]~2_combout ) ) ) )
+
+	.dataa(!\tmp_o[8]~10_combout ),
+	.datab(!\dsr2|tmp[0][26]~2_combout ),
+	.datac(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datad(!\dsr2|tmp[0][26]~1_combout ),
+	.datae(!\uut_reg_ro|r_o[1]~3_combout ),
+	.dataf(!\tmp_o[9]~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][24]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][24]~3 .extended_lut = "off";
+defparam \dsr2|tmp[1][24]~3 .lut_mask = 64'hAFAFCC00A0A0CC00;
+defparam \dsr2|tmp[1][24]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N30
+cyclonev_lcell_comb \dsr2|tmp[1][32]~8 (
+// Equation(s):
+// \dsr2|tmp[1][32]~8_combout  = ( \uut_add_mantovf|Add0~17_sumout  & ( (!\uut_add_mantovf|Add0~13_sumout ) # ((!\uut_add_mantovf|Add0~1_sumout  & (\uut_add_mantovf|Add0~9_sumout )) # (\uut_add_mantovf|Add0~1_sumout  & ((\uut_add_mantovf|Add0~5_sumout )))) ) 
+// ) # ( !\uut_add_mantovf|Add0~17_sumout  & ( (!\uut_add_mantovf|Add0~13_sumout  & ((!\uut_add_mantovf|Add0~1_sumout  & ((\uut_add_mantovf|Add0~5_sumout ))) # (\uut_add_mantovf|Add0~1_sumout  & (\uut_add_mantovf|Add0~9_sumout )))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~9_sumout ),
+	.datac(!\uut_add_mantovf|Add0~13_sumout ),
+	.datad(!\uut_add_mantovf|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][32]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][32]~8 .extended_lut = "off";
+defparam \dsr2|tmp[1][32]~8 .lut_mask = 64'h10B010B0F2F7F2F7;
+defparam \dsr2|tmp[1][32]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N0
+cyclonev_lcell_comb \dsr2|c[20]~0 (
+// Equation(s):
+// \dsr2|c[20]~0_combout  = ( \dsr2|tmp[1][32]~8_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][28]~7_combout ) # (\uut_reg_ro|r_o[2]~0_combout ) ) ) ) # ( !\dsr2|tmp[1][32]~8_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( 
+// (!\uut_reg_ro|r_o[2]~0_combout  & \dsr2|tmp[1][28]~7_combout ) ) ) ) # ( \dsr2|tmp[1][32]~8_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][20]~0_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// ((!\dsr2|tmp[1][24]~3_combout ))) ) ) ) # ( !\dsr2|tmp[1][32]~8_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][20]~0_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][24]~3_combout ))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\dsr2|tmp[1][20]~0_combout ),
+	.datac(!\dsr2|tmp[1][28]~7_combout ),
+	.datad(!\dsr2|tmp[1][24]~3_combout ),
+	.datae(!\dsr2|tmp[1][32]~8_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[20]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[20]~0 .extended_lut = "off";
+defparam \dsr2|c[20]~0 .lut_mask = 64'h772277220A0A5F5F;
+defparam \dsr2|c[20]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N42
+cyclonev_lcell_comb \dsr2|tmp[1][23]~24 (
+// Equation(s):
+// \dsr2|tmp[1][23]~24_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & ((!\dsl1|c[15]~0_combout  & ((\tmp_o[7]~6_combout ))) # (\dsl1|c[15]~0_combout  & (\tmp_o[8]~9_combout )))) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  
+// & ( (\uut_add_mantovf|Add0~1_sumout  & ((!\dsl1|c[15]~0_combout  & ((\tmp_o[7]~6_combout ))) # (\dsl1|c[15]~0_combout  & (\tmp_o[8]~9_combout )))) ) )
+
+	.dataa(!\dsl1|c[15]~0_combout ),
+	.datab(!\tmp_o[8]~9_combout ),
+	.datac(!\tmp_o[7]~6_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][23]~24_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][23]~24 .extended_lut = "off";
+defparam \dsr2|tmp[1][23]~24 .lut_mask = 64'h001B001B1B001B00;
+defparam \dsr2|tmp[1][23]~24 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N36
+cyclonev_lcell_comb \dsr2|tmp[0][25]~23 (
+// Equation(s):
+// \dsr2|tmp[0][25]~23_combout  = ( \dsl1|c[15]~0_combout  & ( (\dsl1|c[9]~4_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ (!\uut_add_mantovf|Add0~13_sumout ))) ) ) # ( !\dsl1|c[15]~0_combout  & ( (\dsl1|c[7]~7_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ 
+// (\uut_add_mantovf|Add0~13_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\dsl1|c[7]~7_combout ),
+	.datad(!\dsl1|c[9]~4_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[15]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][25]~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][25]~23 .extended_lut = "off";
+defparam \dsr2|tmp[0][25]~23 .lut_mask = 64'h0909090900660066;
+defparam \dsr2|tmp[0][25]~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N39
+cyclonev_lcell_comb \dsr2|tmp[1][23]~25 (
+// Equation(s):
+// \dsr2|tmp[1][23]~25_combout  = ( \tmp_o[7]~6_combout  & ( (!\tmp_o[6]~4_combout  & (\dsl1|c[15]~0_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ (\uut_add_mantovf|Add0~13_sumout )))) # (\tmp_o[6]~4_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ 
+// ((\uut_add_mantovf|Add0~13_sumout )))) ) ) # ( !\tmp_o[7]~6_combout  & ( (\tmp_o[6]~4_combout  & (!\dsl1|c[15]~0_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ (\uut_add_mantovf|Add0~13_sumout )))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\tmp_o[6]~4_combout ),
+	.datad(!\dsl1|c[15]~0_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[7]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][23]~25_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][23]~25 .extended_lut = "off";
+defparam \dsr2|tmp[1][23]~25 .lut_mask = 64'h0900090009990999;
+defparam \dsr2|tmp[1][23]~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N0
+cyclonev_lcell_comb \dsr2|tmp[0][25]~22 (
+// Equation(s):
+// \dsr2|tmp[0][25]~22_combout  = (\dsl1|c[8]~6_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ (!\uut_add_mantovf|Add0~13_sumout  $ (\dsl1|c[15]~0_combout ))))
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\dsl1|c[15]~0_combout ),
+	.datad(!\dsl1|c[8]~6_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][25]~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][25]~22 .extended_lut = "off";
+defparam \dsr2|tmp[0][25]~22 .lut_mask = 64'h0069006900690069;
+defparam \dsr2|tmp[0][25]~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N12
+cyclonev_lcell_comb \dsr2|tmp[1][23]~26 (
+// Equation(s):
+// \dsr2|tmp[1][23]~26_combout  = ( \dsr2|tmp[0][25]~22_combout  & ( \l2|l1|out[3]~12_combout  & ( !\uut_reg_ro|r_o[1]~3_combout  ) ) ) # ( !\dsr2|tmp[0][25]~22_combout  & ( \l2|l1|out[3]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # 
+// (!\dsr2|tmp[0][25]~23_combout ) ) ) ) # ( \dsr2|tmp[0][25]~22_combout  & ( !\l2|l1|out[3]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (!\dsr2|tmp[1][23]~24_combout  & !\dsr2|tmp[1][23]~25_combout )) ) ) ) # ( !\dsr2|tmp[0][25]~22_combout  & ( 
+// !\l2|l1|out[3]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (!\dsr2|tmp[1][23]~24_combout  & ((!\dsr2|tmp[1][23]~25_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((!\dsr2|tmp[0][25]~23_combout )))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\dsr2|tmp[1][23]~24_combout ),
+	.datac(!\dsr2|tmp[0][25]~23_combout ),
+	.datad(!\dsr2|tmp[1][23]~25_combout ),
+	.datae(!\dsr2|tmp[0][25]~22_combout ),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][23]~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][23]~26 .extended_lut = "off";
+defparam \dsr2|tmp[1][23]~26 .lut_mask = 64'hD8508800FAFAAAAA;
+defparam \dsr2|tmp[1][23]~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N21
+cyclonev_lcell_comb \tmp_o[3]~12 (
+// Equation(s):
+// \tmp_o[3]~12_combout  = ( !\tmp_o[1]~0_combout  & ( (!\dsl1|c[15]~0_combout  & (\dsl1|tmp[1][1]~8_combout )) # (\dsl1|c[15]~0_combout  & ((\dsl1|tmp[1][2]~5_combout ))) ) )
+
+	.dataa(!\dsl1|tmp[1][1]~8_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(gnd),
+	.datad(!\dsl1|tmp[1][2]~5_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[3]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[3]~12 .extended_lut = "off";
+defparam \tmp_o[3]~12 .lut_mask = 64'h4477447700000000;
+defparam \tmp_o[3]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N24
+cyclonev_lcell_comb \dsr2|tmp[1][19]~34 (
+// Equation(s):
+// \dsr2|tmp[1][19]~34_combout  = ( \tmp_o[3]~12_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout ) # ((!\uut_reg_ro|r_o[1]~3_combout  & ((\tmp_o[4]~1_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[6]~5_combout ))) ) ) ) # ( 
+// !\tmp_o[3]~12_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\tmp_o[4]~1_combout  & \uut_reg_ro|r_o[0]~2_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((!\uut_reg_ro|r_o[0]~2_combout )) # (\tmp_o[6]~5_combout ))) ) ) ) # ( 
+// \tmp_o[3]~12_combout  & ( !\tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((!\uut_reg_ro|r_o[0]~2_combout ) # (\tmp_o[4]~1_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[6]~5_combout  & ((\uut_reg_ro|r_o[0]~2_combout )))) ) ) ) # ( 
+// !\tmp_o[3]~12_combout  & ( !\tmp_o[5]~3_combout  & ( (\uut_reg_ro|r_o[0]~2_combout  & ((!\uut_reg_ro|r_o[1]~3_combout  & ((\tmp_o[4]~1_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[6]~5_combout )))) ) ) )
+
+	.dataa(!\tmp_o[6]~5_combout ),
+	.datab(!\tmp_o[4]~1_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(!\tmp_o[3]~12_combout ),
+	.dataf(!\tmp_o[5]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][19]~34_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][19]~34 .extended_lut = "off";
+defparam \dsr2|tmp[1][19]~34 .lut_mask = 64'h0035F0350F35FF35;
+defparam \dsr2|tmp[1][19]~34 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N54
+cyclonev_lcell_comb \dsr2|tmp[1][15]~38 (
+// Equation(s):
+// \dsr2|tmp[1][15]~38_combout  = ( \dsl1|tmp[1][0]~6_combout  & ( !\tmp_o[1]~0_combout  & ( (\uut_reg_ro|r_o[1]~3_combout  & ((!\dsl1|c[15]~0_combout  & ((\uut_reg_ro|r_o[0]~2_combout ))) # (\dsl1|c[15]~0_combout  & ((!\uut_reg_ro|r_o[0]~2_combout ) # 
+// (\dsl1|tmp[1][1]~8_combout ))))) ) ) ) # ( !\dsl1|tmp[1][0]~6_combout  & ( !\tmp_o[1]~0_combout  & ( (\dsl1|tmp[1][1]~8_combout  & (\dsl1|c[15]~0_combout  & (\uut_reg_ro|r_o[1]~3_combout  & \uut_reg_ro|r_o[0]~2_combout ))) ) ) )
+
+	.dataa(!\dsl1|tmp[1][1]~8_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(!\dsl1|tmp[1][0]~6_combout ),
+	.dataf(!\tmp_o[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][15]~38_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][15]~38 .extended_lut = "off";
+defparam \dsr2|tmp[1][15]~38 .lut_mask = 64'h0001030D00000000;
+defparam \dsr2|tmp[1][15]~38 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N6
+cyclonev_lcell_comb \dsr2|tmp[0][29]~27 (
+// Equation(s):
+// \dsr2|tmp[0][29]~27_combout  = (!\uut_add_mantovf|Add0~13_sumout  & ((!\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[11]~12_combout )) # (\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[13]~9_combout ))))) # (\uut_add_mantovf|Add0~13_sumout  & 
+// ((!\uut_add_mantovf|Add0~1_sumout  & ((\dsl1|c[13]~9_combout ))) # (\uut_add_mantovf|Add0~1_sumout  & (\dsl1|c[11]~12_combout ))))
+
+	.dataa(!\uut_add_mantovf|Add0~13_sumout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\dsl1|c[11]~12_combout ),
+	.datad(!\dsl1|c[13]~9_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][29]~27_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][29]~27 .extended_lut = "off";
+defparam \dsr2|tmp[0][29]~27 .lut_mask = 64'h096F096F096F096F;
+defparam \dsr2|tmp[0][29]~27 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N39
+cyclonev_lcell_comb \dsr2|tmp[0][27]~14 (
+// Equation(s):
+// \dsr2|tmp[0][27]~14_combout  = ( \dsl1|c[11]~12_combout  & ( (!\uut_add_mantovf|Add0~13_sumout  $ (!\uut_add_mantovf|Add0~1_sumout )) # (\dsl1|c[9]~4_combout ) ) ) # ( !\dsl1|c[11]~12_combout  & ( (\dsl1|c[9]~4_combout  & (!\uut_add_mantovf|Add0~13_sumout 
+//  $ (\uut_add_mantovf|Add0~1_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~13_sumout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\dsl1|c[9]~4_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsl1|c[11]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][27]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][27]~14 .extended_lut = "off";
+defparam \dsr2|tmp[0][27]~14 .lut_mask = 64'h090909096F6F6F6F;
+defparam \dsr2|tmp[0][27]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N24
+cyclonev_lcell_comb \dsr2|tmp[1][27]~28 (
+// Equation(s):
+// \dsr2|tmp[1][27]~28_combout  = ( \dsl1|c[10]~5_combout  & ( \dsr2|tmp[0][27]~4_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # (\dsl1|c[12]~11_combout ) ) ) ) # ( !\dsl1|c[10]~5_combout  & ( \dsr2|tmp[0][27]~4_combout  & ( (\dsl1|c[12]~11_combout  & 
+// \uut_reg_ro|r_o[1]~3_combout ) ) ) ) # ( \dsl1|c[10]~5_combout  & ( !\dsr2|tmp[0][27]~4_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][27]~14_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][29]~27_combout )) ) ) ) # ( 
+// !\dsl1|c[10]~5_combout  & ( !\dsr2|tmp[0][27]~4_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][27]~14_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][29]~27_combout )) ) ) )
+
+	.dataa(!\dsl1|c[12]~11_combout ),
+	.datab(!\dsr2|tmp[0][29]~27_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\dsr2|tmp[0][27]~14_combout ),
+	.datae(!\dsl1|c[10]~5_combout ),
+	.dataf(!\dsr2|tmp[0][27]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][27]~28_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][27]~28 .extended_lut = "off";
+defparam \dsr2|tmp[1][27]~28 .lut_mask = 64'h03F303F30505F5F5;
+defparam \dsr2|tmp[1][27]~28 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N12
+cyclonev_lcell_comb \dsr2|c[15]~20 (
+// Equation(s):
+// \dsr2|c[15]~20_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|tmp[1][27]~28_combout  ) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( !\dsr2|tmp[1][23]~26_combout  ) ) ) # ( 
+// \uut_reg_ro|r_o[2]~0_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|tmp[1][19]~34_combout  ) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|tmp[1][15]~38_combout  ) ) )
+
+	.dataa(!\dsr2|tmp[1][23]~26_combout ),
+	.datab(!\dsr2|tmp[1][19]~34_combout ),
+	.datac(!\dsr2|tmp[1][15]~38_combout ),
+	.datad(!\dsr2|tmp[1][27]~28_combout ),
+	.datae(!\uut_reg_ro|r_o[2]~0_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[15]~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[15]~20 .extended_lut = "off";
+defparam \dsr2|c[15]~20 .lut_mask = 64'h0F0F3333AAAA00FF;
+defparam \dsr2|c[15]~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N3
+cyclonev_lcell_comb \tmp_o[2]~13 (
+// Equation(s):
+// \tmp_o[2]~13_combout  = ( \dsl1|tmp[1][1]~8_combout  & ( (!\tmp_o[1]~0_combout  & ((\dsl1|tmp[1][0]~6_combout ) # (\dsl1|c[15]~0_combout ))) ) ) # ( !\dsl1|tmp[1][1]~8_combout  & ( (!\dsl1|c[15]~0_combout  & (!\tmp_o[1]~0_combout  & 
+// \dsl1|tmp[1][0]~6_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\tmp_o[1]~0_combout ),
+	.datad(!\dsl1|tmp[1][0]~6_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|tmp[1][1]~8_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[2]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[2]~13 .extended_lut = "off";
+defparam \tmp_o[2]~13 .lut_mask = 64'h00C000C030F030F0;
+defparam \tmp_o[2]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N18
+cyclonev_lcell_comb \tmp_o[1]~14 (
+// Equation(s):
+// \tmp_o[1]~14_combout  = ( !\tmp_o[1]~0_combout  & ( (\dsl1|c[15]~0_combout  & \dsl1|tmp[1][0]~6_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\dsl1|tmp[1][0]~6_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[1]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[1]~14 .extended_lut = "off";
+defparam \tmp_o[1]~14 .lut_mask = 64'h0303030300000000;
+defparam \tmp_o[1]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N48
+cyclonev_lcell_comb \dsr2|tmp[1][16]~39 (
+// Equation(s):
+// \dsr2|tmp[1][16]~39_combout  = ( \tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (\uut_reg_ro|r_o[0]~2_combout )) # (\uut_reg_ro|r_o[1]~3_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[2]~13_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & 
+// ((\tmp_o[3]~12_combout ))))) ) ) # ( !\tmp_o[1]~14_combout  & ( (\uut_reg_ro|r_o[1]~3_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[2]~13_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[3]~12_combout ))))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datac(!\tmp_o[2]~13_combout ),
+	.datad(!\tmp_o[3]~12_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][16]~39_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][16]~39 .extended_lut = "off";
+defparam \dsr2|tmp[1][16]~39 .lut_mask = 64'h0415041526372637;
+defparam \dsr2|tmp[1][16]~39 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N18
+cyclonev_lcell_comb \dsr2|c[16]~21 (
+// Equation(s):
+// \dsr2|c[16]~21_combout  = ( \dsr2|tmp[1][20]~0_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][24]~3_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][28]~7_combout )) ) ) ) # ( 
+// !\dsr2|tmp[1][20]~0_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][24]~3_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][28]~7_combout )) ) ) ) # ( \dsr2|tmp[1][20]~0_combout  & ( 
+// !\uut_reg_ro|r_o[3]~1_combout  & ( (\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][16]~39_combout ) ) ) ) # ( !\dsr2|tmp[1][20]~0_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][16]~39_combout  & !\uut_reg_ro|r_o[2]~0_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[1][28]~7_combout ),
+	.datab(!\dsr2|tmp[1][24]~3_combout ),
+	.datac(!\dsr2|tmp[1][16]~39_combout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(!\dsr2|tmp[1][20]~0_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[16]~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[16]~21 .extended_lut = "off";
+defparam \dsr2|c[16]~21 .lut_mask = 64'h0F000FFFCC55CC55;
+defparam \dsr2|c[16]~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N54
+cyclonev_lcell_comb \dsr2|tmp[1][22]~16 (
+// Equation(s):
+// \dsr2|tmp[1][22]~16_combout  = ( \uut_reg_ro|r_o[1]~3_combout  & ( \tmp_o[8]~10_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout ) # (\tmp_o[9]~8_combout ) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & ( \tmp_o[8]~10_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & 
+// (\tmp_o[6]~5_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[7]~7_combout ))) ) ) ) # ( \uut_reg_ro|r_o[1]~3_combout  & ( !\tmp_o[8]~10_combout  & ( (\tmp_o[9]~8_combout  & \uut_reg_ro|r_o[0]~2_combout ) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & ( 
+// !\tmp_o[8]~10_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[6]~5_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[7]~7_combout ))) ) ) )
+
+	.dataa(!\tmp_o[6]~5_combout ),
+	.datab(!\tmp_o[9]~8_combout ),
+	.datac(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datad(!\tmp_o[7]~7_combout ),
+	.datae(!\uut_reg_ro|r_o[1]~3_combout ),
+	.dataf(!\tmp_o[8]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][22]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][22]~16 .extended_lut = "off";
+defparam \dsr2|tmp[1][22]~16 .lut_mask = 64'h505F0303505FF3F3;
+defparam \dsr2|tmp[1][22]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N36
+cyclonev_lcell_comb \dsr2|tmp[0][26]~17 (
+// Equation(s):
+// \dsr2|tmp[0][26]~17_combout  = ( \dsl1|c[8]~6_combout  & ( (!\uut_add_mantovf|Add0~1_sumout  $ (\uut_add_mantovf|Add0~13_sumout )) # (\dsl1|c[10]~5_combout ) ) ) # ( !\dsl1|c[8]~6_combout  & ( (\dsl1|c[10]~5_combout  & (!\uut_add_mantovf|Add0~1_sumout  $ 
+// (!\uut_add_mantovf|Add0~13_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\uut_add_mantovf|Add0~13_sumout ),
+	.datad(!\dsl1|c[10]~5_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[8]~6_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][26]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][26]~17 .extended_lut = "off";
+defparam \dsr2|tmp[0][26]~17 .lut_mask = 64'h003C003CC3FFC3FF;
+defparam \dsr2|tmp[0][26]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N48
+cyclonev_lcell_comb \dsr2|tmp[1][26]~18 (
+// Equation(s):
+// \dsr2|tmp[1][26]~18_combout  = ( \dsr2|tmp[0][26]~17_combout  & ( \dsl1|c[11]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((!\dsr2|tmp[0][27]~4_combout ) # (\dsl1|c[9]~4_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[0][27]~4_combout 
+// )) # (\dsr2|tmp[0][28]~6_combout ))) ) ) ) # ( !\dsr2|tmp[0][26]~17_combout  & ( \dsl1|c[11]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[0][27]~4_combout  & \dsl1|c[9]~4_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & 
+// (((\dsr2|tmp[0][27]~4_combout )) # (\dsr2|tmp[0][28]~6_combout ))) ) ) ) # ( \dsr2|tmp[0][26]~17_combout  & ( !\dsl1|c[11]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((!\dsr2|tmp[0][27]~4_combout ) # (\dsl1|c[9]~4_combout )))) # 
+// (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][28]~6_combout  & (!\dsr2|tmp[0][27]~4_combout ))) ) ) ) # ( !\dsr2|tmp[0][26]~17_combout  & ( !\dsl1|c[11]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[0][27]~4_combout  & 
+// \dsl1|c[9]~4_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][28]~6_combout  & (!\dsr2|tmp[0][27]~4_combout ))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\dsr2|tmp[0][28]~6_combout ),
+	.datac(!\dsr2|tmp[0][27]~4_combout ),
+	.datad(!\dsl1|c[9]~4_combout ),
+	.datae(!\dsr2|tmp[0][26]~17_combout ),
+	.dataf(!\dsl1|c[11]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][26]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][26]~18 .extended_lut = "off";
+defparam \dsr2|tmp[1][26]~18 .lut_mask = 64'h101AB0BA151FB5BF;
+defparam \dsr2|tmp[1][26]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N24
+cyclonev_lcell_comb \dsr2|tmp[1][32]~19 (
+// Equation(s):
+// \dsr2|tmp[1][32]~19_combout  = ( \uut_add_mantovf|Add0~9_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  $ (!\uut_add_mantovf|Add0~13_sumout )) # (\uut_add_mantovf|Add0~5_sumout ) ) ) # ( !\uut_add_mantovf|Add0~9_sumout  & ( (\uut_add_mantovf|Add0~5_sumout  
+// & (!\uut_add_mantovf|Add0~1_sumout  $ (\uut_add_mantovf|Add0~13_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\uut_add_mantovf|Add0~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][32]~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][32]~19 .extended_lut = "off";
+defparam \dsr2|tmp[1][32]~19 .lut_mask = 64'h090909096F6F6F6F;
+defparam \dsr2|tmp[1][32]~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N30
+cyclonev_lcell_comb \dsr2|tmp[1][30]~20 (
+// Equation(s):
+// \dsr2|tmp[1][30]~20_combout  = ( \dsr2|tmp[0][30]~5_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((!\dsr2|tmp[0][27]~4_combout ) # ((\dsl1|c[13]~9_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[1][32]~19_combout )))) ) ) # ( 
+// !\dsr2|tmp[0][30]~5_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][27]~4_combout  & ((\dsl1|c[13]~9_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[1][32]~19_combout )))) ) )
+
+	.dataa(!\dsr2|tmp[0][27]~4_combout ),
+	.datab(!\dsr2|tmp[1][32]~19_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\dsl1|c[13]~9_combout ),
+	.datae(gnd),
+	.dataf(!\dsr2|tmp[0][30]~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][30]~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][30]~20 .extended_lut = "off";
+defparam \dsr2|tmp[1][30]~20 .lut_mask = 64'h03530353A3F3A3F3;
+defparam \dsr2|tmp[1][30]~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N6
+cyclonev_lcell_comb \dsr2|tmp[1][18]~35 (
+// Equation(s):
+// \dsr2|tmp[1][18]~35_combout  = ( \tmp_o[3]~12_combout  & ( \tmp_o[5]~3_combout  & ( ((!\uut_reg_ro|r_o[1]~3_combout  & ((\tmp_o[2]~13_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[4]~1_combout ))) # (\uut_reg_ro|r_o[0]~2_combout ) ) ) ) # ( 
+// !\tmp_o[3]~12_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\tmp_o[2]~13_combout  & !\uut_reg_ro|r_o[0]~2_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((\uut_reg_ro|r_o[0]~2_combout )) # (\tmp_o[4]~1_combout ))) ) ) ) # ( 
+// \tmp_o[3]~12_combout  & ( !\tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\uut_reg_ro|r_o[0]~2_combout ) # (\tmp_o[2]~13_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[4]~1_combout  & ((!\uut_reg_ro|r_o[0]~2_combout )))) ) ) ) # ( 
+// !\tmp_o[3]~12_combout  & ( !\tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & ((!\uut_reg_ro|r_o[1]~3_combout  & ((\tmp_o[2]~13_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\tmp_o[4]~1_combout )))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\tmp_o[4]~1_combout ),
+	.datac(!\tmp_o[2]~13_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(!\tmp_o[3]~12_combout ),
+	.dataf(!\tmp_o[5]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][18]~35_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][18]~35 .extended_lut = "off";
+defparam \dsr2|tmp[1][18]~35 .lut_mask = 64'h1B001BAA1B551BFF;
+defparam \dsr2|tmp[1][18]~35 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N12
+cyclonev_lcell_comb \dsr2|c[18]~18 (
+// Equation(s):
+// \dsr2|c[18]~18_combout  = ( \dsr2|tmp[1][18]~35_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][26]~18_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][30]~20_combout ))) ) ) ) # ( 
+// !\dsr2|tmp[1][18]~35_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][26]~18_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][30]~20_combout ))) ) ) ) # ( \dsr2|tmp[1][18]~35_combout  & ( 
+// !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][22]~16_combout ) ) ) ) # ( !\dsr2|tmp[1][18]~35_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][22]~16_combout  & \uut_reg_ro|r_o[2]~0_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[1][22]~16_combout ),
+	.datab(!\dsr2|tmp[1][26]~18_combout ),
+	.datac(!\dsr2|tmp[1][30]~20_combout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(!\dsr2|tmp[1][18]~35_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[18]~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[18]~18 .extended_lut = "off";
+defparam \dsr2|c[18]~18 .lut_mask = 64'h0055FF55330F330F;
+defparam \dsr2|c[18]~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N54
+cyclonev_lcell_comb \dsr2|tmp[0][31]~10 (
+// Equation(s):
+// \dsr2|tmp[0][31]~10_combout  = ( \uut_add_mantovf|Add0~5_sumout  & ( ((!\dsl1|c[15]~0_combout  & (\dsl1|c[13]~9_combout )) # (\dsl1|c[15]~0_combout  & ((\dsl1|c[14]~2_combout )))) # (\uut_reg_ro|r_o[0]~2_combout ) ) ) # ( !\uut_add_mantovf|Add0~5_sumout  
+// & ( (!\uut_reg_ro|r_o[0]~2_combout  & ((!\dsl1|c[15]~0_combout  & (\dsl1|c[13]~9_combout )) # (\dsl1|c[15]~0_combout  & ((\dsl1|c[14]~2_combout ))))) ) )
+
+	.dataa(!\dsl1|c[13]~9_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\dsl1|c[14]~2_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][31]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][31]~10 .extended_lut = "off";
+defparam \dsr2|tmp[0][31]~10 .lut_mask = 64'h4700470047FF47FF;
+defparam \dsr2|tmp[0][31]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N57
+cyclonev_lcell_comb \dsr2|tmp[0][29]~9 (
+// Equation(s):
+// \dsr2|tmp[0][29]~9_combout  = ( \dsl1|c[11]~12_combout  & ( (!\dsl1|c[15]~0_combout  & (((!\uut_reg_ro|r_o[0]~2_combout ) # (\dsl1|c[12]~11_combout )))) # (\dsl1|c[15]~0_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & ((\dsl1|c[12]~11_combout ))) # 
+// (\uut_reg_ro|r_o[0]~2_combout  & (\dsl1|c[13]~9_combout )))) ) ) # ( !\dsl1|c[11]~12_combout  & ( (!\dsl1|c[15]~0_combout  & (((\uut_reg_ro|r_o[0]~2_combout  & \dsl1|c[12]~11_combout )))) # (\dsl1|c[15]~0_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & 
+// ((\dsl1|c[12]~11_combout ))) # (\uut_reg_ro|r_o[0]~2_combout  & (\dsl1|c[13]~9_combout )))) ) )
+
+	.dataa(!\dsl1|c[13]~9_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datad(!\dsl1|c[12]~11_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[11]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][29]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][29]~9 .extended_lut = "off";
+defparam \dsr2|tmp[0][29]~9 .lut_mask = 64'h013D013DC1FDC1FD;
+defparam \dsr2|tmp[0][29]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N18
+cyclonev_lcell_comb \dsr2|tmp[0][27]~31 (
+// Equation(s):
+// \dsr2|tmp[0][27]~31_combout  = ( \dsl1|c[15]~0_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & (\dsl1|c[10]~5_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\dsl1|c[11]~12_combout ))) ) ) # ( !\dsl1|c[15]~0_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & 
+// (\dsl1|c[9]~4_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\dsl1|c[10]~5_combout ))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datab(!\dsl1|c[9]~4_combout ),
+	.datac(!\dsl1|c[10]~5_combout ),
+	.datad(!\dsl1|c[11]~12_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[15]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][27]~31_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][27]~31 .extended_lut = "off";
+defparam \dsr2|tmp[0][27]~31 .lut_mask = 64'h272727270A5F0A5F;
+defparam \dsr2|tmp[0][27]~31 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N21
+cyclonev_lcell_comb \dsr2|tmp[0][25]~30 (
+// Equation(s):
+// \dsr2|tmp[0][25]~30_combout  = ( \dsl1|c[7]~7_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & (((!\dsl1|c[15]~0_combout ) # (\dsl1|c[8]~6_combout )))) # (\uut_reg_ro|r_o[0]~2_combout  & ((!\dsl1|c[15]~0_combout  & ((\dsl1|c[8]~6_combout ))) # 
+// (\dsl1|c[15]~0_combout  & (\dsl1|c[9]~4_combout )))) ) ) # ( !\dsl1|c[7]~7_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & (((\dsl1|c[15]~0_combout  & \dsl1|c[8]~6_combout )))) # (\uut_reg_ro|r_o[0]~2_combout  & ((!\dsl1|c[15]~0_combout  & 
+// ((\dsl1|c[8]~6_combout ))) # (\dsl1|c[15]~0_combout  & (\dsl1|c[9]~4_combout )))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datab(!\dsl1|c[9]~4_combout ),
+	.datac(!\dsl1|c[15]~0_combout ),
+	.datad(!\dsl1|c[8]~6_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[7]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][25]~30_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][25]~30 .extended_lut = "off";
+defparam \dsr2|tmp[0][25]~30 .lut_mask = 64'h015B015BA1FBA1FB;
+defparam \dsr2|tmp[0][25]~30 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N12
+cyclonev_lcell_comb \dsr2|tmp[2][25]~32 (
+// Equation(s):
+// \dsr2|tmp[2][25]~32_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( \dsr2|tmp[0][25]~30_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][29]~9_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][31]~10_combout )) ) ) ) # ( 
+// !\uut_reg_ro|r_o[2]~0_combout  & ( \dsr2|tmp[0][25]~30_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # (\dsr2|tmp[0][27]~31_combout ) ) ) ) # ( \uut_reg_ro|r_o[2]~0_combout  & ( !\dsr2|tmp[0][25]~30_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & 
+// ((\dsr2|tmp[0][29]~9_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][31]~10_combout )) ) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( !\dsr2|tmp[0][25]~30_combout  & ( (\dsr2|tmp[0][27]~31_combout  & \uut_reg_ro|r_o[1]~3_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[0][31]~10_combout ),
+	.datab(!\dsr2|tmp[0][29]~9_combout ),
+	.datac(!\dsr2|tmp[0][27]~31_combout ),
+	.datad(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datae(!\uut_reg_ro|r_o[2]~0_combout ),
+	.dataf(!\dsr2|tmp[0][25]~30_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[2][25]~32_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[2][25]~32 .extended_lut = "off";
+defparam \dsr2|tmp[2][25]~32 .lut_mask = 64'h000F3355FF0F3355;
+defparam \dsr2|tmp[2][25]~32 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N27
+cyclonev_lcell_comb \rnd_ulp[0]~5 (
+// Equation(s):
+// \rnd_ulp[0]~5_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (((\dsr2|tmp[2][25]~32_combout ) # (\dsr2|tmp[1][19]~34_combout )) # (\dsr2|tmp[1][20]~0_combout )) # (\dsr2|tmp[1][18]~35_combout ) ) )
+
+	.dataa(!\dsr2|tmp[1][18]~35_combout ),
+	.datab(!\dsr2|tmp[1][20]~0_combout ),
+	.datac(!\dsr2|tmp[1][19]~34_combout ),
+	.datad(!\dsr2|tmp[2][25]~32_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~5 .extended_lut = "off";
+defparam \rnd_ulp[0]~5 .lut_mask = 64'h000000007FFF7FFF;
+defparam \rnd_ulp[0]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N42
+cyclonev_lcell_comb \dsr2|tmp[1][21]~15 (
+// Equation(s):
+// \dsr2|tmp[1][21]~15_combout  = ( \tmp_o[6]~5_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[7]~7_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[8]~10_combout )))) ) ) ) # ( 
+// !\tmp_o[6]~5_combout  & ( \tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((!\uut_reg_ro|r_o[0]~2_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[7]~7_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & 
+// ((\tmp_o[8]~10_combout ))))) ) ) ) # ( \tmp_o[6]~5_combout  & ( !\tmp_o[5]~3_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & (((\uut_reg_ro|r_o[0]~2_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[7]~7_combout )) 
+// # (\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[8]~10_combout ))))) ) ) ) # ( !\tmp_o[6]~5_combout  & ( !\tmp_o[5]~3_combout  & ( (\uut_reg_ro|r_o[1]~3_combout  & ((!\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[7]~7_combout )) # (\uut_reg_ro|r_o[0]~2_combout  & 
+// ((\tmp_o[8]~10_combout ))))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\tmp_o[7]~7_combout ),
+	.datac(!\tmp_o[8]~10_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(!\tmp_o[6]~5_combout ),
+	.dataf(!\tmp_o[5]~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][21]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][21]~15 .extended_lut = "off";
+defparam \dsr2|tmp[1][21]~15 .lut_mask = 64'h110511AFBB05BBAF;
+defparam \dsr2|tmp[1][21]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N51
+cyclonev_lcell_comb \rnd_ulp[0]~2 (
+// Equation(s):
+// \rnd_ulp[0]~2_combout  = ( \tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & !\uut_reg_ro|r_o[0]~2_combout ) ) ) # ( !\tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # ((!\tmp_o[2]~13_combout  & ((!\uut_reg_ro|r_o[0]~2_combout ) # 
+// (!\tmp_o[3]~12_combout )))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datac(!\tmp_o[2]~13_combout ),
+	.datad(!\tmp_o[3]~12_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~2 .extended_lut = "off";
+defparam \rnd_ulp[0]~2 .lut_mask = 64'hFAEAFAEA88888888;
+defparam \rnd_ulp[0]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N12
+cyclonev_lcell_comb \dsr2|tmp[1][17]~37 (
+// Equation(s):
+// \dsr2|tmp[1][17]~37_combout  = ( \uut_reg_ro|r_o[1]~3_combout  & ( \tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[3]~12_combout ))) # (\uut_reg_ro|r_o[0]~2_combout  & (\tmp_o[4]~1_combout )) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & 
+// ( \tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout ) # (\tmp_o[2]~13_combout ) ) ) ) # ( \uut_reg_ro|r_o[1]~3_combout  & ( !\tmp_o[1]~14_combout  & ( (!\uut_reg_ro|r_o[0]~2_combout  & ((\tmp_o[3]~12_combout ))) # (\uut_reg_ro|r_o[0]~2_combout  & 
+// (\tmp_o[4]~1_combout )) ) ) ) # ( !\uut_reg_ro|r_o[1]~3_combout  & ( !\tmp_o[1]~14_combout  & ( (\tmp_o[2]~13_combout  & \uut_reg_ro|r_o[0]~2_combout ) ) ) )
+
+	.dataa(!\tmp_o[2]~13_combout ),
+	.datab(!\tmp_o[4]~1_combout ),
+	.datac(!\tmp_o[3]~12_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(!\uut_reg_ro|r_o[1]~3_combout ),
+	.dataf(!\tmp_o[1]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][17]~37_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][17]~37 .extended_lut = "off";
+defparam \dsr2|tmp[1][17]~37 .lut_mask = 64'h00550F33FF550F33;
+defparam \dsr2|tmp[1][17]~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N36
+cyclonev_lcell_comb \rnd_ulp[0]~3 (
+// Equation(s):
+// \rnd_ulp[0]~3_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\dsr2|tmp[1][21]~15_combout  & (\rnd_ulp[0]~2_combout  & !\dsr2|tmp[1][17]~37_combout )) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\dsr2|tmp[1][17]~37_combout  & 
+// ((!\uut_reg_ro|r_o[2]~0_combout ) # ((!\dsr2|tmp[1][21]~15_combout  & \rnd_ulp[0]~2_combout )))) ) )
+
+	.dataa(!\dsr2|tmp[1][21]~15_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\rnd_ulp[0]~2_combout ),
+	.datad(!\dsr2|tmp[1][17]~37_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~3 .extended_lut = "off";
+defparam \rnd_ulp[0]~3 .lut_mask = 64'hCE00CE000A000A00;
+defparam \rnd_ulp[0]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N33
+cyclonev_lcell_comb \dsr2|tmp[0][25]~13 (
+// Equation(s):
+// \dsr2|tmp[0][25]~13_combout  = ( \dsl1|c[7]~7_combout  & ( (!\uut_add_mantovf|Add0~13_sumout  $ (\uut_add_mantovf|Add0~1_sumout )) # (\dsl1|c[9]~4_combout ) ) ) # ( !\dsl1|c[7]~7_combout  & ( (\dsl1|c[9]~4_combout  & (!\uut_add_mantovf|Add0~13_sumout  $ 
+// (!\uut_add_mantovf|Add0~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\dsl1|c[9]~4_combout ),
+	.datac(!\uut_add_mantovf|Add0~13_sumout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[7]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][25]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][25]~13 .extended_lut = "off";
+defparam \dsr2|tmp[0][25]~13 .lut_mask = 64'h03300330F33FF33F;
+defparam \dsr2|tmp[0][25]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N42
+cyclonev_lcell_comb \dsr2|c[21]~1 (
+// Equation(s):
+// \dsr2|c[21]~1_combout  = ( \dsl1|c[10]~5_combout  & ( \dsr2|tmp[0][27]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((!\dsr2|tmp[0][27]~4_combout  & (!\dsr2|tmp[0][25]~13_combout )) # (\dsr2|tmp[0][27]~4_combout  & ((!\dsl1|c[8]~6_combout ))))) ) ) ) 
+// # ( !\dsl1|c[10]~5_combout  & ( \dsr2|tmp[0][27]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((!\dsr2|tmp[0][27]~4_combout  & (!\dsr2|tmp[0][25]~13_combout )) # (\dsr2|tmp[0][27]~4_combout  & ((!\dsl1|c[8]~6_combout ))))) # 
+// (\uut_reg_ro|r_o[1]~3_combout  & (((\dsr2|tmp[0][27]~4_combout )))) ) ) ) # ( \dsl1|c[10]~5_combout  & ( !\dsr2|tmp[0][27]~14_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((!\dsr2|tmp[0][27]~4_combout  & (!\dsr2|tmp[0][25]~13_combout )) # 
+// (\dsr2|tmp[0][27]~4_combout  & ((!\dsl1|c[8]~6_combout ))))) # (\uut_reg_ro|r_o[1]~3_combout  & (((!\dsr2|tmp[0][27]~4_combout )))) ) ) ) # ( !\dsl1|c[10]~5_combout  & ( !\dsr2|tmp[0][27]~14_combout  & ( ((!\dsr2|tmp[0][27]~4_combout  & 
+// (!\dsr2|tmp[0][25]~13_combout )) # (\dsr2|tmp[0][27]~4_combout  & ((!\dsl1|c[8]~6_combout )))) # (\uut_reg_ro|r_o[1]~3_combout ) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\dsr2|tmp[0][25]~13_combout ),
+	.datac(!\dsr2|tmp[0][27]~4_combout ),
+	.datad(!\dsl1|c[8]~6_combout ),
+	.datae(!\dsl1|c[10]~5_combout ),
+	.dataf(!\dsr2|tmp[0][27]~14_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[21]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[21]~1 .extended_lut = "off";
+defparam \dsr2|c[21]~1 .lut_mask = 64'hDFD5DAD08F858A80;
+defparam \dsr2|c[21]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N3
+cyclonev_lcell_comb \rnd_ulp[0]~1 (
+// Equation(s):
+// \rnd_ulp[0]~1_combout  = ( \uut_add_mantovf|Add0~21_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & (!\uut_add_mantovf|Add0~13_sumout  & (!\uut_add_mantovf|Add0~17_sumout  & !\uut_add_mantovf|Add0~25_sumout ))) # (\uut_add_mantovf|Add0~1_sumout  & 
+// (\uut_add_mantovf|Add0~25_sumout  & ((!\uut_add_mantovf|Add0~13_sumout ) # (!\uut_add_mantovf|Add0~17_sumout )))) ) ) # ( !\uut_add_mantovf|Add0~21_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & (!\uut_add_mantovf|Add0~25_sumout  & 
+// ((\uut_add_mantovf|Add0~17_sumout ) # (\uut_add_mantovf|Add0~13_sumout )))) # (\uut_add_mantovf|Add0~1_sumout  & (\uut_add_mantovf|Add0~13_sumout  & (\uut_add_mantovf|Add0~17_sumout  & \uut_add_mantovf|Add0~25_sumout ))) ) )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~13_sumout ),
+	.datac(!\uut_add_mantovf|Add0~17_sumout ),
+	.datad(!\uut_add_mantovf|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~1 .extended_lut = "off";
+defparam \rnd_ulp[0]~1 .lut_mask = 64'h2A012A0180548054;
+defparam \rnd_ulp[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y7_N24
+cyclonev_lcell_comb \rnd_ulp[0]~0 (
+// Equation(s):
+// \rnd_ulp[0]~0_combout  = ( !\dsr2|tmp[1][22]~16_combout  & ( \l2|l1|out[3]~12_combout  & ( (!\uut_reg_ro|r_o[1]~3_combout ) # (!\dsr2|tmp[0][25]~30_combout ) ) ) ) # ( !\dsr2|tmp[1][22]~16_combout  & ( !\l2|l1|out[3]~12_combout  & ( 
+// (!\uut_reg_ro|r_o[1]~3_combout  & (!\dsr2|tmp[1][23]~24_combout  & ((!\dsr2|tmp[1][23]~25_combout )))) # (\uut_reg_ro|r_o[1]~3_combout  & (((!\dsr2|tmp[0][25]~30_combout )))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datab(!\dsr2|tmp[1][23]~24_combout ),
+	.datac(!\dsr2|tmp[0][25]~30_combout ),
+	.datad(!\dsr2|tmp[1][23]~25_combout ),
+	.datae(!\dsr2|tmp[1][22]~16_combout ),
+	.dataf(!\l2|l1|out[3]~12_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~0 .extended_lut = "off";
+defparam \rnd_ulp[0]~0 .lut_mask = 64'hD8500000FAFA0000;
+defparam \rnd_ulp[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y7_N0
+cyclonev_lcell_comb \dsr2|tmp[1][14]~36 (
+// Equation(s):
+// \dsr2|tmp[1][14]~36_combout  = ( !\tmp_o[1]~0_combout  & ( (\dsl1|tmp[1][0]~6_combout  & (\dsl1|c[15]~0_combout  & (\uut_reg_ro|r_o[1]~3_combout  & \uut_reg_ro|r_o[0]~2_combout ))) ) )
+
+	.dataa(!\dsl1|tmp[1][0]~6_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datae(gnd),
+	.dataf(!\tmp_o[1]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][14]~36_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][14]~36 .extended_lut = "off";
+defparam \dsr2|tmp[1][14]~36 .lut_mask = 64'h0001000100000000;
+defparam \dsr2|tmp[1][14]~36 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N48
+cyclonev_lcell_comb \dsr2|c[14]~19 (
+// Equation(s):
+// \dsr2|c[14]~19_combout  = ( \dsr2|tmp[1][18]~35_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][22]~16_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][26]~18_combout ))) ) ) ) # ( 
+// !\dsr2|tmp[1][18]~35_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][22]~16_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][26]~18_combout ))) ) ) ) # ( \dsr2|tmp[1][18]~35_combout  & ( 
+// !\uut_reg_ro|r_o[3]~1_combout  & ( (\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][14]~36_combout ) ) ) ) # ( !\dsr2|tmp[1][18]~35_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][14]~36_combout  & !\uut_reg_ro|r_o[2]~0_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[1][22]~16_combout ),
+	.datab(!\dsr2|tmp[1][26]~18_combout ),
+	.datac(!\dsr2|tmp[1][14]~36_combout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(!\dsr2|tmp[1][18]~35_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[14]~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[14]~19 .extended_lut = "off";
+defparam \dsr2|c[14]~19 .lut_mask = 64'h0F000FFF55335533;
+defparam \dsr2|c[14]~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N54
+cyclonev_lcell_comb \rnd_ulp[0]~4 (
+// Equation(s):
+// \rnd_ulp[0]~4_combout  = ( \rnd_ulp[0]~0_combout  & ( !\dsr2|c[14]~19_combout  & ( (\rnd_ulp[0]~3_combout  & ((!\rnd_ulp[0]~1_combout ) # ((\dsr2|c[21]~1_combout  & \dsr2|tmp[1][24]~3_combout )))) ) ) ) # ( !\rnd_ulp[0]~0_combout  & ( 
+// !\dsr2|c[14]~19_combout  & ( (\rnd_ulp[0]~3_combout  & !\rnd_ulp[0]~1_combout ) ) ) )
+
+	.dataa(!\rnd_ulp[0]~3_combout ),
+	.datab(!\dsr2|c[21]~1_combout ),
+	.datac(!\rnd_ulp[0]~1_combout ),
+	.datad(!\dsr2|tmp[1][24]~3_combout ),
+	.datae(!\rnd_ulp[0]~0_combout ),
+	.dataf(!\dsr2|c[14]~19_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~4 .extended_lut = "off";
+defparam \rnd_ulp[0]~4 .lut_mask = 64'h5050505100000000;
+defparam \rnd_ulp[0]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N54
+cyclonev_lcell_comb \rnd_ulp[0]~6 (
+// Equation(s):
+// \rnd_ulp[0]~6_combout  = ( \rnd_ulp[0]~5_combout  & ( \rnd_ulp[0]~4_combout  ) ) # ( !\rnd_ulp[0]~5_combout  & ( \rnd_ulp[0]~4_combout  & ( (((\dsr2|c[18]~18_combout ) # (\dsr2|c[16]~21_combout )) # (\dsr2|c[15]~20_combout )) # (\dsr2|c[20]~0_combout ) ) 
+// ) ) # ( \rnd_ulp[0]~5_combout  & ( !\rnd_ulp[0]~4_combout  ) ) # ( !\rnd_ulp[0]~5_combout  & ( !\rnd_ulp[0]~4_combout  ) )
+
+	.dataa(!\dsr2|c[20]~0_combout ),
+	.datab(!\dsr2|c[15]~20_combout ),
+	.datac(!\dsr2|c[16]~21_combout ),
+	.datad(!\dsr2|c[18]~18_combout ),
+	.datae(!\rnd_ulp[0]~5_combout ),
+	.dataf(!\rnd_ulp[0]~4_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\rnd_ulp[0]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \rnd_ulp[0]~6 .extended_lut = "off";
+defparam \rnd_ulp[0]~6 .lut_mask = 64'hFFFFFFFF7FFFFFFF;
+defparam \rnd_ulp[0]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N33
+cyclonev_lcell_comb \tmp_o[15]~11 (
+// Equation(s):
+// \tmp_o[15]~11_combout  = ( \dsl1|c[15]~0_combout  & ( \dsl1|c[14]~2_combout  ) ) # ( !\dsl1|c[15]~0_combout  & ( \dsl1|c[13]~9_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsl1|c[13]~9_combout ),
+	.datad(!\dsl1|c[14]~2_combout ),
+	.datae(gnd),
+	.dataf(!\dsl1|c[15]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp_o[15]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp_o[15]~11 .extended_lut = "off";
+defparam \tmp_o[15]~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
+defparam \tmp_o[15]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X53_Y7_N36
+cyclonev_lcell_comb \dsr2|tmp[1][31]~29 (
+// Equation(s):
+// \dsr2|tmp[1][31]~29_combout  = ( \uut_add_mantovf|Add0~5_sumout  & ( \uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout ) # ((!\uut_add_mantovf|Add0~17_sumout  & ((\uut_add_mantovf|Add0~9_sumout ))) # (\uut_add_mantovf|Add0~17_sumout  & 
+// (\tmp_o[15]~11_combout ))) ) ) ) # ( !\uut_add_mantovf|Add0~5_sumout  & ( \uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & (!\uut_add_mantovf|Add0~17_sumout )) # (\uut_add_mantovf|Add0~1_sumout  & ((!\uut_add_mantovf|Add0~17_sumout 
+//  & ((\uut_add_mantovf|Add0~9_sumout ))) # (\uut_add_mantovf|Add0~17_sumout  & (\tmp_o[15]~11_combout )))) ) ) ) # ( \uut_add_mantovf|Add0~5_sumout  & ( !\uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & 
+// ((!\uut_add_mantovf|Add0~17_sumout  & (\tmp_o[15]~11_combout )) # (\uut_add_mantovf|Add0~17_sumout  & ((\uut_add_mantovf|Add0~9_sumout ))))) # (\uut_add_mantovf|Add0~1_sumout  & (!\uut_add_mantovf|Add0~17_sumout )) ) ) ) # ( 
+// !\uut_add_mantovf|Add0~5_sumout  & ( !\uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & ((!\uut_add_mantovf|Add0~17_sumout  & (\tmp_o[15]~11_combout )) # (\uut_add_mantovf|Add0~17_sumout  & ((\uut_add_mantovf|Add0~9_sumout ))))) ) ) 
+// )
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_add_mantovf|Add0~17_sumout ),
+	.datac(!\tmp_o[15]~11_combout ),
+	.datad(!\uut_add_mantovf|Add0~9_sumout ),
+	.datae(!\uut_add_mantovf|Add0~5_sumout ),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][31]~29_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][31]~29 .extended_lut = "off";
+defparam \dsr2|tmp[1][31]~29 .lut_mask = 64'h082A4C6E89CDABEF;
+defparam \dsr2|tmp[1][31]~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N6
+cyclonev_lcell_comb \dsr2|c[19]~16 (
+// Equation(s):
+// \dsr2|c[19]~16_combout  = ( \dsr2|tmp[1][31]~29_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][27]~28_combout ) # (\uut_reg_ro|r_o[2]~0_combout ) ) ) ) # ( !\dsr2|tmp[1][31]~29_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( 
+// (!\uut_reg_ro|r_o[2]~0_combout  & \dsr2|tmp[1][27]~28_combout ) ) ) ) # ( \dsr2|tmp[1][31]~29_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][19]~34_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// ((!\dsr2|tmp[1][23]~26_combout ))) ) ) ) # ( !\dsr2|tmp[1][31]~29_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][19]~34_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][23]~26_combout ))) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\dsr2|tmp[1][19]~34_combout ),
+	.datac(!\dsr2|tmp[1][23]~26_combout ),
+	.datad(!\dsr2|tmp[1][27]~28_combout ),
+	.datae(!\dsr2|tmp[1][31]~29_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[19]~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[19]~16 .extended_lut = "off";
+defparam \dsr2|c[19]~16 .lut_mask = 64'h7272727200AA55FF;
+defparam \dsr2|c[19]~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N0
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~61 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~61_sumout  = SUM(( \dsr2|c[19]~16_combout  ) + ( (\rnd_ulp[0]~6_combout  & \dsr2|c[19]~16_combout ) ) + ( !VCC ))
+// \uut_add_ulp|a1|Add0~62  = CARRY(( \dsr2|c[19]~16_combout  ) + ( (\rnd_ulp[0]~6_combout  & \dsr2|c[19]~16_combout ) ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\rnd_ulp[0]~6_combout ),
+	.datac(!\dsr2|c[19]~16_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~61_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~62 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~61 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~61 .lut_mask = 64'h0000FCFC00000F0F;
+defparam \uut_add_ulp|a1|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N3
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~1 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~1_sumout  = SUM(( \dsr2|c[20]~0_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~62  ))
+// \uut_add_ulp|a1|Add0~2  = CARRY(( \dsr2|c[20]~0_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~62  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsr2|c[20]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~62 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~1_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~1 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \uut_add_ulp|a1|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N48
+cyclonev_lcell_comb \tmp1_o_rnd[0]~0 (
+// Equation(s):
+// \tmp1_o_rnd[0]~0_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\uut_add_ulp|a1|Add0~61_sumout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|c[19]~16_combout )) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( 
+// \uut_add_ulp|a1|Add0~61_sumout  ) )
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(gnd),
+	.datac(!\dsr2|c[19]~16_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~61_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tmp1_o_rnd[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tmp1_o_rnd[0]~0 .extended_lut = "off";
+defparam \tmp1_o_rnd[0]~0 .lut_mask = 64'h00FF00FF05AF05AF;
+defparam \tmp1_o_rnd[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N0
+cyclonev_lcell_comb \Add2~1 (
+// Equation(s):
+// \Add2~1_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~1_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~1_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[20]~0_combout )))) ) + ( !\tmp1_o_rnd[0]~0_combout  ) + ( !VCC ))
+// \Add2~2  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~1_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~1_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[20]~0_combout )))) ) + ( !\tmp1_o_rnd[0]~0_combout  ) + ( !VCC ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[20]~0_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\tmp1_o_rnd[0]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~1_sumout ),
+	.cout(\Add2~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~1 .extended_lut = "off";
+defparam \Add2~1 .lut_mask = 64'h000000FF0000FE10;
+defparam \Add2~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N33
+cyclonev_lcell_comb \out~1 (
+// Equation(s):
+// \out~1_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_ulp|a1|Add0~1_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|c[20]~0_combout )) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~1_sumout  ) )
+
+	.dataa(!\dsr2|c[20]~0_combout ),
+	.datab(gnd),
+	.datac(!\uut_add_ulp|a1|Add0~1_sumout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~1 .extended_lut = "off";
+defparam \out~1 .lut_mask = 64'h0F0F0F0F0F550F55;
+defparam \out~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N48
+cyclonev_lcell_comb \out~2 (
+// Equation(s):
+// \out~2_combout  = ( \out~1_combout  & ( (\out~0_combout  & ((!\ls~0_combout ) # (\Add2~1_sumout ))) ) ) # ( !\out~1_combout  & ( (\out~0_combout  & (\ls~0_combout  & \Add2~1_sumout )) ) )
+
+	.dataa(!\out~0_combout ),
+	.datab(!\ls~0_combout ),
+	.datac(!\Add2~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\out~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~2 .extended_lut = "off";
+defparam \out~2 .lut_mask = 64'h0101010145454545;
+defparam \out~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N33
+cyclonev_lcell_comb \dsr2|tmp[0][33]~11 (
+// Equation(s):
+// \dsr2|tmp[0][33]~11_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout ) # (\uut_add_mantovf|Add0~9_sumout ) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~1_sumout  & \uut_add_mantovf|Add0~9_sumout ) 
+// ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(!\uut_add_mantovf|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[0][33]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[0][33]~11 .extended_lut = "off";
+defparam \dsr2|tmp[0][33]~11 .lut_mask = 64'h00F000F0F0FFF0FF;
+defparam \dsr2|tmp[0][33]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N24
+cyclonev_lcell_comb \dsr2|tmp[2][29]~12 (
+// Equation(s):
+// \dsr2|tmp[2][29]~12_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( \uut_add_mantovf|Add0~1_sumout  & ( (\uut_reg_ro|r_o[1]~3_combout ) # (\dsr2|tmp[0][33]~11_combout ) ) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( \uut_add_mantovf|Add0~1_sumout  & ( 
+// (!\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][29]~9_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][31]~10_combout )) ) ) ) # ( \uut_reg_ro|r_o[2]~0_combout  & ( !\uut_add_mantovf|Add0~1_sumout  & ( (\dsr2|tmp[0][33]~11_combout  & 
+// !\uut_reg_ro|r_o[1]~3_combout ) ) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( !\uut_add_mantovf|Add0~1_sumout  & ( (!\uut_reg_ro|r_o[1]~3_combout  & ((\dsr2|tmp[0][29]~9_combout ))) # (\uut_reg_ro|r_o[1]~3_combout  & (\dsr2|tmp[0][31]~10_combout )) ) ) )
+
+	.dataa(!\dsr2|tmp[0][33]~11_combout ),
+	.datab(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datac(!\dsr2|tmp[0][31]~10_combout ),
+	.datad(!\dsr2|tmp[0][29]~9_combout ),
+	.datae(!\uut_reg_ro|r_o[2]~0_combout ),
+	.dataf(!\uut_add_mantovf|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[2][29]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[2][29]~12 .extended_lut = "off";
+defparam \dsr2|tmp[2][29]~12 .lut_mask = 64'h03CF444403CF7777;
+defparam \dsr2|tmp[2][29]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N39
+cyclonev_lcell_comb \dsr2|c[21]~2 (
+// Equation(s):
+// \dsr2|c[21]~2_combout  = (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][21]~15_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|c[21]~1_combout )))
+
+	.dataa(!\dsr2|tmp[1][21]~15_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[21]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[21]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[21]~2 .extended_lut = "off";
+defparam \dsr2|c[21]~2 .lut_mask = 64'h7474747474747474;
+defparam \dsr2|c[21]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N42
+cyclonev_lcell_comb \dsr2|c[21]~3 (
+// Equation(s):
+// \dsr2|c[21]~3_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|tmp[2][29]~12_combout  ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|c[21]~2_combout  ) )
+
+	.dataa(!\dsr2|tmp[2][29]~12_combout ),
+	.datab(!\dsr2|c[21]~2_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[21]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[21]~3 .extended_lut = "off";
+defparam \dsr2|c[21]~3 .lut_mask = 64'h3333333355555555;
+defparam \dsr2|c[21]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N6
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~5 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~5_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|c[21]~2_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][29]~12_combout ))) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~2  ))
+// \uut_add_ulp|a1|Add0~6  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|c[21]~2_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][29]~12_combout ))) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~2  ))
+
+	.dataa(!\dsr2|c[21]~2_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|tmp[2][29]~12_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~5_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~5 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~5 .lut_mask = 64'h0000FFFF00004747;
+defparam \uut_add_ulp|a1|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N48
+cyclonev_lcell_comb \out~3 (
+// Equation(s):
+// \out~3_combout  = ( \uut_add_ulp|a1|Add0~5_sumout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # ((!\uut_reg_ro|r_o[3]~1_combout ) # (\dsr2|c[21]~3_combout )) ) ) # ( !\uut_add_ulp|a1|Add0~5_sumout  & ( (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|c[21]~3_combout  & 
+// \uut_reg_ro|r_o[3]~1_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[21]~3_combout ),
+	.datad(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~3 .extended_lut = "off";
+defparam \out~3 .lut_mask = 64'h00030003FFCFFFCF;
+defparam \out~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N3
+cyclonev_lcell_comb \Add2~5 (
+// Equation(s):
+// \Add2~5_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~5_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~5_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[21]~3_combout )))) ) + ( GND ) + ( \Add2~2  ))
+// \Add2~6  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~5_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~5_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[21]~3_combout )))) ) + ( GND ) + ( \Add2~2  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[21]~3_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~5_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~5_sumout ),
+	.cout(\Add2~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~5 .extended_lut = "off";
+defparam \Add2~5 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N51
+cyclonev_lcell_comb \out~4 (
+// Equation(s):
+// \out~4_combout  = (\out~0_combout  & ((!\ls~0_combout  & (\out~3_combout )) # (\ls~0_combout  & ((\Add2~5_sumout )))))
+
+	.dataa(!\out~0_combout ),
+	.datab(!\ls~0_combout ),
+	.datac(!\out~3_combout ),
+	.datad(!\Add2~5_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~4 .extended_lut = "off";
+defparam \out~4 .lut_mask = 64'h0415041504150415;
+defparam \out~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N36
+cyclonev_lcell_comb \out~7 (
+// Equation(s):
+// \out~7_combout  = (!\ls~0_combout  & \out~0_combout )
+
+	.dataa(gnd),
+	.datab(!\ls~0_combout ),
+	.datac(!\out~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~7 .extended_lut = "off";
+defparam \out~7 .lut_mask = 64'h0C0C0C0C0C0C0C0C;
+defparam \out~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N0
+cyclonev_lcell_comb \dsr2|tmp[1][34]~21 (
+// Equation(s):
+// \dsr2|tmp[1][34]~21_combout  = ( \uut_add_mantovf|Add0~13_sumout  & ( (\uut_add_mantovf|Add0~1_sumout  & !\uut_add_mantovf|Add0~17_sumout ) ) ) # ( !\uut_add_mantovf|Add0~13_sumout  & ( (!\uut_add_mantovf|Add0~17_sumout ) # (\uut_add_mantovf|Add0~1_sumout 
+// ) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(gnd),
+	.datad(!\uut_add_mantovf|Add0~17_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[1][34]~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[1][34]~21 .extended_lut = "off";
+defparam \dsr2|tmp[1][34]~21 .lut_mask = 64'hFF33FF3333003300;
+defparam \dsr2|tmp[1][34]~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N6
+cyclonev_lcell_comb \dsr2|c[22]~4 (
+// Equation(s):
+// \dsr2|c[22]~4_combout  = ( \dsr2|tmp[1][26]~18_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][30]~20_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][34]~21_combout )) ) ) ) # ( 
+// !\dsr2|tmp[1][26]~18_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][30]~20_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][34]~21_combout )) ) ) ) # ( \dsr2|tmp[1][26]~18_combout  & ( 
+// !\uut_reg_ro|r_o[3]~1_combout  & ( (\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][22]~16_combout ) ) ) ) # ( !\dsr2|tmp[1][26]~18_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][22]~16_combout  & !\uut_reg_ro|r_o[2]~0_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[1][34]~21_combout ),
+	.datab(!\dsr2|tmp[1][22]~16_combout ),
+	.datac(!\dsr2|tmp[1][30]~20_combout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(!\dsr2|tmp[1][26]~18_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[22]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[22]~4 .extended_lut = "off";
+defparam \dsr2|c[22]~4 .lut_mask = 64'h330033FF0F550F55;
+defparam \dsr2|c[22]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N9
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~9 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~9_sumout  = SUM(( \dsr2|c[22]~4_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~6  ))
+// \uut_add_ulp|a1|Add0~10  = CARRY(( \dsr2|c[22]~4_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsr2|c[22]~4_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~9_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~9 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \uut_add_ulp|a1|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N6
+cyclonev_lcell_comb \Add2~9 (
+// Equation(s):
+// \Add2~9_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~9_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~9_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[22]~4_combout )))) ) + ( GND ) + ( \Add2~6  ))
+// \Add2~10  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~9_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~9_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[22]~4_combout )))) ) + ( GND ) + ( \Add2~6  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[22]~4_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~9_sumout ),
+	.cout(\Add2~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~9 .extended_lut = "off";
+defparam \Add2~9 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N36
+cyclonev_lcell_comb \out~6 (
+// Equation(s):
+// \out~6_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\uut_add_ulp|a1|Add0~9_sumout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|c[22]~4_combout ))) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~9_sumout  ) )
+
+	.dataa(gnd),
+	.datab(!\uut_add_ulp|a1|Add0~9_sumout ),
+	.datac(!\dsr2|c[22]~4_combout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~6 .extended_lut = "off";
+defparam \out~6 .lut_mask = 64'h33333333330F330F;
+defparam \out~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N33
+cyclonev_lcell_comb \out~5 (
+// Equation(s):
+// \out~5_combout  = (\ls~0_combout  & \out~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ls~0_combout ),
+	.datad(!\out~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~5 .extended_lut = "off";
+defparam \out~5 .lut_mask = 64'h000F000F000F000F;
+defparam \out~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N45
+cyclonev_lcell_comb \out~8 (
+// Equation(s):
+// \out~8_combout  = ( \out~5_combout  & ( ((\out~7_combout  & \out~6_combout )) # (\Add2~9_sumout ) ) ) # ( !\out~5_combout  & ( (\out~7_combout  & \out~6_combout ) ) )
+
+	.dataa(!\out~7_combout ),
+	.datab(gnd),
+	.datac(!\Add2~9_sumout ),
+	.datad(!\out~6_combout ),
+	.datae(gnd),
+	.dataf(!\out~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~8 .extended_lut = "off";
+defparam \out~8 .lut_mask = 64'h005500550F5F0F5F;
+defparam \out~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N36
+cyclonev_lcell_comb \dsr2|c[23]~5 (
+// Equation(s):
+// \dsr2|c[23]~5_combout  = ( \uut_add_mantovf|Add0~1_sumout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (\dsr2|tmp[1][31]~29_combout ) # (\uut_reg_ro|r_o[2]~0_combout ) ) ) ) # ( !\uut_add_mantovf|Add0~1_sumout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( 
+// (!\uut_reg_ro|r_o[2]~0_combout  & \dsr2|tmp[1][31]~29_combout ) ) ) ) # ( \uut_add_mantovf|Add0~1_sumout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][23]~26_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (\dsr2|tmp[1][27]~28_combout )) ) ) ) # ( !\uut_add_mantovf|Add0~1_sumout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][23]~26_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][27]~28_combout )) ) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\dsr2|tmp[1][27]~28_combout ),
+	.datac(!\dsr2|tmp[1][23]~26_combout ),
+	.datad(!\dsr2|tmp[1][31]~29_combout ),
+	.datae(!\uut_add_mantovf|Add0~1_sumout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[23]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[23]~5 .extended_lut = "off";
+defparam \dsr2|c[23]~5 .lut_mask = 64'hB1B1B1B100AA55FF;
+defparam \dsr2|c[23]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N12
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~13 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~13_sumout  = SUM(( \dsr2|c[23]~5_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~10  ))
+// \uut_add_ulp|a1|Add0~14  = CARRY(( \dsr2|c[23]~5_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(!\dsr2|c[23]~5_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~13_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~13 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~13 .lut_mask = 64'h0000FFFF00003333;
+defparam \uut_add_ulp|a1|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N9
+cyclonev_lcell_comb \Add2~13 (
+// Equation(s):
+// \Add2~13_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~13_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~13_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[23]~5_combout )))) ) + ( \Add2~10  ))
+// \Add2~14  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~13_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~13_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[23]~5_combout )))) ) + ( \Add2~10  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[23]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(\Add2~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~13_sumout ),
+	.cout(\Add2~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~13 .extended_lut = "off";
+defparam \Add2~13 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N57
+cyclonev_lcell_comb \out~9 (
+// Equation(s):
+// \out~9_combout  = ( \uut_add_ulp|a1|Add0~13_sumout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # ((!\uut_reg_ro|r_o[3]~1_combout ) # (\dsr2|c[23]~5_combout )) ) ) # ( !\uut_add_ulp|a1|Add0~13_sumout  & ( (\uut_reg_ro|r_o[2]~0_combout  & 
+// (\uut_reg_ro|r_o[3]~1_combout  & \dsr2|c[23]~5_combout )) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|c[23]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~9 .extended_lut = "off";
+defparam \out~9 .lut_mask = 64'h01010101EFEFEFEF;
+defparam \out~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N51
+cyclonev_lcell_comb \out~10 (
+// Equation(s):
+// \out~10_combout  = ( \out~9_combout  & ( ((\out~5_combout  & \Add2~13_sumout )) # (\out~7_combout ) ) ) # ( !\out~9_combout  & ( (\out~5_combout  & \Add2~13_sumout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\Add2~13_sumout ),
+	.datad(!\out~7_combout ),
+	.datae(gnd),
+	.dataf(!\out~9_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~10 .extended_lut = "off";
+defparam \out~10 .lut_mask = 64'h0505050505FF05FF;
+defparam \out~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N42
+cyclonev_lcell_comb \dsr2|c[24]~6 (
+// Equation(s):
+// \dsr2|c[24]~6_combout  = ( \uut_add_mantovf|Add0~1_sumout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][32]~8_combout ) ) ) ) # ( !\uut_add_mantovf|Add0~1_sumout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( 
+// (\dsr2|tmp[1][32]~8_combout  & !\uut_reg_ro|r_o[2]~0_combout ) ) ) ) # ( \uut_add_mantovf|Add0~1_sumout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][24]~3_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (\dsr2|tmp[1][28]~7_combout )) ) ) ) # ( !\uut_add_mantovf|Add0~1_sumout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\dsr2|tmp[1][24]~3_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][28]~7_combout )) ) ) )
+
+	.dataa(!\dsr2|tmp[1][32]~8_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|tmp[1][28]~7_combout ),
+	.datad(!\dsr2|tmp[1][24]~3_combout ),
+	.datae(!\uut_add_mantovf|Add0~1_sumout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[24]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[24]~6 .extended_lut = "off";
+defparam \dsr2|c[24]~6 .lut_mask = 64'hCF03CF0344447777;
+defparam \dsr2|c[24]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N15
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~17 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~17_sumout  = SUM(( \dsr2|c[24]~6_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~14  ))
+// \uut_add_ulp|a1|Add0~18  = CARRY(( \dsr2|c[24]~6_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~14  ))
+
+	.dataa(!\dsr2|c[24]~6_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~17_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~17 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~17 .lut_mask = 64'h0000FFFF00005555;
+defparam \uut_add_ulp|a1|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N51
+cyclonev_lcell_comb \out~11 (
+// Equation(s):
+// \out~11_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( (!\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_ulp|a1|Add0~17_sumout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[24]~6_combout ))) ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( 
+// \uut_add_ulp|a1|Add0~17_sumout  ) )
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(gnd),
+	.datac(!\uut_add_ulp|a1|Add0~17_sumout ),
+	.datad(!\dsr2|c[24]~6_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~11 .extended_lut = "off";
+defparam \out~11 .lut_mask = 64'h0F0F0F0F0A5F0A5F;
+defparam \out~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N12
+cyclonev_lcell_comb \Add2~17 (
+// Equation(s):
+// \Add2~17_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~17_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~17_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[24]~6_combout )))) ) + ( \Add2~14  ))
+// \Add2~18  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~17_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~17_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[24]~6_combout )))) ) + ( \Add2~14  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[24]~6_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(\Add2~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~17_sumout ),
+	.cout(\Add2~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~17 .extended_lut = "off";
+defparam \Add2~17 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N24
+cyclonev_lcell_comb \out~12 (
+// Equation(s):
+// \out~12_combout  = ( \out~5_combout  & ( ((\out~7_combout  & \out~11_combout )) # (\Add2~17_sumout ) ) ) # ( !\out~5_combout  & ( (\out~7_combout  & \out~11_combout ) ) )
+
+	.dataa(!\out~7_combout ),
+	.datab(gnd),
+	.datac(!\out~11_combout ),
+	.datad(!\Add2~17_sumout ),
+	.datae(gnd),
+	.dataf(!\out~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~12 .extended_lut = "off";
+defparam \out~12 .lut_mask = 64'h0505050505FF05FF;
+defparam \out~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N45
+cyclonev_lcell_comb \dsr2|tmp[2][33]~33 (
+// Equation(s):
+// \dsr2|tmp[2][33]~33_combout  = ( \uut_add_mantovf|Add0~1_sumout  & ( ((\uut_reg_ro|r_o[2]~0_combout ) # (\uut_reg_ro|r_o[1]~3_combout )) # (\dsr2|tmp[0][33]~11_combout ) ) ) # ( !\uut_add_mantovf|Add0~1_sumout  & ( (\dsr2|tmp[0][33]~11_combout  & 
+// (!\uut_reg_ro|r_o[1]~3_combout  & !\uut_reg_ro|r_o[2]~0_combout )) ) )
+
+	.dataa(!\dsr2|tmp[0][33]~11_combout ),
+	.datab(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datac(gnd),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_mantovf|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|tmp[2][33]~33_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|tmp[2][33]~33 .extended_lut = "off";
+defparam \dsr2|tmp[2][33]~33 .lut_mask = 64'h4400440077FF77FF;
+defparam \dsr2|tmp[2][33]~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N51
+cyclonev_lcell_comb \dsr2|c[25]~7 (
+// Equation(s):
+// \dsr2|c[25]~7_combout  = (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|tmp[2][25]~32_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][33]~33_combout )))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(gnd),
+	.datac(!\dsr2|tmp[2][25]~32_combout ),
+	.datad(!\dsr2|tmp[2][33]~33_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[25]~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[25]~7 .extended_lut = "off";
+defparam \dsr2|c[25]~7 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
+defparam \dsr2|c[25]~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N18
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~21 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~21_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|tmp[2][25]~32_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][33]~33_combout ))) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~18  ))
+// \uut_add_ulp|a1|Add0~22  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|tmp[2][25]~32_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][33]~33_combout ))) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~18  ))
+
+	.dataa(!\dsr2|tmp[2][25]~32_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|tmp[2][33]~33_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~21_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~21 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~21 .lut_mask = 64'h0000FFFF00004747;
+defparam \uut_add_ulp|a1|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N15
+cyclonev_lcell_comb \Add2~21 (
+// Equation(s):
+// \Add2~21_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~21_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~21_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[25]~7_combout )))) ) + ( GND ) + ( \Add2~18  ))
+// \Add2~22  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~21_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~21_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[25]~7_combout )))) ) + ( GND ) + ( \Add2~18  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[25]~7_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~21_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~21_sumout ),
+	.cout(\Add2~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~21 .extended_lut = "off";
+defparam \Add2~21 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N3
+cyclonev_lcell_comb \out~13 (
+// Equation(s):
+// \out~13_combout  = ( \dsr2|c[25]~7_combout  & ( ((\uut_reg_ro|r_o[2]~0_combout  & \uut_reg_ro|r_o[3]~1_combout )) # (\uut_add_ulp|a1|Add0~21_sumout ) ) ) # ( !\dsr2|c[25]~7_combout  & ( (\uut_add_ulp|a1|Add0~21_sumout  & ((!\uut_reg_ro|r_o[2]~0_combout ) 
+// # (!\uut_reg_ro|r_o[3]~1_combout ))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(gnd),
+	.datad(!\uut_add_ulp|a1|Add0~21_sumout ),
+	.datae(gnd),
+	.dataf(!\dsr2|c[25]~7_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~13 .extended_lut = "off";
+defparam \out~13 .lut_mask = 64'h00EE00EE11FF11FF;
+defparam \out~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N27
+cyclonev_lcell_comb \out~14 (
+// Equation(s):
+// \out~14_combout  = ( \out~5_combout  & ( ((\out~7_combout  & \out~13_combout )) # (\Add2~21_sumout ) ) ) # ( !\out~5_combout  & ( (\out~7_combout  & \out~13_combout ) ) )
+
+	.dataa(!\out~7_combout ),
+	.datab(gnd),
+	.datac(!\Add2~21_sumout ),
+	.datad(!\out~13_combout ),
+	.datae(gnd),
+	.dataf(!\out~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~14 .extended_lut = "off";
+defparam \out~14 .lut_mask = 64'h005500550F5F0F5F;
+defparam \out~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N18
+cyclonev_lcell_comb \dsr2|c[26]~8 (
+// Equation(s):
+// \dsr2|c[26]~8_combout  = ( \dsr2|tmp[1][26]~18_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][34]~21_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_mantovf|Add0~1_sumout ))) ) ) ) # ( 
+// !\dsr2|tmp[1][26]~18_combout  & ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][34]~21_combout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_mantovf|Add0~1_sumout ))) ) ) ) # ( \dsr2|tmp[1][26]~18_combout  & ( 
+// !\uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][30]~20_combout ) ) ) ) # ( !\dsr2|tmp[1][26]~18_combout  & ( !\uut_reg_ro|r_o[3]~1_combout  & ( (\uut_reg_ro|r_o[2]~0_combout  & \dsr2|tmp[1][30]~20_combout ) ) ) )
+
+	.dataa(!\dsr2|tmp[1][34]~21_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|tmp[1][30]~20_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(!\dsr2|tmp[1][26]~18_combout ),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[26]~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[26]~8 .extended_lut = "off";
+defparam \dsr2|c[26]~8 .lut_mask = 64'h0303CFCF44774477;
+defparam \dsr2|c[26]~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N21
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~25 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~25_sumout  = SUM(( \dsr2|c[26]~8_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~22  ))
+// \uut_add_ulp|a1|Add0~26  = CARRY(( \dsr2|c[26]~8_combout  ) + ( GND ) + ( \uut_add_ulp|a1|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsr2|c[26]~8_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~25_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~25 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \uut_add_ulp|a1|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N39
+cyclonev_lcell_comb \out~15 (
+// Equation(s):
+// \out~15_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\uut_add_ulp|a1|Add0~25_sumout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|c[26]~8_combout ))) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~25_sumout  ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(gnd),
+	.datac(!\uut_add_ulp|a1|Add0~25_sumout ),
+	.datad(!\dsr2|c[26]~8_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~15 .extended_lut = "off";
+defparam \out~15 .lut_mask = 64'h0F0F0F0F0A5F0A5F;
+defparam \out~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N18
+cyclonev_lcell_comb \Add2~25 (
+// Equation(s):
+// \Add2~25_sumout  = SUM(( (!\uut_reg_ro|r_o[2]~0_combout  & (((!\uut_add_ulp|a1|Add0~25_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_add_ulp|a1|Add0~25_sumout ))) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// (!\dsr2|c[26]~8_combout )))) ) + ( GND ) + ( \Add2~22  ))
+// \Add2~26  = CARRY(( (!\uut_reg_ro|r_o[2]~0_combout  & (((!\uut_add_ulp|a1|Add0~25_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_add_ulp|a1|Add0~25_sumout ))) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// (!\dsr2|c[26]~8_combout )))) ) + ( GND ) + ( \Add2~22  ))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|c[26]~8_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~25_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~25_sumout ),
+	.cout(\Add2~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~25 .extended_lut = "off";
+defparam \Add2~25 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N42
+cyclonev_lcell_comb \out~16 (
+// Equation(s):
+// \out~16_combout  = ( \Add2~25_sumout  & ( ((\out~7_combout  & \out~15_combout )) # (\out~5_combout ) ) ) # ( !\Add2~25_sumout  & ( (\out~7_combout  & \out~15_combout ) ) )
+
+	.dataa(!\out~7_combout ),
+	.datab(!\out~15_combout ),
+	.datac(!\out~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add2~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~16_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~16 .extended_lut = "off";
+defparam \out~16 .lut_mask = 64'h111111111F1F1F1F;
+defparam \out~16 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N24
+cyclonev_lcell_comb \dsr2|c[27]~9 (
+// Equation(s):
+// \dsr2|c[27]~9_combout  = ( \dsr2|tmp[1][27]~28_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # (\dsr2|tmp[1][31]~29_combout ) ) ) # ( !\dsr2|tmp[1][27]~28_combout  & ( (\uut_reg_ro|r_o[2]~0_combout  & \dsr2|tmp[1][31]~29_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datad(!\dsr2|tmp[1][31]~29_combout ),
+	.datae(gnd),
+	.dataf(!\dsr2|tmp[1][27]~28_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[27]~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[27]~9 .extended_lut = "off";
+defparam \dsr2|c[27]~9 .lut_mask = 64'h000F000FF0FFF0FF;
+defparam \dsr2|c[27]~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N24
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~29 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~29_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[27]~9_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~26  ))
+// \uut_add_ulp|a1|Add0~30  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[27]~9_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~26  ))
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|c[27]~9_combout ),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~29_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~29 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~29 .lut_mask = 64'h0000EE2200000000;
+defparam \uut_add_ulp|a1|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N30
+cyclonev_lcell_comb \dsr2|c[27]~10 (
+// Equation(s):
+// \dsr2|c[27]~10_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( \uut_add_mantovf|Add0~1_sumout  ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|c[27]~9_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dsr2|c[27]~9_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[27]~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[27]~10 .extended_lut = "off";
+defparam \dsr2|c[27]~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
+defparam \dsr2|c[27]~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N54
+cyclonev_lcell_comb \out~17 (
+// Equation(s):
+// \out~17_combout  = ( \dsr2|c[27]~10_combout  & ( ((\uut_reg_ro|r_o[2]~0_combout  & \uut_reg_ro|r_o[3]~1_combout )) # (\uut_add_ulp|a1|Add0~29_sumout ) ) ) # ( !\dsr2|c[27]~10_combout  & ( (\uut_add_ulp|a1|Add0~29_sumout  & ((!\uut_reg_ro|r_o[2]~0_combout 
+// ) # (!\uut_reg_ro|r_o[3]~1_combout ))) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_ulp|a1|Add0~29_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|c[27]~10_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~17 .extended_lut = "off";
+defparam \out~17 .lut_mask = 64'h0E0E0E0E1F1F1F1F;
+defparam \out~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N21
+cyclonev_lcell_comb \Add2~29 (
+// Equation(s):
+// \Add2~29_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & (((!\uut_add_ulp|a1|Add0~29_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_add_ulp|a1|Add0~29_sumout ))) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// (!\dsr2|c[27]~10_combout )))) ) + ( \Add2~26  ))
+// \Add2~30  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & (((!\uut_add_ulp|a1|Add0~29_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_add_ulp|a1|Add0~29_sumout ))) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// (!\dsr2|c[27]~10_combout )))) ) + ( \Add2~26  ))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|c[27]~10_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(\Add2~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~29_sumout ),
+	.cout(\Add2~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~29 .extended_lut = "off";
+defparam \Add2~29 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N6
+cyclonev_lcell_comb \out~18 (
+// Equation(s):
+// \out~18_combout  = ( \Add2~29_sumout  & ( ((\out~17_combout  & \out~7_combout )) # (\out~5_combout ) ) ) # ( !\Add2~29_sumout  & ( (\out~17_combout  & \out~7_combout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\out~17_combout ),
+	.datad(!\out~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add2~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~18_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~18 .extended_lut = "off";
+defparam \out~18 .lut_mask = 64'h000F000F555F555F;
+defparam \out~18 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N33
+cyclonev_lcell_comb \dsr2|c[28]~11 (
+// Equation(s):
+// \dsr2|c[28]~11_combout  = ( \uut_reg_ro|r_o[2]~0_combout  & ( \dsr2|tmp[1][32]~8_combout  ) ) # ( !\uut_reg_ro|r_o[2]~0_combout  & ( \dsr2|tmp[1][28]~7_combout  ) )
+
+	.dataa(!\dsr2|tmp[1][28]~7_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dsr2|tmp[1][32]~8_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[28]~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[28]~11 .extended_lut = "off";
+defparam \dsr2|c[28]~11 .lut_mask = 64'h5555555500FF00FF;
+defparam \dsr2|c[28]~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X48_Y6_N48
+cyclonev_lcell_comb \dsr2|c[28]~12 (
+// Equation(s):
+// \dsr2|c[28]~12_combout  = (!\uut_reg_ro|r_o[3]~1_combout  & (\dsr2|c[28]~11_combout )) # (\uut_reg_ro|r_o[3]~1_combout  & ((\uut_add_mantovf|Add0~1_sumout )))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(gnd),
+	.datac(!\dsr2|c[28]~11_combout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[28]~12_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[28]~12 .extended_lut = "off";
+defparam \dsr2|c[28]~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
+defparam \dsr2|c[28]~12 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N27
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~33 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~33_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[28]~11_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~30  ))
+// \uut_add_ulp|a1|Add0~34  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[28]~11_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|c[28]~11_combout ),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~33_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~33 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~33 .lut_mask = 64'h0000FC3000000000;
+defparam \uut_add_ulp|a1|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N51
+cyclonev_lcell_comb \out~19 (
+// Equation(s):
+// \out~19_combout  = ( \uut_add_ulp|a1|Add0~33_sumout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # ((!\uut_reg_ro|r_o[3]~1_combout ) # (\dsr2|c[28]~12_combout )) ) ) # ( !\uut_add_ulp|a1|Add0~33_sumout  & ( (\uut_reg_ro|r_o[2]~0_combout  & 
+// (\dsr2|c[28]~12_combout  & \uut_reg_ro|r_o[3]~1_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[28]~12_combout ),
+	.datad(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~19_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~19 .extended_lut = "off";
+defparam \out~19 .lut_mask = 64'h00030003FFCFFFCF;
+defparam \out~19 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N24
+cyclonev_lcell_comb \Add2~33 (
+// Equation(s):
+// \Add2~33_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~33_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~33_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[28]~12_combout )))) ) + ( \Add2~30  ))
+// \Add2~34  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~33_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~33_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[28]~12_combout )))) ) + ( \Add2~30  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[28]~12_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(\Add2~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~33_sumout ),
+	.cout(\Add2~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~33 .extended_lut = "off";
+defparam \Add2~33 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N9
+cyclonev_lcell_comb \out~20 (
+// Equation(s):
+// \out~20_combout  = ( \Add2~33_sumout  & ( ((\out~19_combout  & \out~7_combout )) # (\out~5_combout ) ) ) # ( !\Add2~33_sumout  & ( (\out~19_combout  & \out~7_combout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\out~19_combout ),
+	.datad(!\out~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add2~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~20_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~20 .extended_lut = "off";
+defparam \out~20 .lut_mask = 64'h000F000F555F555F;
+defparam \out~20 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N45
+cyclonev_lcell_comb \dsr2|c[29]~13 (
+// Equation(s):
+// \dsr2|c[29]~13_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( \uut_add_mantovf|Add0~1_sumout  ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|tmp[2][29]~12_combout  ) )
+
+	.dataa(!\dsr2|tmp[2][29]~12_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[29]~13_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[29]~13 .extended_lut = "off";
+defparam \dsr2|c[29]~13 .lut_mask = 64'h5555555500FF00FF;
+defparam \dsr2|c[29]~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N30
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~37 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~37_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][29]~12_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~34  ))
+// \uut_add_ulp|a1|Add0~38  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][29]~12_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~34  ))
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(gnd),
+	.datad(!\dsr2|tmp[2][29]~12_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~37_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~37 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~37 .lut_mask = 64'h0000FFFF000011DD;
+defparam \uut_add_ulp|a1|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N15
+cyclonev_lcell_comb \out~21 (
+// Equation(s):
+// \out~21_combout  = ( \uut_add_ulp|a1|Add0~37_sumout  & ( (!\uut_reg_ro|r_o[2]~0_combout ) # ((!\uut_reg_ro|r_o[3]~1_combout ) # (\dsr2|c[29]~13_combout )) ) ) # ( !\uut_add_ulp|a1|Add0~37_sumout  & ( (\uut_reg_ro|r_o[2]~0_combout  & 
+// (\uut_reg_ro|r_o[3]~1_combout  & \dsr2|c[29]~13_combout )) ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(gnd),
+	.datad(!\dsr2|c[29]~13_combout ),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~21_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~21 .extended_lut = "off";
+defparam \out~21 .lut_mask = 64'h00110011EEFFEEFF;
+defparam \out~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N27
+cyclonev_lcell_comb \Add2~37 (
+// Equation(s):
+// \Add2~37_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~37_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~37_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[29]~13_combout )))) ) + ( \Add2~34  ))
+// \Add2~38  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~37_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~37_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[29]~13_combout )))) ) + ( \Add2~34  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[29]~13_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~37_sumout ),
+	.datag(gnd),
+	.cin(\Add2~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~37_sumout ),
+	.cout(\Add2~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~37 .extended_lut = "off";
+defparam \Add2~37 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N48
+cyclonev_lcell_comb \out~22 (
+// Equation(s):
+// \out~22_combout  = ( \out~5_combout  & ( ((\out~21_combout  & \out~7_combout )) # (\Add2~37_sumout ) ) ) # ( !\out~5_combout  & ( (\out~21_combout  & \out~7_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\out~21_combout ),
+	.datac(!\out~7_combout ),
+	.datad(!\Add2~37_sumout ),
+	.datae(gnd),
+	.dataf(!\out~5_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~22_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~22 .extended_lut = "off";
+defparam \out~22 .lut_mask = 64'h0303030303FF03FF;
+defparam \out~22 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N54
+cyclonev_lcell_comb \dsr2|c[30]~14 (
+// Equation(s):
+// \dsr2|c[30]~14_combout  = (!\uut_reg_ro|r_o[2]~0_combout  & ((\dsr2|tmp[1][30]~20_combout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|tmp[1][34]~21_combout ))
+
+	.dataa(!\dsr2|tmp[1][34]~21_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|tmp[1][30]~20_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[30]~14_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[30]~14 .extended_lut = "off";
+defparam \dsr2|c[30]~14 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
+defparam \dsr2|c[30]~14 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N57
+cyclonev_lcell_comb \dsr2|c[30]~15 (
+// Equation(s):
+// \dsr2|c[30]~15_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( \uut_add_mantovf|Add0~1_sumout  ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( \dsr2|c[30]~14_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(!\dsr2|c[30]~14_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[30]~15_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[30]~15 .extended_lut = "off";
+defparam \dsr2|c[30]~15 .lut_mask = 64'h00FF00FF0F0F0F0F;
+defparam \dsr2|c[30]~15 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N33
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~41 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~41_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[30]~14_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~38  ))
+// \uut_add_ulp|a1|Add0~42  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|c[30]~14_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~38  ))
+
+	.dataa(!\uut_add_mantovf|Add0~1_sumout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\dsr2|c[30]~14_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~41_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~41 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~41 .lut_mask = 64'h0000FFFF00001D1D;
+defparam \uut_add_ulp|a1|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N30
+cyclonev_lcell_comb \Add2~41 (
+// Equation(s):
+// \Add2~41_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~41_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~41_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[30]~15_combout )))) ) + ( GND ) + ( \Add2~38  ))
+// \Add2~42  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~41_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~41_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\dsr2|c[30]~15_combout )))) ) + ( GND ) + ( \Add2~38  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\dsr2|c[30]~15_combout ),
+	.datad(!\uut_add_ulp|a1|Add0~41_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~41_sumout ),
+	.cout(\Add2~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~41 .extended_lut = "off";
+defparam \Add2~41 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X52_Y6_N3
+cyclonev_lcell_comb \out~23 (
+// Equation(s):
+// \out~23_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_ulp|a1|Add0~41_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & (\dsr2|c[30]~15_combout )) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~41_sumout  ) )
+
+	.dataa(!\dsr2|c[30]~15_combout ),
+	.datab(gnd),
+	.datac(!\uut_add_ulp|a1|Add0~41_sumout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~23_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~23 .extended_lut = "off";
+defparam \out~23 .lut_mask = 64'h0F0F0F0F0F550F55;
+defparam \out~23 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N18
+cyclonev_lcell_comb \out~24 (
+// Equation(s):
+// \out~24_combout  = ( \out~23_combout  & ( ((\out~5_combout  & \Add2~41_sumout )) # (\out~7_combout ) ) ) # ( !\out~23_combout  & ( (\out~5_combout  & \Add2~41_sumout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\out~7_combout ),
+	.datad(!\Add2~41_sumout ),
+	.datae(gnd),
+	.dataf(!\out~23_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~24_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~24 .extended_lut = "off";
+defparam \out~24 .lut_mask = 64'h005500550F5F0F5F;
+defparam \out~24 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N36
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~45 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~45_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[1][31]~29_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )))) # 
+// (\uut_reg_ro|r_o[2]~0_combout  & (((\uut_add_mantovf|Add0~1_sumout )))) ) + ( \uut_add_ulp|a1|Add0~42  ))
+// \uut_add_ulp|a1|Add0~46  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[1][31]~29_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (((\uut_add_mantovf|Add0~1_sumout )))) ) + ( \uut_add_ulp|a1|Add0~42  ))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|tmp[1][31]~29_combout ),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~45_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~45 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~45 .lut_mask = 64'h0000F87000000000;
+defparam \uut_add_ulp|a1|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N12
+cyclonev_lcell_comb \out~25 (
+// Equation(s):
+// \out~25_combout  = (!\uut_reg_ro|r_o[2]~0_combout  & (((\uut_add_ulp|a1|Add0~45_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_ulp|a1|Add0~45_sumout )) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// ((\uut_add_mantovf|Add0~1_sumout )))))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_ulp|a1|Add0~45_sumout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~25_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~25 .extended_lut = "off";
+defparam \out~25 .lut_mask = 64'h0E1F0E1F0E1F0E1F;
+defparam \out~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N33
+cyclonev_lcell_comb \Add2~45 (
+// Equation(s):
+// \Add2~45_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~45_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~45_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( \Add2~42  ))
+// \Add2~46  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~45_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~45_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( \Add2~42  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~45_sumout ),
+	.datag(gnd),
+	.cin(\Add2~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~45_sumout ),
+	.cout(\Add2~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~45 .extended_lut = "off";
+defparam \Add2~45 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N30
+cyclonev_lcell_comb \out~26 (
+// Equation(s):
+// \out~26_combout  = ( \Add2~45_sumout  & ( ((\out~25_combout  & \out~7_combout )) # (\out~5_combout ) ) ) # ( !\Add2~45_sumout  & ( (\out~25_combout  & \out~7_combout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(!\out~25_combout ),
+	.datac(!\out~7_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\Add2~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~26_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~26 .extended_lut = "off";
+defparam \out~26 .lut_mask = 64'h0303030357575757;
+defparam \out~26 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N39
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~49 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~49_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[1][32]~8_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout 
+//  & (((\uut_add_mantovf|Add0~1_sumout )))) ) + ( \uut_add_ulp|a1|Add0~46  ))
+// \uut_add_ulp|a1|Add0~50  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[1][32]~8_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (((\uut_add_mantovf|Add0~1_sumout )))) ) + ( \uut_add_ulp|a1|Add0~46  ))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|tmp[1][32]~8_combout ),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~49_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~49 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~49 .lut_mask = 64'h0000F87000000000;
+defparam \uut_add_ulp|a1|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N0
+cyclonev_lcell_comb \out~27 (
+// Equation(s):
+// \out~27_combout  = (!\uut_reg_ro|r_o[2]~0_combout  & (((\uut_add_ulp|a1|Add0~49_sumout )))) # (\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_ulp|a1|Add0~49_sumout )) # (\uut_reg_ro|r_o[3]~1_combout  & 
+// ((\uut_add_mantovf|Add0~1_sumout )))))
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datac(!\uut_add_ulp|a1|Add0~49_sumout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~27_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~27 .extended_lut = "off";
+defparam \out~27 .lut_mask = 64'h0E1F0E1F0E1F0E1F;
+defparam \out~27 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N36
+cyclonev_lcell_comb \Add2~49 (
+// Equation(s):
+// \Add2~49_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~49_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~49_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( \Add2~46  ))
+// \Add2~50  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~49_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~49_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( \Add2~46  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~49_sumout ),
+	.datag(gnd),
+	.cin(\Add2~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~49_sumout ),
+	.cout(\Add2~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~49 .extended_lut = "off";
+defparam \Add2~49 .lut_mask = 64'h000001EF00000000;
+defparam \Add2~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N21
+cyclonev_lcell_comb \out~28 (
+// Equation(s):
+// \out~28_combout  = ( \Add2~49_sumout  & ( ((\out~27_combout  & \out~7_combout )) # (\out~5_combout ) ) ) # ( !\Add2~49_sumout  & ( (\out~27_combout  & \out~7_combout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\out~27_combout ),
+	.datad(!\out~7_combout ),
+	.datae(gnd),
+	.dataf(!\Add2~49_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~28_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~28 .extended_lut = "off";
+defparam \out~28 .lut_mask = 64'h000F000F555F555F;
+defparam \out~28 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N42
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~53 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~53_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][33]~33_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~50  ))
+// \uut_add_ulp|a1|Add0~54  = CARRY(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & ((\dsr2|tmp[2][33]~33_combout ))) # (\uut_reg_ro|r_o[3]~1_combout  & (\uut_add_mantovf|Add0~1_sumout )) ) + ( \uut_add_ulp|a1|Add0~50  ))
+
+	.dataa(gnd),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dsr2|tmp[2][33]~33_combout ),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~53_sumout ),
+	.cout(\uut_add_ulp|a1|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~53 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~53 .lut_mask = 64'h0000FC0C00000000;
+defparam \uut_add_ulp|a1|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N39
+cyclonev_lcell_comb \Add2~53 (
+// Equation(s):
+// \Add2~53_sumout  = SUM(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~53_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~53_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( GND ) + ( \Add2~50  ))
+// \Add2~54  = CARRY(( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~53_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~53_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( GND ) + ( \Add2~50  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(!\uut_add_ulp|a1|Add0~53_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\Add2~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~53_sumout ),
+	.cout(\Add2~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~53 .extended_lut = "off";
+defparam \Add2~53 .lut_mask = 64'h0000FFFF0000FE10;
+defparam \Add2~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N57
+cyclonev_lcell_comb \out~29 (
+// Equation(s):
+// \out~29_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\uut_add_ulp|a1|Add0~53_sumout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_mantovf|Add0~1_sumout ))) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~53_sumout  ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(gnd),
+	.datac(!\uut_add_ulp|a1|Add0~53_sumout ),
+	.datad(!\uut_add_mantovf|Add0~1_sumout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~29_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~29 .extended_lut = "off";
+defparam \out~29 .lut_mask = 64'h0F0F0F0F0A5F0A5F;
+defparam \out~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N54
+cyclonev_lcell_comb \out~30 (
+// Equation(s):
+// \out~30_combout  = ( \out~29_combout  & ( ((\out~5_combout  & \Add2~53_sumout )) # (\out~7_combout ) ) ) # ( !\out~29_combout  & ( (\out~5_combout  & \Add2~53_sumout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\out~7_combout ),
+	.datad(!\Add2~53_sumout ),
+	.datae(gnd),
+	.dataf(!\out~29_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~30_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~30 .extended_lut = "off";
+defparam \out~30 .lut_mask = 64'h005500550F5F0F5F;
+defparam \out~30 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N54
+cyclonev_lcell_comb \dsr2|c[13]~17 (
+// Equation(s):
+// \dsr2|c[13]~17_combout  = ( \uut_reg_ro|r_o[3]~1_combout  ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( \uut_reg_ro|r_o[2]~0_combout  ) )
+
+	.dataa(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dsr2|c[13]~17_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dsr2|c[13]~17 .extended_lut = "off";
+defparam \dsr2|c[13]~17 .lut_mask = 64'h55555555FFFFFFFF;
+defparam \dsr2|c[13]~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X47_Y6_N45
+cyclonev_lcell_comb \uut_add_ulp|a1|Add0~57 (
+// Equation(s):
+// \uut_add_ulp|a1|Add0~57_sumout  = SUM(( !\uut_add_mantovf|Add0~1_sumout  $ ((((\dsr2|c[13]~17_combout ) # (\uut_reg_ro|r_o[1]~3_combout )) # (\uut_reg_ro|r_o[0]~2_combout ))) ) + ( GND ) + ( \uut_add_ulp|a1|Add0~54  ))
+
+	.dataa(!\uut_reg_ro|r_o[0]~2_combout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\uut_reg_ro|r_o[1]~3_combout ),
+	.datad(!\dsr2|c[13]~17_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\uut_add_ulp|a1|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\uut_add_ulp|a1|Add0~57_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \uut_add_ulp|a1|Add0~57 .extended_lut = "off";
+defparam \uut_add_ulp|a1|Add0~57 .lut_mask = 64'h0000FFFF00009333;
+defparam \uut_add_ulp|a1|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y6_N42
+cyclonev_lcell_comb \Add2~57 (
+// Equation(s):
+// \Add2~57_sumout  = SUM(( GND ) + ( (!\uut_reg_ro|r_o[3]~1_combout  & (((!\uut_add_ulp|a1|Add0~57_sumout )))) # (\uut_reg_ro|r_o[3]~1_combout  & ((!\uut_reg_ro|r_o[2]~0_combout  & ((!\uut_add_ulp|a1|Add0~57_sumout ))) # (\uut_reg_ro|r_o[2]~0_combout  & 
+// (!\uut_add_mantovf|Add0~1_sumout )))) ) + ( \Add2~54  ))
+
+	.dataa(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datab(!\uut_add_mantovf|Add0~1_sumout ),
+	.datac(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\uut_add_ulp|a1|Add0~57_sumout ),
+	.datag(gnd),
+	.cin(\Add2~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\Add2~57_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \Add2~57 .extended_lut = "off";
+defparam \Add2~57 .lut_mask = 64'h000001FB00000000;
+defparam \Add2~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X51_Y6_N18
+cyclonev_lcell_comb \out~31 (
+// Equation(s):
+// \out~31_combout  = ( \uut_reg_ro|r_o[3]~1_combout  & ( (!\uut_reg_ro|r_o[2]~0_combout  & (\uut_add_ulp|a1|Add0~57_sumout )) # (\uut_reg_ro|r_o[2]~0_combout  & ((\uut_add_mantovf|Add0~1_sumout ))) ) ) # ( !\uut_reg_ro|r_o[3]~1_combout  & ( 
+// \uut_add_ulp|a1|Add0~57_sumout  ) )
+
+	.dataa(gnd),
+	.datab(!\uut_add_ulp|a1|Add0~57_sumout ),
+	.datac(!\uut_add_mantovf|Add0~1_sumout ),
+	.datad(!\uut_reg_ro|r_o[2]~0_combout ),
+	.datae(gnd),
+	.dataf(!\uut_reg_ro|r_o[3]~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~31_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~31 .extended_lut = "off";
+defparam \out~31 .lut_mask = 64'h33333333330F330F;
+defparam \out~31 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y4_N57
+cyclonev_lcell_comb \out~32 (
+// Equation(s):
+// \out~32_combout  = ( \out~31_combout  & ( ((\out~5_combout  & \Add2~57_sumout )) # (\out~7_combout ) ) ) # ( !\out~31_combout  & ( (\out~5_combout  & \Add2~57_sumout ) ) )
+
+	.dataa(!\out~5_combout ),
+	.datab(gnd),
+	.datac(!\Add2~57_sumout ),
+	.datad(!\out~7_combout ),
+	.datae(gnd),
+	.dataf(!\out~31_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~32_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~32 .extended_lut = "off";
+defparam \out~32 .lut_mask = 64'h0505050505FF05FF;
+defparam \out~32 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X50_Y7_N3
+cyclonev_lcell_comb \out~33 (
+// Equation(s):
+// \out~33_combout  = ( \inf~0_combout  ) # ( !\inf~0_combout  & ( (\zero~0_combout  & (\ls~0_combout  & ((\dsl1|c[14]~2_combout ) # (\dsl1|c[15]~0_combout )))) ) )
+
+	.dataa(!\zero~0_combout ),
+	.datab(!\dsl1|c[15]~0_combout ),
+	.datac(!\ls~0_combout ),
+	.datad(!\dsl1|c[14]~2_combout ),
+	.datae(gnd),
+	.dataf(!\inf~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\out~33_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \out~33 .extended_lut = "off";
+defparam \out~33 .lut_mask = 64'h01050105FFFFFFFF;
+defparam \out~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X89_Y8_N55
+cyclonev_io_ibuf \start~input (
+	.i(start),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\start~input_o ));
+// synopsys translate_off
+defparam \start~input .bus_hold = "false";
+defparam \start~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y12_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/Reference Code/add/vsim.wlf b/Reference Code/add/vsim.wlf
new file mode 100644
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Binary files /dev/null and b/Reference Code/add/vsim.wlf differ
diff --git a/Reference Code/add/work/_info b/Reference Code/add/work/_info
new file mode 100644
index 0000000000000000000000000000000000000000..6f3097bda0dc9c95a216f3d62f1d433b875764c2
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diff --git a/Reference Code/add/work/_lib.qdb b/Reference Code/add/work/_lib.qdb
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index 0000000000000000000000000000000000000000..17f228118d64a9711790d7e0ea102138e3ee33be
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diff --git a/Reference Code/add/work/_lib1_12.qdb b/Reference Code/add/work/_lib1_12.qdb
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diff --git a/Reference Code/add/work/_lib1_12.qpg b/Reference Code/add/work/_lib1_12.qpg
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diff --git a/Reference Code/add/work/_lib1_12.qtl b/Reference Code/add/work/_lib1_12.qtl
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diff --git a/Reference Code/add/work/_vmake b/Reference Code/add/work/_vmake
new file mode 100644
index 0000000000000000000000000000000000000000..37aa36a8517ca31d354b0f3f5639f3bc2044a60f
--- /dev/null
+++ b/Reference Code/add/work/_vmake	
@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology
diff --git a/Reference Code/mult/Posit_Multiplier.cr.mti b/Reference Code/mult/Posit_Multiplier.cr.mti
index 0d88022ccd956f06c9ba70899ef4290389379a9f..6faca88028ca98b0e1616d2b59cb118fcc11bd5a 100644
--- a/Reference Code/mult/Posit_Multiplier.cr.mti	
+++ b/Reference Code/mult/Posit_Multiplier.cr.mti	
@@ -1,4 +1,4 @@
-{H:/INDIVIDUAL PROJECT/Posit/mult/posit_mult.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/mult/posit_mult.v}
+{H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult.v}
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module posit_mult
 -- Compiling module data_extract_v1
@@ -18,4 +18,11 @@ Top level modules:
 	sub_N
 	add_1
 
+} {} {}} {H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult_8bit_tb.v} {1 {vlog -work work -stats=none {H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult_8bit_tb.v}
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module posit_mult_8bit_tb_v
+
+Top level modules:
+	posit_mult_8bit_tb_v
+
 } {} {}}
diff --git a/Reference Code/mult/Posit_Multiplier.mpf b/Reference Code/mult/Posit_Multiplier.mpf
index fad8d1b2e17ae2f08f759dbdbe2b109abd18d741..89b086ba714d19d30cc77105a28a97ab6f57bf0e 100644
--- a/Reference Code/mult/Posit_Multiplier.mpf	
+++ b/Reference Code/mult/Posit_Multiplier.mpf	
@@ -411,10 +411,10 @@ Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 2
-Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/mult/posit_mult_8bit_tb.v
-Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1675906005 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/mult/posit_mult.v
-Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1675902966 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult.v
+Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677006368 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = H:/INDIVIDUAL PROJECT/Posit/Reference Code/mult/posit_mult_8bit_tb.v
+Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1677006393 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
diff --git a/Reference Code/mult/error_8bit.txt b/Reference Code/mult/error_8bit.txt
index f304b8accf896cb4343f10993c799ac63787f5b9..6536e3942e6a0513b4a14fd7d6e374d43012b871 100644
--- a/Reference Code/mult/error_8bit.txt	
+++ b/Reference Code/mult/error_8bit.txt	
@@ -29214,3 +29214,36066 @@
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diff --git a/Reference Code/mult/posit_mult.v b/Reference Code/mult/posit_mult.v
index 97a8b24dc88aa6fb4bf88c5488cfbd8dd90b8b4c..aa5d93de68c26ef507e17f6f225cab09b098858f 100644
--- a/Reference Code/mult/posit_mult.v	
+++ b/Reference Code/mult/posit_mult.v	
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+//`timescale 1ns / 1ps
 //(* use_dsp = "no" *)
 module posit_mult(in1, in2, start, out, inf, zero, done);
 
diff --git a/Reference Code/mult/posit_mult_8bit_tb.v b/Reference Code/mult/posit_mult_8bit_tb.v
index bb9d320c8e9e74eab8aad54b9302a045c1105013..520051681a63985d890860c704d50da381f1662c 100644
--- a/Reference Code/mult/posit_mult_8bit_tb.v	
+++ b/Reference Code/mult/posit_mult_8bit_tb.v	
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+//`timescale 1ns / 1ps
 module posit_mult_8bit_tb_v;
 
 function [31:0] log2;
diff --git a/Reference Code/mult/posit_mult_8bit_tb.v.bak b/Reference Code/mult/posit_mult_8bit_tb.v.bak
new file mode 100644
index 0000000000000000000000000000000000000000..bb9d320c8e9e74eab8aad54b9302a045c1105013
--- /dev/null
+++ b/Reference Code/mult/posit_mult_8bit_tb.v.bak	
@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+module posit_mult_8bit_tb_v;
+
+function [31:0] log2;
+input reg [31:0] value;
+	begin
+	value = value-1;
+	for (log2=0; value>0; log2=log2+1)
+        	value = value>>1;
+      	end
+endfunction
+
+parameter N=8;
+parameter Bs=log2(N);
+parameter es=3;
+
+reg [N-1:0] in1, in2;
+reg start; 
+wire [N-1:0] out;
+wire done;
+
+	reg clk;
+	integer outfile;
+
+
+// Instantiate the Unit Under Test (UUT)
+posit_mult #(.N(N), .es(es)) uut (in1, in2, start, out, inf, zero, done);
+
+reg [N-1:0] data1 [1:65534];
+reg [N-1:0] data2 [1:65534];
+initial $readmemb("Pin1_8bit.txt",data1);
+initial $readmemb("Pin2_8bit.txt",data2);
+
+reg [15:0] i;
+	
+	initial begin
+		// Initialize Inputs
+		in1 = 0;
+		in2 = 0;
+		clk = 0;
+		start = 0;
+	
+		
+		// Wait 100 ns for global reset to finish
+		#100 i=0;
+		#20 start = 1;
+                #652790 start = 0;
+		#100;
+		
+		$fclose(outfile);
+		$finish;
+	end
+	
+ always #5 clk=~clk;
+
+  always @(posedge clk) begin			
+ 	in1=data1[i];	
+	in2=data2[i];
+	if(i==16'hffff)
+  	      $finish;
+	else i = i + 1;
+ end
+
+initial outfile = $fopen("error_8bit.txt", "wb");
+
+reg [N-1:0] result [1:65534];
+initial $readmemb("Pout_8bit_ES4.txt",result);
+reg [N-1:0] diff;
+always @(negedge clk) begin
+	if(start)begin
+     	diff = (result[i-1] > out) ? result[i-1]-out : out-result[i-1];
+     	$fwrite(outfile, "%d\n",diff);
+     	end
+end
+endmodule
+
diff --git a/Reference Code/mult/wlft35i893 b/Reference Code/mult/wlft35i893
new file mode 100644
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diff --git a/Reference Code/mult/wlft797cew b/Reference Code/mult/wlft797cew
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diff --git a/Reference Code/mult/work/_info b/Reference Code/mult/work/_info
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