diff --git a/IP_wrappers/PLL_integration_layer.v b/IP_wrappers/PLL_integration_layer.v
new file mode 100644
index 0000000000000000000000000000000000000000..0f22c04c2d880443cc99695bb016867ed3ea18cb
--- /dev/null
+++ b/IP_wrappers/PLL_integration_layer.v
@@ -0,0 +1,341 @@
+// Integration layer for an APB to PLL interface
+
+module snps_PLL_integration_layer #(
+ parameter DEFAULT_DIVVCOP=4'h0,
+ parameter DEFAULT_DIVVCOR=4'h0,
+ parameter DEFAULT_FBDIV=7'h10,
+ parameter DEFAULT_P = 6'h03,
+ parameter DEFAULT_R = 6'h01,
+ parameter DEFAULT_PREDIV = 5'h00
+ )(
+`ifdef POWER_PINS
+ inout wire agnd,
+ inout wire avdd,
+ inout wire avddhv,
+ inout wire dgnd,
+ inout wire dvdd,
+ inout wire vp_vref,
+`endif
+ input wire ref_clk,
+ input wire resetn,
+
+ output wire pll_lock,
+ output wire out_clk1,
+ output wire out_clk2,
+
+ input wire PSELx,
+ input wire [9:0] PADDR,
+ input wire PENABLE,
+ input wire [2:0] PPROT,
+ input wire [3:0] PSTRB,
+ input wire PWRITE,
+ input wire [31:0] PWDATA,
+ output wire [31:0] PRDATA,
+ output wire PREADY,
+ output wire PSLVERR
+);
+
+// Control register
+// Bypass ---------------------------------------------------------------------------------|
+// Enable P -----------------------------------------------------------------------| |
+// Enable R ---------------------------------------------------------------------| | |
+// Gear Shift ---------------------------------------------------------------| | | |
+// bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+
+//
+reg bypass_reg;
+reg enp_reg;
+reg enr_reg;
+reg gear_shift_reg;
+
+reg [11:0] gear_shift_counter;
+reg [11:0] enable_counter;
+
+reg [3:0] divvcop_reg;
+reg [3:0] divvcor_reg;
+reg [6:0] fbdiv_reg;
+reg [5:0] p_reg;
+reg [5:0] r_reg;
+reg [4:0] prediv_reg;
+
+reg pll_lock_reg;
+
+reg [4:0] PLL_test_addr;
+reg PLL_test_wr_en;
+reg PLL_test_rd_en;
+reg [2:0] APB_PLL_counter;
+reg PLL_read_write_done;
+reg [7:0] PLL_data_i;
+wire [7:0] PLL_data_o;
+
+// APB interface
+localparam APB_IDLE = 3'd0,
+ APB_WRITE = 3'd1,
+ APB_READ = 3'd2,
+ APB_WRITE_PLL = 3'd3,
+ APB_READ_PLL = 3'd4;
+
+reg [2:0] apb_current_state;
+reg [2:0] apb_next_state;
+
+reg PSLVERR_reg;
+reg [31:0] PRDATA_reg;
+
+assign PRDATA = PRDATA_reg;
+assign PSLVERR = PSLVERR_reg;
+
+always @(posedge ref_clk or negedge resetn) begin
+ if(~resetn) begin
+ apb_current_state <= APB_IDLE;
+ APB_PLL_counter <= 3'h0;
+ end else begin
+ apb_current_state <= apb_next_state;
+ if(apb_current_state == APB_WRITE_PLL || apb_current_state == APB_READ_PLL) begin
+ APB_PLL_counter <= APB_PLL_counter + 3'h1;
+ end else begin
+ APB_PLL_counter <= 3'h0;
+ end
+ end
+end
+
+always @(*) begin
+ if(~resetn) begin
+ bypass_reg = 1'b0;
+ enp_reg = 1'b0;
+ enr_reg = 1'b0;
+ gear_shift_reg = 1'b1;
+ gear_shift_counter = 16'h0000;
+ enable_counter = 16'h0000;
+ pll_lock_reg = 1'b0;
+
+ // Default startup of PLL
+ // F_vco = 100*20/1 = 1.6 GHz
+ // F_clkoutp = 400 MHz
+ // F_clkoutr = 800 MHz
+ divvcop_reg = DEFAULT_DIVVCOP; // Divvco = 1
+ divvcor_reg = DEFAULT_DIVVCOR; // Divvco = 1
+ fbdiv_reg = DEFAULT_FBDIV; // Feeback = 16
+ p_reg = DEFAULT_P; // p = 4
+ r_reg = DEFAULT_R; // r=2
+ prediv_reg = DEFAULT_PREDIV; // prediv=1
+
+ PSLVERR_reg = 1'b0;
+ PLL_read_write_done = 1'b0;
+ PLL_test_wr_en = 1'b0;
+ PLL_test_rd_en = 1'b0;
+ end else begin
+ if((gear_shift_reg == 1'b1)) begin
+ gear_shift_counter = gear_shift_counter+1;
+ if (gear_shift_counter>12'h200) begin
+ gear_shift_reg = 1'b0;
+ gear_shift_counter = 12'h000;
+ end
+ end else begin
+ if((enp_reg==1'b0)||(enr_reg==1'b0)) begin
+ enable_counter = enable_counter+1;
+ if(enable_counter>12'h200) begin
+ enp_reg = 1'b1;
+ enr_reg = 1'b1;
+ enable_counter = 12'h000;
+ end
+ end
+ end
+ if((enp_reg==1'b1)||(enr_reg==1'b1)) begin
+ pll_lock_reg = pll_lock;
+ end
+ case(apb_current_state)
+ APB_IDLE: begin
+ PSLVERR_reg = 1'b0;
+ PLL_read_write_done = 1'b0;
+ PLL_test_wr_en = 1'b0;
+ PLL_test_rd_en = 1'b0;
+
+ if(PSELx) begin
+ if(PWRITE) begin
+ if(PADDR[9])
+ apb_next_state = APB_WRITE_PLL;
+ else
+ apb_next_state = APB_WRITE;
+ end else begin
+ if(PADDR[9])
+ apb_next_state = APB_READ_PLL;
+ else
+ apb_next_state = APB_READ;
+ end
+ end
+ else begin
+ apb_next_state = APB_IDLE;
+ end
+ end
+ APB_WRITE: begin
+ case(PADDR)
+ 10'h000: begin
+ if(PSTRB[0]==1'b1) begin
+ bypass_reg = PWDATA[0];
+ enp_reg = PWDATA[4];
+ enr_reg = PWDATA[5];
+ gear_shift_reg = PWDATA[7];
+ end else begin
+ PSLVERR_reg = 1'b1;
+ end
+ end
+ 10'h001: begin
+ if(PSTRB[0]==1'b1)
+ gear_shift_counter[7:0] = PWDATA[7:0];
+ if(PSTRB[1]==1'b1)
+ gear_shift_counter[11:8] = PWDATA[11:8];
+ end
+ 10'h002: begin
+ if(PSTRB[0]==1'b1)
+ enable_counter[7:0] = PWDATA[7:0];
+ if(PSTRB[1]==1'b1)
+ enable_counter[11:8] = PWDATA[11:8];
+ end
+ 10'h003: begin
+ if(PSTRB[0]==1'b1)
+ r_reg = PWDATA[5:0];
+ if(PSTRB[1]==1'b1)
+ divvcor_reg = PWDATA[11:8];
+ if(PSTRB[2]==1'b1)
+ p_reg = PWDATA[21:16];
+ if(PSTRB[3]==1'b1)
+ divvcop_reg = PWDATA[27:24];
+ end
+ 10'h004: begin
+ if(PSTRB[0]==1'b1)
+ fbdiv_reg = PWDATA[6:0];
+ if(PSTRB[1]==1'b1)
+ prediv_reg = PWDATA[12:8];
+ end
+
+ endcase
+ apb_next_state = APB_IDLE;
+ end
+ APB_READ: begin
+ case(PADDR)
+ 10'h000: PRDATA_reg = {{24{1'b0}}, gear_shift_reg, 1'b0, enr_reg, enp_reg, {3{1'b0}}, bypass_reg};
+ 10'h001: PRDATA_reg = {{20{1'b0}}, gear_shift_counter};
+ 10'h002: PRDATA_reg = {{20{1'b0}}, enable_counter};
+ 10'h003: PRDATA_reg = {{4{1'b0}}, divvcop_reg, {2{1'b0}}, p_reg, {4{1'b0}}, divvcor_reg, {2{1'b0}}, r_reg};
+ 10'h004: PRDATA_reg = {{19{1'b0}}, prediv_reg, {1{1'b0}}, fbdiv_reg};
+ 10'h005: PRDATA_reg = 32'h534E504C;
+ 10'h006: PRDATA_reg = {{31{1'b0}},pll_lock_reg};
+ endcase
+ apb_next_state = APB_IDLE;
+ end
+ APB_WRITE_PLL: begin
+ case(PADDR)
+ 10'h200: PLL_test_addr = 5'h00;
+ 10'h201: PLL_test_addr = 5'h01;
+ 10'h202: PLL_test_addr = 5'h02;
+ 10'h203: PLL_test_addr = 5'h03;
+ 10'h204: PLL_test_addr = 5'h04;
+ 10'h205: PLL_test_addr = 5'h10;
+ 10'h206: PLL_test_addr = 5'h11;
+ 10'h207: PLL_test_addr = 5'h12;
+ 10'h208: PLL_test_addr = 5'h13;
+ 10'h209: PLL_test_addr = 5'h14;
+ 10'h20A: PLL_test_addr = 5'h15;
+ 10'h20B: PLL_test_addr = 5'h16;
+ 10'h20C: PLL_test_addr = 5'h17;
+ endcase
+ PLL_test_wr_en = 1'b1;
+ PLL_data_i <= PWDATA[7:0];
+ if(APB_PLL_counter > 3'h2) begin
+ PLL_read_write_done = 1'b1;
+ end
+ if(PLL_read_write_done) begin
+ apb_next_state = APB_IDLE;
+ end else begin
+ apb_next_state = APB_WRITE_PLL;
+ end
+ end
+ APB_READ_PLL: begin
+ case(PADDR)
+ 10'h200: PLL_test_addr = 5'h00;
+ 10'h201: PLL_test_addr = 5'h01;
+ 10'h202: PLL_test_addr = 5'h02;
+ 10'h203: PLL_test_addr = 5'h03;
+ 10'h204: PLL_test_addr = 5'h04;
+ 10'h205: PLL_test_addr = 5'h10;
+ 10'h206: PLL_test_addr = 5'h11;
+ 10'h207: PLL_test_addr = 5'h12;
+ 10'h208: PLL_test_addr = 5'h13;
+ 10'h209: PLL_test_addr = 5'h14;
+ 10'h20A: PLL_test_addr = 5'h15;
+ 10'h20B: PLL_test_addr = 5'h16;
+ 10'h20C: PLL_test_addr = 5'h17;
+ endcase
+ PLL_test_rd_en = 1'b1;
+ if(APB_PLL_counter > 3'h2) begin
+ PLL_read_write_done = 1'b1;
+ PRDATA_reg = {{24{1'b0}}, PLL_data_o};
+ end
+ if(PLL_read_write_done) begin
+ apb_next_state = APB_IDLE;
+ end else begin
+ apb_next_state = APB_READ_PLL;
+ end
+ end
+ default: apb_next_state = APB_IDLE;
+ endcase
+ end
+end
+
+
+assign PREADY = ((apb_current_state==APB_READ|apb_current_state==APB_WRITE|PLL_read_write_done==1'b1))? 1'b1:1'b0;
+
+
+dwc_z19606ts_ns u_snps_PLL(
+`ifdef BEHAVIOURAL_SIM
+ // .agnd(64'd0), // Analog and digital clean ground
+ // .avdd(64'h3FECCCCCCCCCCCCD), // Analog clean 0.9V supply
+ // .avddhv(64'h3FFCCCCCCCCCCCCD), // Dedicated analog 1.8V supply
+ // .dgnd(64'd0), // Digital ground
+ // .dvdd(64'h3FECCCCCCCCCCCCD), // Digital 0.9V supply
+ .vp_vref(64'h3FECCCCCCCCCCCCD), // Input reference voltage (similar to AVDD)
+`else
+// .agnd(agnd),
+// .avdd(avdd),
+// .avddhv(avddhv),
+// .dgnd(dgnd),
+// .dvdd(dvdd),
+ .vp_vref(vp_vref),
+`endif
+ // Clock Signals
+ .ref_clk(ref_clk), // Input reference clock signal
+ .clkoutp(out_clk1),
+ .clkoutr(out_clk2),
+
+ .bypass(bypass_reg), //PLL Bypass mode (0: clk_out = PLL output 1:clk_out = ref_clk/(p/r))
+ .divvcop(divvcop_reg), //Output divider for clock P (3:0)
+ .divvcor(divvcor_reg), //Output divider for clock R (3:0)
+ .enp(enp_reg), // Enable output clock P (1: clk_out = PLL output 0: clk_out = 0 or ref_clock/p)
+ .enr(enr_reg), // Enable output clock R (1: clk_out = PLL output 0: clk_out = 0 or ref_clock/r)
+ .fbdiv(fbdiv_reg), // Feedback multiplication facor (7 bits 8-131)
+ .lock(pll_lock), // PLL Lock State
+ .gear_shift(gear_shift_reg), // Locking control, set high for faster PLL locking at cost of phase margin and jitter
+ .p(p_reg), // Post divider division factor P (1-64)
+ .prediv(prediv_reg), // input frequency division factor (1-32)
+ .pwron(1'b1), // Power on control
+ .r(r_reg), // Post divider division factor R (1-64)
+ .rst(~resetn), // Reset signal (set high for 4us whenever PWRON goes high)
+
+ .vregp(), // Output voltage regulator for P clock
+ .vregr(), // Output voltage regulator for R clock
+
+
+ // Test Signals
+ .test_data_i(PLL_data_i), //Data bus input control registers (7:0)
+ .test_rd_en(PLL_test_rd_en), // Control register read enable
+ .test_rst(~resetn), // Control register reset signal
+ .test_sel(PLL_test_addr), // Select lines for control register (4:0)
+ .test_wr_en(PLL_test_wr_en), // Control register write enable
+ .test_data_o(PLL_data_o), //Data bus output control registers (7:0)
+
+ .atb_f_m(), //Signal for sinking or sourcing currents to/from PLL (for internal debug)
+ .atb_s_m(), // Signal for sensing voltages internal to PLL (for internal debug)
+ .atb_s_p() // Signal for sensing voltages internal to PLL (for internal debug)
+);
+
+endmodule
\ No newline at end of file
diff --git a/IP_wrappers/synopsys_PD_sensor_integration.v b/IP_wrappers/synopsys_PD_sensor_integration.v
index 8805489613ff02b5607a156baebcad27952aad36..7c0425cccc6c547e8bba603f5b1bf0e19a7dd502 100644
--- a/IP_wrappers/synopsys_PD_sensor_integration.v
+++ b/IP_wrappers/synopsys_PD_sensor_integration.v
@@ -68,28 +68,11 @@ assign irq_pd_rdy = pd_irq_rdy_reg;
// Main sequential logic
always @(posedge PCLK or negedge aRESETn)begin
if(~aRESETn) begin
- // Software Definable
- pd_enable_reg <= 1'b0;
- pd_clk_div <= 8'd7; // 100MHz/(7*2) = 7.1MHz (max 8 MHz)
-
- pd_config_reg1 <= 8'h00; // Parallel mode, Process detector speed mode
- pd_config_reg2 <= 8'hC0; // Built in delay chain
- pd_config_reg3 <= 8'h21; // W=63 A=32
- pd_cload <= 1'b0;
-
- pd_irq_clear_reg <= 1'b0;
- pd_irq_enabled <= 1'b0;
- pd_run_reg <= 1'b0;
- pd_run_continuous_reg <= 1'b0;
- pd_ready_reg_clr <= 1'b0;
-
// Automatically controlled registers
pd_irq_rdy_reg <= 1'b0;
pd_ready_reg <= 1'b0;
// APB Control
apb_current_state <= APB_IDLE;
- apb_next_state <= APB_IDLE;
- PSLVERR_reg <= 1'b0;
end
else begin
if(pd_irq_enabled && pd_ready)
@@ -97,18 +80,11 @@ always @(posedge PCLK or negedge aRESETn)begin
if(pd_irq_clear_reg)
pd_irq_rdy_reg <= 1'b0;
- if(pd_run_continuous_reg)
- pd_run_reg <= 1'b1;
- if(pd_run_clear) begin
- pd_run_clear <= 1'b0;
- pd_run_reg <= 1'b0;
- end
if(pd_ready)
pd_ready_reg <= 1'b1;
if(pd_ready_reg_clr) begin
- pd_ready_reg_clr <= 1'b0;
pd_ready_reg <= 1'b0;
end
// APB control
@@ -140,28 +116,64 @@ end
reg [2:0] pd_reset_delay;
reg pd_run_delay;
+reg pd_run_delay_reg;
always @(posedge pd_clk_slow or negedge aRESETn) begin
+ if(~aRESETn) begin
+ pd_run_delay_reg <= 1'b0;
+// pd_local_reset <= 1'b0;
+// pd_reset_delay <= 3'h0;
+// pd_run_clear <= 1'b0;
+// pd_run_delay <= 1'b0;
+ end else begin
+ pd_run_delay_reg <= pd_run_delay;
+ end
+end
+
+always @(*) begin
if(~aRESETn) begin
- pd_local_reset <= 1'b0;
- pd_reset_delay <= 3'h0;
- pd_run_clear <= 1'b0;
- pd_run_delay <= 1'b0;
+ pd_enable_reg = 1'b0;
+ pd_clk_div = 8'h14;
+
+ pd_config_reg1 = 8'h00;
+ pd_config_reg2 = 8'hC0;
+ pd_config_reg3 = 8'h21;
+ pd_cload = 1'b0;
+
+ pd_irq_clear_reg = 1'b0;
+ pd_irq_enabled = 1'b0;
+ pd_run_reg = 1'b0;
+ pd_run_continuous_reg = 1'b0;
+ pd_ready_reg_clr = 1'b0;
+ pd_local_reset = 1'b0;
+ pd_reset_delay = 3'h0;
+ pd_run_clear = 1'b0;
+ pd_run_delay = 1'b0;
+
+ PSLVERR_reg = 1'b0;
end else begin
+ if(pd_ready_reg_clr) begin
+ pd_ready_reg_clr = 1'b0;
+ end
+
+ if(pd_run_continuous_reg)
+ pd_run_reg = 1'b1;
+ if(pd_run_clear) begin
+ pd_run_clear = 1'b0;
+ pd_run_reg = 1'b0;
+ end
+
if(~pd_run_continuous_reg & pd_run_reg)
- pd_run_delay <= 1'b1;
- if(pd_run_delay) begin
- pd_run_delay <= 1'b0;
- pd_run_clear <= 1'b1;
+ pd_run_delay = 1'b1;
+ if(pd_run_delay_reg) begin
+ pd_run_delay = 1'b0;
+ pd_run_clear = 1'b1;
end
if(~pd_local_reset)
- pd_reset_delay <= pd_reset_delay + 1'b1;
+ pd_reset_delay = pd_reset_delay + 1'b1;
if(pd_reset_delay>=3'h6)
- pd_local_reset <= 1'b1;
- end
-end
+ pd_local_reset = 1'b1;
-always @(*) begin
case(apb_current_state)
APB_IDLE: begin
PSLVERR_reg = 1'b0;
@@ -179,7 +191,7 @@ always @(*) begin
end
APB_WRITE: begin
case(PADDR)
- 10'h000: begin
+ 2'h0: begin
if(PSTRB[0]==1'b1) begin
pd_enable_reg = PWDATA[0];
pd_run_reg = PWDATA[1];
@@ -216,7 +228,7 @@ always @(*) begin
APB_READ: begin
case(PADDR)
2'h0: PRDATA_reg = {7'h00, pd_ready_reg, 6'h0, pd_irq_clear_reg, pd_irq_enabled, pd_clk_div, 3'h0, pd_local_reset, pd_ready_reg_clr, pd_run_continuous_reg, pd_run_reg, pd_enable_reg};
- 2'h1: PRDATA_reg = {30'h0, pd_data};
+ 2'h1: PRDATA_reg = {20'h0, pd_data};
2'h2: PRDATA_reg = {7'h0, pd_cload, pd_config_reg3, pd_config_reg2, pd_config_reg1}; // Configuration
2'h3: PRDATA_reg = 32'h736E7064; // ID Reg
endcase
@@ -224,6 +236,7 @@ always @(*) begin
end
default: apb_next_state = APB_IDLE;
endcase
+ end
end
assign PREADY = (apb_current_state==APB_READ|apb_current_state==APB_WRITE)? 1'b1:1'b0;
diff --git a/IP_wrappers/synopsys_TS_sensor_integration.v b/IP_wrappers/synopsys_TS_sensor_integration.v
index 907f3d07d2d201b35e984e636287884421057ae9..1755889e1e00bd20b9510babaefb9810b1a162c9 100644
--- a/IP_wrappers/synopsys_TS_sensor_integration.v
+++ b/IP_wrappers/synopsys_TS_sensor_integration.v
@@ -20,7 +20,11 @@ module synopsys_TS_sensor_integration(
output wire PSLVERR,
input wire ts_vcal,
- inout wire [3:0] ts_an_test,
+ inout wire ts_an_test_0,
+ inout wire ts_an_test_1,
+ inout wire ts_an_test_2,
+ inout wire ts_an_test_3,
+
output wire ts_vss_sense,
output wire irq_ts_rdy
);
@@ -75,19 +79,6 @@ assign irq_ts_rdy = ts_irq_rdy_reg;
// Main sequential logic
always @(posedge PCLK or negedge aRESETn)begin
if(~aRESETn) begin
- // Synopsys TS register control logic
- // Software definable
- ts_irq_clear_reg <= 1'b0; //Clear interrupt
- ts_irq_enabled <= 1'b0; //Enable interrupt
- ts_run_reg <= 1'b0;
- ts_enable_reg <= 1'b0; //Enable Temperature sensor
- ts_run_continuous_reg <= 1'b0;
- ts_clk_div <= 8'd24;
- ts_ready_reg_clr <= 1'b0;
-
- ts_sig_en <= 1'b0;
- ts_tm_an <= 4'h0;
- ts_cal <= 1'b0;
// Automatically controlled registers
ts_irq_rdy_reg <= 1'b0;
@@ -95,8 +86,6 @@ always @(posedge PCLK or negedge aRESETn)begin
// APB Control
apb_current_state <= APB_IDLE;
- apb_next_state <= APB_IDLE;
- PSLVERR_reg <= 1'b0;
end
else begin
@@ -106,21 +95,14 @@ always @(posedge PCLK or negedge aRESETn)begin
if (ts_irq_clear_reg)
ts_irq_rdy_reg <= 1'b0;
-
- if(ts_run_continuous_reg)
- ts_run_reg <= 1'b1;
- if(ts_run_clear) begin
- ts_run_clear <= 1'b0;
- ts_run_reg <= 1'b0;
- end
if(ts_ready)
ts_ready_reg <= 1'b1;
-
+
if(ts_ready_reg_clr) begin
- ts_ready_reg_clr <= 1'b0;
ts_ready_reg <= 1'b0;
end
+
// APB control
apb_current_state <= apb_next_state;
end
@@ -150,30 +132,76 @@ end
reg [2:0] ts_reset_delay;
reg ts_run_delay;
+reg ts_ready_reg_clr_del;
always @(posedge ts_clk_slow or negedge aRESETn) begin
if(~aRESETn) begin
- ts_local_reset <= 1'b0;
- ts_run_clear <= 1'b0;
- ts_reset_delay <= 3'h0;
- ts_run_delay <= 1'b0;
+ // ts_local_reset <= 1'b0;
+ // ts_run_clear <= 1'b0;
+ // ts_reset_delay <= 3'h0;
+ // ts_run_delay <= 1'b0;
+ ts_ready_reg_clr_del <= 1'b0;
end else begin
+ // if(~ts_run_continuous_reg & ts_run_reg)
+ // ts_run_delay <= 1'b1;
+ // if(ts_run_delay) begin
+ // ts_run_delay <= 1'b0;
+ // ts_run_clear <= 1'b1;
+ // end
+ // if(~ts_local_reset)
+ // ts_reset_delay <= ts_reset_delay + 1'b1;
+ // if(ts_reset_delay>=3'h6)
+ // ts_local_reset <= 1'b1;
+ ts_ready_reg_clr_del <= ts_ready_reg_clr;
+
+ end
+end
+
+always @(*) begin
+ if(~aRESETn) begin
+ // Synopsys TS register control logic
+ // Software definable
+ ts_irq_clear_reg = 1'b0; //Clear interrupt
+ ts_irq_enabled = 1'b0; //Enable interrupt
+ ts_run_reg = 1'b0;
+ ts_enable_reg = 1'b0; //Enable Temperature sensor
+ ts_run_continuous_reg = 1'b0;
+ ts_clk_div = 8'd24;
+ ts_ready_reg_clr = 1'b0;
+
+ ts_sig_en = 1'b0;
+ ts_tm_an = 4'h0;
+ ts_cal = 1'b0;
+ PSLVERR_reg = 1'b0;
+
+ ts_local_reset = 1'b0;
+ ts_run_clear = 1'b0;
+ ts_reset_delay = 3'h0;
+ ts_run_delay = 1'b0;
+
+ end else begin
+ if(ts_run_continuous_reg)
+ ts_run_reg = 1'b1;
+ if(ts_run_clear) begin
+ ts_run_clear = 1'b0;
+ ts_run_reg = 1'b0;
+ end
+ if(ts_ready_reg_clr_del) begin
+ ts_ready_reg_clr = 1'b0;
+ end
+
if(~ts_run_continuous_reg & ts_run_reg)
- ts_run_delay <= 1'b1;
+ ts_run_delay = 1'b1;
if(ts_run_delay) begin
- ts_run_delay <= 1'b0;
- ts_run_clear <= 1'b1;
+ ts_run_delay = 1'b0;
+ ts_run_clear = 1'b1;
end
if(~ts_local_reset)
- ts_reset_delay <= ts_reset_delay + 1'b1;
+ ts_reset_delay = ts_reset_delay + 1'b1;
if(ts_reset_delay>=3'h6)
- ts_local_reset <= 1'b1;
+ ts_local_reset = 1'b1;
- end
-end
-
-always @(*) begin
case(apb_current_state)
APB_IDLE: begin
PSLVERR_reg = 1'b0;
@@ -233,6 +261,7 @@ always @(*) begin
end
default: apb_next_state = APB_IDLE;
endcase
+ end
end
assign PREADY = (apb_current_state==APB_READ|apb_current_state==APB_WRITE)? 1'b1:1'b0;
@@ -270,10 +299,10 @@ mr74127 u_synopsys_ts(
.dout10(ts_data[10]), // TS Data Out - bit 10
.dout11(ts_data[11]), // TS Data Out - bit 11 (MSB)
.digo(), // TS Bitstream Out
- .an_test0(ts_an_test[0]), // TS Analog test access - signal 0
- .an_test1(ts_an_test[1]), // TS Analog test access - signal 1
- .an_test2(ts_an_test[2]), // TS Analog test access - signal 2
- .an_test3(ts_an_test[3]), // TS Analog test access - signal 3
+ .an_test0(ts_an_test_0), // TS Analog test access - signal 0
+ .an_test1(ts_an_test_1), // TS Analog test access - signal 1
+ .an_test2(ts_an_test_2), // TS Analog test access - signal 2
+ .an_test3(ts_an_test_3), // TS Analog test access - signal 3
.vss_sense(ts_vss_sense) // vss sense (for cal)
);
diff --git a/IP_wrappers/synopsys_VM_sensor_integration.v b/IP_wrappers/synopsys_VM_sensor_integration.v
index bd04ceb18ffe35e53f2b18a01823b3c1746afaed..2c8e1b8ec3f74668e3d39a3437624b18c4b69659 100644
--- a/IP_wrappers/synopsys_VM_sensor_integration.v
+++ b/IP_wrappers/synopsys_VM_sensor_integration.v
@@ -17,4 +17,53 @@ module synopsys_VM_sensor_integration(
);
+
+mr74140 u_snps_VM(
+ .clk(),
+ .pd(),
+ .run(),
+ .rstn(),
+ .sde(1'b0),
+ .tm_se(),
+ .tm_si(),
+ .tm_tval(),
+ .tm_ld(),
+ .tm_te(),
+ .sel_vin0(),
+ .sel_vin1(),
+ .sel_vin2(),
+ .sel_vin3(),
+ .trim0(),
+ .trim1(),
+ .trim2(),
+ .trim3(),
+ .tm_a0(),
+ .tm_a1(),
+ .tm_a2(),
+ .tm_a3(),
+ .an_vm0(),
+ .an_vm1(),
+ .an_vm2(),
+ .an_vm3(),
+ .an_vm4(),
+ .an_vm5(),
+ .an_vm6(),
+ .an_vm7(),
+ .an_vref(),
+ .rdy(),
+ .dout0(),
+ .dout1(),
+ .dout2(),
+ .dout3(),
+ .dout4(),
+ .dout5(),
+ .dout6(),
+ .dout7(),
+ .dout8(),
+ .dout9(),
+ .dout10(),
+ .dout11(),
+ .tm_so()
+);
+
endmodule