From a772308d8c5f9a32b808c5fe689395bffe60b85b Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 6 Nov 2024 11:56:18 +0000
Subject: [PATCH] Increase AXI ID width to 12
---
flist/Top/sram_chiplet_TSMC28nm.flist | 4 ++-
flist/Top/sram_chiplet_vip.flist | 3 ---
.../SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v | 11 ++++----
logical/SRAM/glib/verilog/SRAM_wrapper.v | 12 +++++----
.../verilog/sram_chiplet_apb_subsystem.v | 4 +--
.../verilog/top_sram_chiplet.sv | 26 +++++++++----------
socrates/BP301_SRAM/config/SRAM_ctrl.yaml | 2 +-
.../nic400_sram_chiplet.xml | 10 +++----
socrates/nic400_tb/nic400_tb.xml | 8 +++---
.../nic400_tlx_sram_chiplet.xml | 24 ++++++++---------
synopsys_28nm_slm_integration | 2 +-
verif/cocotb/sram_chiplet_cocotb.sv | 16 ++++++------
12 files changed, 62 insertions(+), 60 deletions(-)
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
index 71955c9..cdcc0c8 100644
--- a/flist/Top/sram_chiplet_TSMC28nm.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -15,6 +15,8 @@
// ============= Verilog library extensions ===========
+libext+.v+.vlib
+$(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
+
// SRAM Chiplet top level
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
@@ -26,7 +28,7 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_emulation.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_vip.flist b/flist/Top/sram_chiplet_vip.flist
index 6dcf50b..3a8e954 100644
--- a/flist/Top/sram_chiplet_vip.flist
+++ b/flist/Top/sram_chiplet_vip.flist
@@ -2,6 +2,3 @@
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/VIP/NIC400_tb.flist
-$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/axi_stream_io/verilog/axi_stream_io.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/f232h_ft1248_stream/verilog/f232h_ft1248_stream.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/f232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
index 9e41377..08b99b1 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
@@ -12,13 +12,14 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module SRAM_wrapper(
+module SRAM_wrapper #(
+ parameter ID_W=12 )(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [3:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +37,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [3:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [3:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +53,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [3:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [31:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/glib/verilog/SRAM_wrapper.v b/logical/SRAM/glib/verilog/SRAM_wrapper.v
index 9e41377..2df8555 100644
--- a/logical/SRAM/glib/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/glib/verilog/SRAM_wrapper.v
@@ -12,13 +12,15 @@
// sie300_axi5_sram_ctrl_expansion_subsystem
// SRAM
-module SRAM_wrapper(
+module SRAM_wrapper #(
+ parameter ID_W = 12
+)(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
- input wire [3:0] AWID,
+ input wire [ID_W-1:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +38,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [3:0] BID,
+ output wire [ID_W-1:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [3:0] ARID,
+ input wire [ID_W-1:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +54,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [3:0] RID,
+ output wire [ID_W-1:0] RID,
output wire [31:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
index 902b6b0..b31d6e5 100644
--- a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+++ b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
@@ -243,10 +243,10 @@ wire pll_clk2_i;
generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
snps_PLL_integration_layer #(
- .DEFAULT_FBDIV(7'h08), // Multiply by 8 (250*8 = 2 GHz)
+ .DEFAULT_FBDIV(7'd20), // Multiply by 8 (250*8 = 2 GHz)
.DEFAULT_DIVVCOP(4'h0), // Divider = 1
.DEFAULT_DIVVCOR(4'h0), // Divider = 1
- .DEFAULT_P(6'h01), // Divider = 2 (out 1 GHz)
+ .DEFAULT_P(6'h00), // Divider = 2 (out 2 GHz)
.DEFAULT_R(6'h07), // Divier = 8 (out 250 MHz)
.DEFAULT_PREDIV(5'h00) // Pre div = 2 (250/1 = 250 MHz)
) u_snps_PLL(
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
index 2ad8a5c..541db65 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
@@ -49,12 +49,12 @@ module top_sram_chiplet #(
);
-
+localparam ID_W = 12;
wire SYS_CLK;
// Main Bus Wires
// - SRAM AXI wires
-wire [3:0] AWID_AXI_SRAM;
+wire [ID_W-1:0] AWID_AXI_SRAM;
wire [31:0] AWADDR_AXI_SRAM;
wire [7:0] AWLEN_AXI_SRAM;
wire [2:0] AWSIZE_AXI_SRAM;
@@ -69,11 +69,11 @@ wire [3:0] WSTRB_AXI_SRAM;
wire WLAST_AXI_SRAM;
wire WVALID_AXI_SRAM;
wire WREADY_AXI_SRAM;
-wire [3:0] BID_AXI_SRAM;
+wire [ID_W-1:0] BID_AXI_SRAM;
wire [1:0] BRESP_AXI_SRAM;
wire BVALID_AXI_SRAM;
wire BREADY_AXI_SRAM;
-wire [3:0] ARID_AXI_SRAM;
+wire [ID_W-1:0] ARID_AXI_SRAM;
wire [31:0] ARADDR_AXI_SRAM;
wire [7:0] ARLEN_AXI_SRAM;
wire [2:0] ARSIZE_AXI_SRAM;
@@ -83,14 +83,14 @@ wire [3:0] ARCACHE_AXI_SRAM;
wire [2:0] ARPROT_AXI_SRAM;
wire ARVALID_AXI_SRAM;
wire ARREADY_AXI_SRAM;
-wire [3:0] RID_AXI_SRAM;
+wire [ID_W-1:0] RID_AXI_SRAM;
wire [31:0] RDATA_AXI_SRAM;
wire [1:0] RRESP_AXI_SRAM;
wire RLAST_AXI_SRAM;
wire RVALID_AXI_SRAM;
wire RREADY_AXI_SRAM;
// - Thin links out wires
-wire [3:0] AWID_AXI_TLX_OUT;
+wire [ID_W-1:0] AWID_AXI_TLX_OUT;
wire [31:0] AWADDR_AXI_TLX_OUT;
wire [7:0] AWLEN_AXI_TLX_OUT;
wire [2:0] AWSIZE_AXI_TLX_OUT;
@@ -105,11 +105,11 @@ wire [3:0] WSTRB_AXI_TLX_OUT;
wire WLAST_AXI_TLX_OUT;
wire WVALID_AXI_TLX_OUT;
wire WREADY_AXI_TLX_OUT;
-wire [3:0] BID_AXI_TLX_OUT;
+wire [ID_W-1:0] BID_AXI_TLX_OUT;
wire [1:0] BRESP_AXI_TLX_OUT;
wire BVALID_AXI_TLX_OUT;
wire BREADY_AXI_TLX_OUT;
-wire [3:0] ARID_AXI_TLX_OUT;
+wire [ID_W-1:0] ARID_AXI_TLX_OUT;
wire [31:0] ARADDR_AXI_TLX_OUT;
wire [7:0] ARLEN_AXI_TLX_OUT;
wire [2:0] ARSIZE_AXI_TLX_OUT;
@@ -119,7 +119,7 @@ wire [3:0] ARCACHE_AXI_TLX_OUT;
wire [2:0] ARPROT_AXI_TLX_OUT;
wire ARVALID_AXI_TLX_OUT;
wire ARREADY_AXI_TLX_OUT;
-wire [3:0] RID_AXI_TLX_OUT;
+wire [ID_W-1:0] RID_AXI_TLX_OUT;
wire [31:0] RDATA_AXI_TLX_OUT;
wire [1:0] RRESP_AXI_TLX_OUT;
wire RLAST_AXI_TLX_OUT;
@@ -137,7 +137,7 @@ wire [31:0] PRDATA_APB_PVT;
wire PSLVERR_APB_PVT;
wire PREADY_APB_PVT;
// - Chiplet In AXI port
-wire [3:0] AWID_AXI_CHIPLET_IN;
+wire [ID_W-1:0] AWID_AXI_CHIPLET_IN;
wire [31:0] AWADDR_AXI_CHIPLET_IN;
wire [7:0] AWLEN_AXI_CHIPLET_IN;
wire [2:0] AWSIZE_AXI_CHIPLET_IN;
@@ -152,11 +152,11 @@ wire [3:0] WSTRB_AXI_CHIPLET_IN;
wire WLAST_AXI_CHIPLET_IN;
wire WVALID_AXI_CHIPLET_IN;
wire WREADY_AXI_CHIPLET_IN;
-wire [3:0] BID_AXI_CHIPLET_IN;
+wire [ID_W-1:0] BID_AXI_CHIPLET_IN;
wire [1:0] BRESP_AXI_CHIPLET_IN;
wire BVALID_AXI_CHIPLET_IN;
wire BREADY_AXI_CHIPLET_IN;
-wire [3:0] ARID_AXI_CHIPLET_IN;
+wire [ID_W-1:0] ARID_AXI_CHIPLET_IN;
wire [31:0] ARADDR_AXI_CHIPLET_IN;
wire [7:0] ARLEN_AXI_CHIPLET_IN;
wire [2:0] ARSIZE_AXI_CHIPLET_IN;
@@ -166,7 +166,7 @@ wire [3:0] ARCACHE_AXI_CHIPLET_IN;
wire [2:0] ARPROT_AXI_CHIPLET_IN;
wire ARVALID_AXI_CHIPLET_IN;
wire ARREADY_AXI_CHIPLET_IN;
-wire [3:0] RID_AXI_CHIPLET_IN;
+wire [ID_W-1:0] RID_AXI_CHIPLET_IN;
wire [31:0] RDATA_AXI_CHIPLET_IN;
wire [1:0] RRESP_AXI_CHIPLET_IN;
wire RLAST_AXI_CHIPLET_IN;
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index b539c5e..9cf86bb 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -63,7 +63,7 @@ DATA_WIDTH: 32
# ID_WIDTH: AXI5 ID width for all channels
# Valid values:
# 2-32
-ID_WIDTH: 4
+ID_WIDTH: 12
#
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index aba6940..dfaa1e1 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>4</GlobalIDWidth>
+ <GlobalIDWidth>12</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -78,7 +78,7 @@
<AXI4SlaveProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
- <VIDWidth>4</VIDWidth>
+ <VIDWidth>12</VIDWidth>
<MultiRegion>false</MultiRegion>
<TrustZoneSlave>non_secure</TrustZoneSlave>
<ReadAcceptance>8</ReadAcceptance>
@@ -210,7 +210,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>4</pl_id_width>
+ <pl_id_width>12</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -386,7 +386,7 @@
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
- <vid_width>4</vid_width>
+ <vid_width>12</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
@@ -1038,9 +1038,9 @@
<name>AXI_CHIPLET_IN</name>
<master_if>AXI_SRAM</master_if>
<master_if>AXI_TLX_OUT</master_if>
- <master_if>apb_group0</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
+ <master_if>apb_group0</master_if>
</slave_if>
</link>
</architecture>
diff --git a/socrates/nic400_tb/nic400_tb.xml b/socrates/nic400_tb/nic400_tb.xml
index 5949711..fb83db2 100644
--- a/socrates/nic400_tb/nic400_tb.xml
+++ b/socrates/nic400_tb/nic400_tb.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>4</GlobalIDWidth>
+ <GlobalIDWidth>12</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -57,7 +57,7 @@
<AXI4SlaveProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
- <VIDWidth>4</VIDWidth>
+ <VIDWidth>12</VIDWidth>
<MultiRegion>false</MultiRegion>
<TrustZoneSlave>non_secure</TrustZoneSlave>
<ReadAcceptance>8</ReadAcceptance>
@@ -142,7 +142,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>4</pl_id_width>
+ <pl_id_width>12</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -292,7 +292,7 @@
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
- <vid_width>4</vid_width>
+ <vid_width>12</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
diff --git a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
index 209d99d..6c10541 100644
--- a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
+++ b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
@@ -15,7 +15,7 @@
<RUSERWidth>0</RUSERWidth>
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
- <IDWidth>4</IDWidth>
+ <IDWidth>12</IDWidth>
<AddressWidth>32</AddressWidth>
<SlaveDataWidth>32</SlaveDataWidth>
<MasterDataWidth>32</MasterDataWidth>
@@ -33,7 +33,7 @@
<SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
<MASTER_CLOCK>clk_m</MASTER_CLOCK>
<FW_USER_DEFINED_WIDTH>16</FW_USER_DEFINED_WIDTH>
- <FW_PACKING_STRATEGY>widest_div_4</FW_PACKING_STRATEGY>
+ <FW_PACKING_STRATEGY>user_def_bytes</FW_PACKING_STRATEGY>
<FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
<REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
<REV_USER_DEFINED_WIDTH>8</REV_USER_DEFINED_WIDTH>
@@ -107,14 +107,14 @@
<SLAVE_PREALLOC_4>false</SLAVE_PREALLOC_4>
<FW_PHYSICAL_LINK>16</FW_PHYSICAL_LINK>
<REV_PHYSICAL_LINK>16</REV_PHYSICAL_LINK>
- <FW_AXI_SIGNAL>151</FW_AXI_SIGNAL>
- <REV_AXI_SIGNAL>45</REV_AXI_SIGNAL>
- <FW_BANDWIDTH_PERCENTAGE>20</FW_BANDWIDTH_PERCENTAGE>
- <FW_UTILIZATION_PERCENTAGE>92</FW_UTILIZATION_PERCENTAGE>
+ <FW_AXI_SIGNAL>167</FW_AXI_SIGNAL>
+ <REV_AXI_SIGNAL>61</REV_AXI_SIGNAL>
+ <FW_BANDWIDTH_PERCENTAGE>19</FW_BANDWIDTH_PERCENTAGE>
+ <FW_UTILIZATION_PERCENTAGE>79</FW_UTILIZATION_PERCENTAGE>
<FW_REDUCTION_PERCENTAGE>90</FW_REDUCTION_PERCENTAGE>
- <REV_BANDWIDTH_PERCENTAGE>24</REV_BANDWIDTH_PERCENTAGE>
- <REV_UTILIZATION_PERCENTAGE>98</REV_UTILIZATION_PERCENTAGE>
- <REV_REDUCTION_PERCENTAGE>78</REV_REDUCTION_PERCENTAGE>
+ <REV_BANDWIDTH_PERCENTAGE>23</REV_BANDWIDTH_PERCENTAGE>
+ <REV_UTILIZATION_PERCENTAGE>96</REV_UTILIZATION_PERCENTAGE>
+ <REV_REDUCTION_PERCENTAGE>80</REV_REDUCTION_PERCENTAGE>
<DPEEnabled>false</DPEEnabled>
<ParityBitWidth>5</ParityBitWidth>
</Parameters>
@@ -226,7 +226,7 @@
<dpe_status>false</dpe_status>
<aruser_width>0</aruser_width>
<cc_type>async</cc_type>
- <pl_id_width>4</pl_id_width>
+ <pl_id_width>12</pl_id_width>
<ruser_width>0</ruser_width>
<wuser_width>0</wuser_width>
</global>
@@ -240,7 +240,7 @@
<pl_clock_ratio>1</pl_clock_ratio>
<dll_link_user_def_width>16</dll_link_user_def_width>
<pl_reg_stages>0</pl_reg_stages>
- <dll_link_width_option>widest_div_4</dll_link_width_option>
+ <dll_link_width_option>user_def_bytes</dll_link_width_option>
</fwd_tlx>
<rev_tlx>
<pl_clock_ratio>1</pl_clock_ratio>
@@ -301,7 +301,7 @@
<slave_if_data_width>32</slave_if_data_width>
<multi_ported>false</multi_ported>
<vn_external>none</vn_external>
- <vid_width>4</vid_width>
+ <vid_width>12</vid_width>
<apb_config>false</apb_config>
<qv_out>false</qv_out>
<master_if_addr_width>32</master_if_addr_width>
diff --git a/synopsys_28nm_slm_integration b/synopsys_28nm_slm_integration
index 5ece300..e88b3d4 160000
--- a/synopsys_28nm_slm_integration
+++ b/synopsys_28nm_slm_integration
@@ -1 +1 @@
-Subproject commit 5ece300bcb4e7dd8cd0c4cc141e7faa8f42e3e23
+Subproject commit e88b3d4335b8416b5d78322f45e099ac9a12a1d0
diff --git a/verif/cocotb/sram_chiplet_cocotb.sv b/verif/cocotb/sram_chiplet_cocotb.sv
index c50a7d4..d21548a 100644
--- a/verif/cocotb/sram_chiplet_cocotb.sv
+++ b/verif/cocotb/sram_chiplet_cocotb.sv
@@ -6,7 +6,7 @@ module sram_chiplet_cocotb(
input wire clk_in,
input wire aresetn,
- input wire [3:0] cocotb_awid,
+ input wire [11:0] cocotb_awid,
input wire [31:0] cocotb_awaddr,
input wire [7:0] cocotb_awlen,
input wire [2:0] cocotb_awsize,
@@ -21,11 +21,11 @@ module sram_chiplet_cocotb(
input wire cocotb_wlast,
input wire cocotb_wvalid,
output wire cocotb_wready,
- output wire [3:0] cocotb_bid,
+ output wire [11:0] cocotb_bid,
output wire [1:0] cocotb_bresp,
output wire cocotb_bvalid,
input wire cocotb_bready,
- input wire [3:0] cocotb_arid,
+ input wire [11:0] cocotb_arid,
input wire [31:0] cocotb_araddr,
input wire [7:0] cocotb_arlen,
input wire [2:0] cocotb_arsize,
@@ -35,7 +35,7 @@ module sram_chiplet_cocotb(
input wire [2:0] cocotb_arprot,
input wire cocotb_arvalid,
output wire cocotb_arready,
- output wire [3:0] cocotb_rid,
+ output wire [11:0] cocotb_rid,
output wire [31:0] cocotb_rdata,
output wire [1:0] cocotb_rresp,
output wire cocotb_rlast,
@@ -55,7 +55,7 @@ TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd[N_CHIPLETS+1]();
TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd[N_CHIPLETS+1]();
-wire [3:0] AWID_AXI_CHIPLET_OUT;
+wire [11:0] AWID_AXI_CHIPLET_OUT;
wire [31:0] AWADDR_AXI_CHIPLET_OUT;
wire [7:0] AWLEN_AXI_CHIPLET_OUT;
wire [2:0] AWSIZE_AXI_CHIPLET_OUT;
@@ -70,11 +70,11 @@ wire [3:0] WSTRB_AXI_CHIPLET_OUT;
wire WLAST_AXI_CHIPLET_OUT;
wire WVALID_AXI_CHIPLET_OUT;
wire WREADY_AXI_CHIPLET_OUT;
-wire [3:0] BID_AXI_CHIPLET_OUT;
+wire [11:0] BID_AXI_CHIPLET_OUT;
wire [1:0] BRESP_AXI_CHIPLET_OUT;
wire BVALID_AXI_CHIPLET_OUT;
wire BREADY_AXI_CHIPLET_OUT;
-wire [3:0] ARID_AXI_CHIPLET_OUT;
+wire [11:0] ARID_AXI_CHIPLET_OUT;
wire [31:0] ARADDR_AXI_CHIPLET_OUT;
wire [7:0] ARLEN_AXI_CHIPLET_OUT;
wire [2:0] ARSIZE_AXI_CHIPLET_OUT;
@@ -84,7 +84,7 @@ wire [3:0] ARCACHE_AXI_CHIPLET_OUT;
wire [2:0] ARPROT_AXI_CHIPLET_OUT;
wire ARVALID_AXI_CHIPLET_OUT;
wire ARREADY_AXI_CHIPLET_OUT;
-wire [3:0] RID_AXI_CHIPLET_OUT;
+wire [11:0] RID_AXI_CHIPLET_OUT;
wire [31:0] RDATA_AXI_CHIPLET_OUT;
wire [1:0] RRESP_AXI_CHIPLET_OUT;
wire RLAST_AXI_CHIPLET_OUT;
--
GitLab