From 8fda30ef5fd24df2c3348191b886c8c1e408b728 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 3 Sep 2024 15:35:47 +0100
Subject: [PATCH] Add Synopsys IP and ASIC flow for Fusion Compiler
---
.gitignore | 14 +
.gitmodules | 3 +
.../Synopsys_FC_flow/FC_flow.tcl | 16 ++
.../Synopsys_FC_flow/design_setup.tcl | 32 +++
.../Synopsys_FC_flow/floorplan/floorplan.def | 13 +
.../Synopsys_FC_flow/floorplan/floorplan.tcl | 51 ++++
.../floorplan/floorplan_compare_data.txt | 115 ++++++++
.../Synopsys_FC_flow/floorplan/fp.tcl | 171 ++++++++++++
.../Synopsys_FC_flow/floorplan/mapfile | 1 +
.../Synopsys_FC_flow/init_placement.tcl | 19 ++
.../Synopsys_FC_flow/power_plan.tcl | 16 ++
.../synopsys_lib_conversion.tcl | 70 +++++
.../constraints/sram_chiplet.sdc | 22 ++
ASIC/TSMC28nm_HPCP/sram_32b_16k.spec | 47 ++++
ASIC/TSMC28nm_HPCP/sram_32b_32k.spec | 2 +-
flist/IP/SIE300.flist | 22 +-
flist/IP/SIE300_sv.flist | 20 ++
flist/IP/Synopsys_VIP.flist | 11 +
flist/Top/sram_chiplet.flist | 14 +-
flist/Top/sram_chiplet_TSMC28nm.flist | 8 +-
flist/Top/sram_chiplet_TSMC28nm_ASIC.flist | 41 +++
flist/Top/sram_chiplet_sv.flist | 18 ++
flows/makefile.asic | 42 ++-
logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v | 101 +-------
.../SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v | 8 +-
logical/SRAM/glib/verilog/SRAM.v | 9 +
.../verilog/sram_chiplet_apb_subsystem.v | 245 ++++++++++++++++++
.../verilog/top_sram_chiplet.sv | 13 +-
makefile | 1 +
pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv | 145 +++++++++++
pad_level/tsmc28nm_hpcp/SRAM_chiplet.v | 53 ----
synopsys_28nm_slm_integration | 1 +
verif/cocotb/makefile | 3 +-
verif/cocotb/sram_chiplet_tests.py | 168 +++++++++++-
34 files changed, 1319 insertions(+), 196 deletions(-)
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/mapfile
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
create mode 100644 ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
create mode 100644 ASIC/TSMC28nm_HPCP/sram_32b_16k.spec
create mode 100644 flist/IP/SIE300_sv.flist
create mode 100644 flist/IP/Synopsys_VIP.flist
create mode 100644 flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
create mode 100644 flist/Top/sram_chiplet_sv.flist
create mode 100644 pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
delete mode 100644 pad_level/tsmc28nm_hpcp/SRAM_chiplet.v
create mode 160000 synopsys_28nm_slm_integration
diff --git a/.gitignore b/.gitignore
index b6ee89a..3fbd165 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,20 @@
.project
.ecmproject
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/cln28ht
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/.*
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/HDL_LIBRARIES
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/PreFrameCheck
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram_chiplet.dlib
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_PD
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_PLL
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_TS
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.svf
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.log
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.txt
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.png
+
logical/nic400_tb
logical/nic400_sram_chiplet/
logical/nic400_tlx_sram_chiplet/
diff --git a/.gitmodules b/.gitmodules
index b6b5886..ea845b0 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
[submodule "soctools_flow"]
path = soctools_flow
url = https://git.soton.ac.uk/soclabs/soctools_flow.git
+[submodule "synopsys_28nm_slm_integration"]
+ path = synopsys_28nm_slm_integration
+ url = https://git.soton.ac.uk/soclabs/synopsys_28nm_slm_integration.git
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
new file mode 100644
index 0000000..f9f2f84
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
@@ -0,0 +1,16 @@
+
+source ./design_setup.tcl
+
+source ./floorplan/fp.tcl
+read_sdc ../constraints/sram_chiplet.sdc
+
+source ./power_plan.tcl
+
+source ./init_placement.tcl
+
+redirect -tee -file ./compile.log {compile_fusion}
+save_lib sram_chiplet.dlib
+
+synthesize_clock_trunks -clock clk
+place_opt
+clock_opt
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
new file mode 100644
index 0000000..a672393
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
@@ -0,0 +1,32 @@
+set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+
+set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
+
+set TLU_cbest $TLU_dir/cbest.tluplus
+set TLU_cworst $TLU_dir/cworst.tluplus
+set TLU_rcbest $TLU_dir/rcbest.tluplus
+set TLU_rcworst $TLU_dir/rcworst.tluplus
+set TLU_map $TLU_dir/tluplus.map
+
+
+
+create_lib sram_chiplet.dlib \
+ -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf \
+ -ref_libs {./cln28ht/ ./sram/ ./Synopsys_PLL/ ./Synopsys_PD/ ./Synopsys_TS/}
+
+source $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/flist/synopsys_flist.tcl
+analyze -format sverilog $env(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
+
+elaborate SRAM_chiplet
+set_top_module SRAM_chiplet
+
+redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
+
+read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
+read_parasitic_tech -name rcworst -tlup $TLU_rcworst -layermap $TLU_map -sanity_check advanced
+
+save_lib sram_chiplet.dlib
+
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
new file mode 100644
index 0000000..6ef2e9d
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
@@ -0,0 +1,13 @@
+#
+# Fusion Compiler write_def
+# Release : U-2022.12
+# User Name : dwn1c21
+# Date : Tue Sep 3 14:17:43 2024
+#
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN SRAM_chiplet ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 0 1529700 ) ( 1789940 1529700 ) ( 1789940 0 ) ;
+END DESIGN
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
new file mode 100644
index 0000000..6f35619
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
@@ -0,0 +1,51 @@
+################################################################################
+#
+# Created by fc write_floorplan on Tue Sep 3 14:17:43 2024
+#
+################################################################################
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+source ${_dirName__0}/fp.tcl
+
+if { [get_attribute -name view_name [current_block]] == "design" } {
+ set __fp_crnt_design_name__ [get_attribute -name design_name [current_block]]
+ set __fp_crnt_label_name__ [get_attribute -name label_name [current_block]]
+ set __fp_crnt_lib_name__ [get_attribute -name lib_name [current_block]]
+ set __fp_crnt_lib_path__ [get_attribute -name source_file_name [current_lib]]
+ set __fp_crnt_abs_name__ ${__fp_crnt_lib_name__}:${__fp_crnt_design_name__}
+ set __fp_crnt_abs_path__ ${__fp_crnt_lib_path__}/${__fp_crnt_design_name__}
+ if { [string length ${__fp_crnt_label_name__} ] != 0 } {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}/${__fp_crnt_label_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/design_label.${__fp_crnt_label_name__}/abs
+ } else {
+ set __fp_crnt_abs_name__ ${__fp_crnt_abs_name__}.abstract
+ set __fp_crnt_abs_path__ ${__fp_crnt_abs_path__}/abs
+ }
+ if { [sizeof_collection [get_blocks -quiet ${__fp_crnt_abs_name__}]] != 0} {
+ if { [get_attribute -name has_editable_abstract [current_block]] } {
+ echo "Design [get_attribute -name full_name [current_block]] has editable abstract view. Re-creating the abstract view after floorplan loading..."
+ set __fp_crnt_abs_type__ [get_attribute -quiet -name abstract_view_type [current_block]]
+ if { [string length ${__fp_crnt_abs_type__} ] == 0 } {
+ if { [file exists "${__fp_crnt_abs_path__}/abs.mc"] } {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ } else {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ }
+ } elseif { ${__fp_crnt_abs_type__} == "placement" } {
+ echo "re-create placement abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract -placement
+ save_lib -all
+ } else {
+ echo "re-create timing abstract view for design [get_attribute -name full_name [current_block]]"
+ create_abstract
+ save_lib -all
+ }
+ }
+ }
+}
+
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
new file mode 100644
index 0000000..eeb6c76
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
@@ -0,0 +1,115 @@
+################################################################################
+#
+# Created by fc compare_floorplans on Tue Sep 3 14:17:43 2024
+#
+# DO NOT EDIT - automatically generated file
+#
+################################################################################
+
+START SRAM_chiplet
+ MACROS
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts { {120.0000 390.0600} {360.0000 590.0600} }
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd { {120.0000 618.3400} {205.0000 693.3400} }
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL { {120.0000 120.0000} {382.5000 360.0000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k { {387.3000 770.0650} {707.9600 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k { {707.9600 770.0650} {1028.6200 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k { {1028.6200 770.0650} {1349.2800 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k { {1349.2800 770.0650} {1669.9400 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k { {1349.2800 120.0000} {1669.9400 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k { {1028.6200 120.0000} {1349.2800 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k { {707.9600 120.0000} {1028.6200 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k { {387.3000 120.0000} {707.9600 759.6350} }
+ PINS
+ clk_in { {894.9700 764.8500} {894.9701 764.8501} }
+ aresetn { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_rev_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_rev_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_rev_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_rev_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_rev_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_rev_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_fwd_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_fwd_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_fwd_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_flow_fwd_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_IN_data_fwd_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_rev_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_rev_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_rev_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_rev_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_rev_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_rev_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_fwd_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_fwd_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_fwd_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_flow_fwd_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
+ TLX_data_fwd_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
+END SRAM_chiplet
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
new file mode 100644
index 0000000..d30045d
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
@@ -0,0 +1,171 @@
+################################################################################
+#
+# Created by fc write_floorplan on Tue Sep 3 14:17:43 2024
+#
+################################################################################
+initialize_floorplan -control_type die -use_site_row -side_length {1790 1530} -core_offset {120}
+
+
+set _dirName__0 [file dirname [file normalize [info script]]]
+
+################################################################################
+# Read DEF
+################################################################################
+
+read_def ${_dirName__0}/floorplan.def
+
+################################################################################
+# Macros
+################################################################################
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 390.0600 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 618.3400 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ }]
+set_attribute -quiet -objects $cellInst -name orientation -value R0
+set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 120.0000 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 707.9600 770.0650 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1028.6200 \
+ 770.0650 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1349.2800 \
+ 770.0650 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1669.9400 \
+ 770.0650 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 1349.2800 \
+ 759.6350 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 1028.6200 \
+ 759.6350 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 707.9600 759.6350 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 387.3000 759.6350 \
+ }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
+
+
+################################################################################
+# User attributes of macros
+################################################################################
+
+
+################################################################################
+# I/O guides
+################################################################################
+
+remove_io_guides -all
+
+
+################################################################################
+# User attributes of I/O guides
+################################################################################
+
+
+################################################################################
+# User attributes of current block
+################################################################################
+
+
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/mapfile b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/mapfile
new file mode 100644
index 0000000..f548a1c
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/mapfile
@@ -0,0 +1 @@
+SRAM_chiplet FLOORPLAN fp.tcl
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
new file mode 100644
index 0000000..b3749f8
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
@@ -0,0 +1,19 @@
+set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library sram_chiplet.dlib
+set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ssg_cworstt_max_0p81v_125c
+
+redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
+
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_cd_pl_rev_M1_m_tlx}]
+change_selection [get_cells u_top_sram_chiplet/u_master_pwr_M1_m_tlx]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_master_pwr_M1_m_tlx}]
+change_selection [get_cells u_top_sram_chiplet/eq_268]
+change_selection [get_cells u_top_sram_chiplet/u_nic400_sram_chiplet]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_nic400_sram_chiplet}]
+change_selection [get_cells u_top_sram_chiplet/u_slave_pwd_M1_m_tlx]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_slave_pwd_M1_m_tlx}]
+change_selection [get_cells u_top_sram_chiplet/u_pl_fwd_M1_m_tlx_m]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_pl_fwd_M1_m_tlx_m}]
+change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper}]
+explore_logic_hierarchy -place -rectangular
+save_lib sram_chiplet.dlib
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
new file mode 100644
index 0000000..b15c60c
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
@@ -0,0 +1,16 @@
+connect_pg_net -automatic
+
+create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
+ -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+
+create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
+ {{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
+create_pg_std_cell_conn_pattern std_pattern -layers M1
+
+set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
+set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core
+set_pg_strategy std_cell_strat -core -pattern {{name: std_pattern} {nets: {VDD VSS}}}
+
+compile_pg -strategies core_ring
+compile_pg -strategies M5M8_mesh
+compile_pg -strategies std_cell_strat
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
new file mode 100644
index 0000000..b32ac35
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
@@ -0,0 +1,70 @@
+# Technology files
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf
+set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.lef
+
+# Standard Cell libraries
+set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
+set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
+set sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
+set sc9mcpp140z_db_file_ff_0p99v_m40C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+
+# SRAM files (using Arm compiler)
+set sram_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k.lef
+set sram_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k.gds2
+set sram_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.db
+
+# Synopsys PLL files
+set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
+set Synopsys_PLL_lef_file $Synopsys_PLL_dir/lef/5m4x0z/dwc_z19606ts_ns_merged.lef
+set Synopsys_PLL_db_file $Synopsys_PLL_dir/timing/lib_pg/dwc_z19606ts_ns_ssg0p81v125c_cworst_pg.db
+set Synopsys_PLL_gds_file $Synopsys_PLL_dir/gds/5m4x0z/dwc_z19606ts_ns.gds
+
+# Synopsys Temperature sensor files
+set Synopsys_TS_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b
+set Synopsys_TS_lef_file $Synopsys_TS_dir/lef/mr74127.lef
+set Synopsys_TS_lib_file $Synopsys_TS_dir/liberty/mr74127_wc_vmin_125c.lib
+set Synopsys_TS_db_file $Synopsys_TS_dir/db/mr74127_wc_vmin_125c.db
+set Synopsys_TS_gds_file $Synopsys_TS_dir/gdsii/mr74127_v1r1.gds
+
+# Synopsys Process detector Files
+set Synopsys_PD_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a
+set Synopsys_PD_lef_file $Synopsys_PD_dir/lef/mr74125.lef
+set Synopsys_PD_lib_file $Synopsys_PD_dir/liberty/mr74125_wc_vmin_125c.lib
+set Synopsys_PD_db_file $Synopsys_PD_dir/db/mr74125_wc_vmin_125c.db
+set Synopsys_PD_gds_file $Synopsys_PD_dir/gds/mr74125_v1r2.gds
+
+
+create_fusion_lib -dbs [list $sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $sc9mcpp140z_lef_file] -technology $cln28ht_tech_file cln28ht
+save_fusion_lib cln28ht
+
+close_fusion_lib cln28ht
+
+read_lib $sram_lib_file
+write_lib -output $sram_db_file -format db sram_sp_hde_ssg_cworstt_0p81v_0p81v_125c
+close_lib sram_sp_hde_ssg_cworstt_0p81v_0p81v_125c
+create_fusion_lib -dbs $sram_db_file -lefs $sram_lef_file -technology $cln28ht_tech_file sram
+save_fusion_lib sram
+close_fusion_lib sram
+
+create_fusion_lib -dbs $Synopsys_PLL_db_file -lefs $Synopsys_PLL_lef_file -technology $cln28ht_tech_file Synopsys_PLL
+save_fusion_lib Synopsys_PLL
+close_fusion_lib Synopsys_PLL
+
+read_lib $Synopsys_TS_lib_file
+write_lib -output $Synopsys_TS_db_file -format db mr74127_wc_vmin_125c
+close_lib -all
+create_fusion_lib -dbs $Synopsys_TS_db_file -lefs $Synopsys_TS_lef_file -technology $cln28ht_tech_file Synopsys_TS
+save_fusion_lib Synopsys_TS
+close_fusion_lib Synopsys_TS
+
+read_lib $Synopsys_PD_lib_file
+write_lib -output $Synopsys_PD_db_file -format db mr74125_wc_vmin_125c
+close_lib -all
+create_fusion_lib -dbs $Synopsys_PD_db_file -lefs $Synopsys_PD_lef_file -technology $cln28ht_tech_file Synopsys_PD
+save_fusion_lib Synopsys_PD
+close_fusion_lib Synopsys_PD
diff --git a/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
new file mode 100644
index 0000000..4e60e01
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
@@ -0,0 +1,22 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### CLOCK DEFINITION
+
+set EXTCLK "clk";
+set_units -time ns;
+
+set_units -capacitance pF;
+set EXTCLK_PERIOD 1;
+set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
+set INTER_CLOCK_UNCERTAINTY 0.1
+
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 0.5" [get_ports clk_in]
diff --git a/ASIC/TSMC28nm_HPCP/sram_32b_16k.spec b/ASIC/TSMC28nm_HPCP/sram_32b_16k.spec
new file mode 100644
index 0000000..56248fd
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/sram_32b_16k.spec
@@ -0,0 +1,47 @@
+# user spec file, compiler sram_sp_hde_2_svt_mvt, version r0p0
+
+EOL_guardband = 0
+activity_factor = 10
+atf = off
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+compiler_type = sp
+corners = ffg_cbestt_0p99v_0p99v_0c,ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ffg_ctypical_0p90v_0p90v_85c,ffg_ctypical_0p99v_0p99v_125c,ssg_cworstt_0p81v_0p81v_0c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,tt_ctypical_0p81v_0p81v_0c,tt_ctypical_0p90v_0p90v_125c,tt_ctypical_0p90v_0p90v_25c,tt_ctypical_0p90v_0p90v_85c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+fci_type = not_fci
+flexible_banking = 8
+frequency = 1000
+instname = sram_32b_16k
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = sram_sp_hde
+lren_bankmask = off
+metal_stack =
+mux = 8
+mvt = LL
+name_case = upper
+pipeline = off
+power_gating = off
+power_type = otc
+prefix =
+pwr_gnd_rename = vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+rcols = 2
+redundancy = off
+retention = on
+right_bus_delim = ]
+rows_p_bl = 256
+rrows = 0
+scan = off
+ser = none
+site_def = off
+wa = off
+words = 16384
+wp_size = 1
+write_mask = on
+write_thru = off
diff --git a/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec b/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
index 92253f8..45c7727 100644
--- a/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
+++ b/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
@@ -20,7 +20,7 @@ frequency = 500
instname = sram_32b_32k
left_bus_delim = [
libertyviewstyle = nldm
-libname = sram_sp_hde
+libname = sram_32b_32k
lren_bankmask = off
metal_stack =
mux = 16
diff --git a/flist/IP/SIE300.flist b/flist/IP/SIE300.flist
index 1ae4565..a93beb0 100644
--- a/flist/IP/SIE300.flist
+++ b/flist/IP/SIE300.flist
@@ -2,23 +2,5 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_addr_dec.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arb.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arq.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_awq.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_axi_mux.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_bq.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_clamp.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_eam.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo_core.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_lpi_ctrl.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_one_hot.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rbeat.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_resp_gen.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rq.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wbeat.sv
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wq.sv
\ No newline at end of file
+
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300_sv.flist
\ No newline at end of file
diff --git a/flist/IP/SIE300_sv.flist b/flist/IP/SIE300_sv.flist
new file mode 100644
index 0000000..85eb182
--- /dev/null
+++ b/flist/IP/SIE300_sv.flist
@@ -0,0 +1,20 @@
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_addr_dec.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arb.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_awq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_axi_mux.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_bq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_clamp.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_eam.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo_core.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_lpi_ctrl.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_one_hot.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rbeat.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_resp_gen.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wbeat.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wq.sv
diff --git a/flist/IP/Synopsys_VIP.flist b/flist/IP/Synopsys_VIP.flist
new file mode 100644
index 0000000..87ea944
--- /dev/null
+++ b/flist/IP/Synopsys_VIP.flist
@@ -0,0 +1,11 @@
+
++incdir+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b/model/verilog/
+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b/model/verilog/mr74127.v
+
++incdir+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a/model/verilog
+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a/model/verilog/mr74125.v
+
++incdir+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_vm_shrink_tsmc28hpcp_1.00a/synopsys/dwc_sensors_vm_shrink_tsmc28hpcp/1.00a/model/verilog
+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_vm_shrink_tsmc28hpcp_1.00a/synopsys/dwc_sensors_vm_shrink_tsmc28hpcp/1.00a/model/verilog/mr74140.v
+
+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro/behavior/dwc_z19606ts_ns_gtech.v
\ No newline at end of file
diff --git a/flist/Top/sram_chiplet.flist b/flist/Top/sram_chiplet.flist
index e8c4654..258ec16 100644
--- a/flist/Top/sram_chiplet.flist
+++ b/flist/Top/sram_chiplet.flist
@@ -15,10 +15,7 @@
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/interfaces
-
-// SRAM Chiplet top level
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
// SRAM Chiplet - SRAM
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM_wrapper.v
@@ -26,6 +23,12 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_VM_sensor_integration.v
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/Synopsys_VIP.flist
// Testbench IP
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_vip.flist
@@ -37,4 +40,5 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chip
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/NIC400.flist
// SIE300 SRAM controller
--f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300.flist
\ No newline at end of file
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300.flist
+
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
index 8b11a2a..0ddb049 100644
--- a/flist/Top/sram_chiplet_TSMC28nm.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -16,7 +16,7 @@
+libext+.v+.vlib
// SRAM Chiplet top level
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
// SRAM Chiplet - SRAM
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
@@ -25,6 +25,12 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_emulation.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_VM_sensor_integration.v
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/Synopsys_VIP.flist
// Testbench IP
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_vip.flist
diff --git a/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
new file mode 100644
index 0000000..59c67af
--- /dev/null
+++ b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
@@ -0,0 +1,41 @@
+//-----------------------------------------------------------------------------
+// SRAM Chiplet IP Filelist for TSMC 28nm HPC+
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// SRAM Chiplet top level
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
+
+// SRAM Chiplet - SRAM
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+
+// SRAM Chiplet - APB subsystem
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_VM_sensor_integration.v
+
+// Thin links
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/TLX400.flist
+
+// SRAM Chiplet - NIC400
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/NIC400.flist
+
+// SIE300 SRAM controller
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300.flist
+
diff --git a/flist/Top/sram_chiplet_sv.flist b/flist/Top/sram_chiplet_sv.flist
new file mode 100644
index 0000000..d927cfc
--- /dev/null
+++ b/flist/Top/sram_chiplet_sv.flist
@@ -0,0 +1,18 @@
+//-----------------------------------------------------------------------------
+// SRAM Chiplet IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/interfaces
+
+// SRAM Chiplet top level
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
diff --git a/flows/makefile.asic b/flows/makefile.asic
index bea50ad..ebd3767 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -11,19 +11,41 @@ SYNOPSYS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/synopsys_flist.tcl
# Location of Macros
MEMORIES_DIR := $(SOCLABS_SRAM_CHIPLET_DIR)/memories
-SRAM_SPEC_FILE := $(SOCLABS_SRAM_CHIPLET_DIR)/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
+MEM_32K_DIR := $(MEMORIES_DIR)/sram_32b_32k
+MEM_16K_DIR := $(MEMORIES_DIR)/sram_32b_16k
+
+SRAM_32K_SPEC_FILE := $(SOCLABS_SRAM_CHIPLET_DIR)/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
+SRAM_16K_SPEC_FILE := $(SOCLABS_SRAM_CHIPLET_DIR)/ASIC/TSMC28nm_HPCP/sram_32b_16k.spec
flist_synopsys:
@mkdir -p $(TCL_ASIC_FLIST_DIR)
@(cd $(TCL_ASIC_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(SYNOPSYS_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_SRAM_CHIPLET_ASIC_DIR)/src;)
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC_ASIC) -o $(SYNOPSYS_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_SRAM_CHIPLET_ASIC_DIR)/src;)
+
+gen_memories_frontend:
+ @mkdir -p $(MEMORIES_DIR)
+ @mkdir -p $(MEM_32K_DIR)
+ @mkdir -p $(MEM_16K_DIR)
+ echo "Generating 32K SRAM Memory"
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(SRAM_32K_SPEC_FILE)
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(SRAM_32K_SPEC_FILE)
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(SRAM_32K_SPEC_FILE)
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(SRAM_32K_SPEC_FILE)
+ echo "Generating 16K SRAM Memory"
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(MEM_16K_DIR)
-gen_memories:
+gen_memories_backend:
@mkdir -p $(MEMORIES_DIR)
- echo "Generating SRAM Memory"
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(SRAM_SPEC_FILE)
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(SRAM_SPEC_FILE)
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(SRAM_SPEC_FILE)
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(SRAM_SPEC_FILE)
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_SPEC_FILE)
- cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_SPEC_FILE)
+ @mkdir -p $(MEM_32K_DIR)
+ @mkdir -p $(MEM_16K_DIR)
+ echo "Generating 32K SRAM Memory"
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_32K_SPEC_FILE)
+ cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_32K_SPEC_FILE)
+ echo "Generating 16K SRAM Memory"
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(MEM_16K_DIR)
+
+gen_memories: gen_memories_frontend gen_memories_backend
\ No newline at end of file
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
index 08ab779..99cea2b 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
@@ -10,6 +10,7 @@ module SRAM (
);
localparam N_MEMS = 8;
+localparam SEL_W = 3;
reg [N_MEMS-1:0] CEN_i; //Active low chip select
wire [31:0] wena_i;
@@ -26,7 +27,7 @@ generate for(i=0; i<N_MEMS; i = i + 1) begin: g_srams
.CLK(clk),
.CEN(CEN_i[i]),
.GWEN(gwen_i),
- .A(memaddr[14:0]),
+ .A(memaddr[16:2]),
.D(memd),
.WEN(wena_i),
.STOV(1'b0),
@@ -38,97 +39,15 @@ generate for(i=0; i<N_MEMS; i = i + 1) begin: g_srams
end endgenerate
+integer j;
always @(*) begin
- case(memaddr[20:15])
- 6'h00 : begin
- CEN_i[0]=memcen;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[0];
- end
- 6'h01 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=memcen;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[1];
- end
- 6'h02 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=memcen;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[2];
- end
- 6'h03 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=memcen;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[3];
- end
- 6'h04 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=memcen;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[4];
- end
- 6'h05 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=memcen;
- CEN_i[6]=1'b1;
- CEN_i[7]=1'b1;
- memq = q_i[5];
- end
- 6'h06 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=memcen;
- CEN_i[7]=1'b1;
- memq = q_i[6];
- end
- 6'h07 : begin
- CEN_i[0]=1'b1;
- CEN_i[1]=1'b1;
- CEN_i[2]=1'b1;
- CEN_i[3]=1'b1;
- CEN_i[4]=1'b1;
- CEN_i[5]=1'b1;
- CEN_i[6]=1'b1;
- CEN_i[7]=memcen;
- memq = q_i[7];
- end
- endcase
+ for(j=0; j<N_MEMS; j=j+1) begin
+ if(j==memaddr[(SEL_W+17-1):17])
+ CEN_i[j] = memcen;
+ else
+ CEN_i[j] = 1'b1;
+ end
+ memq = q_i[memaddr[(SEL_W+17-1):17]];
end
endmodule
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
index 1615cb2..b5bc425 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
@@ -18,7 +18,7 @@ module SRAM_wrapper(
input wire AWVALID,
output wire AWREADY,
- input wire [4:0] AWID,
+ input wire [3:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
@@ -36,12 +36,12 @@ module SRAM_wrapper(
output wire BVALID,
input wire BREADY,
- output wire [4:0] BID,
+ output wire [3:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
- input wire [4:0] ARID,
+ input wire [3:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
@@ -52,7 +52,7 @@ module SRAM_wrapper(
output wire RVALID,
input wire RREADY,
- output wire [4:0] RID,
+ output wire [3:0] RID,
output wire [31:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
diff --git a/logical/SRAM/glib/verilog/SRAM.v b/logical/SRAM/glib/verilog/SRAM.v
index 42fd655..a7ec6e0 100644
--- a/logical/SRAM/glib/verilog/SRAM.v
+++ b/logical/SRAM/glib/verilog/SRAM.v
@@ -28,6 +28,15 @@ module SRAM (
reg [31:0] mem [MEM_DEPTH-1:0];
assign WriteEnable = (memwen != {4{1'b1}}) ? 1'b1 : 1'b0;
+`ifdef INITIALIZE_MEMORY
+ integer i;
+ initial begin
+ #0;
+ for(i=0;i < MEM_DEPTH;i = i + 1)
+ mem[i] = {32{1'b0}};
+ end
+`endif
+
always @ (posedge clk)
begin : p_memaccess
// Only access the memory when the chip is enabled
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
index 8c366c7..566c48a 100644
--- a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+++ b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
@@ -1,6 +1,251 @@
module sram_chiplet_apb_subsystem(
+ input wire ref_clk,
+ input wire PCLK,
+ input wire aRESETn,
+ input wire [31:0] PADDR_APB_PVT,
+ input wire [31:0] PWDATA_APB_PVT,
+ input wire PWRITE_APB_PVT,
+ input wire [2:0] PPROT_APB_PVT,
+ input wire [3:0] PSTRB_APB_PVT,
+ input wire PENABLE_APB_PVT,
+ input wire PSELx_APB_PVT,
+ output wire [31:0] PRDATA_APB_PVT,
+ output wire PSLVERR_APB_PVT,
+ output wire PREADY_APB_PVT
);
+localparam SNPS_PVT_TS_0_ENABLE=1;
+localparam SNPS_PVT_PD_0_ENABLE=1;
+localparam SNPS_PVT_VM_0_ENABLE=1;
+localparam SNPS_PLL_ENABLE=1;
+
+wire snps_PVT_ts0_psel;
+wire snps_PVT_ts0_pready;
+wire [31:0] snps_PVT_ts0_prdata;
+wire snps_PVT_ts0_pslverr;
+
+wire snps_PVT_pd0_psel;
+wire snps_PVT_pd0_pready;
+wire [31:0] snps_PVT_pd0_prdata;
+wire snps_PVT_pd0_pslverr;
+
+wire snps_PVT_vm0_psel;
+wire snps_PVT_vm0_pready;
+wire [31:0] snps_PVT_vm0_prdata;
+wire snps_PVT_vm0_pslverr;
+
+wire snps_PLL_psel;
+wire snps_PLL_pready;
+wire [31:0] snps_PLL_prdata;
+wire snps_PLL_pslverr;
+
+
+cmsdk_apb_slave_mux #(
+ .PORT0_ENABLE (SNPS_PVT_TS_0_ENABLE),
+ .PORT1_ENABLE (0),
+ .PORT2_ENABLE (0),
+ .PORT3_ENABLE (0),
+ .PORT4_ENABLE (0),
+ .PORT5_ENABLE (0),
+ .PORT6_ENABLE (SNPS_PVT_PD_0_ENABLE),
+ .PORT7_ENABLE (SNPS_PVT_VM_0_ENABLE),
+ .PORT8_ENABLE (SNPS_PLL_ENABLE),
+ .PORT9_ENABLE (0),
+ .PORT10_ENABLE (0),
+ .PORT11_ENABLE (0),
+ .PORT12_ENABLE (0),
+ .PORT13_ENABLE (0),
+ .PORT14_ENABLE (0),
+ .PORT15_ENABLE (0)
+) u_apb_PVT_slave_mux (
+ // Inputs
+ .DECODE4BIT (PADDR_APB_PVT[15:12]),
+ .PSEL (PSELx_APB_PVT),
+ // PSEL (output) and return status & data (inputs) for each port
+ .PSEL0 (snps_PVT_ts0_psel),
+ .PREADY0 (snps_PVT_ts0_pready),
+ .PRDATA0 (snps_PVT_ts0_prdata),
+ .PSLVERR0 (snps_PVT_ts0_pslverr),
+
+ .PSEL1 (),
+ .PREADY1 (1'b1),
+ .PRDATA1 ({32{1'b0}}),
+ .PSLVERR1 (1'b1),
+
+ .PSEL2 (),
+ .PREADY2 (1'b1),
+ .PRDATA2 ({32{1'b0}}),
+ .PSLVERR2 (1'b1),
+
+ .PSEL3 (),
+ .PREADY3 (1'b1),
+ .PRDATA3 ({32{1'b0}}),
+ .PSLVERR3 (1'b1),
+
+ .PSEL4 (),
+ .PREADY4 (1'b1),
+ .PRDATA4 ({32{1'b0}}),
+ .PSLVERR4 (1'b1),
+
+ .PSEL5 (),
+ .PREADY5 (1'b1),
+ .PRDATA5 ({32{1'b0}}),
+ .PSLVERR5 (1'b1),
+
+ .PSEL6 (snps_PVT_pd0_psel),
+ .PREADY6 (snps_PVT_pd0_pready),
+ .PRDATA6 (snps_PVT_pd0_prdata),
+ .PSLVERR6 (snps_PVT_pd0_pslverr),
+
+ .PSEL7 (snps_PVT_vm0_psel),
+ .PREADY7 (snps_PVT_vm0_pready),
+ .PRDATA7 (snps_PVT_vm0_prdata),
+ .PSLVERR7 (snps_PVT_vm0_pslverr),
+
+ .PSEL8 (snps_PLL_psel),
+ .PREADY8 (snps_PLL_pready),
+ .PRDATA8 (snps_PLL_prdata),
+ .PSLVERR8 (snps_PLL_pslverr),
+
+ .PSEL9 (),
+ .PREADY9 (1'b1),
+ .PRDATA9 ({32{1'b0}}),
+ .PSLVERR9 (1'b1),
+
+ .PSEL10 (),
+ .PREADY10 (1'b1),
+ .PRDATA10 ({32{1'b0}}),
+ .PSLVERR10 (1'b1),
+
+ .PSEL11 (),
+ .PREADY11 (1'b1),
+ .PRDATA11 ({32{1'b0}}),
+ .PSLVERR11 (1'b1),
+
+ .PSEL12 (),
+ .PREADY12 (1'b1),
+ .PRDATA12 ({32{1'b0}}),
+ .PSLVERR12 (1'b1),
+
+ .PSEL13 (),
+ .PREADY13 (1'b1),
+ .PRDATA13 ({32{1'b0}}),
+ .PSLVERR13 (1'b1),
+
+ .PSEL14 (),
+ .PREADY14 (1'b1),
+ .PRDATA14 ({32{1'b0}}),
+ .PSLVERR14 (1'b1),
+
+ .PSEL15 (),
+ .PREADY15 (1'b1),
+ .PRDATA15 ({32{1'b0}}),
+ .PSLVERR15 (1'b1),
+
+ // Output
+ .PREADY (PREADY_APB_PVT),
+ .PRDATA (PRDATA_APB_PVT),
+ .PSLVERR (PSLVERR_APB_PVT)
+ );
+
+generate if(SNPS_PVT_TS_0_ENABLE==1)begin: gen_snps_PVT_ts0
+ synopsys_TS_sensor_integration u_snps_PVT_ts0(
+ .PCLK(PCLK),
+ .aRESETn(aRESETn),
+
+ .PSELx(snps_PVT_ts0_psel),
+ .PADDR(PADDR_APB_PVT[3:2]),
+ .PENABLE(PENABLE_APB_PVT),
+ .PPROT(PPROT_APB_PVT),
+ .PSTRB(PSTRB_APB_PVT),
+ .PWRITE(PWRITE_APB_PVT),
+ .PWDATA(PWDATA_APB_PVT),
+ .PRDATA(snps_PVT_ts0_prdata),
+ .PREADY(snps_PVT_ts0_pready),
+ .PSLVERR(snps_PVT_ts0_pslverr),
+
+ .ts_vcal(TS_VCAL),
+ .ts_an_test_0(),
+ .ts_an_test_1(),
+ .ts_an_test_2(),
+ .ts_an_test_3(),
+ .ts_vss_sense(TS_VSS_SENSE),
+ .irq_ts_rdy(irq_ts_rdy)
+ );
+end else begin: gen_no_snps_PVT_ts0
+ assign snps_PVT_ts0_prdata = {32{1'b0}};
+ assign snps_PVT_ts0_pready = 1'b1;
+ assign snps_PVT_ts0_pslverr = 1'b1;
+ assign irq_ts_rdy = 1'b0;
+end endgenerate
+
+generate if(SNPS_PVT_PD_0_ENABLE==1)begin: gen_snps_PVT_pd0
+ synopsys_PD_sensor_integration u_snps_PVT_pd0(
+ .PCLK(PCLK),
+ .aRESETn(aRESETn),
+ .PSELx(snps_PVT_pd0_psel),
+ .PADDR(PADDR_APB_PVT[3:2]),
+ .PENABLE(PENABLE_APB_PVT),
+ .PPROT(PPROT_APB_PVT),
+ .PSTRB(PSTRB_APB_PVT),
+ .PWRITE(PWRITE_APB_PVT),
+ .PWDATA(PWDATA_APB_PVT),
+ .PRDATA(snps_PVT_pd0_prdata),
+ .PREADY(snps_PVT_pd0_pready),
+ .PSLVERR(snps_PVT_pd0_pslverr),
+ .irq_pd_rdy(irq_pd_rdy)
+ );
+end else begin: gen_no_snps_PVT_pd0
+ assign snps_PVT_pd0_prdata = {32{1'b0}};
+ assign snps_PVT_pd0_pready = 1'b1;
+ assign snps_PVT_pd0_pslverr = 1'b1;
+ assign irq_pd_rdy = 1'b0;
+end endgenerate
+
+generate if(SNPS_PVT_VM_0_ENABLE==1)begin: gen_snps_PVT_vm0
+
+
+end else begin: gen_no_snps_PVT_vm0
+ assign snps_PVT_vm0_prdata = {32{1'b0}};
+ assign snps_PVT_vm0_pready = 1'b1;
+ assign snps_PVT_vm0_pslverr = 1'b1;
+ assign irq_vm_rdy = 1'b0;
+end endgenerate
+
+generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
+ snps_PLL_integration_layer #(
+ .DEFAULT_FBDIV(7'h08), // Multiply by 8 (250*8 = 2 GHz)
+ .DEFAULT_DIVVCOP(4'h0), // Divider = 1
+ .DEFAULT_DIVVCOR(4'h0), // Divider = 1
+ .DEFAULT_P(6'h01), // Divider = 2 (out 1 GHz)
+ .DEFAULT_R(6'h07), // Divier = 8 (out 250 MHz)
+ .DEFAULT_PREDIV(5'h00) // Pre div = 2 (250/1 = 250 MHz)
+ ) u_snps_PLL(
+ .ref_clk(PCLK),
+ .resetn(aRESETn),
+ .pll_lock(),
+
+ .out_clk1(),
+ .out_clk2(),
+
+ .PSELx(snps_PLL_psel),
+ .PADDR(PADDR_APB_PVT[11:2]),
+ .PENABLE(PENABLE_APB_PVT),
+ .PPROT(PPROT_APB_PVT),
+ .PSTRB(PSTRB_APB_PVT),
+ .PWRITE(PWRITE_APB_PVT),
+ .PWDATA(PWDATA_APB_PVT),
+ .PRDATA(snps_PLL_prdata),
+ .PREADY(snps_PLL_pready),
+ .PSLVERR(snps_PLL_pslverr)
+ );
+end else begin: gen_no_snps_PLL
+ assign snps_PLL_prdata = {32{1'b0}};
+ assign snps_PLL_pready = 1'b1;
+ assign snps_PLL_pslverr = 1'b1;
+end endgenerate
+
+
endmodule
\ No newline at end of file
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
index 9c80679..34510f4 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
@@ -488,7 +488,18 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
);
sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
-
+ .PCLK(SYS_CLK),
+ .aRESETn(aRESETn),
+ .PADDR_APB_PVT(PADDR_APB_PVT),
+ .PWDATA_APB_PVT(PWDATA_APB_PVT),
+ .PWRITE_APB_PVT(PWRITE_APB_PVT),
+ .PPROT_APB_PVT(PPROT_APB_PVT),
+ .PSTRB_APB_PVT(PSTRB_APB_PVT),
+ .PENABLE_APB_PVT(PENABLE_APB_PVT),
+ .PSELx_APB_PVT(PSELx_APB_PVT),
+ .PRDATA_APB_PVT(PRDATA_APB_PVT),
+ .PSLVERR_APB_PVT(PSLVERR_APB_PVT),
+ .PREADY_APB_PVT(PREADY_APB_PVT)
);
SRAM_wrapper u_SRAM_wrapper(
diff --git a/makefile b/makefile
index c389567..f60a4ca 100644
--- a/makefile
+++ b/makefile
@@ -43,6 +43,7 @@ SIM_DIR ?= $(SIM_TOP_DIR)
ifeq ($(ASIC),yes)
+ DESIGN_VC_ASIC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm.flist
else
DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet.flist
diff --git a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
new file mode 100644
index 0000000..e344f36
--- /dev/null
+++ b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
@@ -0,0 +1,145 @@
+//-----------------------------------------------------------------------------
+// Top pad level of SRAM chiplet for TSMC 28nm HPC+
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+`include "tlx_interfaces.sv"
+module SRAM_chiplet(
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ input wire clk_in,
+ input wire aresetn,
+
+ // TLX_IN_data_rev_0 tlx out
+ output wire [15:0] TLX_IN_data_rev_0_tdata,
+ output wire TLX_IN_data_rev_0_tvalid,
+ input wire TLX_IN_data_rev_0_tready,
+
+ //TLX_IN_flow_rev_0 tlx out
+ output wire [2:0] TLX_IN_flow_rev_0_tdata,
+ output wire TLX_IN_flow_rev_0_tvalid,
+ input wire TLX_IN_flow_rev_0_tready,
+
+ //tlx in
+ input wire [1:0] TLX_IN_flow_fwd_0_tdata,
+ input wire TLX_IN_flow_fwd_0_tvalid,
+ output wire TLX_IN_flow_fwd_0_tready,
+
+ //tlx in
+ input wire [15:0] TLX_IN_data_fwd_0_tdata,
+ input wire TLX_IN_data_fwd_0_tvalid,
+ output wire TLX_IN_data_fwd_0_tready,
+
+ //tlx in
+ input wire [15:0] TLX_data_rev_1_tdata,
+ input wire TLX_data_rev_1_tvalid,
+ output wire TLX_data_rev_1_tready,
+
+ //tlx in
+ input wire [2:0] TLX_flow_rev_1_tdata,
+ input wire TLX_flow_rev_1_tvalid,
+ output wire TLX_flow_rev_1_tready,
+
+ // tlx out
+ output wire [1:0] TLX_flow_fwd_1_tdata,
+ output wire TLX_flow_fwd_1_tvalid,
+ input wire TLX_flow_fwd_1_tready,
+
+ // tlx out
+ output wire [15:0] TLX_data_fwd_1_tdata,
+ output wire TLX_data_fwd_1_tvalid,
+ input wire TLX_data_fwd_1_tready
+);
+
+
+// Thin links from NIC_TB to SRAM_chiplet_0
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_IN_flow_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_IN_flow_fwd_0();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_fwd_0();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_1();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_1();
+
+ // TLX_IN_data_rev_0 tlx out
+assign TLX_IN_data_rev_0_tdata = TLX_IN_data_rev_0.tdata;
+assign TLX_IN_data_rev_0_tvalid = TLX_IN_data_rev_0.tvalid;
+assign TLX_IN_data_rev_0.tready = TLX_IN_data_rev_0_tready;
+
+ //TLX_IN_flow_rev_0 tlx out
+assign TLX_IN_flow_rev_0_tdata = TLX_IN_flow_rev_0.tdata;
+assign TLX_IN_flow_rev_0_tvalid = TLX_IN_flow_rev_0.tvalid;
+assign TLX_IN_flow_rev_0.tready = TLX_IN_flow_rev_0_tready;
+
+ //tlx in
+assign TLX_IN_flow_fwd_0.tdata = TLX_IN_flow_fwd_0_tdata;
+assign TLX_IN_flow_fwd_0.tvalid = TLX_IN_flow_fwd_0_tvalid;
+assign TLX_IN_flow_fwd_0_tready = TLX_IN_flow_fwd_0.tready;
+
+ //tlx in
+assign TLX_IN_data_fwd_0.tdata = TLX_IN_data_fwd_0_tdata;
+assign TLX_IN_data_fwd_0.tvalid = TLX_IN_data_fwd_0_tvalid;
+assign TLX_IN_data_fwd_0_tready = TLX_IN_data_fwd_0.tready;
+
+ //tlx in
+assign TLX_data_rev_1.tdata = TLX_data_rev_1_tdata;
+assign TLX_data_rev_1.tvalid = TLX_data_rev_1_tvalid;
+assign TLX_data_rev_1_tready = TLX_data_rev_1.tready;
+
+ //tlx in
+assign TLX_flow_rev_1.tdata = TLX_flow_rev_1_tdata;
+assign TLX_flow_rev_1.tvalid = TLX_flow_rev_1_tvalid;
+assign TLX_flow_rev_1_tready = TLX_flow_rev_1.tready;
+
+ // tlx out
+assign TLX_flow_fwd_1_tdata = TLX_flow_fwd_1.tdata;
+assign TLX_flow_fwd_1_tvalid = TLX_flow_fwd_1.tvalid;
+assign TLX_flow_fwd_1.tready = TLX_flow_fwd_1_tready;
+
+ // tlx out
+assign TLX_data_fwd_1_tdata = TLX_data_fwd_1.tdata;
+assign TLX_data_fwd_1_tvalid = TLX_data_fwd_1.tvalid;
+assign TLX_data_fwd_1.tready = TLX_data_fwd_1_tready;
+
+
+
+top_sram_chiplet u_top_sram_chiplet(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_IN_data_rev_0),
+ .TLX_IN_flow_rev(TLX_IN_flow_rev_0),
+ .TLX_IN_flow_fwd(TLX_IN_flow_fwd_0),
+ .TLX_IN_data_fwd(TLX_IN_data_fwd_0),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_1),
+ .TLX_OUT_flow_rev(TLX_flow_rev_1),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_1),
+ .TLX_OUT_data_fwd(TLX_data_fwd_1),
+
+ // FT1248
+
+
+ // Address Select pins
+ .addr_sel(3'b000)
+);
+
+endmodule
\ No newline at end of file
diff --git a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v
deleted file mode 100644
index 3dadbfe..0000000
--- a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v
+++ /dev/null
@@ -1,53 +0,0 @@
-//-----------------------------------------------------------------------------
-// Top pad level of SRAM chiplet for TSMC 28nm HPC+
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// Daniel Newbrook (d.newbrook@soton.ac.uk)
-//
-// Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module SRAM_chiplet(
-`ifdef POWER_PINS
- inout wire VDDIO,
- inout wire VSSIO,
- inout wire VDD,
- inout wire VSS,
-`endif
-
-);
-
-
-
-top_sram_chiplet u_top_sram_chiplet(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Axi stream master (tdata out) from PL
- .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
- .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
- .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
-
- // Axi Stream master (tdata out) from PL
- .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
- .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
- .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
-
- // Axi Stream Slave (tdata in) to DL
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
-
- // Axi Stream slave (tdata in) to DL
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data)
-);
-
-endmodule
\ No newline at end of file
diff --git a/synopsys_28nm_slm_integration b/synopsys_28nm_slm_integration
new file mode 160000
index 0000000..e9f59a1
--- /dev/null
+++ b/synopsys_28nm_slm_integration
@@ -0,0 +1 @@
+Subproject commit e9f59a1bd14b8350d3b493a42943fcfef07de5ba
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
index b188645..3a69115 100644
--- a/verif/cocotb/makefile
+++ b/verif/cocotb/makefile
@@ -32,7 +32,8 @@ TOPLEVEL = sram_chiplet_cocotb
MODULE = sram_chiplet_tests
VERILOG_SOURCES += ./sram_chiplet_cocotb.sv
-
+EXTRA_ARGS += +define+BEHAVIOURAL_SIM
+EXTRA_ARGS += +define+INITIALIZE_MEMORY
ifeq ($(SIM), icarus)
PLUSARGS += -fst
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
index 429d946..71921bc 100644
--- a/verif/cocotb/sram_chiplet_tests.py
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -25,6 +25,15 @@ from cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiMaster, AxiRam, AxiBurstType, AxiSlave
+CHIPLET_0_BASE=0x00000000
+CHIPLET_0_APB_BASE=0x001F0000
+CHIPLET_0_TS_BASE = CHIPLET_0_APB_BASE
+CHIPLET_0_PD_BASE = CHIPLET_0_APB_BASE + 6*0x1000
+CHIPLET_0_VM_BASE = CHIPLET_0_APB_BASE + 7*0x1000
+CHIPLET_0_PLL_BASE = CHIPLET_0_APB_BASE + 8*0x1000
+
+CHIPLET_0_SRAM_MAX_ADDR = 0x100000
+
class TB:
def __init__(self,dut):
self.dut = dut
@@ -32,7 +41,7 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
- cocotb.start_soon(Clock(dut.clk_in, 1, units="ns").start())
+ cocotb.start_soon(Clock(dut.clk_in, 4, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut,"cocotb"), dut.clk_in, dut.aresetn, reset_active_level=False)
def set_idle_generator(self, generator=None):
if generator:
@@ -50,10 +59,7 @@ class TB:
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
async def cycle_reset(self):
self.dut.aresetn.setimmediatevalue(0)
- await RisingEdge(self.dut.clk_in)
- await RisingEdge(self.dut.clk_in)
- await RisingEdge(self.dut.clk_in)
- await RisingEdge(self.dut.clk_in)
+ await Timer(time=4,units='us')
self.dut.aresetn.value = 1
await RisingEdge(self.dut.clk_in)
async def delay(self, cycle):
@@ -62,13 +68,13 @@ class TB:
async def init_sram(dut, tb, base_addr, size=0x8000):
data = bytearray([0]*2048)
- for offset in range(0, size-0x800, 0x800):
+ for offset in range(0, size, 0x800):
await tb.axi_master.write(base_addr+offset, data)
await RisingEdge(dut.clk_in)
async def SRAM_test_write(dut, tb, base_addr, byte_lanes, size):
for length in list(range(1, byte_lanes*2))+[8192]:
- for offset in list(range(byte_lanes))+list(range(0x1EE000-byte_lanes, 0x1EE000)):
+ for offset in list(range(byte_lanes))+list(range(CHIPLET_0_SRAM_MAX_ADDR-0x20000, CHIPLET_0_SRAM_MAX_ADDR-0x20000+byte_lanes)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset + base_addr
test_data = bytearray([x % 256 for x in range(length)])
@@ -79,7 +85,149 @@ async def SRAM_test_write(dut, tb, base_addr, byte_lanes, size):
await RisingEdge(dut.clk_in)
await RisingEdge(dut.clk_in)
+
+async def SRAM_bank_test(dut, tb, bank_addrs):
+ length = 2048
+ data = bytearray([x % 256 for x in range(length)])
+ for bank_addr in bank_addrs:
+ await tb.axi_master.write(bank_addr, data)
+ read_data = await tb.axi_master.read(bank_addr, length)
+ assert read_data.data == data
+@cocotb.test()
+async def PLL_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_inserter)
+ tb.set_backpressure_generator(backpressure_inserter)
+ # Test ID of PLL Intergration layer
+ PLL_ID = await tb.axi_master.read(CHIPLET_0_PLL_BASE+20,4)
+ assert PLL_ID.data == b'LPNS'
+
+ # Wait for PLL Lock
+ PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
+ tb.log.info(PLL_LOCK.data)
+ while (PLL_LOCK.data == b'\x00'):
+ await Timer(time=100, units='ns')
+ PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
+ # Read write to register
+ PLL_0 = await tb.axi_master.read(CHIPLET_0_PLL_BASE,4)
+ tb.log.info(PLL_0.data)
+ await tb.axi_master.write(CHIPLET_0_PLL_BASE, bytearray(b'\x31\x00\x00\x00'), 4)
+ # Read write to PLL internal register
+ PLL_800 = await tb.axi_master.read(CHIPLET_0_PLL_BASE + 0x800, 4)
+ await tb.axi_master.write(CHIPLET_0_PLL_BASE + 0x800, bytearray(b'\x31\x00\x00\x00'), 4)
+
+
+@cocotb.test()
+async def PD_TEST(dut,idle_insterter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_insterter)
+ tb.set_backpressure_generator(backpressure_inserter)
+
+ # Test ID of PD integration layer
+ PD_ID = await tb.axi_master.read(CHIPLET_0_PD_BASE+0xC,4)
+ assert PD_ID.data == b'dpns'
+
+ # Check config registers
+ PD_CONFIG = await tb.axi_master.read(CHIPLET_0_PD_BASE+0x8,4)
+ tb.log.info(PD_CONFIG.data)
+
+ # Enable PD
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ PD_STATUS_WRITE=bytearray(PD_STATUS.data)
+ PD_STATUS_WRITE[0] = PD_STATUS_WRITE[0]^1
+ await tb.axi_master.write(CHIPLET_0_PD_BASE, PD_STATUS_WRITE, 4)
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE, 4)
+ tb.log.info(PD_STATUS.data[0])
+
+ # Load config
+ PD_REGS = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x8, 4)
+ PD_REGS_WRITE = bytearray(PD_REGS.data)
+ PD_REGS_WRITE[3] = PD_REGS_WRITE[3] ^ 1
+ await tb.axi_master.write(CHIPLET_0_PD_BASE + 0x8, PD_REGS_WRITE, 4)
+ PD_REGS = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x8, 4)
+ PD_REGS_WRITE = bytearray(PD_REGS.data)
+ PD_REGS_WRITE[3] = PD_REGS_WRITE[3] ^ 1
+ await tb.axi_master.write(CHIPLET_0_PD_BASE + 0x8, PD_REGS_WRITE, 4)
+
+ # Start PD
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ PD_STATUS_WRITE=bytearray(PD_STATUS.data)
+ PD_STATUS_WRITE[0] = PD_STATUS_WRITE[0]^2
+ await tb.axi_master.write(CHIPLET_0_PD_BASE, PD_STATUS_WRITE, 4)
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ while(PD_STATUS.data[3] != 1):
+ await Timer(time=100, units='ns')
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+
+ PD_DATA = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x4, 4)
+ prescaler = 32
+ window_size = 63
+ f_clk = 250/42
+
+ pd_out = PD_DATA.data[0] + PD_DATA.data[1]*pow(2,8)
+ frequency = pd_out * prescaler * f_clk / window_size
+ tb.log.info(frequency)
+
+ # Clear ready reg
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ PD_STATUS_WRITE=bytearray(PD_STATUS.data)
+ PD_STATUS_WRITE[0] = PD_STATUS_WRITE[0]^8
+ await tb.axi_master.write(CHIPLET_0_PD_BASE, PD_STATUS_WRITE, 4)
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE, 4)
+ tb.log.info(PD_STATUS.data[0])
+
+
+
+ # Set LVT delay chain
+ PD_REGS = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x8, 4)
+ PD_REGS_WRITE = bytearray(PD_REGS.data)
+ PD_REGS_WRITE[1] = 32 #0x20 set bits [7:5] to 001
+ await tb.axi_master.write(CHIPLET_0_PD_BASE + 0x8, PD_REGS_WRITE, 4)
+ PD_REGS = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x8, 4)
+ PD_REGS_WRITE = bytearray(PD_REGS.data)
+ PD_REGS_WRITE[3] = PD_REGS_WRITE[3] ^ 1
+ await tb.axi_master.write(CHIPLET_0_PD_BASE + 0x8, PD_REGS_WRITE, 4)
+ PD_REGS = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x8, 4)
+ PD_REGS_WRITE = bytearray(PD_REGS.data)
+ PD_REGS_WRITE[3] = PD_REGS_WRITE[3] ^ 1
+ await tb.axi_master.write(CHIPLET_0_PD_BASE + 0x8, PD_REGS_WRITE, 4)
+
+ # Start PD
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ PD_STATUS_WRITE=bytearray(PD_STATUS.data)
+ PD_STATUS_WRITE[0] = PD_STATUS_WRITE[0]^2
+ await tb.axi_master.write(CHIPLET_0_PD_BASE, PD_STATUS_WRITE, 4)
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+ while(PD_STATUS.data[3] != 1):
+ await Timer(time=100, units='ns')
+ PD_STATUS = await tb.axi_master.read(CHIPLET_0_PD_BASE,4)
+
+ PD_DATA = await tb.axi_master.read(CHIPLET_0_PD_BASE + 0x4, 4)
+ prescaler = 32
+ window_size = 63
+ f_clk = 250/42
+
+ pd_out = PD_DATA.data[0] + PD_DATA.data[1]*pow(2,8)
+ frequency = pd_out * prescaler * f_clk / window_size
+ tb.log.info(frequency)
+
+
+
@cocotb.test()
async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
@@ -92,9 +240,11 @@ async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=Non
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
- await init_sram(dut, tb, 0x00000000)
- await init_sram(dut, tb, 0x1F0000 - 0x8000, size=0x8000)
await SRAM_test_write(dut, tb, 0x0, byte_lanes, size)
+ bank_addrs = range(0x00000000, CHIPLET_0_SRAM_MAX_ADDR, 0x20000)
+ await SRAM_bank_test(dut, tb, bank_addrs)
+ bank_addrs = range(CHIPLET_0_SRAM_MAX_ADDR, CHIPLET_0_SRAM_MAX_ADDR + 0xF0000, 0x20000)
+ await SRAM_bank_test(dut, tb, bank_addrs)
@cocotb.test()
async def SRAM_TEST_MULTI_CHIPLET(dut,idle_inserter=None, backpressure_inserter=None, size=None):
--
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