diff --git a/.gitignore b/.gitignore
index 36e5e46bb9c92549ae2469ac31d453fc37c74dea..e1b8ebdacefc51840d3ffa6c6cb2674f489d29d5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,7 @@
.project
.ecmproject
+logical/nic400_tb
logical/nic400_sram_chiplet/
logical/nic400_tlx_sram_chiplet/
logical/SMC
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000000000000000000000000000000000000..9ec29b831304e0fb42024294b07c1b9fdc353bcf
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "socdebug_tech"]
+ path = socdebug_tech
+ url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
diff --git a/flist/sram_chiplet_cocotb.flist b/flist/sram_chiplet_cocotb.flist
new file mode 100644
index 0000000000000000000000000000000000000000..1408d4dcff2e4c31a77c114be13f4a2fecabfda9
--- /dev/null
+++ b/flist/sram_chiplet_cocotb.flist
@@ -0,0 +1,231 @@
+
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/verilog/SRAM_wrapper.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/verilog/SRAM.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+
+#NIC400 nic400_tb
+
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi4PC
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/nic400_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_chan_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_chan_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_decode_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_maskcntl_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_rd_ss_cdas_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_wr_ss_cdas_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_build_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_map_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog/nic400_default_slave_ds_1_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ax4_reg_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_buf_reg_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ful_regd_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_fwd_regd_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rd_reg_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_reg_slice_axi_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rev_regd_slice_tb.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_wr_reg_slice_tb.v
+#TLX Files
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi4PC
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_chan_slice_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_nosync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_and2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_gry_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_gry_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_random_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_m_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_s_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_fwd_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_rev_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_cdc_air_corrupt_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_chan_slice_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_fwd_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_rev_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_fwd_clk_buf_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_master_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_fwd_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_rev_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_rev_clk_buf_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_slave_domain_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux2_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_rd_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_sync_tlx_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_wr_tlx_sram_chiplet.v
+
+#NIC400 SRAM Chiplet
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi4PC
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/ApbPC
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Apb4PC
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Ahb
+EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/AhbPC
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_chan_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_axi_to_itb_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_ahb_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_chan_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_decode_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_itb_to_axi_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_maskcntl_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_rd_ss_cdas_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_wr_ss_cdas_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_chan_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_decode_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_maskcntl_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_rd_ss_cdas_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_wr_ss_cdas_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_lrg_arb_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_build_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_map_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_qv_cmp_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog/nic400_default_slave_ds_1_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ax4_reg_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_buf_reg_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rd_reg_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_reg_slice_axi_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_sram_chiplet.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_wr_reg_slice_sram_chiplet.v
+
+# sie300
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_addr_dec.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arb.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arq.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_awq.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_axi_mux.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_bq.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_clamp.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_eam.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo_core.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_lpi_ctrl.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_one_hot.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rbeat.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_resp_gen.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rq.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wbeat.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wq.sv
diff --git a/logical/SRAM/verilog/SRAM.v b/logical/SRAM/verilog/SRAM.v
new file mode 100644
index 0000000000000000000000000000000000000000..35f5f4b2f470da5e2866744e045874df274d89c5
--- /dev/null
+++ b/logical/SRAM/verilog/SRAM.v
@@ -0,0 +1,76 @@
+
+
+module SRAM (
+ input wire clk,
+ input wire [20:0] memaddr,
+ input wire [31:0] memd,
+ output wire [31:0] memq,
+ input wire memcen,
+ input wire [3:0] memwen
+);
+ parameter MEM_DEPTH = (1<<17);
+
+ wire WriteEnable; // Write data update
+ wire [17:0] Addr;
+ reg [31:0] DataAtAddress; // Current write-data at address
+ reg [31:0] Mask; // Write data-mask
+ reg [31:0] NextData; // Next write-data
+ reg [31:0] iQ; // Memory output data (pipelined)
+
+ integer i; // Write-strobe loop variable
+ integer j; // Mask-bit loop variable
+ assign Addr = memaddr[20:4];
+ // -------------
+ // Memory arrays
+ // -------------
+
+ // Memory array 0 - used in both 32-bit and 64-bit modes
+ reg [31:0] mem [MEM_DEPTH-1:0];
+ assign WriteEnable = (memwen != {4{1'b1}}) ? 1'b1 : 1'b0;
+
+ always @ (posedge clk)
+ begin : p_memaccess
+ // Only access the memory when the chip is enabled
+ if (!memcen)
+ begin
+ // Look-up the data at the current address
+ DataAtAddress[31:0] = mem[Addr];
+
+ // Update the memory and the data output only when permitted
+ if (WriteEnable)
+ begin
+
+ // Determine the byte-lane mask value by testing the individual
+ // bits of the active-low write strobes
+ for (i = 0; i < 4; i = i + 1)
+ for (j = i * 8; j <= (i * 8) + 7; j = j + 1)
+ Mask[j] = ~memwen[i];
+
+ // Determine the value of the next write-data. Term (a) clears
+ // the required byte lanes and term (b) selects the required
+ // byte-lanes of the AXI write data. The two data words are
+ // bit-wise OR'ed together to form the new data word
+ NextData = (DataAtAddress & ~Mask) | // (a)
+ (memd & Mask); // (b)
+
+ mem[Addr] = NextData[31:0]; // Always assign mem array 0
+
+ // Update the data output with new data
+ iQ <= NextData;
+
+ end
+ else
+ // Update the data output with the original data value
+ iQ <= DataAtAddress;
+
+ end
+
+
+ end
+
+
+ // Drive read data output port at the selected stage of the pipeline
+ assign memq = iQ;
+
+
+endmodule
diff --git a/logical/SRAM/verilog/SRAM_wrapper.v b/logical/SRAM/verilog/SRAM_wrapper.v
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1615cb2526b72ad16618038e5079b68d7798cb37 100644
--- a/logical/SRAM/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/verilog/SRAM_wrapper.v
@@ -0,0 +1,153 @@
+//-----------------------------------------------------------------------------
+// Expansion Subsystem SRAM Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// sie300_axi5_sram_ctrl_expansion_subsystem
+// SRAM
+
+module SRAM_wrapper(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire AWVALID,
+ output wire AWREADY,
+ input wire [4:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [2:0] AWPROT,
+ input wire [3:0] AWQOS,
+
+ input wire WVALID,
+ output wire WREADY,
+ input wire [31:0] WDATA,
+ input wire [3:0] WSTRB,
+ input wire WLAST,
+ input wire WPOISON,
+
+ output wire BVALID,
+ input wire BREADY,
+ output wire [4:0] BID,
+ output wire [1:0] BRESP,
+
+ input wire ARVALID,
+ output wire ARREADY,
+ input wire [4:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [2:0] ARPROT,
+ input wire [3:0] ARQOS,
+
+ output wire RVALID,
+ input wire RREADY,
+ output wire [4:0] RID,
+ output wire [31:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire RPOISON,
+ input wire AWAKEUP,
+
+ input wire clk_qreqn,
+ output wire clk_qacceptn,
+ output wire clk_qdeny,
+ output wire clk_qactive,
+
+ input wire pwr_qreqn,
+ output wire pwr_qacceptn,
+ output wire pwr_qdeny,
+ output wire pwr_qactive,
+
+ input wire ext_gt_qreqn,
+ output wire ext_gt_qacceptn,
+ input wire cfg_gate_resp
+
+);
+
+
+wire [20:0] memaddr;
+wire [31:0] memd;
+wire [31:0] memq;
+wire memcen;
+wire [3:0] memwen;
+
+sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
+ .aclk(ACLK),
+ .aresetn(ARESETn),
+ .awvalid_s(AWVALID),
+ .awready_s(AWREADY),
+ .awid_s(AWID),
+ .awaddr_s(AWADDR[20:0]),
+ .awlen_s(AWLEN),
+ .awsize_s(AWSIZE),
+ .awburst_s(AWBURST),
+ .awlock_s(AWLOCK),
+ .awprot_s(AWPROT),
+ .awqos_s(AWQOS),
+ .wvalid_s(WVALID),
+ .wready_s(WREADY),
+ .wdata_s(WDATA),
+ .wstrb_s(WSTRB),
+ .wlast_s(WLAST),
+ .wpoison_s(WPOISON),
+ .bvalid_s(BVALID),
+ .bready_s(BREADY),
+ .bid_s(BID),
+ .bresp_s(BRESP),
+ .arvalid_s(ARVALID),
+ .arready_s(ARREADY),
+ .arid_s(ARID),
+ .araddr_s(ARADDR[20:0]),
+ .arlen_s(ARLEN),
+ .arsize_s(ARSIZE),
+ .arburst_s(ARBURST),
+ .arlock_s(ARLOCK),
+ .arprot_s(ARPROT),
+ .arqos_s(ARQOS),
+ .rvalid_s(RVALID),
+ .rready_s(RREADY),
+ .rid_s(RID),
+ .rdata_s(RDATA),
+ .rresp_s(RRESP),
+ .rlast_s(RLAST),
+ .rpoison_s(RPOISON),
+ .awakeup_s(AWAKEUP),
+ .clk_qreqn(clk_qreqn),
+ .clk_qacceptn(clk_qacceptn),
+ .clk_qdeny(clk_qdeny),
+ .clk_qactive(clk_qactive),
+ .pwr_qreqn(pwr_qreqn),
+ .pwr_qacceptn(pwr_qacceptn),
+ .pwr_qdeny(pwr_qdeny),
+ .pwr_qactive(pwr_qactive),
+ .ext_gt_qreqn(ext_gt_qreqn),
+ .ext_gt_qacceptn(ext_gt_qacceptn),
+ .cfg_gate_resp(cfg_gate_resp),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+SRAM u_SRAM(
+ .clk(ACLK),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+endmodule
\ No newline at end of file
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
new file mode 100644
index 0000000000000000000000000000000000000000..8c366c7b3775950ae7d0df21eaf8cd4a0f7f2d09
--- /dev/null
+++ b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
@@ -0,0 +1,6 @@
+
+module sram_chiplet_apb_subsystem(
+
+);
+
+endmodule
\ No newline at end of file
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.v b/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..fdc45e0334c77c548d6c3fa7cc95b09ddd74943b 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
@@ -0,0 +1,412 @@
+//-----------------------------------------------------------------------------
+// SRAM Chiplet Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// nic400_sram_chiplet
+// nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet
+// nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet
+// sram_chiplet_apb_subsystem
+// SRAM_wrapper
+
+
+module top_sram_chiplet(
+ // Clock and reset
+ input wire SYS_CLK,
+ input wire DL_FWD_CLK,
+ output wire DL_REV_CLK,
+
+ input wire aRESETn,
+ input wire DL_FWD_RESETn,
+ // Thin links interface
+ output wire tvalid_pl_rev_m1_m_tlx_m_stream,
+ input wire tready_pl_rev_m1_m_tlx_m_stream,
+ output wire [15:0] tdata_pl_rev_m1_m_tlx_m_stream,
+
+ output wire tvalid_pl_rev_m1_m_tlx_m_flow,
+ input wire tready_pl_rev_m1_m_tlx_m_flow,
+ output wire [2:0] tdata_pl_rev_m1_m_tlx_m_flow,
+
+ input wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
+ output wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
+ input wire [1:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
+
+ input wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data,
+ output wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_data,
+ input wire [15:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data
+
+ // FT1248
+
+
+);
+
+// Main Bus Wires
+// - SRAM AXI wires
+wire [4:0] AWID_AXI_SRAM;
+wire [31:0] AWADDR_AXI_SRAM;
+wire [7:0] AWLEN_AXI_SRAM;
+wire [2:0] AWSIZE_AXI_SRAM;
+wire [1:0] AWBURST_AXI_SRAM;
+wire AWLOCK_AXI_SRAM;
+wire [3:0] AWCACHE_AXI_SRAM;
+wire [2:0] AWPROT_AXI_SRAM;
+wire AWVALID_AXI_SRAM;
+wire AWREADY_AXI_SRAM;
+wire [31:0] WDATA_AXI_SRAM;
+wire [3:0] WSTRB_AXI_SRAM;
+wire WLAST_AXI_SRAM;
+wire WVALID_AXI_SRAM;
+wire WREADY_AXI_SRAM;
+wire [4:0] BID_AXI_SRAM;
+wire [1:0] BRESP_AXI_SRAM;
+wire BVALID_AXI_SRAM;
+wire BREADY_AXI_SRAM;
+wire [4:0] ARID_AXI_SRAM;
+wire [31:0] ARADDR_AXI_SRAM;
+wire [7:0] ARLEN_AXI_SRAM;
+wire [2:0] ARSIZE_AXI_SRAM;
+wire [1:0] ARBURST_AXI_SRAM;
+wire ARLOCK_AXI_SRAM;
+wire [3:0] ARCACHE_AXI_SRAM;
+wire [2:0] ARPROT_AXI_SRAM;
+wire ARVALID_AXI_SRAM;
+wire ARREADY_AXI_SRAM;
+wire [4:0] RID_AXI_SRAM;
+wire [31:0] RDATA_AXI_SRAM;
+wire [1:0] RRESP_AXI_SRAM;
+wire RLAST_AXI_SRAM;
+wire RVALID_AXI_SRAM;
+wire RREADY_AXI_SRAM;
+// - PVT (silicon lifetime monitoring) APB wires
+wire [31:0] PADDR_APB_PVT;
+wire [31:0] PWDATA_APB_PVT;
+wire PWRITE_APB_PVT;
+wire [2:0] PPROT_APB_PVT;
+wire [3:0] PSTRB_APB_PVT;
+wire PENABLE_APB_PVT;
+wire PSELx_APB_PVT;
+wire [31:0] PRDATA_APB_PVT;
+wire PSLVERR_APB_PVT;
+wire PREADY_APB_PVT;
+// - ADP AHB wires
+wire [31:0] HADDR_AHB_ADP;
+wire [1:0] HTRANS_AHB_ADP;
+wire HWRITE_AHB_ADP;
+wire [2:0] HSIZE_AHB_ADP;
+wire [2:0] HBURST_AHB_ADP;
+wire [3:0] HPROT_AHB_ADP;
+wire [31:0] HWDATA_AHB_ADP;
+wire HSELx_AHB_ADP;
+wire [31:0] HRDATA_AHB_ADP;
+wire HREADY_AHB_ADP;
+wire HREADYOUT_AHB_ADP;
+wire HRESP_AHB_ADP;
+// - Chiplet In AXI port
+wire [3:0] AWID_AXI_CHIPLET_IN;
+wire [31:0] AWADDR_AXI_CHIPLET_IN;
+wire [7:0] AWLEN_AXI_CHIPLET_IN;
+wire [2:0] AWSIZE_AXI_CHIPLET_IN;
+wire [1:0] AWBURST_AXI_CHIPLET_IN;
+wire AWLOCK_AXI_CHIPLET_IN;
+wire [3:0] AWCACHE_AXI_CHIPLET_IN;
+wire [2:0] AWPROT_AXI_CHIPLET_IN;
+wire AWVALID_AXI_CHIPLET_IN;
+wire AWREADY_AXI_CHIPLET_IN;
+wire [31:0] WDATA_AXI_CHIPLET_IN;
+wire [3:0] WSTRB_AXI_CHIPLET_IN;
+wire WLAST_AXI_CHIPLET_IN;
+wire WVALID_AXI_CHIPLET_IN;
+wire WREADY_AXI_CHIPLET_IN;
+wire [3:0] BID_AXI_CHIPLET_IN;
+wire [1:0] BRESP_AXI_CHIPLET_IN;
+wire BVALID_AXI_CHIPLET_IN;
+wire BREADY_AXI_CHIPLET_IN;
+wire [3:0] ARID_AXI_CHIPLET_IN;
+wire [31:0] ARADDR_AXI_CHIPLET_IN;
+wire [7:0] ARLEN_AXI_CHIPLET_IN;
+wire [2:0] ARSIZE_AXI_CHIPLET_IN;
+wire [1:0] ARBURST_AXI_CHIPLET_IN;
+wire ARLOCK_AXI_CHIPLET_IN;
+wire [3:0] ARCACHE_AXI_CHIPLET_IN;
+wire [2:0] ARPROT_AXI_CHIPLET_IN;
+wire ARVALID_AXI_CHIPLET_IN;
+wire ARREADY_AXI_CHIPLET_IN;
+wire [3:0] RID_AXI_CHIPLET_IN;
+wire [31:0] RDATA_AXI_CHIPLET_IN;
+wire [1:0] RRESP_AXI_CHIPLET_IN;
+wire RLAST_AXI_CHIPLET_IN;
+wire RVALID_AXI_CHIPLET_IN;
+wire RREADY_AXI_CHIPLET_IN;
+
+// Thin links internal wires
+wire tvalid_pl_rev_m1_m_tlx_s_stream;
+wire tready_pl_rev_m1_m_tlx_s_stream;
+wire [15:0] tdata_pl_rev_m1_m_tlx_s_stream;
+
+
+wire tvalid_pl_rev_m1_m_tlx_s_flow;
+wire tready_pl_rev_m1_m_tlx_s_flow;
+wire [2:0] tdata_pl_rev_m1_m_tlx_s_flow;
+nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet u_cd_pl_rev_M1_m_tlx(
+ // (tdata out)
+ .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
+ .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
+ .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
+
+ // (tdata in)
+ .tvalid_pl_rev_m1_m_tlx_s_stream(tvalid_pl_rev_m1_m_tlx_s_stream),
+ .tready_pl_rev_m1_m_tlx_s_stream(tready_pl_rev_m1_m_tlx_s_stream),
+ .tdata_pl_rev_m1_m_tlx_s_stream(tdata_pl_rev_m1_m_tlx_s_stream),
+
+ // (tdata out)
+ .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
+ .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
+ .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+
+ // (tdata in)
+ .tvalid_pl_rev_m1_m_tlx_s_flow(tvalid_pl_rev_m1_m_tlx_s_flow),
+ .tready_pl_rev_m1_m_tlx_s_flow(tready_pl_rev_m1_m_tlx_s_flow),
+ .tdata_pl_rev_m1_m_tlx_s_flow(tdata_pl_rev_m1_m_tlx_s_flow),
+
+ .pl_rev_M1_m_tlxclk(SYS_CLK),
+ .pl_rev_M1_m_tlxresetn(aRESETn)
+);
+
+nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
+ // AXI manager power
+ .awid_m1_m_m(AWID_AXI_CHIPLET_IN),
+ .awaddr_m1_m_m(AWADDR_AXI_CHIPLET_IN),
+ .awlen_m1_m_m(AWLEN_AXI_CHIPLET_IN),
+ .awsize_m1_m_m(AWSIZE_AXI_CHIPLET_IN),
+ .awburst_m1_m_m(AWBURST_AXI_CHIPLET_IN),
+ .awlock_m1_m_m(AWLOCK_AXI_CHIPLET_IN),
+ .awcache_m1_m_m(AWCACHE_AXI_CHIPLET_IN),
+ .awprot_m1_m_m(AWPROT_AXI_CHIPLET_IN),
+ .awvalid_m1_m_m(AWVALID_AXI_CHIPLET_IN),
+ .awready_m1_m_m(AWREADY_AXI_CHIPLET_IN),
+ .wdata_m1_m_m(WDATA_AXI_CHIPLET_IN),
+ .wstrb_m1_m_m(WSTRB_AXI_CHIPLET_IN),
+ .wlast_m1_m_m(WLAST_AXI_CHIPLET_IN),
+ .wvalid_m1_m_m(WVALID_AXI_CHIPLET_IN),
+ .wready_m1_m_m(WREADY_AXI_CHIPLET_IN),
+ .bid_m1_m_m(BID_AXI_CHIPLET_IN),
+ .bresp_m1_m_m(BRESP_AXI_CHIPLET_IN),
+ .bvalid_m1_m_m(BVALID_AXI_CHIPLET_IN),
+ .bready_m1_m_m(BREADY_AXI_CHIPLET_IN),
+ .arid_m1_m_m(ARID_AXI_CHIPLET_IN),
+ .araddr_m1_m_m(ARADDR_AXI_CHIPLET_IN),
+ .arlen_m1_m_m(ARLEN_AXI_CHIPLET_IN),
+ .arsize_m1_m_m(ARSIZE_AXI_CHIPLET_IN),
+ .arburst_m1_m_m(ARBURST_AXI_CHIPLET_IN),
+ .arlock_m1_m_m(ARLOCK_AXI_CHIPLET_IN),
+ .arcache_m1_m_m(ARCACHE_AXI_CHIPLET_IN),
+ .arprot_m1_m_m(ARPROT_AXI_CHIPLET_IN),
+ .arvalid_m1_m_m(ARVALID_AXI_CHIPLET_IN),
+ .arready_m1_m_m(ARREADY_AXI_CHIPLET_IN),
+ .rid_m1_m_m(RID_AXI_CHIPLET_IN),
+ .rdata_m1_m_m(RDATA_AXI_CHIPLET_IN),
+ .rresp_m1_m_m(RRESP_AXI_CHIPLET_IN),
+ .rlast_m1_m_m(RLAST_AXI_CHIPLET_IN),
+ .rvalid_m1_m_m(RVALID_AXI_CHIPLET_IN),
+ .rready_m1_m_m(RREADY_AXI_CHIPLET_IN),
+
+ // Thin links data reverse to PL (tdata out)
+ .tvalid_m1_m_tlx_tlx_m_to_pl_rev_data(tvalid_pl_rev_m1_m_tlx_s_stream),
+ .tready_m1_m_tlx_tlx_m_to_pl_rev_data(tready_pl_rev_m1_m_tlx_s_stream),
+ .tdata_m1_m_tlx_tlx_m_to_pl_rev_data(tdata_pl_rev_m1_m_tlx_s_stream),
+
+ // Thin links flow reverse to PL (tdata out)
+ .tvalid_m1_m_tlx_tlx_m_to_pl_rev_flow(tvalid_pl_rev_m1_m_tlx_s_flow),
+ .tready_m1_m_tlx_tlx_m_to_pl_rev_flow(tready_pl_rev_m1_m_tlx_s_flow),
+ .tdata_m1_m_tlx_tlx_m_to_pl_rev_flow(tdata_pl_rev_m1_m_tlx_s_flow),
+
+ // Thin links data forward from PL (tdata in)
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+
+ // Thin links flow forward from PL (tdata in)
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+
+ // Master clock
+ .clk_mclk(SYS_CLK),
+ .clk_mresetn(aRESETn),
+ // DL clock
+ .dl_fwd_M1_m_tlxclk(DL_FWD_CLK),
+ .dl_fwd_M1_m_tlxresetn(DL_FWD_RESETn)
+);
+
+nic400_sram_chiplet u_nic400_sram_chiplet(
+ .AWID_AXI_SRAM(AWID_AXI_SRAM),
+ .AWADDR_AXI_SRAM(AWADDR_AXI_SRAM),
+ .AWLEN_AXI_SRAM(AWLEN_AXI_SRAM),
+ .AWSIZE_AXI_SRAM(AWSIZE_AXI_SRAM),
+ .AWBURST_AXI_SRAM(AWBURST_AXI_SRAM),
+ .AWLOCK_AXI_SRAM(AWLOCK_AXI_SRAM),
+ .AWCACHE_AXI_SRAM(AWCACHE_AXI_SRAM),
+ .AWPROT_AXI_SRAM(AWPROT_AXI_SRAM),
+ .AWVALID_AXI_SRAM(AWVALID_AXI_SRAM),
+ .AWREADY_AXI_SRAM(AWREADY_AXI_SRAM),
+ .WDATA_AXI_SRAM(WDATA_AXI_SRAM),
+ .WSTRB_AXI_SRAM(WSTRB_AXI_SRAM),
+ .WLAST_AXI_SRAM(WLAST_AXI_SRAM),
+ .WVALID_AXI_SRAM(WVALID_AXI_SRAM),
+ .WREADY_AXI_SRAM(WREADY_AXI_SRAM),
+ .BID_AXI_SRAM(BID_AXI_SRAM),
+ .BRESP_AXI_SRAM(BRESP_AXI_SRAM),
+ .BVALID_AXI_SRAM(BVALID_AXI_SRAM),
+ .BREADY_AXI_SRAM(BREADY_AXI_SRAM),
+ .ARID_AXI_SRAM(ARID_AXI_SRAM),
+ .ARADDR_AXI_SRAM(ARADDR_AXI_SRAM),
+ .ARLEN_AXI_SRAM(ARLEN_AXI_SRAM),
+ .ARSIZE_AXI_SRAM(ARSIZE_AXI_SRAM),
+ .ARBURST_AXI_SRAM(ARBURST_AXI_SRAM),
+ .ARLOCK_AXI_SRAM(ARLOCK_AXI_SRAM),
+ .ARCACHE_AXI_SRAM(ARCACHE_AXI_SRAM),
+ .ARPROT_AXI_SRAM(ARPROT_AXI_SRAM),
+ .ARVALID_AXI_SRAM(ARVALID_AXI_SRAM),
+ .ARREADY_AXI_SRAM(ARREADY_AXI_SRAM),
+ .RID_AXI_SRAM(RID_AXI_SRAM),
+ .RDATA_AXI_SRAM(RDATA_AXI_SRAM),
+ .RRESP_AXI_SRAM(RRESP_AXI_SRAM),
+ .RLAST_AXI_SRAM(RLAST_AXI_SRAM),
+ .RVALID_AXI_SRAM(RVALID_AXI_SRAM),
+ .RREADY_AXI_SRAM(RREADY_AXI_SRAM),
+
+ .PADDR_APB_PVT(PADDR_APB_PVT),
+ .PWDATA_APB_PVT(PWDATA_APB_PVT),
+ .PWRITE_APB_PVT(PWRITE_APB_PVT),
+ .PPROT_APB_PVT(PPROT_APB_PVT),
+ .PSTRB_APB_PVT(PSTRB_APB_PVT),
+ .PENABLE_APB_PVT(PENABLE_APB_PVT),
+ .PSELx_APB_PVT(PSELx_APB_PVT),
+ .PRDATA_APB_PVT(PRDATA_APB_PVT),
+ .PSLVERR_APB_PVT(PSLVERR_APB_PVT),
+ .PREADY_APB_PVT(PREADY_APB_PVT),
+
+ .HADDR_AHB_ADP(HADDR_AHB_ADP),
+ .HTRANS_AHB_ADP(HTRANS_AHB_ADP),
+ .HWRITE_AHB_ADP(HWRITE_AHB_ADP),
+ .HSIZE_AHB_ADP(HSIZE_AHB_ADP),
+ .HBURST_AHB_ADP(HBURST_AHB_ADP),
+ .HPROT_AHB_ADP(HPROT_AHB_ADP),
+ .HWDATA_AHB_ADP(HWDATA_AHB_ADP),
+ .HSELx_AHB_ADP(HSELx_AHB_ADP),
+ .HRDATA_AHB_ADP(HRDATA_AHB_ADP),
+ .HREADY_AHB_ADP(HREADY_AHB_ADP),
+ .HREADYOUT_AHB_ADP(HREADYOUT_AHB_ADP),
+ .HRESP_AHB_ADP(HRESP_AHB_ADP),
+
+ .AWID_AXI_CHIPLET_IN(AWID_AXI_CHIPLET_IN),
+ .AWADDR_AXI_CHIPLET_IN(AWADDR_AXI_CHIPLET_IN),
+ .AWLEN_AXI_CHIPLET_IN(AWLEN_AXI_CHIPLET_IN),
+ .AWSIZE_AXI_CHIPLET_IN(AWSIZE_AXI_CHIPLET_IN),
+ .AWBURST_AXI_CHIPLET_IN(AWBURST_AXI_CHIPLET_IN),
+ .AWLOCK_AXI_CHIPLET_IN(AWLOCK_AXI_CHIPLET_IN),
+ .AWCACHE_AXI_CHIPLET_IN(AWCACHE_AXI_CHIPLET_IN),
+ .AWPROT_AXI_CHIPLET_IN(AWPROT_AXI_CHIPLET_IN),
+ .AWVALID_AXI_CHIPLET_IN(AWVALID_AXI_CHIPLET_IN),
+ .AWREADY_AXI_CHIPLET_IN(AWREADY_AXI_CHIPLET_IN),
+ .WDATA_AXI_CHIPLET_IN(WDATA_AXI_CHIPLET_IN),
+ .WSTRB_AXI_CHIPLET_IN(WSTRB_AXI_CHIPLET_IN),
+ .WLAST_AXI_CHIPLET_IN(WLAST_AXI_CHIPLET_IN),
+ .WVALID_AXI_CHIPLET_IN(WVALID_AXI_CHIPLET_IN),
+ .WREADY_AXI_CHIPLET_IN(WREADY_AXI_CHIPLET_IN),
+ .BID_AXI_CHIPLET_IN(BID_AXI_CHIPLET_IN),
+ .BRESP_AXI_CHIPLET_IN(BRESP_AXI_CHIPLET_IN),
+ .BVALID_AXI_CHIPLET_IN(BVALID_AXI_CHIPLET_IN),
+ .BREADY_AXI_CHIPLET_IN(BREADY_AXI_CHIPLET_IN),
+ .ARID_AXI_CHIPLET_IN(ARID_AXI_CHIPLET_IN),
+ .ARADDR_AXI_CHIPLET_IN(ARADDR_AXI_CHIPLET_IN),
+ .ARLEN_AXI_CHIPLET_IN(ARLEN_AXI_CHIPLET_IN),
+ .ARSIZE_AXI_CHIPLET_IN(ARSIZE_AXI_CHIPLET_IN),
+ .ARBURST_AXI_CHIPLET_IN(ARBURST_AXI_CHIPLET_IN),
+ .ARLOCK_AXI_CHIPLET_IN(ARLOCK_AXI_CHIPLET_IN),
+ .ARCACHE_AXI_CHIPLET_IN(ARCACHE_AXI_CHIPLET_IN),
+ .ARPROT_AXI_CHIPLET_IN(ARPROT_AXI_CHIPLET_IN),
+ .ARVALID_AXI_CHIPLET_IN(ARVALID_AXI_CHIPLET_IN),
+ .ARREADY_AXI_CHIPLET_IN(ARREADY_AXI_CHIPLET_IN),
+ .RID_AXI_CHIPLET_IN(RID_AXI_CHIPLET_IN),
+ .RDATA_AXI_CHIPLET_IN(RDATA_AXI_CHIPLET_IN),
+ .RRESP_AXI_CHIPLET_IN(RRESP_AXI_CHIPLET_IN),
+ .RLAST_AXI_CHIPLET_IN(RLAST_AXI_CHIPLET_IN),
+ .RVALID_AXI_CHIPLET_IN(RVALID_AXI_CHIPLET_IN),
+ .RREADY_AXI_CHIPLET_IN(RREADY_AXI_CHIPLET_IN),
+
+ .clk0clk(SYS_CLK),
+ .clk0clken(1'b1),
+ .clk0resetn(aRESETn)
+);
+
+sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
+
+);
+
+SRAM_wrapper u_SRAM_wrapper(
+ .ACLK(SYS_CLK),
+ .ARESETn(aRESETn),
+
+ .AWVALID(AWVALID_AXI_SRAM),
+ .AWREADY(AWREADY_AXI_SRAM),
+ .AWID(AWID_AXI_SRAM),
+ .AWADDR(AWADDR_AXI_SRAM),
+ .AWLEN(AWLEN_AXI_SRAM),
+ .AWSIZE(AWSIZE_AXI_SRAM),
+ .AWBURST(AWBURST_AXI_SRAM),
+ .AWLOCK(AWLOCK_AXI_SRAM),
+ .AWPROT(AWPROT_AXI_SRAM),
+ .AWQOS(),
+ .WVALID(WVALID_AXI_SRAM),
+ .WREADY(WREADY_AXI_SRAM),
+ .WDATA(WDATA_AXI_SRAM),
+ .WSTRB(WSTRB_AXI_SRAM),
+ .WLAST(WLAST_AXI_SRAM),
+ .BVALID(BVALID_AXI_SRAM),
+ .BREADY(BREADY_AXI_SRAM),
+ .BID(BID_AXI_SRAM),
+ .BRESP(BRESP_AXI_SRAM),
+ .ARVALID(ARVALID_AXI_SRAM),
+ .ARREADY(ARREADY_AXI_SRAM),
+ .ARID(ARID_AXI_SRAM),
+ .ARADDR(ARADDR_AXI_SRAM),
+ .ARLEN(ARLEN_AXI_SRAM),
+ .ARSIZE(ARSIZE_AXI_SRAM),
+ .ARBURST(ARBURST_AXI_SRAM),
+ .ARLOCK(ARLOCK_AXI_SRAM),
+ .ARPROT(ARPROT_AXI_SRAM),
+ .ARQOS(),
+ .RVALID(RVALID_AXI_SRAM),
+ .RREADY(RREADY_AXI_SRAM),
+ .RID(RID_AXI_SRAM),
+ .RDATA(RDATA_AXI_SRAM),
+ .RRESP(RRESP_AXI_SRAM),
+ .RLAST(RLAST_AXI_SRAM),
+ .AWAKEUP(1'b1),
+
+ .WPOISON(1'b0),
+ .RPOISON(),
+
+ .clk_qreqn(1'b1),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+
+ .pwr_qreqn(1'b1),
+ .pwr_qacceptn(),
+ .pwr_qdeny(),
+ .pwr_qactive(),
+
+ .ext_gt_qreqn(1'b1),
+ .ext_gt_qacceptn(),
+ .cfg_gate_resp(1'b0)
+);
+
+endmodule
diff --git a/socdebug_tech b/socdebug_tech
new file mode 160000
index 0000000000000000000000000000000000000000..7572912a3cde67880b0579db6f2e970ebaf2002d
--- /dev/null
+++ b/socdebug_tech
@@ -0,0 +1 @@
+Subproject commit 7572912a3cde67880b0579db6f2e970ebaf2002d
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index ec3ef9fb85d9f7000461193298c47c97cd4537ad..2f6d055d00f3315893135d8584820584a4750ce7 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -63,7 +63,7 @@ DATA_WIDTH: 32
# ID_WIDTH: AXI5 ID width for all channels
# Valid values:
# 2-32
-ID_WIDTH: 4
+ID_WIDTH: 5
#
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index fe98640e57ed7b538eec921298d96e9935c05945..62145b3902d61cce8e61faa2825dae3fd7ef864a 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>1</GlobalIDWidth>
+ <GlobalIDWidth>5</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -66,11 +66,11 @@
<AXI4SlaveProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
- <VIDWidth>0</VIDWidth>
+ <VIDWidth>4</VIDWidth>
<MultiRegion>false</MultiRegion>
<TrustZoneSlave>non_secure</TrustZoneSlave>
- <ReadAcceptance>16</ReadAcceptance>
- <WriteAcceptance>16</WriteAcceptance>
+ <ReadAcceptance>8</ReadAcceptance>
+ <WriteAcceptance>8</WriteAcceptance>
<QoSTypeAXI>fixed</QoSTypeAXI>
<QoSValue>0</QoSValue>
<TransactionRateRegulation>false</TransactionRateRegulation>
@@ -92,9 +92,9 @@
<IDWidth>0</IDWidth>
<MultiRegion>false</MultiRegion>
<TrustZoneMaster>non_secure</TrustZoneMaster>
- <ReadIssuing>1</ReadIssuing>
- <WriteIssuing>1</WriteIssuing>
- <TotalIssuing>1</TotalIssuing>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
<MultiPorted>false</MultiPorted>
<IDWidthReduction>true</IDWidthReduction>
<OutputSignals>false</OutputSignals>
@@ -211,7 +211,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>1</pl_id_width>
+ <pl_id_width>5</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -371,7 +371,7 @@
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
- <vid_width>0</vid_width>
+ <vid_width>4</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
@@ -971,9 +971,9 @@
<dest>AXI_CHIPLET_IN</dest>
<dest_port>AXI_CHIPLET_IN_s</dest_port>
<lock>false</lock>
- <out_reads>16</out_reads>
- <out_trans>32</out_trans>
- <out_writes>16</out_writes>
+ <out_reads>8</out_reads>
+ <out_trans>16</out_trans>
+ <out_writes>8</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
<src>external</src>
@@ -1003,9 +1003,9 @@
<dest>external</dest>
<dest_port>AXI_SRAM</dest_port>
<lock>false</lock>
- <out_reads>1</out_reads>
- <out_trans>1</out_trans>
- <out_writes>1</out_writes>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
<src>AXI_SRAM</src>
@@ -1032,9 +1032,9 @@
<dest>bm0</dest>
<dest_port>axi_s_0</dest_port>
<lock>false</lock>
- <out_reads def="true">16</out_reads>
- <out_trans>32</out_trans>
- <out_writes def="true">16</out_writes>
+ <out_reads def="true">8</out_reads>
+ <out_trans>16</out_trans>
+ <out_writes def="true">8</out_writes>
<protocol>axi4</protocol>
<src>AXI_CHIPLET_IN</src>
<src_port>AXI_CHIPLET_IN_m</src_port>
@@ -1054,9 +1054,9 @@
<dest>AXI_SRAM</dest>
<dest_port>AXI_SRAM_s</dest_port>
<lock>false</lock>
- <out_reads>1</out_reads>
- <out_trans>1</out_trans>
- <out_writes>1</out_writes>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
<src_port>axi_m_1</src_port>
@@ -1066,8 +1066,8 @@
<dest_port>axi_s_1</dest_port>
<lock>false</lock>
<out_reads def="true">1</out_reads>
- <out_trans>3</out_trans>
- <out_writes def="true">2</out_writes>
+ <out_trans>5</out_trans>
+ <out_writes def="true">4</out_writes>
<protocol>axi4</protocol>
<src>AHB_ADP</src>
<src_port>AHB_ADP_m</src_port>
@@ -1087,19 +1087,19 @@
<link>
<slave_if>
<name>AXI_CHIPLET_IN</name>
- <master_if>AXI_SRAM</master_if>
- <master_if>apb_group0</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>AXI_SRAM</master_if>
</slave_if>
</link>
<link>
<slave_if>
<name>AHB_ADP</name>
- <master_if>AXI_SRAM</master_if>
- <master_if>apb_group0</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>AXI_SRAM</master_if>
</slave_if>
</link>
</architecture>
diff --git a/socrates/nic400_tb/nic400_tb.xml b/socrates/nic400_tb/nic400_tb.xml
index e5ed83f8b9f70e1d785c26052daca3c1018b88be..6142c38fa060e0388a8333335f3af302de15bd74 100644
--- a/socrates/nic400_tb/nic400_tb.xml
+++ b/socrates/nic400_tb/nic400_tb.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>0</GlobalIDWidth>
+ <GlobalIDWidth>4</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -51,13 +51,558 @@
<ExternalGroups/>
<APBGroups/>
</Groups>
- <Interfaces/>
+ <Interfaces>
+ <SlaveInterface>
+ <Name>AXI_COCOTB</Name>
+ <AXI4SlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <VIDWidth>4</VIDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneSlave>non_secure</TrustZoneSlave>
+ <ReadAcceptance>8</ReadAcceptance>
+ <WriteAcceptance>8</WriteAcceptance>
+ <QoSTypeAXI>fixed</QoSTypeAXI>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <VNExternal>false</VNExternal>
+ </AXI4SlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>single_slave</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>AXI_CHIPLET_OUT</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>true</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ </Interfaces>
<MemoryMaps>
+ <MemoryMap>
+ <Name>mm0</Name>
+ <MemoryMapSource>
+ <InterfaceRef>AXI_COCOTB</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>AXI_CHIPLET_OUT</InterfaceRef>
+ <Offset>0</Offset>
+ <Range>2097152</Range>
+ <Visibility>true</Visibility>
+ <Region>0</Region>
+ </MappedBlock>
+ </MemoryMap>
</MemoryMaps>
- <Paths/>
+ <Paths>
+ <Path>
+ <Source>
+ <InterfaceRef>AXI_COCOTB</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>AXI_CHIPLET_OUT</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ </Paths>
<VirtualNetworks/>
</Specification>
- <Architecture/>
+ <Architecture>
+ <NICConfigFile><periph>
+ <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
+ <validator_version_info major_revision="22" minor_revision="1" />
+ <global>
+ <address0x0 def="true">bottom</address0x0>
+ <aruser_width>0</aruser_width>
+ <awuser_width>0</awuser_width>
+ <buser_width>0</buser_width>
+ <cc_type>async</cc_type>
+ <default_protocol>axi4</default_protocol>
+ <dpe_glb_enable def="true">false</dpe_glb_enable>
+ <dpe_status>false</dpe_status>
+ <dpe_width def="true">5</dpe_width>
+ <gen_caps>true</gen_caps>
+ <hcg_en>false</hcg_en>
+ <license_status>unlicensed_nic</license_status>
+ <periph_id3 def="true">0</periph_id3>
+ <pl_id_width>4</pl_id_width>
+ <qos_status>false</qos_status>
+ <rsb_arch_central_ring>false</rsb_arch_central_ring>
+ <ruser_width>0</ruser_width>
+ <sas_visible def="true">false</sas_visible>
+ <start_iid>0</start_iid>
+ <taxonomy>masterslave</taxonomy>
+ <thin_links_status def="true">false</thin_links_status>
+ <uppercase_ext_sig>true</uppercase_ext_sig>
+ <virtual_networks />
+ <virtual_networks_status>false</virtual_networks_status>
+ <wuser_width>0</wuser_width>
+ </global>
+ <clocks>
+ <domain freq="100">clk0</domain>
+ </clocks>
+ <asib>
+ <address_ranges>
+ <name>mm0</name>
+ <range>
+ <addr_max>0x1FFFFF</addr_max>
+ <addr_min>0x0</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_CHIPLET_OUT</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <cds>singleslave</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_COCOTB</name>
+ <protocol>axi4</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if_addr_width>32</slave_if_addr_width>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vid_width>4</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>AXI_COCOTB_m</master_if_port_name>
+ <slave_if_port_name>AXI_COCOTB_s</slave_if_port_name>
+ </asib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>65</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>true</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_CHIPLET_OUT</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>AXI_CHIPLET_OUT_m</master_if_port_name>
+ <slave_if_port_name>AXI_CHIPLET_OUT_s</slave_if_port_name>
+ </amib>
+ <inter>
+ <clock_domain>clk0</clock_domain>
+ <data_width>32</data_width>
+ <expanded>false</expanded>
+ <height>20</height>
+ <impl>mlayer</impl>
+ <master_if>
+ <name>axi_m_0</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>63</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_1</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>83</y>
+ </master_if>
+ <name>bm0</name>
+ <protocol>axi4</protocol>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>63</y>
+ </slave_if>
+ <sparse>
+ <cds>singleslave</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_0</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <type>busmatrix</type>
+ <width>0</width>
+ <x>500</x>
+ <y>45</y>
+ <master_if_port_name>axi_m_0,axi_m_1</master_if_port_name>
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <inter>
+ <name>ds_1</name>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <type>default_slave</type>
+ <x>500</x>
+ <y>500</y>
+ <master_if_port_name />
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>AXI_COCOTB</dest>
+ <dest_port>AXI_COCOTB_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>16</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>AXI_COCOTB</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>AXI_CHIPLET_OUT</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>AXI_CHIPLET_OUT</src>
+ <src_port>AXI_CHIPLET_OUT_m</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <dest>bm0</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">8</out_reads>
+ <out_trans>16</out_trans>
+ <out_writes def="true">8</out_writes>
+ <protocol>axi4</protocol>
+ <src>AXI_COCOTB</src>
+ <src_port>AXI_COCOTB_m</src_port>
+ </connect>
+ <connect>
+ <dest>AXI_CHIPLET_OUT</dest>
+ <dest_port>AXI_CHIPLET_OUT_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
+ <connect>
+ <dest>ds_1</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_1</src_port>
+ </connect>
+ <architecture>
+ <link>
+ <slave_if>
+ <name>AXI_COCOTB</name>
+ <master_if>AXI_CHIPLET_OUT</master_if>
+ </slave_if>
+ </link>
+ </architecture>
+</periph>
+</NICConfigFile>
+ </Architecture>
<Deliverables>
<IPXACT/>
<RTL/>
diff --git a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
index 281f5543a27913af8ca9dc3cdee38fe75d505afe..e394faacf4434179f5ddd3d6675df88b75b54120 100644
--- a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
+++ b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
@@ -26,13 +26,13 @@
<MasterTotalIssuing>16</MasterTotalIssuing>
<MultiRegion>false</MultiRegion>
<LockSupport>false</LockSupport>
- <SLAVE_PROTOCOL>AXI</SLAVE_PROTOCOL>
- <MASTER_PROTOCOL>AXI</MASTER_PROTOCOL>
+ <SLAVE_PROTOCOL>AXI4</SLAVE_PROTOCOL>
+ <MASTER_PROTOCOL>AXI4</MASTER_PROTOCOL>
<EarlyWriteResponse>true</EarlyWriteResponse>
<AllowBrokenBurst>false</AllowBrokenBurst>
<SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
<MASTER_CLOCK>clk_m</MASTER_CLOCK>
- <FW_USER_DEFINED_WIDTH>8</FW_USER_DEFINED_WIDTH>
+ <FW_USER_DEFINED_WIDTH>24</FW_USER_DEFINED_WIDTH>
<FW_PACKING_STRATEGY>widest_div_4</FW_PACKING_STRATEGY>
<FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
<REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
@@ -107,11 +107,11 @@
<SLAVE_PREALLOC_4>false</SLAVE_PREALLOC_4>
<FW_PHYSICAL_LINK>16</FW_PHYSICAL_LINK>
<REV_PHYSICAL_LINK>16</REV_PHYSICAL_LINK>
- <FW_AXI_SIGNAL>145</FW_AXI_SIGNAL>
+ <FW_AXI_SIGNAL>151</FW_AXI_SIGNAL>
<REV_AXI_SIGNAL>45</REV_AXI_SIGNAL>
- <FW_BANDWIDTH_PERCENTAGE>17</FW_BANDWIDTH_PERCENTAGE>
- <FW_UTILIZATION_PERCENTAGE>86</FW_UTILIZATION_PERCENTAGE>
- <FW_REDUCTION_PERCENTAGE>91</FW_REDUCTION_PERCENTAGE>
+ <FW_BANDWIDTH_PERCENTAGE>20</FW_BANDWIDTH_PERCENTAGE>
+ <FW_UTILIZATION_PERCENTAGE>92</FW_UTILIZATION_PERCENTAGE>
+ <FW_REDUCTION_PERCENTAGE>90</FW_REDUCTION_PERCENTAGE>
<REV_BANDWIDTH_PERCENTAGE>24</REV_BANDWIDTH_PERCENTAGE>
<REV_UTILIZATION_PERCENTAGE>98</REV_UTILIZATION_PERCENTAGE>
<REV_REDUCTION_PERCENTAGE>78</REV_REDUCTION_PERCENTAGE>
@@ -157,7 +157,7 @@
<Interfaces>
<SlaveInterface>
<Name>M1_s</Name>
- <AXISlaveProtocol>
+ <AXI4SlaveProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
<ARUSEREnabled>false</ARUSEREnabled>
@@ -165,12 +165,12 @@
<RUSEREnabled>false</RUSEREnabled>
<WUSEREnabled>false</WUSEREnabled>
<BUSEREnabled>false</BUSEREnabled>
- </AXISlaveProtocol>
+ </AXI4SlaveProtocol>
<ClockRef>clk_s</ClockRef>
</SlaveInterface>
<MasterInterface>
<Name>M1_m</Name>
- <AXIMasterProtocol>
+ <AXI4MasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
<ARUSEREnabled>false</ARUSEREnabled>
@@ -178,7 +178,7 @@
<RUSEREnabled>false</RUSEREnabled>
<WUSEREnabled>false</WUSEREnabled>
<BUSEREnabled>false</BUSEREnabled>
- </AXIMasterProtocol>
+ </AXI4MasterProtocol>
<ClockRef>clk_m</ClockRef>
</MasterInterface>
</Interfaces>
@@ -238,7 +238,7 @@
<power_domain_crossing>false</power_domain_crossing>
<fwd_tlx>
<pl_clock_ratio>1</pl_clock_ratio>
- <dll_link_user_def_width>8</dll_link_user_def_width>
+ <dll_link_user_def_width>24</dll_link_user_def_width>
<pl_reg_stages>0</pl_reg_stages>
<dll_link_width_option>widest_div_4</dll_link_width_option>
</fwd_tlx>
@@ -307,7 +307,7 @@
<master_if_addr_width>32</master_if_addr_width>
<clock_domain_name_slave_if>clk_s</clock_domain_name_slave_if>
<clock_domain_name_master_if>clk_m</clock_domain_name_master_if>
- <protocol>axi</protocol>
+ <protocol>axi4</protocol>
<dest_type>peripheral</dest_type>
<name>M1_m</name>
<vn_external_bridge>none</vn_external_bridge>
@@ -384,7 +384,7 @@
<out_trans>16</out_trans>
<dest>external</dest>
<src_port>M1_m_m</src_port>
- <protocol>axi</protocol>
+ <protocol>axi4</protocol>
<buser>false</buser>
<out_reads>16</out_reads>
<lock>false</lock>
@@ -400,7 +400,7 @@
<out_trans>32</out_trans>
<dest>M1_m</dest>
<src_port>M1_m_s</src_port>
- <protocol>axi</protocol>
+ <protocol>axi4</protocol>
<buser>false</buser>
<out_reads>16</out_reads>
<lock>false</lock>
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..00ee7c3e5018472de0170f2c6e913560272f61f2
--- /dev/null
+++ b/verif/cocotb/makefile
@@ -0,0 +1,68 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= questa
+WAVES ?= 0
+GUI ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+DUT = sram_chiplet_cocotb
+TOPLEVEL = sram_chiplet_cocotb
+MODULE = sram_chiplet_tests
+
+VERILOG_SOURCES += ./sram_chiplet_cocotb.v
+
+
+ifeq ($(SIM), icarus)
+ PLUSARGS += -fst
+
+ COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+
+ ifeq ($(WAVES), 1)
+ VERILOG_SOURCES += iverilog_dump.v
+ COMPILE_ARGS += -s iverilog_dump
+ endif
+else ifeq ($(SIM), verilator)
+ COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
+
+ COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+ ifeq ($(WAVES), 1)
+ COMPILE_ARGS += --trace-fst
+ endif
+endif
+include $(SOCLABS_SRAM_CHIPLET_DIR)/flist/sram_chiplet_cocotb.flist
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+ echo 'module iverilog_dump();' > $@
+ echo 'initial begin' >> $@
+ echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
+ echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
+ echo 'end' >> $@
+ echo 'endmodule' >> $@
+
+clean::
+ @rm -rf iverilog_dump.v
+ @rm -rf dump.fst $(TOPLEVEL).fst
diff --git a/verif/cocotb/sram_chiplet_cocotb.v b/verif/cocotb/sram_chiplet_cocotb.v
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c07106c9ffc8d3a6a6fdef3c84ab9f5b5e7c1eb1 100644
--- a/verif/cocotb/sram_chiplet_cocotb.v
+++ b/verif/cocotb/sram_chiplet_cocotb.v
@@ -0,0 +1,299 @@
+`timescale 1ns/1ps
+
+module sram_chiplet_cocotb(
+ input wire clk_in,
+ input wire aresetn,
+
+ input wire [3:0] cocotb_awid,
+ input wire [31:0] cocotb_awaddr,
+ input wire [7:0] cocotb_awlen,
+ input wire [2:0] cocotb_awsize,
+ input wire [1:0] cocotb_awburst,
+ input wire cocotb_awlock,
+ input wire [3:0] cocotb_awcache,
+ input wire [2:0] cocotb_awprot,
+ input wire cocotb_awvalid,
+ output wire cocotb_awready,
+ input wire [31:0] cocotb_wdata,
+ input wire [3:0] cocotb_wstrb,
+ input wire cocotb_wlast,
+ input wire cocotb_wvalid,
+ output wire cocotb_wready,
+ output wire [3:0] cocotb_bid,
+ output wire [1:0] cocotb_bresp,
+ output wire cocotb_bvalid,
+ input wire cocotb_bready,
+ input wire [3:0] cocotb_arid,
+ input wire [31:0] cocotb_araddr,
+ input wire [7:0] cocotb_arlen,
+ input wire [2:0] cocotb_arsize,
+ input wire [1:0] cocotb_arburst,
+ input wire cocotb_arlock,
+ input wire [3:0] cocotb_arcache,
+ input wire [2:0] cocotb_arprot,
+ input wire cocotb_arvalid,
+ output wire cocotb_arready,
+ output wire [3:0] cocotb_rid,
+ output wire [31:0] cocotb_rdata,
+ output wire [1:0] cocotb_rresp,
+ output wire cocotb_rlast,
+ output wire cocotb_rvalid,
+ input wire cocotb_rready
+
+);
+
+
+wire DL_REV_CLK;
+wire tvalid_pl_rev_m1_m_tlx_m_stream;
+wire tready_pl_rev_m1_m_tlx_m_stream;
+wire [15:0] tdata_pl_rev_m1_m_tlx_m_stream;
+wire tvalid_pl_rev_m1_m_tlx_m_flow;
+wire tready_pl_rev_m1_m_tlx_m_flow;
+wire [2:0] tdata_pl_rev_m1_m_tlx_m_flow;
+wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
+wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
+wire [1:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
+wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data;
+wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_data;
+wire [15:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data;
+
+
+wire [3:0] AWID_AXI_CHIPLET_OUT;
+wire [31:0] AWADDR_AXI_CHIPLET_OUT;
+wire [7:0] AWLEN_AXI_CHIPLET_OUT;
+wire [2:0] AWSIZE_AXI_CHIPLET_OUT;
+wire [1:0] AWBURST_AXI_CHIPLET_OUT;
+wire AWLOCK_AXI_CHIPLET_OUT;
+wire [3:0] AWCACHE_AXI_CHIPLET_OUT;
+wire [2:0] AWPROT_AXI_CHIPLET_OUT;
+wire AWVALID_AXI_CHIPLET_OUT;
+wire AWREADY_AXI_CHIPLET_OUT;
+wire [31:0] WDATA_AXI_CHIPLET_OUT;
+wire [3:0] WSTRB_AXI_CHIPLET_OUT;
+wire WLAST_AXI_CHIPLET_OUT;
+wire WVALID_AXI_CHIPLET_OUT;
+wire WREADY_AXI_CHIPLET_OUT;
+wire [3:0] BID_AXI_CHIPLET_OUT;
+wire [1:0] BRESP_AXI_CHIPLET_OUT;
+wire BVALID_AXI_CHIPLET_OUT;
+wire BREADY_AXI_CHIPLET_OUT;
+wire [3:0] ARID_AXI_CHIPLET_OUT;
+wire [31:0] ARADDR_AXI_CHIPLET_OUT;
+wire [7:0] ARLEN_AXI_CHIPLET_OUT;
+wire [2:0] ARSIZE_AXI_CHIPLET_OUT;
+wire [1:0] ARBURST_AXI_CHIPLET_OUT;
+wire ARLOCK_AXI_CHIPLET_OUT;
+wire [3:0] ARCACHE_AXI_CHIPLET_OUT;
+wire [2:0] ARPROT_AXI_CHIPLET_OUT;
+wire ARVALID_AXI_CHIPLET_OUT;
+wire ARREADY_AXI_CHIPLET_OUT;
+wire [3:0] RID_AXI_CHIPLET_OUT;
+wire [31:0] RDATA_AXI_CHIPLET_OUT;
+wire [1:0] RRESP_AXI_CHIPLET_OUT;
+wire RLAST_AXI_CHIPLET_OUT;
+wire RVALID_AXI_CHIPLET_OUT;
+wire RREADY_AXI_CHIPLET_OUT;
+
+wire tvalid_m1_m_tlx_fwd_ib_axi_stream;
+wire tready_m1_m_tlx_fwd_ib_axi_stream;
+wire [15:0] tdata_m1_m_tlx_fwd_ib_axi_stream;
+
+wire tvalid_m1_m_tlx_fwd_ib_flow;
+wire tready_m1_m_tlx_fwd_ib_flow;
+wire [1:0] tdata_m1_m_tlx_fwd_ib_flow;
+nic400_tb u_nic400_tb(
+ .AWID_AXI_CHIPLET_OUT(AWID_AXI_CHIPLET_OUT),
+ .AWADDR_AXI_CHIPLET_OUT(AWADDR_AXI_CHIPLET_OUT),
+ .AWLEN_AXI_CHIPLET_OUT(AWLEN_AXI_CHIPLET_OUT),
+ .AWSIZE_AXI_CHIPLET_OUT(AWSIZE_AXI_CHIPLET_OUT),
+ .AWBURST_AXI_CHIPLET_OUT(AWBURST_AXI_CHIPLET_OUT),
+ .AWLOCK_AXI_CHIPLET_OUT(AWLOCK_AXI_CHIPLET_OUT),
+ .AWCACHE_AXI_CHIPLET_OUT(AWCACHE_AXI_CHIPLET_OUT),
+ .AWPROT_AXI_CHIPLET_OUT(AWPROT_AXI_CHIPLET_OUT),
+ .AWVALID_AXI_CHIPLET_OUT(AWVALID_AXI_CHIPLET_OUT),
+ .AWREADY_AXI_CHIPLET_OUT(AWREADY_AXI_CHIPLET_OUT),
+ .WDATA_AXI_CHIPLET_OUT(WDATA_AXI_CHIPLET_OUT),
+ .WSTRB_AXI_CHIPLET_OUT(WSTRB_AXI_CHIPLET_OUT),
+ .WLAST_AXI_CHIPLET_OUT(WLAST_AXI_CHIPLET_OUT),
+ .WVALID_AXI_CHIPLET_OUT(WVALID_AXI_CHIPLET_OUT),
+ .WREADY_AXI_CHIPLET_OUT(WREADY_AXI_CHIPLET_OUT),
+ .BID_AXI_CHIPLET_OUT(BID_AXI_CHIPLET_OUT),
+ .BRESP_AXI_CHIPLET_OUT(BRESP_AXI_CHIPLET_OUT),
+ .BVALID_AXI_CHIPLET_OUT(BVALID_AXI_CHIPLET_OUT),
+ .BREADY_AXI_CHIPLET_OUT(BREADY_AXI_CHIPLET_OUT),
+ .ARID_AXI_CHIPLET_OUT(ARID_AXI_CHIPLET_OUT),
+ .ARADDR_AXI_CHIPLET_OUT(ARADDR_AXI_CHIPLET_OUT),
+ .ARLEN_AXI_CHIPLET_OUT(ARLEN_AXI_CHIPLET_OUT),
+ .ARSIZE_AXI_CHIPLET_OUT(ARSIZE_AXI_CHIPLET_OUT),
+ .ARBURST_AXI_CHIPLET_OUT(ARBURST_AXI_CHIPLET_OUT),
+ .ARLOCK_AXI_CHIPLET_OUT(ARLOCK_AXI_CHIPLET_OUT),
+ .ARCACHE_AXI_CHIPLET_OUT(ARCACHE_AXI_CHIPLET_OUT),
+ .ARPROT_AXI_CHIPLET_OUT(ARPROT_AXI_CHIPLET_OUT),
+ .ARVALID_AXI_CHIPLET_OUT(ARVALID_AXI_CHIPLET_OUT),
+ .ARREADY_AXI_CHIPLET_OUT(ARREADY_AXI_CHIPLET_OUT),
+ .RID_AXI_CHIPLET_OUT(RID_AXI_CHIPLET_OUT),
+ .RDATA_AXI_CHIPLET_OUT(RDATA_AXI_CHIPLET_OUT),
+ .RRESP_AXI_CHIPLET_OUT(RRESP_AXI_CHIPLET_OUT),
+ .RLAST_AXI_CHIPLET_OUT(RLAST_AXI_CHIPLET_OUT),
+ .RVALID_AXI_CHIPLET_OUT(RVALID_AXI_CHIPLET_OUT),
+ .RREADY_AXI_CHIPLET_OUT(RREADY_AXI_CHIPLET_OUT),
+
+ .AWID_AXI_COCOTB(cocotb_awid),
+ .AWADDR_AXI_COCOTB(cocotb_awaddr),
+ .AWLEN_AXI_COCOTB(cocotb_awlen),
+ .AWSIZE_AXI_COCOTB(cocotb_awsize),
+ .AWBURST_AXI_COCOTB(cocotb_awburst),
+ .AWLOCK_AXI_COCOTB(cocotb_awlock),
+ .AWCACHE_AXI_COCOTB(cocotb_awcache),
+ .AWPROT_AXI_COCOTB(cocotb_awprot),
+ .AWVALID_AXI_COCOTB(cocotb_awvalid),
+ .AWREADY_AXI_COCOTB(cocotb_awready),
+ .WDATA_AXI_COCOTB(cocotb_wdata),
+ .WSTRB_AXI_COCOTB(cocotb_wstrb),
+ .WLAST_AXI_COCOTB(cocotb_wlast),
+ .WVALID_AXI_COCOTB(cocotb_wvalid),
+ .WREADY_AXI_COCOTB(cocotb_wready),
+ .BID_AXI_COCOTB(cocotb_bid),
+ .BRESP_AXI_COCOTB(cocotb_bresp),
+ .BVALID_AXI_COCOTB(cocotb_bvalid),
+ .BREADY_AXI_COCOTB(cocotb_bready),
+ .ARID_AXI_COCOTB(cocotb_arid),
+ .ARADDR_AXI_COCOTB(cocotb_araddr),
+ .ARLEN_AXI_COCOTB(cocotb_arlen),
+ .ARSIZE_AXI_COCOTB(cocotb_arsize),
+ .ARBURST_AXI_COCOTB(cocotb_arburst),
+ .ARLOCK_AXI_COCOTB(cocotb_arlock),
+ .ARCACHE_AXI_COCOTB(cocotb_arcache),
+ .ARPROT_AXI_COCOTB(cocotb_arprot),
+ .ARVALID_AXI_COCOTB(cocotb_arvalid),
+ .ARREADY_AXI_COCOTB(cocotb_arready),
+ .RID_AXI_COCOTB(cocotb_rid),
+ .RDATA_AXI_COCOTB(cocotb_rdata),
+ .RRESP_AXI_COCOTB(cocotb_rresp),
+ .RLAST_AXI_COCOTB(cocotb_rlast),
+ .RVALID_AXI_COCOTB(cocotb_rvalid),
+ .RREADY_AXI_COCOTB(cocotb_rready),
+
+ .clk0clk(clk_in),
+ .clk0resetn(aresetn)
+);
+
+
+nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
+ .awid_m1_m_s(AWID_AXI_CHIPLET_OUT),
+ .awaddr_m1_m_s(AWADDR_AXI_CHIPLET_OUT),
+ .awlen_m1_m_s(AWLEN_AXI_CHIPLET_OUT),
+ .awsize_m1_m_s(AWSIZE_AXI_CHIPLET_OUT),
+ .awburst_m1_m_s(AWBURST_AXI_CHIPLET_OUT),
+ .awlock_m1_m_s(AWLOCK_AXI_CHIPLET_OUT),
+ .awcache_m1_m_s(AWCACHE_AXI_CHIPLET_OUT),
+ .awprot_m1_m_s(AWPROT_AXI_CHIPLET_OUT),
+ .awvalid_m1_m_s(AWVALID_AXI_CHIPLET_OUT),
+ .awready_m1_m_s(AWREADY_AXI_CHIPLET_OUT),
+ .wdata_m1_m_s(WDATA_AXI_CHIPLET_OUT),
+ .wstrb_m1_m_s(WSTRB_AXI_CHIPLET_OUT),
+ .wlast_m1_m_s(WLAST_AXI_CHIPLET_OUT),
+ .wvalid_m1_m_s(WVALID_AXI_CHIPLET_OUT),
+ .wready_m1_m_s(WREADY_AXI_CHIPLET_OUT),
+ .bid_m1_m_s(BID_AXI_CHIPLET_OUT),
+ .bresp_m1_m_s(BRESP_AXI_CHIPLET_OUT),
+ .bvalid_m1_m_s(BVALID_AXI_CHIPLET_OUT),
+ .bready_m1_m_s(BREADY_AXI_CHIPLET_OUT),
+ .arid_m1_m_s(ARID_AXI_CHIPLET_OUT),
+ .araddr_m1_m_s(ARADDR_AXI_CHIPLET_OUT),
+ .arlen_m1_m_s(ARLEN_AXI_CHIPLET_OUT),
+ .arsize_m1_m_s(ARSIZE_AXI_CHIPLET_OUT),
+ .arburst_m1_m_s(ARBURST_AXI_CHIPLET_OUT),
+ .arlock_m1_m_s(ARLOCK_AXI_CHIPLET_OUT),
+ .arcache_m1_m_s(ARCACHE_AXI_CHIPLET_OUT),
+ .arprot_m1_m_s(ARPROT_AXI_CHIPLET_OUT),
+ .arvalid_m1_m_s(ARVALID_AXI_CHIPLET_OUT),
+ .arready_m1_m_s(ARREADY_AXI_CHIPLET_OUT),
+ .rid_m1_m_s(RID_AXI_CHIPLET_OUT),
+ .rdata_m1_m_s(RDATA_AXI_CHIPLET_OUT),
+ .rresp_m1_m_s(RRESP_AXI_CHIPLET_OUT),
+ .rlast_m1_m_s(RLAST_AXI_CHIPLET_OUT),
+ .rvalid_m1_m_s(RVALID_AXI_CHIPLET_OUT),
+ .rready_m1_m_s(RREADY_AXI_CHIPLET_OUT),
+
+ // Axi Stream master (tdata out) data stream
+ .tvalid_m1_m_tlx_fwd_ib_axi_stream(tvalid_m1_m_tlx_fwd_ib_axi_stream),
+ .tready_m1_m_tlx_fwd_ib_axi_stream(tready_m1_m_tlx_fwd_ib_axi_stream),
+ .tdata_m1_m_tlx_fwd_ib_axi_stream(tdata_m1_m_tlx_fwd_ib_axi_stream),
+
+ // Axi Stream master (tdata out) data flow
+ .tvalid_m1_m_tlx_fwd_ib_flow(tvalid_m1_m_tlx_fwd_ib_flow),
+ .tready_m1_m_tlx_fwd_ib_flow(tready_m1_m_tlx_fwd_ib_flow),
+ .tdata_m1_m_tlx_fwd_ib_flow(tdata_m1_m_tlx_fwd_ib_flow),
+
+ // Axi Stream slave (tdata in) rev flow from SRAM chiplet PL
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(tready_pl_rev_m1_m_tlx_m_flow),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+
+ // Axi stream slave (tdata in) rev data from SRAM chiplet PL
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(tvalid_pl_rev_m1_m_tlx_m_stream),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_data(tready_pl_rev_m1_m_tlx_m_stream),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(tdata_pl_rev_m1_m_tlx_m_stream),
+
+ .clk_sclk(clk_in),
+ .clk_sresetn(aresetn),
+ .dl_rev_M1_m_tlxclk(clk_in),
+ .dl_rev_M1_m_tlxresetn(aresetn)
+);
+
+nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
+ // axi sream master (tdata out)
+ .tvalid_pl_fwd_m1_m_tlx_m_stream(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tready_pl_fwd_m1_m_tlx_m_stream(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tdata_pl_fwd_m1_m_tlx_m_stream(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+
+ // axi stream slave (tdata in)
+ .tvalid_pl_fwd_m1_m_tlx_s_stream(tvalid_m1_m_tlx_fwd_ib_axi_stream),
+ .tready_pl_fwd_m1_m_tlx_s_stream(tready_m1_m_tlx_fwd_ib_axi_stream),
+ .tdata_pl_fwd_m1_m_tlx_s_stream(tdata_m1_m_tlx_fwd_ib_axi_stream),
+
+ // axi stream master (tdata out)
+ .tvalid_pl_fwd_m1_m_tlx_m_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tready_pl_fwd_m1_m_tlx_m_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tdata_pl_fwd_m1_m_tlx_m_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+
+ // axi stream slave (tdata in)
+ .tvalid_pl_fwd_m1_m_tlx_s_flow(tvalid_m1_m_tlx_fwd_ib_flow),
+ .tready_pl_fwd_m1_m_tlx_s_flow(tready_m1_m_tlx_fwd_ib_flow),
+ .tdata_pl_fwd_m1_m_tlx_s_flow(tdata_m1_m_tlx_fwd_ib_flow),
+
+ .pl_fwd_M1_m_tlxclk(clk_in),
+ .pl_fwd_M1_m_tlxresetn(aresetn)
+);
+
+top_sram_chiplet u_top_sram_chiplet(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Axi stream master (tdata out) from PL
+ .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
+ .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
+ .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
+
+ // Axi Stream master (tdata out) from PL
+ .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
+ .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
+ .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+
+ // Axi Stream Slave (tdata in) to DL
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+
+ // Axi Stream slave (tdata in) to DL
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data)
+);
+
+endmodule
\ No newline at end of file
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
new file mode 100644
index 0000000000000000000000000000000000000000..ddeadc2546e20e7096c956d722a43da8291e8370
--- /dev/null
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -0,0 +1,76 @@
+#-----------------------------------------------------------------------------
+# SRAM Chiplet cocoTB script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright � 2021-4, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+# CocoTB Testcases:
+# SRAM_test_write
+# SRAM_test_write_words
+
+import itertools
+import logging
+import os
+from numpy import random
+import numpy as np
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, ClockCycles
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster, AxiRam, AxiBurstType, AxiSlave
+
+class TB:
+ def __init__(self,dut):
+ self.dut = dut
+
+ self.log = logging.getLogger("cocotb.tb")
+ self.log.setLevel(logging.DEBUG)
+
+ cocotb.start_soon(Clock(dut.clk_in, 1, units="ns").start())
+ self.axi_master = AxiMaster(AxiBus.from_prefix(dut,"cocotb"), dut.clk_in, dut.aresetn, reset_active_level=False)
+ def set_idle_generator(self, generator=None):
+ if generator:
+ self.axi_master.write_if.aw_channel.set_pause_generator(generator())
+ self.axi_master.write_if.w_channel.set_pause_generator(generator())
+ self.axi_master.read_if.ar_channel.set_pause_generator(generator())
+ self.axi_ram.write_if.b_channel.set_pause_generator(generator())
+ self.axi_ram.read_if.r_channel.set_pause_generator(generator())
+ def set_backpressure_generator(self, generator=None):
+ if generator:
+ self.axi_master.write_if.b_channel.set_pause_generator(generator())
+ self.axi_master.read_if.r_channel.set_pause_generator(generator())
+ self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
+ self.axi_ram.write_if.w_channel.set_pause_generator(generator())
+ self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
+ async def cycle_reset(self):
+ self.dut.aresetn.setimmediatevalue(0)
+ await RisingEdge(self.dut.clk_in)
+ await RisingEdge(self.dut.clk_in)
+ await RisingEdge(self.dut.clk_in)
+ await RisingEdge(self.dut.clk_in)
+ self.dut.aresetn.value = 1
+ await RisingEdge(self.dut.clk_in)
+ async def delay(self, cycle):
+ for i in range(cycle):
+ await RisingEdge(self.dut.clk_in)
+
+@cocotb.test()
+async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_inserter)
+ tb.set_backpressure_generator(backpressure_inserter)
+ data = bytearray([0]*2048)
+ await tb.axi_master.write(0x00000000, data)