From 807067795d5f58ebfcd2eb83bdf950ca4acd8731 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 3 Sep 2024 16:28:44 +0100
Subject: [PATCH] Initial Add slim 16k SRAM
---
.../synopsys_lib_conversion.tcl | 14 +++++---
flist/Top/sram_chiplet_TSMC28nm.flist | 3 +-
flows/makefile.asic | 12 +++----
logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v | 35 +++++++++++++++++--
4 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
index b32ac35..b053c7f 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
@@ -13,10 +13,16 @@ set sc9mcpp140z_db_file_ff_0p99v_m40C $sc9mcpp140z_base_path/db/sc9mcpp140z_cl
set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
# SRAM files (using Arm compiler)
-set sram_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k.lef
-set sram_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k.gds2
-set sram_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_32k_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.lef
+set sram_32k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.gds2
+set sram_32k_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_32k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.db
+
+set sram_16k_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.lef
+set sram_16k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.gds2
+set sram_16k_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_16k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c.db
+
# Synopsys PLL files
set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
index 0ddb049..83f5ae7 100644
--- a/flist/Top/sram_chiplet_TSMC28nm.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -21,7 +21,8 @@
// SRAM Chiplet - SRAM
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_emulation.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_emulation.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_emulation.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
diff --git a/flows/makefile.asic b/flows/makefile.asic
index ebd3767..60d8fcd 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -32,10 +32,10 @@ gen_memories_frontend:
cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(SRAM_32K_SPEC_FILE)
cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(SRAM_32K_SPEC_FILE)
echo "Generating 16K SRAM Memory"
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(MEM_16K_DIR)
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(MEM_16K_DIR)
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(MEM_16K_DIR)
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(SRAM_16K_SPEC_FILE)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(SRAM_16K_SPEC_FILE)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(SRAM_16K_SPEC_FILE)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(SRAM_16K_SPEC_FILE)
gen_memories_backend:
@mkdir -p $(MEMORIES_DIR)
@@ -45,7 +45,7 @@ gen_memories_backend:
cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_32K_SPEC_FILE)
cd $(MEM_32K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_32K_SPEC_FILE)
echo "Generating 16K SRAM Memory"
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(MEM_16K_DIR)
- cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(MEM_16K_DIR)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_16K_SPEC_FILE)
+ cd $(MEM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_16K_SPEC_FILE)
gen_memories: gen_memories_frontend gen_memories_backend
\ No newline at end of file
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
index 99cea2b..6f82eb4 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
@@ -12,16 +12,16 @@ module SRAM (
localparam N_MEMS = 8;
localparam SEL_W = 3;
-reg [N_MEMS-1:0] CEN_i; //Active low chip select
+reg [N_MEMS:0] CEN_i; //Active low chip select
wire [31:0] wena_i;
wire gwen_i;
-wire [31:0] q_i[0:N_MEMS-1];
+wire [31:0] q_i[0:N_MEMS];
assign wena_i = {{8{memwen[3]}}, {8{memwen[2]}}, {8{memwen[1]}}, {8{memwen[0]}}};
assign gwen_i = &memwen;
genvar i;
-generate for(i=0; i<N_MEMS; i = i + 1) begin: g_srams
+generate for(i=0; i<N_MEMS-1; i = i + 1) begin: g_srams
sram_32b_32k u_sram_32b_32k(
.Q(q_i[i]),
.CLK(clk),
@@ -39,6 +39,35 @@ generate for(i=0; i<N_MEMS; i = i + 1) begin: g_srams
end endgenerate
+sram_32b_16k u_sram_32b_16k_0(
+ .Q(q_i[N_MEMS-1]),
+ .CLK(clk),
+ .CEN(CEN_i[N_MEMS-1]),
+ .GWEN(gwen_i),
+ .A(memaddr[16:2]),
+ .D(memd),
+ .WEN(wena_i),
+ .STOV(1'b0),
+ .EMA(3'b011),
+ .EMAW(2'b01),
+ .EMAS(1'b0),
+ .RET1N(1'b1)
+);
+sram_32b_16k u_sram_32b_16k_0(
+ .Q(q_i[N_MEMS]),
+ .CLK(clk),
+ .CEN(CEN_i[N_MEMS]),
+ .GWEN(gwen_i),
+ .A(memaddr[16:2]),
+ .D(memd),
+ .WEN(wena_i),
+ .STOV(1'b0),
+ .EMA(3'b011),
+ .EMAW(2'b01),
+ .EMAS(1'b0),
+ .RET1N(1'b1)
+);
+
integer j;
always @(*) begin
for(j=0; j<N_MEMS; j=j+1) begin
--
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