From 79ab6f6a085a93a77772005a5fbafc0879c12d15 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 27 Aug 2024 12:40:06 +0100
Subject: [PATCH] Update address ranges and fix byte writes and reads

---
 logical/SRAM/verilog/SRAM.v                   |   2 +-
 makefile                                      |   9 +-
 .../nic400_sram_chiplet.xml                   |  22 +-
 .../nic400_tlx_sram_chiplet.xml               | 205 +-----------------
 verif/cocotb/sram_chiplet_tests.py            |  25 ++-
 5 files changed, 44 insertions(+), 219 deletions(-)

diff --git a/logical/SRAM/verilog/SRAM.v b/logical/SRAM/verilog/SRAM.v
index 35f5f4b..9684460 100644
--- a/logical/SRAM/verilog/SRAM.v
+++ b/logical/SRAM/verilog/SRAM.v
@@ -19,7 +19,7 @@ module SRAM (
 
   integer                  i;     // Write-strobe loop variable
   integer                  j;     // Mask-bit loop variable
-  assign Addr = memaddr[20:4];
+  assign Addr = memaddr[20:2];
   // -------------
   // Memory arrays
   // -------------
diff --git a/makefile b/makefile
index cfdae38..5880139 100644
--- a/makefile
+++ b/makefile
@@ -6,11 +6,16 @@ include ./make.cfg
 
 build_sie300_sram_ctrl:
 	@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
-build_nic400:
+build_nic400_sram_chiplet:
 	socrates_cli --project sram_chiplet -data ../ --flow build.configured.component configuredComponentName=nic400_sram_chiplet
+build_nic400_tb:
+	socrates_cli --project sram_chiplet -data ../ --flow build.configured.component configuredComponentName=nic400_tb
+build_tlx_sram_chiplet:
+	socrates_cli --project sram_chiplet -data ../ --flow build.configured.component configuredComponentName=nic400_tlx_sram_chiplet
+
 
 make_project:
 	socrates_cli --project sram_chiplet -data ../ --flow AddNewProject
 
-first_time_setup: make_project build_sie300_sram_ctrl
+first_time_setup: make_project build_sie300_sram_ctrl build_nic400_sram_chiplet build_nic400_tb build_tlx_sram_chiplet
 
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index 62145b3..5079c85 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -152,13 +152,13 @@
         <MappedBlock>
           <InterfaceRef>AXI_SRAM</InterfaceRef>
           <Offset>0</Offset>
-          <Range>65536</Range>
+          <Range>2031616</Range>
           <Visibility>true</Visibility>
         </MappedBlock>
         <MappedBlock>
           <InterfaceRef>APB_PVT</InterfaceRef>
-          <Offset>65536</Offset>
-          <Range>4096</Range>
+          <Offset>2031616</Offset>
+          <Range>65536</Range>
           <Visibility>true</Visibility>
         </MappedBlock>
       </MemoryMap>
@@ -231,7 +231,7 @@
         &lt;address_ranges&gt;
             &lt;name&gt;mm0&lt;/name&gt;
             &lt;range&gt;
-                &lt;addr_max&gt;0xFFFF&lt;/addr_max&gt;
+                &lt;addr_max&gt;0x1EFFFF&lt;/addr_max&gt;
                 &lt;addr_min&gt;0x0&lt;/addr_min&gt;
                 &lt;remap&gt;
                     &lt;bit&gt;default&lt;/bit&gt;
@@ -241,8 +241,8 @@
                 &lt;/remap&gt;
             &lt;/range&gt;
             &lt;range&gt;
-                &lt;addr_max&gt;0x10FFF&lt;/addr_max&gt;
-                &lt;addr_min&gt;0x10000&lt;/addr_min&gt;
+                &lt;addr_max&gt;0x1FFFFF&lt;/addr_max&gt;
+                &lt;addr_min&gt;0x1F0000&lt;/addr_min&gt;
                 &lt;remap&gt;
                     &lt;bit&gt;default&lt;/bit&gt;
                     &lt;present&gt;true&lt;/present&gt;
@@ -383,7 +383,7 @@
         &lt;address_ranges&gt;
             &lt;name&gt;mm0&lt;/name&gt;
             &lt;range&gt;
-                &lt;addr_max&gt;0xFFFF&lt;/addr_max&gt;
+                &lt;addr_max&gt;0x1EFFFF&lt;/addr_max&gt;
                 &lt;addr_min&gt;0x0&lt;/addr_min&gt;
                 &lt;remap&gt;
                     &lt;bit&gt;default&lt;/bit&gt;
@@ -393,8 +393,8 @@
                 &lt;/remap&gt;
             &lt;/range&gt;
             &lt;range&gt;
-                &lt;addr_max&gt;0x10FFF&lt;/addr_max&gt;
-                &lt;addr_min&gt;0x10000&lt;/addr_min&gt;
+                &lt;addr_max&gt;0x1FFFFF&lt;/addr_max&gt;
+                &lt;addr_min&gt;0x1F0000&lt;/addr_min&gt;
                 &lt;remap&gt;
                     &lt;bit&gt;default&lt;/bit&gt;
                     &lt;present&gt;true&lt;/present&gt;
@@ -1087,19 +1087,19 @@
         &lt;link&gt;
             &lt;slave_if&gt;
                 &lt;name&gt;AXI_CHIPLET_IN&lt;/name&gt;
+                &lt;master_if&gt;AXI_SRAM&lt;/master_if&gt;
                 &lt;master_if&gt;APB_PVT&lt;parent&gt;apb_group0&lt;/parent&gt;
                 &lt;/master_if&gt;
                 &lt;master_if&gt;apb_group0&lt;/master_if&gt;
-                &lt;master_if&gt;AXI_SRAM&lt;/master_if&gt;
             &lt;/slave_if&gt;
         &lt;/link&gt;
         &lt;link&gt;
             &lt;slave_if&gt;
                 &lt;name&gt;AHB_ADP&lt;/name&gt;
+                &lt;master_if&gt;AXI_SRAM&lt;/master_if&gt;
                 &lt;master_if&gt;APB_PVT&lt;parent&gt;apb_group0&lt;/parent&gt;
                 &lt;/master_if&gt;
                 &lt;master_if&gt;apb_group0&lt;/master_if&gt;
-                &lt;master_if&gt;AXI_SRAM&lt;/master_if&gt;
             &lt;/slave_if&gt;
         &lt;/link&gt;
     &lt;/architecture&gt;
diff --git a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
index e394faa..55348a4 100644
--- a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
+++ b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
@@ -32,7 +32,7 @@
       <AllowBrokenBurst>false</AllowBrokenBurst>
       <SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
       <MASTER_CLOCK>clk_m</MASTER_CLOCK>
-      <FW_USER_DEFINED_WIDTH>24</FW_USER_DEFINED_WIDTH>
+      <FW_USER_DEFINED_WIDTH>16</FW_USER_DEFINED_WIDTH>
       <FW_PACKING_STRATEGY>widest_div_4</FW_PACKING_STRATEGY>
       <FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
       <REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
@@ -209,208 +209,7 @@
     </Paths>
     <VirtualNetworks/>
   </Specification>
-  <Architecture>
-    <NICConfigFile>&lt;?xml version=&quot;1.0&quot; encoding=&quot;iso-8859-1&quot; ?&gt;
-&lt;periph&gt;
-&lt;product_version_info major_version=&quot;00&quot; minor_revision=&quot;2&quot; major_revision=&quot;1&quot; minor_version=&quot;0&quot; part_quality=&quot;rel&quot; minor_code=&quot;50000&quot; major_group=&quot;bu&quot; product_code=&quot;nic400_tlx&quot;/&gt;
-&lt;validator_version_info minor_revision=&quot;1&quot; major_revision=&quot;22&quot; /&gt;
-   &lt;global&gt;
-      &lt;qos_status&gt;false&lt;/qos_status&gt;
-      &lt;buser_width&gt;0&lt;/buser_width&gt;
-      &lt;hcg_en&gt;false&lt;/hcg_en&gt;
-      &lt;virtual_networks_status&gt;false&lt;/virtual_networks_status&gt;
-      &lt;rsb_arch_central_ring&gt;false&lt;/rsb_arch_central_ring&gt;
-      &lt;thin_links_status&gt;true&lt;/thin_links_status&gt;
-      &lt;awuser_width&gt;0&lt;/awuser_width&gt;
-      &lt;license_status&gt;unlicensed_nic&lt;/license_status&gt;
-      &lt;dpe_status&gt;false&lt;/dpe_status&gt;
-      &lt;aruser_width&gt;0&lt;/aruser_width&gt;
-      &lt;cc_type&gt;async&lt;/cc_type&gt;
-      &lt;pl_id_width&gt;4&lt;/pl_id_width&gt;
-      &lt;ruser_width&gt;0&lt;/ruser_width&gt;
-      &lt;wuser_width&gt;0&lt;/wuser_width&gt;
-   &lt;/global&gt;
-   &lt;amib&gt;
-      &lt;master_if_port_name&gt;M1_m_m&lt;/master_if_port_name&gt;
-      &lt;multi_region&gt;false&lt;/multi_region&gt;
-      &lt;tide&gt;0&lt;/tide&gt;
-      &lt;tlx&gt;
-         &lt;power_domain_crossing&gt;false&lt;/power_domain_crossing&gt;
-         &lt;fwd_tlx&gt;
-            &lt;pl_clock_ratio&gt;1&lt;/pl_clock_ratio&gt;
-            &lt;dll_link_user_def_width&gt;24&lt;/dll_link_user_def_width&gt;
-            &lt;pl_reg_stages&gt;0&lt;/pl_reg_stages&gt;
-            &lt;dll_link_width_option&gt;widest_div_4&lt;/dll_link_width_option&gt;
-         &lt;/fwd_tlx&gt;
-         &lt;rev_tlx&gt;
-            &lt;pl_clock_ratio&gt;1&lt;/pl_clock_ratio&gt;
-            &lt;dll_link_user_def_width&gt;8&lt;/dll_link_user_def_width&gt;
-            &lt;pl_reg_stages&gt;0&lt;/pl_reg_stages&gt;
-            &lt;dll_link_width_option&gt;widest_div_4&lt;/dll_link_width_option&gt;
-         &lt;/rev_tlx&gt;
-         &lt;tlx_enable&gt;true&lt;/tlx_enable&gt;
-         &lt;ahb_bridge&gt;false&lt;/ahb_bridge&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fifo&lt;/type&gt;
-            &lt;impl&gt;present&lt;/impl&gt;
-            &lt;depth&gt;6&lt;/depth&gt;
-            &lt;name&gt;aw&lt;/name&gt;
-            &lt;location&gt;boundary&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fifo&lt;/type&gt;
-            &lt;impl&gt;present&lt;/impl&gt;
-            &lt;depth&gt;6&lt;/depth&gt;
-            &lt;name&gt;w&lt;/name&gt;
-            &lt;location&gt;boundary&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fifo&lt;/type&gt;
-            &lt;impl&gt;present&lt;/impl&gt;
-            &lt;depth&gt;6&lt;/depth&gt;
-            &lt;name&gt;b&lt;/name&gt;
-            &lt;location&gt;boundary&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fifo&lt;/type&gt;
-            &lt;impl&gt;present&lt;/impl&gt;
-            &lt;depth&gt;6&lt;/depth&gt;
-            &lt;name&gt;ar&lt;/name&gt;
-            &lt;location&gt;boundary&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fifo&lt;/type&gt;
-            &lt;impl&gt;present&lt;/impl&gt;
-            &lt;depth&gt;6&lt;/depth&gt;
-            &lt;name&gt;r&lt;/name&gt;
-            &lt;location&gt;boundary&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fwd&lt;/type&gt;
-            &lt;impl&gt;absent&lt;/impl&gt;
-            &lt;name&gt;d&lt;/name&gt;
-            &lt;location&gt;tlx_fwd&lt;/location&gt;
-         &lt;/reg&gt;
-         &lt;reg&gt;
-            &lt;type&gt;fwd&lt;/type&gt;
-            &lt;impl&gt;absent&lt;/impl&gt;
-            &lt;name&gt;d&lt;/name&gt;
-            &lt;location&gt;tlx_rev&lt;/location&gt;
-         &lt;/reg&gt;
-      &lt;/tlx&gt;
-      &lt;slave_if_data_width&gt;32&lt;/slave_if_data_width&gt;
-      &lt;multi_ported&gt;false&lt;/multi_ported&gt;
-      &lt;vn_external&gt;none&lt;/vn_external&gt;
-      &lt;vid_width&gt;4&lt;/vid_width&gt;
-      &lt;apb_config&gt;false&lt;/apb_config&gt;
-      &lt;qv_out&gt;false&lt;/qv_out&gt;
-      &lt;master_if_addr_width&gt;32&lt;/master_if_addr_width&gt;
-      &lt;clock_domain_name_slave_if&gt;clk_s&lt;/clock_domain_name_slave_if&gt;
-      &lt;clock_domain_name_master_if&gt;clk_m&lt;/clock_domain_name_master_if&gt;
-      &lt;protocol&gt;axi4&lt;/protocol&gt;
-      &lt;dest_type&gt;peripheral&lt;/dest_type&gt;
-      &lt;name&gt;M1_m&lt;/name&gt;
-      &lt;vn_external_bridge&gt;none&lt;/vn_external_bridge&gt;
-      &lt;trustzone&gt;nsec&lt;/trustzone&gt;
-      &lt;slave_if_port_name&gt;M1_m_s&lt;/slave_if_port_name&gt;
-      &lt;clock_boundary&gt;async&lt;/clock_boundary&gt;
-      &lt;master_if_data_width&gt;32&lt;/master_if_data_width&gt;
-      &lt;reg&gt;
-         &lt;type&gt;rev&lt;/type&gt;
-         &lt;impl&gt;present&lt;/impl&gt;
-         &lt;name&gt;aw&lt;/name&gt;
-         &lt;location&gt;slave_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;rev&lt;/type&gt;
-         &lt;impl&gt;present&lt;/impl&gt;
-         &lt;name&gt;w&lt;/name&gt;
-         &lt;location&gt;slave_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;rev&lt;/type&gt;
-         &lt;impl&gt;present&lt;/impl&gt;
-         &lt;name&gt;ar&lt;/name&gt;
-         &lt;location&gt;slave_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;b&lt;/name&gt;
-         &lt;location&gt;slave_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;r&lt;/name&gt;
-         &lt;location&gt;slave_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;aw&lt;/name&gt;
-         &lt;location&gt;master_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;w&lt;/name&gt;
-         &lt;location&gt;master_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;ar&lt;/name&gt;
-         &lt;location&gt;master_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;b&lt;/name&gt;
-         &lt;location&gt;master_port&lt;/location&gt;
-      &lt;/reg&gt;
-      &lt;reg&gt;
-         &lt;type&gt;fwd&lt;/type&gt;
-         &lt;impl&gt;absent&lt;/impl&gt;
-         &lt;name&gt;r&lt;/name&gt;
-         &lt;location&gt;master_port&lt;/location&gt;
-      &lt;/reg&gt;
-   &lt;/amib&gt;
-   &lt;connect&gt;
-      &lt;ruser&gt;false&lt;/ruser&gt;
-      &lt;wuser&gt;false&lt;/wuser&gt;
-      &lt;src&gt;M1_m&lt;/src&gt;
-      &lt;awuser&gt;false&lt;/awuser&gt;
-      &lt;out_trans&gt;16&lt;/out_trans&gt;
-      &lt;dest&gt;external&lt;/dest&gt;
-      &lt;src_port&gt;M1_m_m&lt;/src_port&gt;
-      &lt;protocol&gt;axi4&lt;/protocol&gt;
-      &lt;buser&gt;false&lt;/buser&gt;
-      &lt;out_reads&gt;16&lt;/out_reads&gt;
-      &lt;lock&gt;false&lt;/lock&gt;
-      &lt;out_writes&gt;16&lt;/out_writes&gt;
-      &lt;dest_port&gt;M1_m_m&lt;/dest_port&gt;
-      &lt;aruser&gt;false&lt;/aruser&gt;
-   &lt;/connect&gt;
-   &lt;connect&gt;
-      &lt;ruser&gt;false&lt;/ruser&gt;
-      &lt;wuser&gt;false&lt;/wuser&gt;
-      &lt;src&gt;external&lt;/src&gt;
-      &lt;awuser&gt;false&lt;/awuser&gt;
-      &lt;out_trans&gt;32&lt;/out_trans&gt;
-      &lt;dest&gt;M1_m&lt;/dest&gt;
-      &lt;src_port&gt;M1_m_s&lt;/src_port&gt;
-      &lt;protocol&gt;axi4&lt;/protocol&gt;
-      &lt;buser&gt;false&lt;/buser&gt;
-      &lt;out_reads&gt;16&lt;/out_reads&gt;
-      &lt;lock&gt;false&lt;/lock&gt;
-      &lt;out_writes&gt;16&lt;/out_writes&gt;
-      &lt;dest_port&gt;M1_m_s&lt;/dest_port&gt;
-      &lt;aruser&gt;false&lt;/aruser&gt;
-   &lt;/connect&gt;
-&lt;/periph&gt;
-</NICConfigFile>
-  </Architecture>
+  <Architecture/>
   <Deliverables>
     <IPXACT/>
     <RTL/>
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
index ddeadc2..3b108f6 100644
--- a/verif/cocotb/sram_chiplet_tests.py
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -60,6 +60,26 @@ class TB:
         for i in range(cycle):
             await RisingEdge(self.dut.clk_in)
 
+async def init_sram(dut, tb, base_addr, size=0x8000):
+    data = bytearray([0]*2048)
+    for offset in range(0, size-0x800, 0x800):
+        await tb.axi_master.write(base_addr+offset, data)
+    await RisingEdge(dut.clk_in)
+   
+async def SRAM_test_write(dut, tb, base_addr, byte_lanes, size):
+    for length in list(range(1, byte_lanes*2))+[8192]:
+        for offset in list(range(byte_lanes))+list(range(8192-byte_lanes, 8192)):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset + base_addr
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await tb.axi_master.write(addr, test_data, size=size)
+            data = await tb.axi_master.read(addr, length)
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk_in)
+    await RisingEdge(dut.clk_in)
+ 
 @cocotb.test()
 async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
     tb = TB(dut)
@@ -72,5 +92,6 @@ async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=Non
     await tb.cycle_reset()
     tb.set_idle_generator(idle_inserter)
     tb.set_backpressure_generator(backpressure_inserter)
-    data = bytearray([0]*2048)
-    await tb.axi_master.write(0x00000000, data)
+    await init_sram(dut, tb, 0x00000000)
+    await init_sram(dut, tb, 0x1F0000 - 0x8000, size=0x8000)
+    await SRAM_test_write(dut, tb, 0x0, byte_lanes, size)
-- 
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