From 4e9b15bea7598cfe239b919a2113217838e38b23 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 10 Sep 2024 16:06:57 +0100
Subject: [PATCH] Update ASIC flow, make SRAM 1MB, add clocks for asynchronous
interfaces
---
.gitignore | 4 +-
.../Synopsys_FC_flow/FC_flow.tcl | 54 ++-
.../Synopsys_FC_flow/design_setup.tcl | 2 +-
.../Synopsys_FC_flow/floorplan/floorplan.def | 4 +-
.../Synopsys_FC_flow/floorplan/floorplan.tcl | 2 +-
.../floorplan/floorplan_compare_data.txt | 203 +++++------
.../Synopsys_FC_flow/floorplan/fp.tcl | 40 +--
.../Synopsys_FC_flow/init_placement.tcl | 4 +-
.../synopsys_lib_conversion.tcl | 69 +++-
.../constraints/sram_chiplet.sdc | 23 +-
flist/IP/NIC400.flist | 48 ++-
flist/Top/sram_chiplet.flist | 1 +
flist/Top/sram_chiplet_TSMC28nm.flist | 1 +
flist/Top/sram_chiplet_TSMC28nm_ASIC.flist | 1 +
flist/Top/sram_chiplet_vip.flist | 4 +-
logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v | 29 +-
.../SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v | 6 +-
logical/SRAM/glib/verilog/SRAM.v | 12 +-
logical/SRAM/glib/verilog/SRAM_wrapper.v | 6 +-
.../verilog/sram_chiplet_apb_subsystem.v | 60 +++-
.../verilog/synchr_clock_mux.v | 56 +++
.../verilog/top_sram_chiplet.sv | 46 ++-
pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv | 38 +-
socrates/BP301_SRAM/config/SRAM_ctrl.yaml | 2 +-
.../nic400_sram_chiplet.xml | 127 ++++---
socrates/nic400_tb/nic400_tb.xml | 4 +-
synopsys_28nm_slm_integration | 2 +-
verif/cocotb/sram_chiplet_cocotb.sv | 327 ++++--------------
verif/cocotb/sram_chiplet_tests.py | 100 ++++--
29 files changed, 734 insertions(+), 541 deletions(-)
create mode 100644 logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
diff --git a/.gitignore b/.gitignore
index 3fbd165..7a28c76 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,11 +5,13 @@ ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/cln28ht
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/.*
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/HDL_LIBRARIES
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/PreFrameCheck
-ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram_32k
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram_16k
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram_chiplet.dlib
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_PD
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_PLL
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_TS
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/Synopsys_VM
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.svf
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.log
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/*.txt
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
index f9f2f84..14f6938 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
@@ -1,16 +1,52 @@
+# Main flow for Synopsys fusion compiler
-source ./design_setup.tcl
+set REPORT_DIR $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/reports
+set LOG_DIR $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/logs
-source ./floorplan/fp.tcl
-read_sdc ../constraints/sram_chiplet.sdc
+# Design setup: read libraries and RTL
+redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
-source ./power_plan.tcl
+# Floorplan setup
+redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1695 1530} -core_offset {120}}
+redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
-source ./init_placement.tcl
+# Read Constraints
+redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../constraints/sram_chiplet.sdc}
-redirect -tee -file ./compile.log {compile_fusion}
+# Power Plan
+redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
+
+# Init coarse placement
+redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
+
+# Physical aware synthesis
+redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
+save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
+
+
+# Optimise Placement
+redirect -tee -file $LOG_DIR/09_place_opt.log {place_opt}
+save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_02_opt_place.rep {report_timing}
+
+# CTS
+redirect -tee -file $LOG_DIR/08_CTS.log {synthesize_clock_trees -clock {PLL_CLK REF_CLK TLX_IN_FWD_CLK TLX_OUT_REV_CLK}}
save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_03_CTS.rep {report_timing}
-synthesize_clock_trunks -clock clk
-place_opt
-clock_opt
+# Clock Optimisation
+redirect -tee -file $LOG_DIR/10_clock_opt.log {clock_opt}
+save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_04_clock_opt.rep {report_timing}
+
+
+# Route
+redirect -tee -file $LOG_DIR/11_route.log {route_auto}
+save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_05_route.rep {report_timing}
+
+# Route optimisation
+redirect -tee -file $LOG_DIR/12_route_optimisation.log {optimize_routes}
+save_lib sram_chiplet.dlib
+redirect -tee -file $REPORT_DIR/timing_06_route_opt.rep {report_timing}
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
index a672393..4f70550 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
@@ -13,7 +13,7 @@ set TLU_map $TLU_dir/tluplus.map
create_lib sram_chiplet.dlib \
-technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf \
- -ref_libs {./cln28ht/ ./sram/ ./Synopsys_PLL/ ./Synopsys_PD/ ./Synopsys_TS/}
+ -ref_libs {./cln28ht/ ./sram_16k/ ./sram_32k/ ./Synopsys_PLL/ ./Synopsys_PD/ ./Synopsys_TS/ ./Synopsys_VM/}
source $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/flist/synopsys_flist.tcl
analyze -format sverilog $env(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
index 6ef2e9d..da438bf 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
@@ -2,12 +2,12 @@
# Fusion Compiler write_def
# Release : U-2022.12
# User Name : dwn1c21
-# Date : Tue Sep 3 14:17:43 2024
+# Date : Thu Sep 5 11:23:09 2024
#
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN SRAM_chiplet ;
UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 0 1529700 ) ( 1789940 1529700 ) ( 1789940 0 ) ;
+DIEAREA ( 0 0 ) ( 0 1529700 ) ( 1694880 1529700 ) ( 1694880 0 ) ;
END DESIGN
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
index 6f35619..1bf66cf 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
@@ -1,6 +1,6 @@
################################################################################
#
-# Created by fc write_floorplan on Tue Sep 3 14:17:43 2024
+# Created by fc write_floorplan on Thu Sep 5 11:23:09 2024
#
################################################################################
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
index eeb6c76..e3843c9 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
@@ -1,6 +1,6 @@
################################################################################
#
-# Created by fc compare_floorplans on Tue Sep 3 14:17:43 2024
+# Created by fc compare_floorplans on Thu Sep 5 11:23:09 2024
#
# DO NOT EDIT - automatically generated file
#
@@ -11,105 +11,106 @@ START SRAM_chiplet
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts { {120.0000 390.0600} {360.0000 590.0600} }
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd { {120.0000 618.3400} {205.0000 693.3400} }
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL { {120.0000 120.0000} {382.5000 360.0000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k { {387.3000 770.0650} {707.9600 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k { {707.9600 770.0650} {1028.6200 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k { {1028.6200 770.0650} {1349.2800 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k { {1349.2800 770.0650} {1669.9400 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k { {1349.2800 120.0000} {1669.9400 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k { {1028.6200 120.0000} {1349.2800 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k { {707.9600 120.0000} {1028.6200 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k { {387.3000 120.0000} {707.9600 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k { {120.0600 770.0650} {440.7200 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k { {440.7200 770.0650} {761.3800 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k { {761.3800 770.0650} {1082.0400 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k { {1082.0400 770.0650} {1402.7000 1409.7000} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k { {1082.0400 120.0000} {1402.7000 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k { {761.3800 120.0000} {1082.0400 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k { {440.7200 120.0000} {761.3800 759.6350} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_0 { {1402.7000 120.0000} {1574.8800 758.0750} }
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_1 { {1402.7000 771.6250} {1574.8800 1409.7000} }
PINS
- clk_in { {894.9700 764.8500} {894.9701 764.8501} }
- aresetn { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_rev_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_rev_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_rev_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_rev_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_rev_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_rev_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_fwd_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_fwd_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_fwd_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_flow_fwd_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_IN_data_fwd_0_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_rev_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_rev_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_rev_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_rev_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_rev_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_rev_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_fwd_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_fwd_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_fwd_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_flow_fwd_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[15] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[14] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[13] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[12] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[11] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[10] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[9] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[8] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[7] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[6] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[5] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[4] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[3] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[2] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[1] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tdata[0] { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tvalid { {894.9700 764.8500} {894.9701 764.8501} }
- TLX_data_fwd_1_tready { {894.9700 764.8500} {894.9701 764.8501} }
+ clk_in { {847.4400 764.8500} {847.4401 764.8501} }
+ aresetn { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_rev_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_rev_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_rev_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_rev_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_rev_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_rev_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_fwd_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_fwd_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_fwd_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_flow_fwd_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_IN_data_fwd_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_rev_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_rev_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_rev_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_rev_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_rev_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_rev_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_fwd_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_fwd_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_fwd_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_flow_fwd_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
+ TLX_data_fwd_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
END SRAM_chiplet
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
index d30045d..8319320 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
@@ -1,9 +1,8 @@
################################################################################
#
-# Created by fc write_floorplan on Tue Sep 3 14:17:43 2024
+# Created by fc write_floorplan on Thu Sep 5 11:23:09 2024
#
################################################################################
-initialize_floorplan -control_type die -use_site_row -side_length {1790 1530} -core_offset {120}
set _dirName__0 [file dirname [file normalize [info script]]]
@@ -45,7 +44,7 @@ set_attribute -quiet -objects $cellInst -name status -value placed
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 707.9600 770.0650 \
+set_attribute -quiet -objects $cellInst -name origin -value { 440.7200 770.0650 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
@@ -58,8 +57,8 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1028.6200 \
- 770.0650 }
+set_attribute -quiet -objects $cellInst -name origin -value { 761.3800 770.0650 \
+ }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
@@ -71,7 +70,7 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1349.2800 \
+set_attribute -quiet -objects $cellInst -name origin -value { 1082.0400 \
770.0650 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
@@ -84,7 +83,7 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1669.9400 \
+set_attribute -quiet -objects $cellInst -name origin -value { 1402.7000 \
770.0650 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
@@ -97,7 +96,7 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 1349.2800 \
+set_attribute -quiet -objects $cellInst -name origin -value { 1082.0400 \
759.6350 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
@@ -110,8 +109,8 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 1028.6200 \
- 759.6350 }
+set_attribute -quiet -objects $cellInst -name origin -value { 761.3800 759.6350 \
+ }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
@@ -123,7 +122,7 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
set cellInst [get_cells { \
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 707.9600 759.6350 \
+set_attribute -quiet -objects $cellInst -name origin -value { 440.7200 759.6350 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
@@ -134,17 +133,18 @@ create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } {
u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_0 }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 387.3000 759.6350 \
- }
+set_attribute -quiet -objects $cellInst -name origin -value { 1402.7000 \
+ 758.0750 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_1 }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1574.8800 \
+ 771.6250 }
set_attribute -quiet -objects $cellInst -name status -value placed
-create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
-create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
-create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[7].u_sram_32b_32k }
################################################################################
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
index b3749f8..cbb777b 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
@@ -1,5 +1,7 @@
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library sram_chiplet.dlib
-set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ssg_cworstt_max_0p81v_125c
+set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
+set_temperature -40 -min 125 -corners default
+set_voltage 0.99 -min 0.81 -corners default
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
index b053c7f..d379fd0 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
@@ -16,12 +16,21 @@ set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2
set sram_32k_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.lef
set sram_32k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.gds2
set sram_32k_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.lib
-set sram_32k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_32k_lib_file_tt_0p90v_25c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_tt_ctypical_0p90v_0p90v_25c.lib
+set sram_32k_lib_file_ff_0p99v_m40c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c.lib
+set sram_32k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_32k_db_file_tt_0p90v_25c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_tt_ctypical_0p90v_0p90v_25c.db
+set sram_32k_db_file_ff_0p99v_m40c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c.db
+
set sram_16k_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.lef
set sram_16k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.gds2
set sram_16k_lib_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c.lib
+set sram_16k_lib_file_tt_0p90v_25c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_tt_ctypical_0p90v_0p90v_25c.lib
+set sram_16k_lib_file_ff_0p99v_m40c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c.lib
set sram_16k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c.db
+set sram_16k_db_file_tt_0p90v_25c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_tt_ctypical_0p90v_0p90v_25c.db
+set sram_16k_db_file_ff_0p99v_m40c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c.db
# Synopsys PLL files
@@ -44,23 +53,58 @@ set Synopsys_PD_lib_file $Synopsys_PD_dir/liberty/mr74125_wc_vmin_125c.lib
set Synopsys_PD_db_file $Synopsys_PD_dir/db/mr74125_wc_vmin_125c.db
set Synopsys_PD_gds_file $Synopsys_PD_dir/gds/mr74125_v1r2.gds
+# Synopsys Voltage Monitor files
+set Synopsys_VM_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_vm_shrink_tsmc28hpcp_1.00a/synopsys/dwc_sensors_vm_shrink_tsmc28hpcp/1.00a
+set Synopsys_VM_lef_file $Synopsys_VM_dir/lef/mr74140.lef
+set Synopsys_VM_lib_file $Synopsys_VM_dir/liberty/mr74140_wc_vmin_125c.lib
+set Synopsys_VM_db_file $Synopsys_VM_dir/db/mr74140_wc_vmin_125c.db
+set Synopsys_VM_gds_file $Synopsys_VM_dir/gdsii/mr74140_v1r1.gds
create_fusion_lib -dbs [list $sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $sc9mcpp140z_lef_file] -technology $cln28ht_tech_file cln28ht
save_fusion_lib cln28ht
close_fusion_lib cln28ht
-read_lib $sram_lib_file
-write_lib -output $sram_db_file -format db sram_sp_hde_ssg_cworstt_0p81v_0p81v_125c
-close_lib sram_sp_hde_ssg_cworstt_0p81v_0p81v_125c
-create_fusion_lib -dbs $sram_db_file -lefs $sram_lef_file -technology $cln28ht_tech_file sram
-save_fusion_lib sram
-close_fusion_lib sram
+# 32K SRAM
+read_lib $sram_32k_lib_file_ss_0p81v_125c
+write_lib -output $sram_32k_db_file_ss_0p81v_125c -format db sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c
+close_lib sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c
+
+read_lib $sram_32k_lib_file_tt_0p90v_25c
+write_lib -output $sram_32k_db_file_tt_0p90v_25c -format db sram_32b_32k_tt_ctypical_0p90v_0p90v_25c
+close_lib sram_32b_32k_tt_ctypical_0p90v_0p90v_25c
+
+read_lib $sram_32k_lib_file_ff_0p99v_m40c
+write_lib -output $sram_32k_db_file_ff_0p99v_m40c -format db sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c
+close_lib sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c
+
+create_fusion_lib -dbs [list $sram_32k_db_file_ss_0p81v_125c $sram_32k_db_file_tt_0p90v_25c $sram_32k_db_file_ff_0p99v_m40c] -lefs $sram_32k_lef_file -technology $cln28ht_tech_file sram_32k
+save_fusion_lib sram_32k
+close_fusion_lib sram_32k
+
+# 16K SRAM
+read_lib $sram_16k_lib_file_ss_0p81v_125c
+write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c
+close_lib sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c
+
+read_lib $sram_16k_lib_file_tt_0p90v_25c
+write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db sram_32b_16k_tt_ctypical_0p90v_0p90v_25c
+close_lib sram_32b_16k_tt_ctypical_0p90v_0p90v_25c
+read_lib $sram_16k_lib_file_ff_0p99v_m40c
+write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c
+close_lib sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c
+
+create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
+save_fusion_lib sram_16k
+close_fusion_lib sram_16k
+
+# Synopsys PLL
create_fusion_lib -dbs $Synopsys_PLL_db_file -lefs $Synopsys_PLL_lef_file -technology $cln28ht_tech_file Synopsys_PLL
save_fusion_lib Synopsys_PLL
close_fusion_lib Synopsys_PLL
+# Synopsys TS
read_lib $Synopsys_TS_lib_file
write_lib -output $Synopsys_TS_db_file -format db mr74127_wc_vmin_125c
close_lib -all
@@ -68,9 +112,20 @@ create_fusion_lib -dbs $Synopsys_TS_db_file -lefs $Synopsys_TS_lef_file -technol
save_fusion_lib Synopsys_TS
close_fusion_lib Synopsys_TS
+# Synopsys PD
read_lib $Synopsys_PD_lib_file
write_lib -output $Synopsys_PD_db_file -format db mr74125_wc_vmin_125c
close_lib -all
create_fusion_lib -dbs $Synopsys_PD_db_file -lefs $Synopsys_PD_lef_file -technology $cln28ht_tech_file Synopsys_PD
save_fusion_lib Synopsys_PD
close_fusion_lib Synopsys_PD
+
+# Synopsys VM
+read_lib $Synopsys_VM_lib_file
+write_lib -output $Synopsys_VM_db_file -format db mr74140_wc_vmin_125c
+close_lib -all
+create_fusion_lib -dbs $Synopsys_VM_db_file -lefs $Synopsys_VM_lef_file -technology $cln28ht_tech_file Synopsys_VM
+save_fusion_lib Synopsys_VM
+close_fusion_lib Synopsys_VM
+
+exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
index 4e60e01..4b2202f 100644
--- a/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
+++ b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
@@ -1,5 +1,5 @@
#-----------------------------------------------------------------------------
-# NanoSoC Constraints for Synthesis
+# SRAM Chiplet constraints for ASIC
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
@@ -11,12 +11,23 @@
#### CLOCK DEFINITION
-set EXTCLK "clk";
-set_units -time ns;
+set REF_CLK "REF_CLK";
+set TLX_IN_FWD_CLK "TLX_IN_FWD_CLK"
+set TLX_OUT_REV_CLK "TLX_OUT_REV_CLK"
+set SYS_CLK "PLL_CLK"
+set_units -time ns;
set_units -capacitance pF;
-set EXTCLK_PERIOD 1;
-set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
+
+set REF_CLK_PERIOD 4;
+set TLX_IN_FWD_CLK_PERIOD 1;
+set TLX_OUT_REV_CLK_PERIOD 1;
+set SYS_CLK_PERIOD 1;
+
+set CLK_ERROR 0.35;
set INTER_CLOCK_UNCERTAINTY 0.1
-create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 0.5" [get_ports clk_in]
+create_clock -name "$REF_CLK" -period "$REF_CLK_PERIOD" [get_ports REF_CLK]
+create_clock -name "$TLX_IN_FWD_CLK" -period "$TLX_IN_FWD_CLK_PERIOD" [get_ports IN_FWD_CLK]
+create_clock -name "$TLX_OUT_REV_CLK" -period "$TLX_OUT_REV_CLK_PERIOD" [get_ports OUT_REV_CLK]
+create_generated_clock -name "$SYS_CLK" -source [get_ports REF_CLK] -multiply_by 4 [get_pins u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/PLL_CLK1]
\ No newline at end of file
diff --git a/flist/IP/NIC400.flist b/flist/IP/NIC400.flist
index fa0c1bc..5fdd066 100644
--- a/flist/IP/NIC400.flist
+++ b/flist/IP/NIC400.flist
@@ -1,11 +1,13 @@
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi4PC
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/ApbPC
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Apb4PC
@@ -19,9 +21,10 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog/nic400_amib_AXI_TLX_OUT_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_axi_to_itb_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.verilog
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog/nic400_apb_bridge_master_domain_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog/nic400_apb_bridge_slave_domain_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_chan_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_decode_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_maskcntl_sram_chiplet.v
@@ -45,7 +48,6 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_3_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_sram_chiplet.v
@@ -57,7 +59,43 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml3_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_bypass_sync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_nosync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_sync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_and2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_mux2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_or2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_or3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_gry_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_data_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_gry_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_random_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog/nic400_default_slave_ds_1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_rd_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_sync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_cdc_air_corrupt_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_rd_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_sync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_rd_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_sync_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_sram_chiplet.v
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_cd_clk0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_cd_ref_sram_chiplet.v
+
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ax4_reg_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_buf_reg_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_sram_chiplet.v
diff --git a/flist/Top/sram_chiplet.flist b/flist/Top/sram_chiplet.flist
index 258ec16..c14ebad 100644
--- a/flist/Top/sram_chiplet.flist
+++ b/flist/Top/sram_chiplet.flist
@@ -23,6 +23,7 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
index 83f5ae7..71955c9 100644
--- a/flist/Top/sram_chiplet_TSMC28nm.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -27,6 +27,7 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_emulation.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
index 59c67af..ec6f82a 100644
--- a/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
@@ -25,6 +25,7 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_vip.flist b/flist/Top/sram_chiplet_vip.flist
index a5803cc..6dcf50b 100644
--- a/flist/Top/sram_chiplet_vip.flist
+++ b/flist/Top/sram_chiplet_vip.flist
@@ -2,4 +2,6 @@
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/VIP/NIC400_tb.flist
-
+$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/axi_stream_io/verilog/axi_stream_io.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/f232h_ft1248_stream/verilog/f232h_ft1248_stream.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/socdebug_tech/socket/f232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
index 6f82eb4..6f5ce6d 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
@@ -2,7 +2,7 @@
module SRAM (
input wire clk,
- input wire [20:0] memaddr,
+ input wire [19:0] memaddr,
input wire [31:0] memd,
output reg [31:0] memq,
input wire memcen,
@@ -44,7 +44,7 @@ sram_32b_16k u_sram_32b_16k_0(
.CLK(clk),
.CEN(CEN_i[N_MEMS-1]),
.GWEN(gwen_i),
- .A(memaddr[16:2]),
+ .A(memaddr[15:2]),
.D(memd),
.WEN(wena_i),
.STOV(1'b0),
@@ -53,12 +53,12 @@ sram_32b_16k u_sram_32b_16k_0(
.EMAS(1'b0),
.RET1N(1'b1)
);
-sram_32b_16k u_sram_32b_16k_0(
+sram_32b_16k u_sram_32b_16k_1(
.Q(q_i[N_MEMS]),
.CLK(clk),
.CEN(CEN_i[N_MEMS]),
.GWEN(gwen_i),
- .A(memaddr[16:2]),
+ .A(memaddr[15:2]),
.D(memd),
.WEN(wena_i),
.STOV(1'b0),
@@ -70,13 +70,30 @@ sram_32b_16k u_sram_32b_16k_0(
integer j;
always @(*) begin
- for(j=0; j<N_MEMS; j=j+1) begin
+ for(j=0; j<N_MEMS-1; j=j+1) begin
if(j==memaddr[(SEL_W+17-1):17])
CEN_i[j] = memcen;
else
CEN_i[j] = 1'b1;
end
- memq = q_i[memaddr[(SEL_W+17-1):17]];
+ if(memaddr[SEL_W+16:17]==3'h7) begin
+ if(memaddr[16]==1'b0) begin
+ CEN_i[N_MEMS-1]=memcen;
+ CEN_i[N_MEMS]=1'b1;
+ end
+ else begin
+ CEN_i[N_MEMS]=memcen;
+ CEN_i[N_MEMS-1]=1'b1;
+ end
+ end else
+ CEN_i[N_MEMS:N_MEMS-1]=2'b11;
+ if(memaddr[19:17]==3'h7) begin
+ if(memaddr[16]==1'b1)
+ memq=q_i[N_MEMS];
+ else
+ memq=q_i[N_MEMS-1];
+ end else
+ memq = q_i[memaddr[(SEL_W+17-1):17]];
end
endmodule
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
index b5bc425..9e41377 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
@@ -76,7 +76,7 @@ module SRAM_wrapper(
);
-wire [20:0] memaddr;
+wire [19:0] memaddr;
wire [31:0] memd;
wire [31:0] memq;
wire memcen;
@@ -88,7 +88,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.awvalid_s(AWVALID),
.awready_s(AWREADY),
.awid_s(AWID),
- .awaddr_s(AWADDR[20:0]),
+ .awaddr_s(AWADDR[19:0]),
.awlen_s(AWLEN),
.awsize_s(AWSIZE),
.awburst_s(AWBURST),
@@ -108,7 +108,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.arvalid_s(ARVALID),
.arready_s(ARREADY),
.arid_s(ARID),
- .araddr_s(ARADDR[20:0]),
+ .araddr_s(ARADDR[19:0]),
.arlen_s(ARLEN),
.arsize_s(ARSIZE),
.arburst_s(ARBURST),
diff --git a/logical/SRAM/glib/verilog/SRAM.v b/logical/SRAM/glib/verilog/SRAM.v
index a7ec6e0..d3474c4 100644
--- a/logical/SRAM/glib/verilog/SRAM.v
+++ b/logical/SRAM/glib/verilog/SRAM.v
@@ -2,13 +2,13 @@
module SRAM (
input wire clk,
- input wire [20:0] memaddr,
+ input wire [19:0] memaddr,
input wire [31:0] memd,
output wire [31:0] memq,
input wire memcen,
input wire [3:0] memwen
);
- parameter MEM_DEPTH = 253952;
+ parameter MEM_DEPTH = 262144;
wire WriteEnable; // Write data update
wire [17:0] Addr;
@@ -19,7 +19,7 @@ module SRAM (
integer i; // Write-strobe loop variable
integer j; // Mask-bit loop variable
- assign Addr = memaddr[20:2];
+ assign Addr = memaddr[19:2];
// -------------
// Memory arrays
// -------------
@@ -29,11 +29,11 @@ module SRAM (
assign WriteEnable = (memwen != {4{1'b1}}) ? 1'b1 : 1'b0;
`ifdef INITIALIZE_MEMORY
- integer i;
+ integer k;
initial begin
#0;
- for(i=0;i < MEM_DEPTH;i = i + 1)
- mem[i] = {32{1'b0}};
+ for(k=0;k < MEM_DEPTH;k = k + 1)
+ mem[k] = {32{1'b0}};
end
`endif
diff --git a/logical/SRAM/glib/verilog/SRAM_wrapper.v b/logical/SRAM/glib/verilog/SRAM_wrapper.v
index b5bc425..9e41377 100644
--- a/logical/SRAM/glib/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/glib/verilog/SRAM_wrapper.v
@@ -76,7 +76,7 @@ module SRAM_wrapper(
);
-wire [20:0] memaddr;
+wire [19:0] memaddr;
wire [31:0] memd;
wire [31:0] memq;
wire memcen;
@@ -88,7 +88,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.awvalid_s(AWVALID),
.awready_s(AWREADY),
.awid_s(AWID),
- .awaddr_s(AWADDR[20:0]),
+ .awaddr_s(AWADDR[19:0]),
.awlen_s(AWLEN),
.awsize_s(AWSIZE),
.awburst_s(AWBURST),
@@ -108,7 +108,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.arvalid_s(ARVALID),
.arready_s(ARREADY),
.arid_s(ARID),
- .araddr_s(ARADDR[20:0]),
+ .araddr_s(ARADDR[19:0]),
.arlen_s(ARLEN),
.arsize_s(ARSIZE),
.arburst_s(ARBURST),
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
index 566c48a..902b6b0 100644
--- a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+++ b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
@@ -1,9 +1,33 @@
+//-----------------------------------------------------------------------------
+// SRAM APB subsystem Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Takes as input a FT1248 interface from offchip and uses the soclabs ADP Controller
+// to control an AHB master. AHB to APB, then APB MUX
+//
+// Modules instantiated:
+// cmsdk_apb_slave_mux
+// synopsys_TS_sensor_integration
+// synopsys_PD_sensor_integration
+// synopsys_VM_sensor_integration
+// snps_PLL_integration_layer
+
module sram_chiplet_apb_subsystem(
input wire ref_clk,
- input wire PCLK,
input wire aRESETn,
+ output wire PLL_CLK1,
+ output wire PLL_CLK2,
+ output wire pll_lock,
+
+
input wire [31:0] PADDR_APB_PVT,
input wire [31:0] PWDATA_APB_PVT,
input wire PWRITE_APB_PVT,
@@ -152,7 +176,7 @@ cmsdk_apb_slave_mux #(
generate if(SNPS_PVT_TS_0_ENABLE==1)begin: gen_snps_PVT_ts0
synopsys_TS_sensor_integration u_snps_PVT_ts0(
- .PCLK(PCLK),
+ .PCLK(ref_clk),
.aRESETn(aRESETn),
.PSELx(snps_PVT_ts0_psel),
@@ -183,7 +207,7 @@ end endgenerate
generate if(SNPS_PVT_PD_0_ENABLE==1)begin: gen_snps_PVT_pd0
synopsys_PD_sensor_integration u_snps_PVT_pd0(
- .PCLK(PCLK),
+ .PCLK(ref_clk),
.aRESETn(aRESETn),
.PSELx(snps_PVT_pd0_psel),
.PADDR(PADDR_APB_PVT[3:2]),
@@ -214,6 +238,9 @@ end else begin: gen_no_snps_PVT_vm0
assign irq_vm_rdy = 1'b0;
end endgenerate
+wire pll_clk1_i;
+wire pll_clk2_i;
+
generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
snps_PLL_integration_layer #(
.DEFAULT_FBDIV(7'h08), // Multiply by 8 (250*8 = 2 GHz)
@@ -223,12 +250,12 @@ generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
.DEFAULT_R(6'h07), // Divier = 8 (out 250 MHz)
.DEFAULT_PREDIV(5'h00) // Pre div = 2 (250/1 = 250 MHz)
) u_snps_PLL(
- .ref_clk(PCLK),
+ .ref_clk(ref_clk),
.resetn(aRESETn),
- .pll_lock(),
+ .pll_lock(pll_lock),
- .out_clk1(),
- .out_clk2(),
+ .out_clk1(pll_clk1_i),
+ .out_clk2(pll_clk2_i),
.PSELx(snps_PLL_psel),
.PADDR(PADDR_APB_PVT[11:2]),
@@ -241,11 +268,30 @@ generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
.PREADY(snps_PLL_pready),
.PSLVERR(snps_PLL_pslverr)
);
+
end else begin: gen_no_snps_PLL
assign snps_PLL_prdata = {32{1'b0}};
assign snps_PLL_pready = 1'b1;
assign snps_PLL_pslverr = 1'b1;
+ assign pll_lock = 1'b0;
end endgenerate
+synchr_clock_mux u_sync_clock_mux_1(
+ .aresetn(aRESETn),
+ .clk_1(ref_clk),
+ .clk_2(pll_clk1_i),
+ .sel(pll_lock),
+ .out_clk(PLL_CLK1)
+);
+
+synchr_clock_mux u_sync_clock_mux_2(
+ .aresetn(aRESETn),
+ .clk_1(ref_clk),
+ .clk_2(pll_clk2_i),
+ .sel(pll_lock),
+ .out_clk(PLL_CLK2)
+);
+
+
endmodule
\ No newline at end of file
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v b/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
new file mode 100644
index 0000000..aa53d8c
--- /dev/null
+++ b/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
@@ -0,0 +1,56 @@
+
+module synchr_clock_mux(
+ input wire aresetn,
+ input wire clk_1,
+ input wire clk_2,
+ input wire sel,
+ output wire out_clk
+);
+
+
+wire i_and1;
+wire i_and2;
+wire o_and1;
+wire o_and2;
+
+reg [1:0] sync_clk1;
+reg [1:0] sync_clk2;
+
+assign i_and1 = (~sel) & (~sync_clk2[1]);
+assign i_and2 = sel & (~sync_clk1[1]);
+assign o_and1 = sync_clk1[1] & clk_1;
+assign o_and2 = sync_clk2[1] & clk_2;
+
+always @(posedge clk_1 or negedge aresetn) begin
+ if(~aresetn)
+ sync_clk1[0] <= 1'b1;
+ else
+ sync_clk1[0] <= i_and1;
+end
+
+always @(negedge clk_1 or negedge aresetn) begin
+ if(~aresetn)
+ sync_clk1[1]<= 1'b1;
+ else
+ sync_clk1[1] <= sync_clk1[0];
+end
+
+always @(posedge clk_2 or negedge aresetn) begin
+ if(~aresetn)
+ sync_clk2[0] <= 1'b0;
+ else
+ sync_clk2[0] <= i_and2;
+end
+
+
+always @(negedge clk_2 or negedge aresetn) begin
+ if(~aresetn)
+ sync_clk2[1] <= 1'b0;
+ else
+ sync_clk2[1] <= sync_clk2[0];
+end
+
+assign out_clk = o_and1 | o_and2;
+
+
+endmodule
\ No newline at end of file
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
index 34510f4..2ad8a5c 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
@@ -17,13 +17,21 @@
`include "tlx_interfaces.sv"
-module top_sram_chiplet(
+module top_sram_chiplet #(
+ parameter N_ADDR_SEL_BITS = 6
+ )(
// Clock and reset
- input wire SYS_CLK,
- input wire DL_FWD_CLK,
- output wire DL_REV_CLK,
+ input wire REF_CLK,
input wire aRESETn,
input wire DL_FWD_RESETn,
+ input wire IN_FWD_CLK,
+ output wire IN_REV_CLK,
+ output wire OUT_FWD_CLK,
+ input wire OUT_REV_CLK,
+ output wire OUT_CLK,
+ output wire PLL_LOCK_o,
+ input wire PLL_LOCK_i,
+
// Thin links interface Input
TLX_AXI_stream.out TLX_IN_data_rev,
TLX_AXI_stream.out TLX_IN_flow_rev,
@@ -36,15 +44,14 @@ module top_sram_chiplet(
TLX_AXI_stream.out TLX_OUT_flow_fwd,
TLX_AXI_stream.out TLX_OUT_data_fwd,
- // FT1248
-
-
// Address Select pins
- input wire [2:0] addr_sel
+ input wire [N_ADDR_SEL_BITS-1:0] addr_sel
);
+wire SYS_CLK;
+
// Main Bus Wires
// - SRAM AXI wires
wire [3:0] AWID_AXI_SRAM;
@@ -195,6 +202,8 @@ nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet u_cd_pl_rev_M1_m_tlx(
.pl_rev_M1_m_tlxresetn(aRESETn)
);
+assign IN_REV_CLK = SYS_CLK;
+assign OUT_FWD_CLK = SYS_CLK;
nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
// AXI manager power
.awid_m1_m_m(AWID_AXI_CHIPLET_IN),
@@ -257,7 +266,7 @@ nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
.clk_mclk(SYS_CLK),
.clk_mresetn(aRESETn),
// DL clock
- .dl_fwd_M1_m_tlxclk(DL_FWD_CLK),
+ .dl_fwd_M1_m_tlxclk(IN_FWD_CLK),
.dl_fwd_M1_m_tlxresetn(DL_FWD_RESETn)
);
@@ -265,8 +274,8 @@ nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
wire [31:0] AWADDR_AXI_CHIPLET_IN_i;
wire [31:0] ARADDR_AXI_CHIPLET_IN_i;
-assign AWADDR_AXI_CHIPLET_IN_i = (AWADDR_AXI_CHIPLET_IN[23:21]==addr_sel[2:0]) ? {11'h000,AWADDR_AXI_CHIPLET_IN[20:0]} : AWADDR_AXI_CHIPLET_IN;
-assign ARADDR_AXI_CHIPLET_IN_i = (ARADDR_AXI_CHIPLET_IN[23:21]==addr_sel[2:0]) ? {11'h000,ARADDR_AXI_CHIPLET_IN[20:0]} : ARADDR_AXI_CHIPLET_IN;
+assign AWADDR_AXI_CHIPLET_IN_i = (AWADDR_AXI_CHIPLET_IN[20+:N_ADDR_SEL_BITS]==addr_sel[0+:N_ADDR_SEL_BITS]) ? {AWADDR_AXI_CHIPLET_IN[31:(20+N_ADDR_SEL_BITS)],{N_ADDR_SEL_BITS{1'b0}},AWADDR_AXI_CHIPLET_IN[19:0]} : AWADDR_AXI_CHIPLET_IN;
+assign ARADDR_AXI_CHIPLET_IN_i = (ARADDR_AXI_CHIPLET_IN[20+:N_ADDR_SEL_BITS]==addr_sel[0+:N_ADDR_SEL_BITS]) ? {ARADDR_AXI_CHIPLET_IN[31:(20+N_ADDR_SEL_BITS)],{N_ADDR_SEL_BITS{1'b0}},ARADDR_AXI_CHIPLET_IN[19:0]} : ARADDR_AXI_CHIPLET_IN;
nic400_sram_chiplet u_nic400_sram_chiplet(
.AWID_AXI_SRAM(AWID_AXI_SRAM),
@@ -390,7 +399,10 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.clk0clk(SYS_CLK),
.clk0clken(1'b1),
- .clk0resetn(aRESETn)
+ .clk0resetn(aRESETn),
+ .refclk(SYS_CLK),
+ .refclken(1'b1),
+ .refresetn(aRESETn)
);
// Thin links output
@@ -457,7 +469,7 @@ nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
.clk_sclk(SYS_CLK),
.clk_sresetn(aRESETn),
- .dl_rev_M1_m_tlxclk(SYS_CLK),
+ .dl_rev_M1_m_tlxclk(OUT_REV_CLK),
.dl_rev_M1_m_tlxresetn(aRESETn)
);
@@ -487,9 +499,13 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
);
+wire PLL_LOCK;
sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
- .PCLK(SYS_CLK),
+ .ref_clk(REF_CLK),
+ .PLL_CLK1(SYS_CLK),
+ .PLL_CLK2(OUT_CLK),
.aRESETn(aRESETn),
+ .pll_lock(PLL_LOCK),
.PADDR_APB_PVT(PADDR_APB_PVT),
.PWDATA_APB_PVT(PWDATA_APB_PVT),
.PWRITE_APB_PVT(PWRITE_APB_PVT),
@@ -502,6 +518,8 @@ sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
.PREADY_APB_PVT(PREADY_APB_PVT)
);
+assign PLL_LOCK_o = PLL_LOCK & PLL_LOCK_i;
+
SRAM_wrapper u_SRAM_wrapper(
.ACLK(SYS_CLK),
.ARESETn(aRESETn),
diff --git a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
index e344f36..9ff678c 100644
--- a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
+++ b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
@@ -17,8 +17,16 @@ module SRAM_chiplet(
inout wire VDD,
inout wire VSS,
`endif
- input wire clk_in,
- input wire aresetn,
+ input wire REF_CLK,
+ input wire aRESETn,
+ input wire DL_FWD_RESETn,
+ input wire IN_FWD_CLK,
+ output wire IN_REV_CLK,
+ output wire OUT_FWD_CLK,
+ input wire OUT_REV_CLK,
+ output wire OUT_CLK,
+ output wire PLL_LOCK_o,
+ input wire PLL_LOCK_i,
// TLX_IN_data_rev_0 tlx out
output wire [15:0] TLX_IN_data_rev_0_tdata,
@@ -58,7 +66,9 @@ module SRAM_chiplet(
// tlx out
output wire [15:0] TLX_data_fwd_1_tdata,
output wire TLX_data_fwd_1_tvalid,
- input wire TLX_data_fwd_1_tready
+ input wire TLX_data_fwd_1_tready,
+
+ input wire [5:0] addr_sel
);
@@ -117,12 +127,17 @@ assign TLX_data_fwd_1.tready = TLX_data_fwd_1_tready;
top_sram_chiplet u_top_sram_chiplet(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
+ .REF_CLK(REF_CLK),
+ .aRESETn(aRESETn),
+ .DL_FWD_RESETn(DL_FWD_RESETn),
+
+ .IN_FWD_CLK(IN_FWD_CLK),
+ .IN_REV_CLK(IN_REV_CLK),
+ .OUT_FWD_CLK(OUT_FWD_CLK),
+ .OUT_REV_CLK(OUT_REV_CLK),
+ .OUT_CLK(OUT_CLK),
+ .PLL_LOCK_o(PLL_LOCK_o),
+ .PLL_LOCK_i(PLL_LOCK_i),
// Thin Links In
.TLX_IN_data_rev(TLX_IN_data_rev_0),
@@ -135,11 +150,8 @@ top_sram_chiplet u_top_sram_chiplet(
.TLX_OUT_flow_fwd(TLX_flow_fwd_1),
.TLX_OUT_data_fwd(TLX_data_fwd_1),
- // FT1248
-
-
// Address Select pins
- .addr_sel(3'b000)
+ .addr_sel(addr_sel)
);
endmodule
\ No newline at end of file
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index ec3ef9f..b539c5e 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -49,7 +49,7 @@ CONFIG_NAME: sram_chiplet
# ADDR_WIDTH: AXI5 Address Bus width
# Valid values:
# 14-24
-ADDR_WIDTH: 21
+ADDR_WIDTH: 20
#
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index b34056c..aba6940 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -44,15 +44,27 @@
<ClockDomainType>physical</ClockDomainType>
<PowerDomainRef>pd0</PowerDomainRef>
</ClockDomain>
+ <ClockDomain>
+ <Name>ref</Name>
+ <ClockDomainType>physical</ClockDomainType>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
</ClockDomains>
- <ClockRelations/>
+ <ClockRelations>
+ <ClockRelation>
+ <ClockRef1>ref</ClockRef1>
+ <ClockRef2>clk0</ClockRef2>
+ <Relationship>asynchronous</Relationship>
+ <Programmable>false</Programmable>
+ </ClockRelation>
+ </ClockRelations>
</Domains>
<Groups>
<ExternalGroups/>
<APBGroups>
<APBGroup>
<Name>apb_group0</Name>
- <ClockRef>clk0</ClockRef>
+ <ClockRef>ref</ClockRef>
<ReadIssuingAPB>1</ReadIssuingAPB>
<WriteIssuingAPB>1</WriteIssuingAPB>
<TotalIssuingAPB>1</TotalIssuingAPB>
@@ -103,17 +115,6 @@
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
- <MasterInterface>
- <Name>APB_PVT</Name>
- <APB4MasterProtocol>
- <AddressWidth>32</AddressWidth>
- <DataWidth>32</DataWidth>
- <TrustZoneMasterAPB>non_secure</TrustZoneMasterAPB>
- <APBGroupRef>apb_group0</APBGroupRef>
- </APB4MasterProtocol>
- <GeographicDomainRef>gd0</GeographicDomainRef>
- <ClockRef>clk0</ClockRef>
- </MasterInterface>
<MasterInterface>
<Name>AXI_TLX_OUT</Name>
<AXI4MasterProtocol>
@@ -133,6 +134,17 @@
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
+ <MasterInterface>
+ <Name>APB_PVT</Name>
+ <APB4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <TrustZoneMasterAPB>non_secure</TrustZoneMasterAPB>
+ <APBGroupRef>apb_group0</APBGroupRef>
+ </APB4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
</Interfaces>
<MemoryMaps>
<MemoryMap>
@@ -143,19 +155,19 @@
<MappedBlock>
<InterfaceRef>AXI_SRAM</InterfaceRef>
<Offset>0</Offset>
- <Range>2031616</Range>
+ <Range>1048576</Range>
<Visibility>true</Visibility>
</MappedBlock>
<MappedBlock>
- <InterfaceRef>APB_PVT</InterfaceRef>
- <Offset>2031616</Offset>
- <Range>65536</Range>
+ <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
+ <Offset>1048576</Offset>
+ <Range>66060288</Range>
<Visibility>true</Visibility>
</MappedBlock>
<MappedBlock>
- <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
- <Offset>2097152</Offset>
- <Range>16777216</Range>
+ <InterfaceRef>APB_PVT</InterfaceRef>
+ <Offset>67108864</Offset>
+ <Range>67108864</Range>
<Visibility>true</Visibility>
</MappedBlock>
</MemoryMap>
@@ -170,10 +182,10 @@
<InterfaceRef>AXI_SRAM</InterfaceRef>
</Target>
<Target>
- <InterfaceRef>APB_PVT</InterfaceRef>
+ <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
</Target>
<Target>
- <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
+ <InterfaceRef>APB_PVT</InterfaceRef>
</Target>
</Targets>
</Path>
@@ -213,12 +225,18 @@
</global>
<clocks>
<domain freq="100">clk0</domain>
+ <domain freq="100">ref</domain>
+ <relationship>
+ <clock0>ref</clock0>
+ <clock1>clk0</clock1>
+ <clock_boundary>async</clock_boundary>
+ </relationship>
</clocks>
<asib>
<address_ranges>
<name>mm0</name>
<range>
- <addr_max>0x1EFFFF</addr_max>
+ <addr_max>0xFFFFF</addr_max>
<addr_min>0x0</addr_min>
<remap>
<bit>default</bit>
@@ -228,23 +246,23 @@
</remap>
</range>
<range>
- <addr_max>0x1FFFFF</addr_max>
- <addr_min>0x1F0000</addr_min>
+ <addr_max>0x3FFFFFF</addr_max>
+ <addr_min>0x100000</addr_min>
<remap>
<bit>default</bit>
<present>true</present>
<region>0</region>
- <target>APB_PVT</target>
+ <target>AXI_TLX_OUT</target>
</remap>
</range>
<range>
- <addr_max>0x11FFFFF</addr_max>
- <addr_min>0x200000</addr_min>
+ <addr_max>0x7FFFFFF</addr_max>
+ <addr_min>0x4000000</addr_min>
<remap>
<bit>default</bit>
<present>true</present>
<region>0</region>
- <target>AXI_TLX_OUT</target>
+ <target>APB_PVT</target>
</remap>
</range>
</address_ranges>
@@ -628,8 +646,8 @@
<y>0</y>
</apb_port>
<apb_slave_no>63</apb_slave_no>
- <clock_boundary>none</clock_boundary>
- <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_boundary>async</clock_boundary>
+ <clock_domain_name_master_if>ref</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
@@ -640,6 +658,27 @@
<name>apb_group0</name>
<protocol>apb</protocol>
<qv_out>false</qv_out>
+ <reg>
+ <depth>2</depth>
+ <impl>present</impl>
+ <location>boundary</location>
+ <name>a</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth>2</depth>
+ <impl>present</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth>2</depth>
+ <impl>present</impl>
+ <location>boundary</location>
+ <name>d</name>
+ <type>fifo</type>
+ </reg>
<reg>
<impl def="true">absent</impl>
<location>slave_port</location>
@@ -688,28 +727,8 @@
<name>w</name>
<type def="true">full</type>
</reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>a</name>
- <type>fifo</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>d</name>
- <type>fifo</type>
- </reg>
- <reg>
- <depth def="true">2</depth>
- <impl def="true">absent</impl>
- <location>boundary</location>
- <name>w</name>
- <type>fifo</type>
- </reg>
<slave_if_data_width>32</slave_if_data_width>
+ <tide>0</tide>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
@@ -1017,11 +1036,11 @@
<link>
<slave_if>
<name>AXI_CHIPLET_IN</name>
- <master_if>AXI_TLX_OUT</master_if>
<master_if>AXI_SRAM</master_if>
+ <master_if>AXI_TLX_OUT</master_if>
+ <master_if>apb_group0</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
- <master_if>apb_group0</master_if>
</slave_if>
</link>
</architecture>
diff --git a/socrates/nic400_tb/nic400_tb.xml b/socrates/nic400_tb/nic400_tb.xml
index 5798eaf..5949711 100644
--- a/socrates/nic400_tb/nic400_tb.xml
+++ b/socrates/nic400_tb/nic400_tb.xml
@@ -104,7 +104,7 @@
<MappedBlock>
<InterfaceRef>AXI_CHIPLET_OUT</InterfaceRef>
<Offset>0</Offset>
- <Range>16777216</Range>
+ <Range>536870912</Range>
<Visibility>true</Visibility>
<Region>0</Region>
</MappedBlock>
@@ -162,7 +162,7 @@
<address_ranges>
<name>mm0</name>
<range>
- <addr_max>0xFFFFFF</addr_max>
+ <addr_max>0x1FFFFFFF</addr_max>
<addr_min>0x0</addr_min>
<remap>
<bit>default</bit>
diff --git a/synopsys_28nm_slm_integration b/synopsys_28nm_slm_integration
index e9f59a1..5ece300 160000
--- a/synopsys_28nm_slm_integration
+++ b/synopsys_28nm_slm_integration
@@ -1 +1 @@
-Subproject commit e9f59a1bd14b8350d3b493a42943fcfef07de5ba
+Subproject commit 5ece300bcb4e7dd8cd0c4cc141e7faa8f42e3e23
diff --git a/verif/cocotb/sram_chiplet_cocotb.sv b/verif/cocotb/sram_chiplet_cocotb.sv
index 5bb4a2d..c50a7d4 100644
--- a/verif/cocotb/sram_chiplet_cocotb.sv
+++ b/verif/cocotb/sram_chiplet_cocotb.sv
@@ -40,68 +40,19 @@ module sram_chiplet_cocotb(
output wire [1:0] cocotb_rresp,
output wire cocotb_rlast,
output wire cocotb_rvalid,
- input wire cocotb_rready
-
+ input wire cocotb_rready
);
+parameter N_ADDR_SEL_BITS=6;
+parameter N_CHIPLETS=8;
+wire DL_REV_CLK[N_CHIPLETS+1];
+wire DL_FWD_CLK[N_CHIPLETS+1];
-wire DL_REV_CLK;
-
-// Thin links from NIC_TB to SRAM_chiplet_0
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_0();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_IN_flow_rev_0();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_IN_flow_fwd_0();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_fwd_0();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_1();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_1();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_1();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_1();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_2();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_2();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_2();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_2();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_3();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_3();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_3();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_3();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_4();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_4();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_4();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_4();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_5();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_5();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_5();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_5();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_6();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_6();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_6();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_6();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_7();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_7();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_7();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_7();
-
-// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_8();
-TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_8();
-TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_8();
-TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_8();
-
-
+// Thin links array
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev[N_CHIPLETS+1]();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev[N_CHIPLETS+1]();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd[N_CHIPLETS+1]();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd[N_CHIPLETS+1]();
wire [3:0] AWID_AXI_CHIPLET_OUT;
@@ -273,26 +224,26 @@ nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
.tdata_m1_m_tlx_fwd_ib_flow(tdata_m1_m_tlx_fwd_ib_flow),
// Axi Stream slave (tdata in) rev flow from SRAM chiplet PL
- .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tvalid),
- .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tready),
- .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tdata),
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_flow_rev[0].tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_flow_rev[0].tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_flow_rev[0].tdata),
// Axi stream slave (tdata in) rev data from SRAM chiplet PL
- .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tvalid),
- .tready_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tready),
- .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tdata),
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_data_rev[0].tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_data_rev[0].tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_data_rev[0].tdata),
.clk_sclk(clk_in),
.clk_sresetn(aresetn),
- .dl_rev_M1_m_tlxclk(clk_in),
+ .dl_rev_M1_m_tlxclk(DL_REV_CLK[0]),
.dl_rev_M1_m_tlxresetn(aresetn)
);
nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
// axi sream master (tdata out)
- .tvalid_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tvalid),
- .tready_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tready),
- .tdata_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tdata),
+ .tvalid_pl_fwd_m1_m_tlx_m_stream(TLX_data_fwd[0].tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_stream(TLX_data_fwd[0].tready),
+ .tdata_pl_fwd_m1_m_tlx_m_stream(TLX_data_fwd[0].tdata),
// axi stream slave (tdata in)
.tvalid_pl_fwd_m1_m_tlx_s_stream(tvalid_m1_m_tlx_fwd_ib_axi_stream),
@@ -300,9 +251,9 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
.tdata_pl_fwd_m1_m_tlx_s_stream(tdata_m1_m_tlx_fwd_ib_axi_stream),
// axi stream master (tdata out)
- .tvalid_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tvalid),
- .tready_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tready),
- .tdata_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tdata),
+ .tvalid_pl_fwd_m1_m_tlx_m_flow(TLX_flow_fwd[0].tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_flow(TLX_flow_fwd[0].tready),
+ .tdata_pl_fwd_m1_m_tlx_m_flow(TLX_flow_fwd[0].tdata),
// axi stream slave (tdata in)
.tvalid_pl_fwd_m1_m_tlx_s_flow(tvalid_m1_m_tlx_fwd_ib_flow),
@@ -313,189 +264,53 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
.pl_fwd_M1_m_tlxresetn(aresetn)
);
-top_sram_chiplet u_top_sram_chiplet_0(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_IN_data_rev_0),
- .TLX_IN_flow_rev(TLX_IN_flow_rev_0),
- .TLX_IN_flow_fwd(TLX_IN_flow_fwd_0),
- .TLX_IN_data_fwd(TLX_IN_data_fwd_0),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_1),
- .TLX_OUT_flow_rev(TLX_flow_rev_1),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_1),
- .TLX_OUT_data_fwd(TLX_data_fwd_1),
-
- // Address select
- .addr_sel(3'h0)
-);
-
-top_sram_chiplet u_top_sram_chiplet_1(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_1),
- .TLX_IN_flow_rev(TLX_flow_rev_1),
- .TLX_IN_flow_fwd(TLX_flow_fwd_1),
- .TLX_IN_data_fwd(TLX_data_fwd_1),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_2),
- .TLX_OUT_flow_rev(TLX_flow_rev_2),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_2),
- .TLX_OUT_data_fwd(TLX_data_fwd_2),
-
- // Address select
- .addr_sel(3'h1)
-);
-
-top_sram_chiplet u_top_sram_chiplet_2(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_2),
- .TLX_IN_flow_rev(TLX_flow_rev_2),
- .TLX_IN_flow_fwd(TLX_flow_fwd_2),
- .TLX_IN_data_fwd(TLX_data_fwd_2),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_3),
- .TLX_OUT_flow_rev(TLX_flow_rev_3),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_3),
- .TLX_OUT_data_fwd(TLX_data_fwd_3),
-
- // Address select
- .addr_sel(3'h2)
-);
-
-
-top_sram_chiplet u_top_sram_chiplet_3(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_3),
- .TLX_IN_flow_rev(TLX_flow_rev_3),
- .TLX_IN_flow_fwd(TLX_flow_fwd_3),
- .TLX_IN_data_fwd(TLX_data_fwd_3),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_4),
- .TLX_OUT_flow_rev(TLX_flow_rev_4),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_4),
- .TLX_OUT_data_fwd(TLX_data_fwd_4),
-
- // Address select
- .addr_sel(3'h3)
-);
-
-top_sram_chiplet u_top_sram_chiplet_4(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_4),
- .TLX_IN_flow_rev(TLX_flow_rev_4),
- .TLX_IN_flow_fwd(TLX_flow_fwd_4),
- .TLX_IN_data_fwd(TLX_data_fwd_4),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_5),
- .TLX_OUT_flow_rev(TLX_flow_rev_5),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_5),
- .TLX_OUT_data_fwd(TLX_data_fwd_5),
-
- // Address select
- .addr_sel(3'h4)
-);
-
-top_sram_chiplet u_top_sram_chiplet_5(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_5),
- .TLX_IN_flow_rev(TLX_flow_rev_5),
- .TLX_IN_flow_fwd(TLX_flow_fwd_5),
- .TLX_IN_data_fwd(TLX_data_fwd_5),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_6),
- .TLX_OUT_flow_rev(TLX_flow_rev_6),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_6),
- .TLX_OUT_data_fwd(TLX_data_fwd_6),
-
- // Address select
- .addr_sel(3'h5)
-);
-
-top_sram_chiplet u_top_sram_chiplet_6(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_6),
- .TLX_IN_flow_rev(TLX_flow_rev_6),
- .TLX_IN_flow_fwd(TLX_flow_fwd_6),
- .TLX_IN_data_fwd(TLX_data_fwd_6),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_7),
- .TLX_OUT_flow_rev(TLX_flow_rev_7),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_7),
- .TLX_OUT_data_fwd(TLX_data_fwd_7),
-
- // Address select
- .addr_sel(3'h6)
-);
-
-top_sram_chiplet u_top_sram_chiplet_7(
- .SYS_CLK(clk_in),
- .DL_FWD_CLK(clk_in),
- .DL_REV_CLK(DL_REV_CLK),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
-
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev_7),
- .TLX_IN_flow_rev(TLX_flow_rev_7),
- .TLX_IN_flow_fwd(TLX_flow_fwd_7),
- .TLX_IN_data_fwd(TLX_data_fwd_7),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev_8),
- .TLX_OUT_flow_rev(TLX_flow_rev_8),
- .TLX_OUT_flow_fwd(TLX_flow_fwd_8),
- .TLX_OUT_data_fwd(TLX_data_fwd_8),
-
- // Address select
- .addr_sel(3'h7)
-);
+wire [N_CHIPLETS:0] ref_clk;
+reg [1:0] clock_div;
+always @(posedge clk_in or negedge aresetn) begin
+ if(~aresetn)
+ clock_div <= 2'b00;
+ else
+ clock_div <= clock_div + 1;
+end
+
+assign ref_clk[0] = clock_div[1];
+
+wire [N_CHIPLETS:0] PLL_LOCK;
+assign DL_FWD_CLK[0] = clk_in;
+
+genvar i;
+generate
+ for(i=0; i<N_CHIPLETS;i=i+1) begin: gen_chiplets
+ top_sram_chiplet u_top_sram_chiplet(
+ .REF_CLK(ref_clk[0]),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+ .OUT_CLK(ref_clk[i+1]),
+ .PLL_LOCK_o(PLL_LOCK[i]),
+ .PLL_LOCK_i(PLL_LOCK[i+1]),
+ .IN_FWD_CLK(DL_FWD_CLK[i]),
+ .IN_REV_CLK(DL_REV_CLK[i]),
+ .OUT_FWD_CLK(DL_FWD_CLK[i+1]),
+ .OUT_REV_CLK(DL_REV_CLK[i+1]),
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev[i]),
+ .TLX_IN_flow_rev(TLX_flow_rev[i]),
+ .TLX_IN_flow_fwd(TLX_flow_fwd[i]),
+ .TLX_IN_data_fwd(TLX_data_fwd[i]),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev[i+1]),
+ .TLX_OUT_flow_rev(TLX_flow_rev[i+1]),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd[i+1]),
+ .TLX_OUT_data_fwd(TLX_data_fwd[i+1]),
+
+ // Address select
+ .addr_sel(i[N_ADDR_SEL_BITS-1:0])
+
+ );
+ end
+endgenerate
+
+assign PLL_LOCK[N_CHIPLETS]=1'b1;
endmodule
\ No newline at end of file
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
index 71921bc..e58ea83 100644
--- a/verif/cocotb/sram_chiplet_tests.py
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -25,8 +25,9 @@ from cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiMaster, AxiRam, AxiBurstType, AxiSlave
+
CHIPLET_0_BASE=0x00000000
-CHIPLET_0_APB_BASE=0x001F0000
+CHIPLET_0_APB_BASE= 0x4000000
CHIPLET_0_TS_BASE = CHIPLET_0_APB_BASE
CHIPLET_0_PD_BASE = CHIPLET_0_APB_BASE + 6*0x1000
CHIPLET_0_VM_BASE = CHIPLET_0_APB_BASE + 7*0x1000
@@ -41,7 +42,7 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
- cocotb.start_soon(Clock(dut.clk_in, 4, units="ns").start())
+ cocotb.start_soon(Clock(dut.clk_in, 1, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut,"cocotb"), dut.clk_in, dut.aresetn, reset_active_level=False)
def set_idle_generator(self, generator=None):
if generator:
@@ -93,19 +94,22 @@ async def SRAM_bank_test(dut, tb, bank_addrs):
await tb.axi_master.write(bank_addr, data)
read_data = await tb.axi_master.read(bank_addr, length)
assert read_data.data == data
+
+async def wait_for_PLL(dut, tb):
+ await RisingEdge(dut.PLL_LOCK[0])
+ await ClockCycles(dut.clk_in,20)
+
@cocotb.test()
async def PLL_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
- byte_lanes = tb.axi_master.write_if.byte_lanes
- max_burst_size = tb.axi_master.write_if.max_burst_size
-
- if size is None:
- size = max_burst_size
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
+
+ #await wait_for_PLL(dut,tb)
+
# Test ID of PLL Intergration layer
PLL_ID = await tb.axi_master.read(CHIPLET_0_PLL_BASE+20,4)
assert PLL_ID.data == b'LPNS'
@@ -130,7 +134,6 @@ async def PD_TEST(dut,idle_insterter=None, backpressure_inserter=None, size=None
tb = TB(dut)
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
-
if size is None:
size = max_burst_size
@@ -241,9 +244,7 @@ async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=Non
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
await SRAM_test_write(dut, tb, 0x0, byte_lanes, size)
- bank_addrs = range(0x00000000, CHIPLET_0_SRAM_MAX_ADDR, 0x20000)
- await SRAM_bank_test(dut, tb, bank_addrs)
- bank_addrs = range(CHIPLET_0_SRAM_MAX_ADDR, CHIPLET_0_SRAM_MAX_ADDR + 0xF0000, 0x20000)
+ bank_addrs = range(0x00000000, CHIPLET_0_SRAM_MAX_ADDR, 0x10000)
await SRAM_bank_test(dut, tb, bank_addrs)
@cocotb.test()
@@ -258,24 +259,24 @@ async def SRAM_TEST_MULTI_CHIPLET(dut,idle_inserter=None, backpressure_inserter=
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
-
- N=13824
+ await wait_for_PLL(dut, tb)
+ N=1024
data = bytearray([x % 256 for x in range(N)])
- addresses = [0x000000, 0x200000, 0x400000, 0x600000, 0x800000, 0xA00000, 0xC00000, 0xE00000]
+ addresses = range(0,0x800000, 0x100000)
BW_write = []
BW_read = []
for addr in addresses:
- start_time = cocotb.utils.get_sim_time()
+ start_time = cocotb.utils.get_sim_time(units='ns')
await tb.axi_master.write(addr, data, size=size)
- end_time = cocotb.utils.get_sim_time()
- BW_write.append(1e3*N*8/(end_time-start_time))
+ end_time = cocotb.utils.get_sim_time(units='ns')
+ BW_write.append(N*8/(end_time-start_time))
- start_time = cocotb.utils.get_sim_time()
+ start_time = cocotb.utils.get_sim_time(units='ns')
d_read = await tb.axi_master.read(addr,N)
- end_time = cocotb.utils.get_sim_time()
- BW_read.append(1e3*N*8/(end_time-start_time))
+ end_time = cocotb.utils.get_sim_time(units='ns')
+ BW_read.append(N*8/(end_time-start_time))
assert d_read.data == data
@@ -283,3 +284,62 @@ async def SRAM_TEST_MULTI_CHIPLET(dut,idle_inserter=None, backpressure_inserter=
for x in range(len(addresses)):
tb.log.info("%d \t\t %f \t\t\t %f",x, BW_write[x], BW_read[x])
+
+# ------------------------------------------------------------------------------------------#
+# ---------------------- SRAM Concerrent access test ---------------------------------------#
+# #
+# Starts multiple writes concurrently, one to each sram chiplet and waits for writes to #
+# finish. After each write has finished, a read access is initiated to the same address #
+# #
+@cocotb.test()
+async def SRAM_CONC_ACCESS(dut,idle_inserter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_inserter)
+ tb.set_backpressure_generator(backpressure_inserter)
+ await wait_for_PLL(dut, tb)
+ N=8192
+ data = bytearray([x % 256 for x in range(N)])
+ d_read = []
+ write_ops = []
+ read_ops = []
+
+ addresses = range(0,0x800000, 0x100000)
+ start_time = cocotb.utils.get_sim_time(units='ns')
+ for addr in addresses:
+ write_ops.append(tb.axi_master.init_write(addr, data, size=size))
+
+ for i in range(0,len(write_ops)):
+ await write_ops[i].wait()
+ read_ops.append(tb.axi_master.init_read(addresses[i],N))
+
+ for read_op in read_ops:
+ await read_op.wait()
+ end_time = cocotb.utils.get_sim_time(units='ns')
+ BW = (2*N*8*len(addresses))/(end_time-start_time)
+ tb.log.info("Total Bandwidth (Gbps) (read and write) : %f", BW)
+
+@cocotb.test()
+async def SRAM_TEST_CROSS_BOUND(dut,idle_inserter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_inserter)
+ tb.set_backpressure_generator(backpressure_inserter)
+ N=256
+ data = bytearray([x % 256 for x in range(N)])
+
+ await tb.axi_master.write(0xFFF80, data, size=size)
+ d_read = await tb.axi_master.read(0xFFF80,N)
+ assert d_read.data == data
\ No newline at end of file
--
GitLab