diff --git a/.gitignore b/.gitignore
index 7a28c763970438c12d72db5d97db50efd7417f64..9274f7c87daff3001d5bb8573182efc67291f9d5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,8 +1,19 @@
.project
.ecmproject
+.metadata
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/cln28ht
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/cln28ht_pmk
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/cln28ht_ret
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/bump_lib
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/io_lib
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/pad_lib
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/.*
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/DRC
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/pna_output
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/legalizer_debug_plots
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/RAIL_DATABASE
+ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/clock_auto_exceptions*
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/HDL_LIBRARIES
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/PreFrameCheck
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/sram_32k
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
index 14f6938df6ca6548577b3f04b4942c0a0751a4ee..9d20a616c1b2188d5ff837683d062781e4f34361 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/FC_flow.tcl
@@ -7,20 +7,39 @@ set LOG_DIR $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/logs
redirect -tee -file $LOG_DIR/01_design_setup.log {source ./design_setup.tcl}
# Floorplan setup
-redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {1695 1530} -core_offset {120}}
+redirect -tee -file $LOG_DIR/02_init_floorplan.log {initialize_floorplan -control_type die -use_site_row -side_length {2171 2640} -core_offset {160}}
redirect -tee -file $LOG_DIR/03_floorplan.log {source ./floorplan/fp.tcl}
+
+
+source ./io_plan.tcl
+save_lib sram_chiplet.dlib
+
# Read Constraints
redirect -tee -file $LOG_DIR/04_constraints.log {read_sdc ../constraints/sram_chiplet.sdc}
# Power Plan
+load_upf ../sram_chiplet.upf
redirect -tee -file $LOG_DIR/05_power_plan.log {source ./power_plan.tcl}
+# Route RDL
+place_io
+route_rdl_flip_chip -layers AP
+
+create_io_filler_cells -io_guides [get_io_guides {main_io.top main_io.left main_io.right main_io.bottom}] \
+ -reference_cells {PFILLER20_G PFILLER10_G PFILLER5_G PFILLER1_G PFILLER05_G PFILLER0005_G} \
+ -prefix IOFILL
+
# Init coarse placement
redirect -tee -file $LOG_DIR/06_init_placement.log {source ./init_placement.tcl}
+current_corner default
+set_operating_conditions -max_library cln28ht -max ffg_cbestt_min_0p99v_m40c -min_library cln28ht -min ssg_cworstt_max_0p81v_125c
+# CHECK THE TIMING ANALYSIS IN THE GUI
+
# Physical aware synthesis
redirect -tee -file $LOG_DIR/07_compile.log {compile_fusion}
+set_operating_conditions -max_library cln28ht -max ffg_cbestt_min_0p99v_m40c -min_library cln28ht -min ssg_cworstt_max_0p81v_125c
save_lib sram_chiplet.dlib
redirect -tee -file $REPORT_DIR/timing_01_compile.rep {report_timing}
@@ -31,7 +50,7 @@ save_lib sram_chiplet.dlib
redirect -tee -file $REPORT_DIR/timing_02_opt_place.rep {report_timing}
# CTS
-redirect -tee -file $LOG_DIR/08_CTS.log {synthesize_clock_trees -clock {PLL_CLK REF_CLK TLX_IN_FWD_CLK TLX_OUT_REV_CLK}}
+redirect -tee -file $LOG_DIR/08_CTS.log {synthesize_clock_trees -clock [get_clocks]}
save_lib sram_chiplet.dlib
redirect -tee -file $REPORT_DIR/timing_03_CTS.rep {report_timing}
@@ -40,6 +59,7 @@ redirect -tee -file $LOG_DIR/10_clock_opt.log {clock_opt}
save_lib sram_chiplet.dlib
redirect -tee -file $REPORT_DIR/timing_04_clock_opt.rep {report_timing}
+create_stdcell_fillers -lib_cells {FILL128_A12PP140ZTS_C35 FILL16_A12PP140ZTS_C35 FILL1_A12PP140ZTS_C35 FILL2_A12PP140ZTS_C35 FILL32_A12PP140ZTS_C35 FILL3_A12PP140ZTS_C35 FILL4_A12PP140ZTS_C35}
# Route
redirect -tee -file $LOG_DIR/11_route.log {route_auto}
@@ -50,3 +70,32 @@ redirect -tee -file $REPORT_DIR/timing_05_route.rep {report_timing}
redirect -tee -file $LOG_DIR/12_route_optimisation.log {optimize_routes}
save_lib sram_chiplet.dlib
redirect -tee -file $REPORT_DIR/timing_06_route_opt.rep {report_timing}
+
+## Paths Please Edit for your system
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set pmk_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0
+set ret_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_rklo_lvt_svt_c30_c35/r1p0
+set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
+set Synopsys_TS_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b
+set Synopsys_PD_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a
+set Synopsys_VM_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_vm_shrink_tsmc28hpcp_1.00a/synopsys/dwc_sensors_vm_shrink_tsmc28hpcp/1.00a
+
+set standard_cell_gds_file $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
+set pmk_gds_file $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
+set ret_gds_file $ret_base_path/gds2/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.gds2
+set sram_32k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.gds2
+set sram_16k_gds_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.gds2
+set Synopsys_PLL_gds_file $Synopsys_PLL_dir/gds/5m4x0z/dwc_z19606ts_ns.gds
+set Synopsys_TS_gds_file $Synopsys_TS_dir/gdsii/mr74127_v1r1.gds
+set Synopsys_PD_gds_file $Synopsys_PD_dir/gds/mr74125_v1r2.gds
+set Synopsys_VM_gds_file $Synopsys_VM_dir/gdsii/mr74140_v1r1.gds
+
+set OUT_DIR $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET
+
+write_gds -lib_cell_view frame -layer_map /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/milkyway/1p8m_5x2z_utalrdl/stream_out_layer_map -allow_design_mismatch -long_names -hierarchy all -units 1000 -merge_files [list $standard_cell_gds_file $pmk_gds_file $ret_gds_file $sram_32k_gds_file $sram_16k_gds_file $Synopsys_PLL_gds_file $Synopsys_TS_gds_file $Synopsys_PD_gds_file] $OUT_DIR/sram_chiplet.gds
+write_verilog -top_module_first -hierarchy all \
+ -exclude {corner_cells filler_cells flip_chip_pad_cells pad_spacer_cells pg_netlist spare_cells} $OUT_DIR/sram_chiplet_gate.v
+write_sdf $OUT_DIR/sram_chiplet_gate.sdf
+
+
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/calibre_drc b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/calibre_drc
new file mode 100644
index 0000000000000000000000000000000000000000..528c3e36d6facfecadc825057c0c3045a5130481
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/calibre_drc
@@ -0,0 +1,8 @@
+*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/CMOS/util/LOGIC_TopMz_DRC/CLN28HP_8M_5X2Z_002.22a.encrypt
+*drcRunDir: /home/dwn1c21/SoC-Labs/TAPEOUT/jan2025/sram_chiplet/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/DRC
+*drcLayoutPaths: /home/dwn1c21/SoC-Labs/TAPEOUT/jan2025/sram_chiplet/imp/ASIC/SRAM_CHIPLET/sram_chiplet.gds
+*drcLayoutPrimary: SRAM_chiplet
+*cmnRunMT: 1
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
index 4f70550f12c35bc6300002f9029e13da60825bce..fc2e19c89614bf1e3b381848be03ca18c8c19e40 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/design_setup.tcl
@@ -1,4 +1,4 @@
-set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
set TLU_dir /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/synopsys_tluplus/1p8m_5x2z_utalrdl
@@ -9,11 +9,9 @@ set TLU_rcbest $TLU_dir/rcbest.tluplus
set TLU_rcworst $TLU_dir/rcworst.tluplus
set TLU_map $TLU_dir/tluplus.map
-
-
create_lib sram_chiplet.dlib \
- -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf \
- -ref_libs {./cln28ht/ ./sram_16k/ ./sram_32k/ ./Synopsys_PLL/ ./Synopsys_PD/ ./Synopsys_TS/ ./Synopsys_VM/}
+ -technology $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf \
+ -ref_libs {./cln28ht/ ./cln28ht_pmk/ ./cln28ht_ret/ ./sram_16k/ ./sram_32k/ ./Synopsys_PLL/ ./Synopsys_PD/ ./Synopsys_TS/ ./Synopsys_VM/ ./io_lib/ ./pad_lib/ ./bump_lib/}
source $env(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/flist/synopsys_flist.tcl
analyze -format sverilog $env(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
@@ -22,7 +20,7 @@ elaborate SRAM_chiplet
set_top_module SRAM_chiplet
redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary cln28ht}
-
+redirect -tee -file ./lib_cell_summary.log {report_lib -cell_summary pad_lib}
read_parasitic_tech -name cbest -tlup $TLU_cbest -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name cworst -tlup $TLU_cworst -layermap $TLU_map -sanity_check advanced
read_parasitic_tech -name rcbest -tlup $TLU_rcbest -layermap $TLU_map -sanity_check advanced
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
index da438bfb918d3c0e7bbae8bc980b91090a213c91..10ae45f8f6d4045dfdba5cd1ea2f37af6112c817 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.def
@@ -2,12 +2,122 @@
# Fusion Compiler write_def
# Release : U-2022.12
# User Name : dwn1c21
-# Date : Thu Sep 5 11:23:09 2024
+# Date : Tue Dec 17 14:29:32 2024
#
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN SRAM_chiplet ;
UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 0 1529700 ) ( 1694880 1529700 ) ( 1694880 0 ) ;
+DIEAREA ( 0 0 ) ( 0 2639600 ) ( 2170940 2639600 ) ( 2170940 0 ) ;
+PINS 108 ;
+ - PAD_REF_CLK + NET PAD_REF_CLK + DIRECTION INPUT + USE CLOCK ;
+ - PAD_aRESETn + NET PAD_aRESETn + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_DL_FWD_RESETn + NET PAD_DL_FWD_RESETn + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_IN_FWD_CLK + NET PAD_IN_FWD_CLK + DIRECTION INPUT + USE CLOCK ;
+ - PAD_IN_REV_CLK + NET PAD_IN_REV_CLK + DIRECTION OUTPUT + USE CLOCK ;
+ - PAD_OUT_FWD_CLK + NET PAD_OUT_FWD_CLK + DIRECTION OUTPUT + USE CLOCK ;
+ - PAD_OUT_REV_CLK + NET PAD_OUT_REV_CLK + DIRECTION INPUT + USE CLOCK ;
+ - PAD_PLL_LOCK_o + NET PAD_PLL_LOCK_o + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_PLL_LOCK_i + NET PAD_PLL_LOCK_i + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[15] + NET PAD_TLX_IN_data_rev_0_tdata[15] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[14] + NET PAD_TLX_IN_data_rev_0_tdata[14] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[13] + NET PAD_TLX_IN_data_rev_0_tdata[13] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[12] + NET PAD_TLX_IN_data_rev_0_tdata[12] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[11] + NET PAD_TLX_IN_data_rev_0_tdata[11] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[10] + NET PAD_TLX_IN_data_rev_0_tdata[10] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[9] + NET PAD_TLX_IN_data_rev_0_tdata[9] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[8] + NET PAD_TLX_IN_data_rev_0_tdata[8] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[7] + NET PAD_TLX_IN_data_rev_0_tdata[7] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[6] + NET PAD_TLX_IN_data_rev_0_tdata[6] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[5] + NET PAD_TLX_IN_data_rev_0_tdata[5] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[4] + NET PAD_TLX_IN_data_rev_0_tdata[4] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[3] + NET PAD_TLX_IN_data_rev_0_tdata[3] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[2] + NET PAD_TLX_IN_data_rev_0_tdata[2] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[1] + NET PAD_TLX_IN_data_rev_0_tdata[1] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tdata[0] + NET PAD_TLX_IN_data_rev_0_tdata[0] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tvalid + NET PAD_TLX_IN_data_rev_0_tvalid + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_rev_0_tready + NET PAD_TLX_IN_data_rev_0_tready + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_rev_0_tdata[2] + NET PAD_TLX_IN_flow_rev_0_tdata[2] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_rev_0_tdata[1] + NET PAD_TLX_IN_flow_rev_0_tdata[1] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_rev_0_tdata[0] + NET PAD_TLX_IN_flow_rev_0_tdata[0] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_rev_0_tvalid + NET PAD_TLX_IN_flow_rev_0_tvalid + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_rev_0_tready + NET PAD_TLX_IN_flow_rev_0_tready + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_fwd_0_tdata[1] + NET PAD_TLX_IN_flow_fwd_0_tdata[1] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_fwd_0_tdata[0] + NET PAD_TLX_IN_flow_fwd_0_tdata[0] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_fwd_0_tvalid + NET PAD_TLX_IN_flow_fwd_0_tvalid + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_flow_fwd_0_tready + NET PAD_TLX_IN_flow_fwd_0_tready + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[15] + NET PAD_TLX_IN_data_fwd_0_tdata[15] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[14] + NET PAD_TLX_IN_data_fwd_0_tdata[14] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[13] + NET PAD_TLX_IN_data_fwd_0_tdata[13] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[12] + NET PAD_TLX_IN_data_fwd_0_tdata[12] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[11] + NET PAD_TLX_IN_data_fwd_0_tdata[11] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[10] + NET PAD_TLX_IN_data_fwd_0_tdata[10] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[9] + NET PAD_TLX_IN_data_fwd_0_tdata[9] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[8] + NET PAD_TLX_IN_data_fwd_0_tdata[8] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[7] + NET PAD_TLX_IN_data_fwd_0_tdata[7] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[6] + NET PAD_TLX_IN_data_fwd_0_tdata[6] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[5] + NET PAD_TLX_IN_data_fwd_0_tdata[5] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[4] + NET PAD_TLX_IN_data_fwd_0_tdata[4] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[3] + NET PAD_TLX_IN_data_fwd_0_tdata[3] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[2] + NET PAD_TLX_IN_data_fwd_0_tdata[2] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[1] + NET PAD_TLX_IN_data_fwd_0_tdata[1] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tdata[0] + NET PAD_TLX_IN_data_fwd_0_tdata[0] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tvalid + NET PAD_TLX_IN_data_fwd_0_tvalid + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_IN_data_fwd_0_tready + NET PAD_TLX_IN_data_fwd_0_tready + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[15] + NET PAD_TLX_data_rev_1_tdata[15] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[14] + NET PAD_TLX_data_rev_1_tdata[14] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[13] + NET PAD_TLX_data_rev_1_tdata[13] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[12] + NET PAD_TLX_data_rev_1_tdata[12] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[11] + NET PAD_TLX_data_rev_1_tdata[11] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[10] + NET PAD_TLX_data_rev_1_tdata[10] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[9] + NET PAD_TLX_data_rev_1_tdata[9] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[8] + NET PAD_TLX_data_rev_1_tdata[8] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[7] + NET PAD_TLX_data_rev_1_tdata[7] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[6] + NET PAD_TLX_data_rev_1_tdata[6] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[5] + NET PAD_TLX_data_rev_1_tdata[5] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[4] + NET PAD_TLX_data_rev_1_tdata[4] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[3] + NET PAD_TLX_data_rev_1_tdata[3] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[2] + NET PAD_TLX_data_rev_1_tdata[2] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[1] + NET PAD_TLX_data_rev_1_tdata[1] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tdata[0] + NET PAD_TLX_data_rev_1_tdata[0] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tvalid + NET PAD_TLX_data_rev_1_tvalid + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_rev_1_tready + NET PAD_TLX_data_rev_1_tready + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_flow_rev_1_tdata[2] + NET PAD_TLX_flow_rev_1_tdata[2] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_flow_rev_1_tdata[1] + NET PAD_TLX_flow_rev_1_tdata[1] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_flow_rev_1_tdata[0] + NET PAD_TLX_flow_rev_1_tdata[0] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_flow_rev_1_tvalid + NET PAD_TLX_flow_rev_1_tvalid + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_flow_rev_1_tready + NET PAD_TLX_flow_rev_1_tready + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_flow_fwd_1_tdata[1] + NET PAD_TLX_flow_fwd_1_tdata[1] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_flow_fwd_1_tdata[0] + NET PAD_TLX_flow_fwd_1_tdata[0] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_flow_fwd_1_tvalid + NET PAD_TLX_flow_fwd_1_tvalid + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_flow_fwd_1_tready + NET PAD_TLX_flow_fwd_1_tready + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[15] + NET PAD_TLX_data_fwd_1_tdata[15] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[14] + NET PAD_TLX_data_fwd_1_tdata[14] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[13] + NET PAD_TLX_data_fwd_1_tdata[13] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[12] + NET PAD_TLX_data_fwd_1_tdata[12] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[11] + NET PAD_TLX_data_fwd_1_tdata[11] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[10] + NET PAD_TLX_data_fwd_1_tdata[10] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[9] + NET PAD_TLX_data_fwd_1_tdata[9] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[8] + NET PAD_TLX_data_fwd_1_tdata[8] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[7] + NET PAD_TLX_data_fwd_1_tdata[7] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[6] + NET PAD_TLX_data_fwd_1_tdata[6] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[5] + NET PAD_TLX_data_fwd_1_tdata[5] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[4] + NET PAD_TLX_data_fwd_1_tdata[4] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[3] + NET PAD_TLX_data_fwd_1_tdata[3] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[2] + NET PAD_TLX_data_fwd_1_tdata[2] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[1] + NET PAD_TLX_data_fwd_1_tdata[1] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tdata[0] + NET PAD_TLX_data_fwd_1_tdata[0] + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tvalid + NET PAD_TLX_data_fwd_1_tvalid + DIRECTION OUTPUT + USE SIGNAL ;
+ - PAD_TLX_data_fwd_1_tready + NET PAD_TLX_data_fwd_1_tready + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_addr_sel[3] + NET PAD_addr_sel[3] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_addr_sel[2] + NET PAD_addr_sel[2] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_addr_sel[1] + NET PAD_addr_sel[1] + DIRECTION INPUT + USE SIGNAL ;
+ - PAD_addr_sel[0] + NET PAD_addr_sel[0] + DIRECTION INPUT + USE SIGNAL ;
+ - AGND + NET AGND + SPECIAL + DIRECTION INPUT + USE GROUND ;
+ - AVDD + NET AVDD + SPECIAL + DIRECTION INPUT + USE POWER ;
+ - AVDDHV + NET AVDDHV + SPECIAL + DIRECTION INPUT + USE POWER ;
+ - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER ;
+ - VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND ;
+END PINS
END DESIGN
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
index 1bf66cf1039899fd45583b2ea3da72226f2c6192..b8723b2a652866bae7109dd80124d66ac08bacff 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan.tcl
@@ -1,6 +1,6 @@
################################################################################
#
-# Created by fc write_floorplan on Thu Sep 5 11:23:09 2024
+# Created by fc write_floorplan on Tue Dec 17 14:29:32 2024
#
################################################################################
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
index e3843c91279d6e617658099475e3f4fe72e8b41b..643340b7d87f7b7e62fb8119b07206101322b5bd 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/floorplan_compare_data.txt
@@ -1,6 +1,6 @@
################################################################################
#
-# Created by fc compare_floorplans on Thu Sep 5 11:23:09 2024
+# Created by fc compare_floorplans on Tue Dec 17 14:29:32 2024
#
# DO NOT EDIT - automatically generated file
#
@@ -8,109 +8,128 @@
START SRAM_chiplet
MACROS
- u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts { {120.0000 390.0600} {360.0000 590.0600} }
- u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd { {120.0000 618.3400} {205.0000 693.3400} }
- u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL { {120.0000 120.0000} {382.5000 360.0000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k { {120.0600 770.0650} {440.7200 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k { {440.7200 770.0650} {761.3800 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k { {761.3800 770.0650} {1082.0400 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k { {1082.0400 770.0650} {1402.7000 1409.7000} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k { {1082.0400 120.0000} {1402.7000 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k { {761.3800 120.0000} {1082.0400 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k { {440.7200 120.0000} {761.3800 759.6350} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_0 { {1402.7000 120.0000} {1574.8800 758.0750} }
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_1 { {1402.7000 771.6250} {1574.8800 1409.7000} }
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts { {479.5000 160.0000} {719.5000 360.0000} }
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd { {776.5000 160.0000} {861.5000 235.0000} }
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL { {160.0000 160.0000} {422.5000 400.0000} }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k { {160.0000 438.9100} {480.6600 1078.5450} }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k { {495.6600 438.9100} {816.3200 1078.5450} }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k { {831.3200 438.9100} {1151.9800 1078.5450} }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N { {1166.9800 430.9100} {1487.6400 1070.5450} }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k { {160.0000 1824.1800} {480.6600 2463.8150} }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k { {495.6600 1824.1800} {816.3200 2463.8150} }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k { {160.0000 1131.5450} {480.6600 1771.1800} }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N { {495.6600 1131.5450} {816.3200 1771.1800} }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k { {831.3200 1824.1800} {1151.9800 2463.8150} }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k { {1166.9800 1824.1800} {1487.6400 2463.8150} }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k { {831.3200 1131.5450} {1151.9800 1771.1800} }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N { {1166.9800 1127.5450} {1487.6400 1767.1800} }
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k { {1502.6400 1824.1800} {1823.3000 2463.8150} }
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k { {1502.6400 1127.5450} {1823.3000 1767.1800} }
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k { {1502.6400 430.9100} {1823.3000 1070.5450} }
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 { {1838.3000 1824.1800} {2010.4800 2462.2550} }
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 { {1838.3000 1129.1050} {2010.4800 1767.1800} }
PINS
- clk_in { {847.4400 764.8500} {847.4401 764.8501} }
- aresetn { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_rev_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_rev_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_rev_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_rev_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_rev_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_rev_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_fwd_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_fwd_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_fwd_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_flow_fwd_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_IN_data_fwd_0_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_rev_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_rev_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_rev_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_rev_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_rev_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_rev_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_fwd_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_fwd_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_fwd_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_flow_fwd_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[15] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[14] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[13] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[12] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[11] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[10] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[9] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[8] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[7] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[6] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[5] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[4] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[3] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[2] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[1] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tdata[0] { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tvalid { {847.4400 764.8500} {847.4401 764.8501} }
- TLX_data_fwd_1_tready { {847.4400 764.8500} {847.4401 764.8501} }
+ PAD_REF_CLK { {70.0500 806.6250} {73.0500 822.6750} }
+ PAD_aRESETn { {70.0500 1140.6250} {73.0500 1156.6750} }
+ PAD_DL_FWD_RESETn { {70.0500 1307.6250} {73.0500 1323.6750} }
+ PAD_IN_FWD_CLK { {1578.4750 2566.5500} {1594.5250 2569.5500} }
+ PAD_IN_REV_CLK { {70.0500 2071.4750} {73.0500 2087.5250} }
+ PAD_OUT_FWD_CLK { {1578.4750 70.0500} {1594.5250 73.0500} }
+ PAD_OUT_REV_CLK { {70.0500 401.4750} {73.0500 417.5250} }
+ PAD_PLL_LOCK_o { {2097.8900 305.6250} {2100.8900 321.6750} }
+ PAD_PLL_LOCK_i { {2097.8900 2309.6250} {2100.8900 2325.6750} }
+ PAD_TLX_IN_data_rev_0_tdata[15] { {2097.8900 1904.4750} {2100.8900 1920.5250} }
+ PAD_TLX_IN_data_rev_0_tdata[14] { {1516.4500 2566.5500} {1532.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[13] { {1349.4500 2566.5500} {1365.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[12] { {1182.4500 2566.5500} {1198.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[11] { {1015.4500 2566.5500} {1031.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[10] { {848.4500 2566.5500} {864.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[9] { {681.4500 2566.5500} {697.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[8] { {511.5000 2566.5500} {527.5500 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[7] { {2097.8900 2071.4750} {2100.8900 2087.5250} }
+ PAD_TLX_IN_data_rev_0_tdata[6] { {1663.4500 2566.5500} {1679.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[5] { {1496.4500 2566.5500} {1512.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[4] { {1329.4500 2566.5500} {1345.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[3] { {1162.4500 2566.5500} {1178.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[2] { {995.4500 2566.5500} {1011.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[1] { {828.4500 2566.5500} {844.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tdata[0] { {661.4500 2566.5500} {677.5000 2569.5500} }
+ PAD_TLX_IN_data_rev_0_tvalid { {2097.8900 2213.7750} {2100.8900 2229.8250} }
+ PAD_TLX_IN_data_rev_0_tready { {70.0500 2213.7750} {73.0500 2229.8250} }
+ PAD_TLX_IN_flow_rev_0_tdata[2] { {2097.8900 2046.7750} {2100.8900 2062.8250} }
+ PAD_TLX_IN_flow_rev_0_tdata[1] { {70.0500 1904.4750} {73.0500 1920.5250} }
+ PAD_TLX_IN_flow_rev_0_tdata[0] { {70.0500 2046.7750} {73.0500 2062.8250} }
+ PAD_TLX_IN_flow_rev_0_tvalid { {2097.8900 1975.6250} {2100.8900 1991.6750} }
+ PAD_TLX_IN_flow_rev_0_tready { {70.0500 1975.6250} {73.0500 1991.6750} }
+ PAD_TLX_IN_flow_fwd_0_tdata[1] { {1683.4500 2566.5500} {1699.5000 2569.5500} }
+ PAD_TLX_IN_flow_fwd_0_tdata[0] { {70.0500 2238.4750} {73.0500 2254.5250} }
+ PAD_TLX_IN_flow_fwd_0_tvalid { {2097.8900 2238.4750} {2100.8900 2254.5250} }
+ PAD_TLX_IN_flow_fwd_0_tready { {70.0500 2309.6250} {73.0500 2325.6750} }
+ PAD_TLX_IN_data_fwd_0_tdata[15] { {1643.4500 2566.5500} {1659.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[14] { {1476.4500 2566.5500} {1492.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[13] { {1309.4500 2566.5500} {1325.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[12] { {1142.4500 2566.5500} {1158.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[11] { {975.4500 2566.5500} {991.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[10] { {808.4500 2566.5500} {824.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[9] { {641.4500 2566.5500} {657.5000 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[8] { {344.5000 2566.5500} {360.5500 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[7] { {1912.4750 2566.5500} {1928.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[6] { {1411.4750 2566.5500} {1427.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[5] { {1244.4750 2566.5500} {1260.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[4] { {1077.4750 2566.5500} {1093.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[3] { {910.4750 2566.5500} {926.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[2] { {743.4750 2566.5500} {759.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[1] { {576.4750 2566.5500} {592.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tdata[0] { {242.4750 2566.5500} {258.5250 2569.5500} }
+ PAD_TLX_IN_data_fwd_0_tvalid { {2097.8900 2476.6250} {2100.8900 2492.6750} }
+ PAD_TLX_IN_data_fwd_0_tready { {70.0500 2476.6250} {73.0500 2492.6750} }
+ PAD_TLX_data_rev_1_tdata[15] { {2097.8900 568.4750} {2100.8900 584.5250} }
+ PAD_TLX_data_rev_1_tdata[14] { {1513.5000 70.0500} {1529.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[13] { {1346.5000 70.0500} {1362.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[12] { {1179.5000 70.0500} {1195.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[11] { {1012.5000 70.0500} {1028.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[10] { {845.5000 70.0500} {861.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[9] { {678.5000 70.0500} {694.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[8] { {511.5000 70.0500} {527.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[7] { {2097.8900 401.4750} {2100.8900 417.5250} }
+ PAD_TLX_data_rev_1_tdata[6] { {1660.5000 70.0500} {1676.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[5] { {1493.5000 70.0500} {1509.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[4] { {1326.5000 70.0500} {1342.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[3] { {1159.5000 70.0500} {1175.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[2] { {992.5000 70.0500} {1008.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[1] { {825.5000 70.0500} {841.5500 73.0500} }
+ PAD_TLX_data_rev_1_tdata[0] { {658.5000 70.0500} {674.5500 73.0500} }
+ PAD_TLX_data_rev_1_tvalid { {2097.8900 543.7750} {2100.8900 559.8250} }
+ PAD_TLX_data_rev_1_tready { {70.0500 543.7750} {73.0500 559.8250} }
+ PAD_TLX_flow_rev_1_tdata[2] { {2097.8900 710.7750} {2100.8900 726.8250} }
+ PAD_TLX_flow_rev_1_tdata[1] { {70.0500 568.4750} {73.0500 584.5250} }
+ PAD_TLX_flow_rev_1_tdata[0] { {70.0500 710.7750} {73.0500 726.8250} }
+ PAD_TLX_flow_rev_1_tvalid { {2097.8900 639.6250} {2100.8900 655.6750} }
+ PAD_TLX_flow_rev_1_tready { {70.0500 639.6250} {73.0500 655.6750} }
+ PAD_TLX_flow_fwd_1_tdata[1] { {1680.5000 70.0500} {1696.5500 73.0500} }
+ PAD_TLX_flow_fwd_1_tdata[0] { {70.0500 234.4750} {73.0500 250.5250} }
+ PAD_TLX_flow_fwd_1_tvalid { {2097.8900 234.4750} {2100.8900 250.5250} }
+ PAD_TLX_flow_fwd_1_tready { {70.0500 305.6250} {73.0500 321.6750} }
+ PAD_TLX_data_fwd_1_tdata[15] { {1640.5000 70.0500} {1656.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[14] { {1473.5000 70.0500} {1489.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[13] { {1306.5000 70.0500} {1322.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[12] { {1139.5000 70.0500} {1155.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[11] { {972.5000 70.0500} {988.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[10] { {805.5000 70.0500} {821.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[9] { {638.5000 70.0500} {654.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[8] { {344.5000 70.0500} {360.5500 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[7] { {1912.4750 70.0500} {1928.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[6] { {1411.4750 70.0500} {1427.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[5] { {1244.4750 70.0500} {1260.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[4] { {1077.4750 70.0500} {1093.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[3] { {910.4750 70.0500} {926.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[2] { {743.4750 70.0500} {759.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[1] { {576.4750 70.0500} {592.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tdata[0] { {242.4750 70.0500} {258.5250 73.0500} }
+ PAD_TLX_data_fwd_1_tvalid { {2097.8900 138.6250} {2100.8900 154.6750} }
+ PAD_TLX_data_fwd_1_tready { {70.0500 138.6250} {73.0500 154.6750} }
+ PAD_addr_sel[3] { {2097.8900 1140.6250} {2100.8900 1156.6750} }
+ PAD_addr_sel[2] { {2097.8900 1307.6250} {2100.8900 1323.6750} }
+ PAD_addr_sel[1] { {2097.8900 1474.6250} {2100.8900 1490.6750} }
+ PAD_addr_sel[0] { {2097.8900 1641.6250} {2100.8900 1657.6750} }
END SRAM_chiplet
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
index 8319320eb82902f777e786e0eeaac77b3f39fa38..bad519807fc47e43062e5e5260c47d489a1f8714 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/floorplan/fp.tcl
@@ -1,12 +1,32 @@
################################################################################
#
-# Created by fc write_floorplan on Thu Sep 5 11:23:09 2024
+# Created by fc write_floorplan on Tue Dec 17 14:29:32 2024
#
################################################################################
set _dirName__0 [file dirname [file normalize [info script]]]
+################################################################################
+# Pins
+################################################################################
+
+set __pins [get_terminals -quiet]
+if {[sizeof_collection $__pins] > 0} {
+set __termShapes [get_shapes -of_objects [get_terminals * -quiet] -quiet]
+if {[sizeof_collection $__termShapes] > 0} {
+remove_shapes $__termShapes -force
+}
+set __termVias [get_vias -of_objects [get_terminals * -quiet] -quiet]
+if {[sizeof_collection $__termVias] > 0} {
+remove_vias $__termVias -force
+}
+set __termShapePatterns [get_shape_patterns -of_objects [get_terminals * -quiet] -quiet]
+if {[sizeof_collection $__termShapePatterns] > 0} {
+remove_shape_patterns $__termShapePatterns
+}
+}
+
################################################################################
# Read DEF
################################################################################
@@ -21,130 +41,324 @@ set cellInst [get_cells { \
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R0
-set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 390.0600 \
+set_attribute -quiet -objects $cellInst -name origin -value { 479.5000 160.0000 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
+ }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
+ }
set cellInst [get_cells { \
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R0
-set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 618.3400 \
+set_attribute -quiet -objects $cellInst -name origin -value { 776.5000 160.0000 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
+ }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
+ }
set cellInst [get_cells { \
u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
}]
set_attribute -quiet -objects $cellInst -name orientation -value R0
-set_attribute -quiet -objects $cellInst -name origin -value { 120.0000 120.0000 \
+set_attribute -quiet -objects $cellInst -name origin -value { 160.0000 160.0000 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 440.7200 770.0650 \
+set_attribute -quiet -objects $cellInst -name origin -value { 480.6600 438.9100 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[0].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 761.3800 770.0650 \
+set_attribute -quiet -objects $cellInst -name origin -value { 816.3200 438.9100 \
}
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[1].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1082.0400 \
- 770.0650 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1151.9800 \
+ 438.9100 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[2].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1402.7000 \
- 770.0650 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1487.6400 \
+ 430.9100 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[3].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 480.6600 \
+ 1824.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 816.3200 \
+ 1824.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 1082.0400 \
- 759.6350 }
+set_attribute -quiet -objects $cellInst -name origin -value { 160.0000 \
+ 1771.1800 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[4].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 761.3800 759.6350 \
- }
+set_attribute -quiet -objects $cellInst -name origin -value { 495.6600 \
+ 1771.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1151.9800 \
+ 1824.1800 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[5].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }]
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 1487.6400 \
+ 1824.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 440.7200 759.6350 \
- }
+set_attribute -quiet -objects $cellInst -name origin -value { 831.3200 \
+ 1771.1800 }
set_attribute -quiet -objects $cellInst -name status -value placed
create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k }
create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/g_srams[6].u_sram_32b_32k }
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_0 }]
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N }]
set_attribute -quiet -objects $cellInst -name orientation -value R270
-set_attribute -quiet -objects $cellInst -name origin -value { 1402.7000 \
- 758.0750 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1166.9800 \
+ 1767.1800 }
set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N }
set cellInst [get_cells { \
- u_top_sram_chiplet/u_SRAM_wrapper/u_SRAM/u_sram_32b_16k_1 }]
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k }]
set_attribute -quiet -objects $cellInst -name orientation -value R90
-set_attribute -quiet -objects $cellInst -name origin -value { 1574.8800 \
- 771.6250 }
+set_attribute -quiet -objects $cellInst -name origin -value { 1823.3000 \
+ 1824.1800 }
set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 1502.6400 \
+ 1767.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 1502.6400 \
+ 1070.5450 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 }]
+set_attribute -quiet -objects $cellInst -name orientation -value R90
+set_attribute -quiet -objects $cellInst -name origin -value { 2010.4800 \
+ 1824.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0 }
+
+set cellInst [get_cells { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 }]
+set_attribute -quiet -objects $cellInst -name orientation -value R270
+set_attribute -quiet -objects $cellInst -name origin -value { 1838.3000 \
+ 1767.1800 }
+set_attribute -quiet -objects $cellInst -name status -value placed
+create_keepout_margin -type hard -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 }
+create_keepout_margin -type soft -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 }
+create_keepout_margin -type hard_macro -outer { 1.0000 1.0000 1.0000 1.0000 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 }
+create_keepout_margin -type routing_blockage -outer { 1.0000 1.0000 1.0000 \
+ 1.0000 } -layers { M1 VIA1 M2 VIA2 } { \
+ u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1 }
################################################################################
@@ -152,20 +366,178 @@ set_attribute -quiet -objects $cellInst -name status -value placed
################################################################################
+################################################################################
+# Bounds and user attributes of bound shapes
+################################################################################
+
+remove_bounds -all
+
+
+################################################################################
+# User attributes of bounds
+################################################################################
+
+
+################################################################################
+# Pin guides
+################################################################################
+
+remove_pin_guides -all
+
+
+################################################################################
+# Module Boundaries
+################################################################################
+
+set hbCells [get_cells -quiet -filter hierarchy_type==boundary -hierarchical]
+if [sizeof_collection $hbCells] {
+ set_cell_hierarchy_type -type normal $hbCells
+}
+
+set_cell_hierarchy_type -boundary { {725.7711 1679.4784} {2010.9400 2479.6000} \
+ } -type boundary u_top_sram_chiplet/u_SRAM_wrapper_2
+set_cell_hierarchy_type -boundary { {160.0000 160.0000} {1595.5097 887.4354} } \
+ -type boundary u_top_sram_chiplet/u_SRAM_wrapper_3
+
+################################################################################
+# Bump regions
+################################################################################
+
+remove_bump_regions -all
+
+remove_pseudo_tsv_defs -all
+
+remove_bump_regions -all
+
+remove_bump_region_patterns -all
+
+################################################################################
+# set attributes of pseudo bumps
+################################################################################
+
+################################################################################
+# set attributes of pseudo tsvs
+################################################################################
+
+################################################################################
+# User attributes of bump region
+################################################################################
+
################################################################################
# I/O guides
################################################################################
remove_io_guides -all
+create_io_guide -name main_io.top -side top -line { {110.0000 2639.6000} \
+ 1950.9400 } -offset {0.0000 0.0000} -pad_cells { \
+ TLX_data_tdata[0].u_TLX_IN_data_fwd_tdata u_PAD_VDDIO_top \
+ TLX_data_tdata[1].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[2].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[3].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[4].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[5].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[6].u_TLX_IN_data_fwd_tdata u_PAD_IN_FWD_CLK u_PAD_VSSIO_top \
+ TLX_data_tdata[7].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[8].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[9].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[10].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[11].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[12].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[13].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[14].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[15].u_TLX_IN_data_fwd_tdata u_PAD_TLX_IN_flow_fwd_0_tdata_1 \
+ TLX_data_tdata[0].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[1].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[2].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[3].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[4].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[5].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[6].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[8].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[9].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[10].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[11].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[12].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[13].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[14].u_TLX_IN_data_rev_tdata }
+create_io_guide -name main_io.bottom -side bottom -line { {2060.9400 0.0000} \
+ 1950.9400 } -offset {0.0000 0.0000} -pad_cells { \
+ TLX_data_tdata[8].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[9].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[10].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[11].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[12].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[13].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[14].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[0].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[1].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[2].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[3].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[4].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[5].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[6].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[8].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[9].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[10].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[11].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[12].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[13].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[14].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[15].u_TLX_data_fwd_1_tdata u_PAD_TLX_flow_fwd_1_tdata_1 \
+ TLX_data_tdata[0].u_TLX_data_fwd_1_tdata u_PAD_VDDIO_bottom \
+ TLX_data_tdata[1].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[2].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[3].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[4].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[5].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[6].u_TLX_data_fwd_1_tdata u_PAD_OUT_FWD_CLK \
+ u_PAD_VSSIO_bottom TLX_data_tdata[7].u_TLX_data_fwd_1_tdata }
+create_io_guide -name main_io.left -side left -line { {0.0000 110.0000} \
+ 2419.6000 } -offset {0.0000 0.0000} -pad_cells { \
+ u_PAD_TLX_IN_data_fwd_0_tready u_PAD_TLX_IN_flow_fwd_0_tready \
+ u_PAD_TLX_IN_flow_fwd_0_tdata_0 u_PAD_VDD_top \
+ u_PAD_TLX_IN_data_rev_0_tready u_PAD_IN_REV_CLK \
+ u_PAD_TLX_IN_flow_rev_0_tready u_PAD_TLX_IN_flow_rev_0_tdata_0 \
+ u_PAD_TLX_IN_flow_rev_0_tdata_1 u_PAD_VDD_left u_PAD_VDDIO_POC_left \
+ u_PAD_VSSIO_left u_PAD_DL_FWD_RESETn u_PAD_aRESETn u_PAD_VSS_left \
+ u_PAD_REF_CLK u_PAD_AGNDHV_left u_PAD_AGND_left u_PAD_AVDD_left \
+ u_PAD_AVDDHV_left u_PAD_TLX_flow_rev_1_tready u_PAD_TLX_flow_rev_1_tdata_0 \
+ u_PAD_TLX_flow_rev_1_tdata_1 u_PAD_VDD_bottom u_PAD_TLX_data_rev_1_tready \
+ u_PAD_OUT_REV_CLK u_PAD_TLX_flow_fwd_1_tready u_PAD_TLX_flow_fwd_1_tdata_0 \
+ u_PAD_TLX_data_fwd_1_tready }
+create_io_guide -name main_io.right -side right -line { {2170.9400 2529.6000} \
+ 2419.6000 } -offset {0.0000 0.0000} -pad_cells { \
+ u_PAD_TLX_IN_data_fwd_0_tvalid u_PAD_TLX_IN_flow_fwd_0_tvalid \
+ u_PAD_PLL_LOCK_i TLX_data_tdata[7].u_TLX_IN_data_rev_tdata \
+ u_PAD_TLX_IN_data_rev_0_tvalid u_PAD_VSS_top \
+ TLX_data_tdata[15].u_TLX_IN_data_rev_tdata u_PAD_TLX_IN_flow_rev_0_tdata_2 \
+ u_PAD_TLX_IN_flow_rev_0_tvalid u_PAD_VSS_right \
+ gen_addr_sel[0].u_PAD_addr_sel gen_addr_sel[1].u_PAD_addr_sel \
+ gen_addr_sel[2].u_PAD_addr_sel gen_addr_sel[3].u_PAD_addr_sel \
+ u_PAD_VDD_right u_PAD_VDDIO_right u_PAD_VSSIO_right \
+ TLX_data_tdata[15].u_TLX_data_rev_1_tdata u_PAD_TLX_flow_rev_1_tdata_2 \
+ u_PAD_TLX_flow_rev_1_tvalid TLX_data_tdata[7].u_TLX_data_rev_1_tdata \
+ u_PAD_TLX_data_rev_1_tvalid u_PAD_VSS_bottom u_PAD_TLX_flow_fwd_1_tvalid \
+ u_PAD_PLL_LOCK_o u_PAD_TLX_data_fwd_1_tvalid }
################################################################################
# User attributes of I/O guides
################################################################################
+################################################################################
+# Terminals/shapes/vias of ports with user attributes
+################################################################################
+
+################################################################################
+# User attributes of ports
+################################################################################
+
+
################################################################################
# User attributes of current block
################################################################################
+set_attribute [current_design] expanded_util 0.19
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
index cbb777bcfa121c92b0b1a4ca12688e25069b47c3..8f9dab4d46dc651d8babef23a2729c98dffe09fa 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/init_placement.tcl
@@ -1,7 +1,15 @@
+current_corner default
set_parasitic_parameters -early_spec cbest -early_temperature -40 -late_spec cworst -late_temperature 125 -library sram_chiplet.dlib
-set_operating_conditions -max_library cln28ht -max ssg_cworstt_max_0p81v_125c -min_library cln28ht -min ffg_cbestt_min_0p99v_m40c
-set_temperature -40 -min 125 -corners default
-set_voltage 0.99 -min 0.81 -corners default
+set_operating_conditions -max_library cln28ht -max ffg_cbestt_min_0p99v_m40c -min_library cln28ht -min ssg_cworstt_max_0p81v_125c
+set_process_number -early 1 -late 1 -corners default
+set_temperature 125 -min -40 -corners default
+set_voltage 0.81 -min 0.99 -corners default
+
+set_voltage 0.99 -min 0.81 -corners default -object_list [list [get_supply_nets VDD] [get_supply_nets AVDD]]
+set_voltage 1.98 -min 1.62 -corners default -object_list [list [get_supply_nets AVDDHV]]
+set_voltage 0.00 -corners default -object_list [list [get_supply_nets VSS] [get_supply_nets AGND]]
+
+
redirect -tee -file ./precompile_checks.log {compile_fusion -check_only}
@@ -15,7 +23,13 @@ change_selection [get_cells u_top_sram_chiplet/u_slave_pwd_M1_m_tlx]
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_slave_pwd_M1_m_tlx}]
change_selection [get_cells u_top_sram_chiplet/u_pl_fwd_M1_m_tlx_m]
explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_pl_fwd_M1_m_tlx_m}]
-change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper]
-explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper}]
+change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper_0]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper_0}]
+change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper_1]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper_1}]
+change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper_2]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper_2}]
+change_selection [get_cells u_top_sram_chiplet/u_SRAM_wrapper_3]
+explore_logic_hierarchy -create_module_boundary -nested -cell [get_cells -design [current_block] {u_top_sram_chiplet/u_SRAM_wrapper_3}]
explore_logic_hierarchy -place -rectangular
save_lib sram_chiplet.dlib
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/io_plan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/io_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..407e1fcb7496cafc49312458220975f07a60bfbd
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/io_plan.tcl
@@ -0,0 +1,289 @@
+create_bump_array -name bump_array -lib_cell PAD80MTB_EU -origin {36.850 100.000} -delta {167 167}
+
+remove_io_guides -all
+
+# Top IO Guide
+create_io_guide -name {main_io.top} -side top -line {{110.000 2639.600} 1950.94} -offset {0.000 0.000} -pad_cells [list \
+ TLX_data_tdata[0].u_TLX_IN_data_fwd_tdata \
+ u_PAD_VDDIO_top \
+ TLX_data_tdata[1].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[2].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[3].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[4].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[5].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[6].u_TLX_IN_data_fwd_tdata \
+ u_PAD_IN_FWD_CLK \
+ u_PAD_VSSIO_top \
+ TLX_data_tdata[7].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[8].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[9].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[10].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[11].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[12].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[13].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[14].u_TLX_IN_data_fwd_tdata \
+ TLX_data_tdata[15].u_TLX_IN_data_fwd_tdata \
+ u_PAD_TLX_IN_flow_fwd_0_tdata_1 \
+ TLX_data_tdata[0].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[1].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[2].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[3].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[4].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[5].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[6].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[8].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[9].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[10].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[11].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[12].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[13].u_TLX_IN_data_rev_tdata \
+ TLX_data_tdata[14].u_TLX_IN_data_rev_tdata ]
+
+create_io_guide -name {main_io.bottom} -side bottom -line {{2060.940 0.000} 1950.94} -offset {0.000 0.000} -pad_cells [list \
+ TLX_data_tdata[8].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[9].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[10].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[11].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[12].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[13].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[14].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[0].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[1].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[2].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[3].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[4].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[5].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[6].u_TLX_data_rev_1_tdata \
+ TLX_data_tdata[8].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[9].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[10].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[11].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[12].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[13].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[14].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[15].u_TLX_data_fwd_1_tdata \
+ u_PAD_TLX_flow_fwd_1_tdata_1 \
+ TLX_data_tdata[0].u_TLX_data_fwd_1_tdata \
+ u_PAD_VDDIO_bottom \
+ TLX_data_tdata[1].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[2].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[3].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[4].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[5].u_TLX_data_fwd_1_tdata \
+ TLX_data_tdata[6].u_TLX_data_fwd_1_tdata \
+ u_PAD_OUT_FWD_CLK \
+ u_PAD_VSSIO_bottom \
+ TLX_data_tdata[7].u_TLX_data_fwd_1_tdata ]
+
+create_io_guide -name {main_io.left} -side left -line {{0.000 110.000} 2419.6} -offset {0.000 0.000} -pad_cells [list \
+ u_PAD_TLX_IN_data_fwd_0_tready \
+ u_PAD_TLX_IN_flow_fwd_0_tready \
+ u_PAD_TLX_IN_flow_fwd_0_tdata_0 \
+ u_PAD_VDD_top \
+ u_PAD_TLX_IN_data_rev_0_tready \
+ u_PAD_IN_REV_CLK \
+ u_PAD_TLX_IN_flow_rev_0_tready \
+ u_PAD_TLX_IN_flow_rev_0_tdata_0 \
+ u_PAD_TLX_IN_flow_rev_0_tdata_1 \
+ u_PAD_VDD_left \
+ u_PAD_VDDIO_POC_left \
+ u_PAD_VSSIO_left \
+ u_PAD_DL_FWD_RESETn \
+ u_PAD_aRESETn \
+ u_PAD_VSS_left \
+ u_PAD_REF_CLK \
+ u_PAD_AGNDHV_left \
+ u_PAD_AGND_left \
+ u_PAD_AVDD_left \
+ u_PAD_AVDDHV_left \
+ u_PAD_TLX_flow_rev_1_tready \
+ u_PAD_TLX_flow_rev_1_tdata_0 \
+ u_PAD_TLX_flow_rev_1_tdata_1 \
+ u_PAD_VDD_bottom \
+ u_PAD_TLX_data_rev_1_tready \
+ u_PAD_OUT_REV_CLK \
+ u_PAD_TLX_flow_fwd_1_tready \
+ u_PAD_TLX_flow_fwd_1_tdata_0 \
+ u_PAD_TLX_data_fwd_1_tready ]
+
+create_io_guide -name {main_io.right} -side right -line {{2170.940 2529.600} 2419.6} -offset {0.000 0.000} -pad_cells [list \
+ u_PAD_TLX_IN_data_fwd_0_tvalid \
+ u_PAD_TLX_IN_flow_fwd_0_tvalid \
+ u_PAD_PLL_LOCK_i \
+ TLX_data_tdata[7].u_TLX_IN_data_rev_tdata \
+ u_PAD_TLX_IN_data_rev_0_tvalid \
+ u_PAD_VSS_top \
+ TLX_data_tdata[15].u_TLX_IN_data_rev_tdata \
+ u_PAD_TLX_IN_flow_rev_0_tdata_2 \
+ u_PAD_TLX_IN_flow_rev_0_tvalid \
+ u_PAD_VSS_right \
+ u_PAD_VDD_top_right \
+ gen_addr_sel[0].u_PAD_addr_sel \
+ gen_addr_sel[1].u_PAD_addr_sel \
+ gen_addr_sel[2].u_PAD_addr_sel \
+ gen_addr_sel[3].u_PAD_addr_sel \
+ u_PAD_VDD_right \
+ u_PAD_VDDIO_right \
+ u_PAD_VSSIO_right \
+ TLX_data_tdata[15].u_TLX_data_rev_1_tdata \
+ u_PAD_TLX_flow_rev_1_tdata_2 \
+ u_PAD_TLX_flow_rev_1_tvalid \
+ TLX_data_tdata[7].u_TLX_data_rev_1_tdata \
+ u_PAD_TLX_data_rev_1_tvalid \
+ u_PAD_VSS_bottom \
+ u_PAD_TLX_flow_fwd_1_tvalid \
+ u_PAD_PLL_LOCK_o \
+ u_PAD_TLX_data_fwd_1_tvalid ]
+
+create_io_corner_cell {main_io.left main_io.top} -reference_cell PCORNER_G
+create_io_corner_cell {main_io.bottom main_io.left} -reference_cell PCORNER_G
+create_io_corner_cell {main_io.top main_io.right} -reference_cell PCORNER_G
+create_io_corner_cell {main_io.right main_io.bottom} -reference_cell PCORNER_G
+
+
+# Top IO
+create_matching_type -name "TLX_IN_fwd_tready" -uniquify 0 [list [get_cells bump_array_14_0] [get_pins u_PAD_TLX_IN_data_fwd_0_tready/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata0" -uniquify 0 [list [get_cells bump_array_14_1] [get_pins TLX_data_tdata[0].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "VDDIO_top" -uniquify 0 [list [get_cells bump_array_14_2] [get_pins u_PAD_VDDIO_top/VDDPST]]
+create_matching_type -name "TLX_IN_fwd_tdata1" -uniquify 0 [list [get_cells bump_array_14_3] [get_pins TLX_data_tdata[1].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata2" -uniquify 0 [list [get_cells bump_array_14_4] [get_pins TLX_data_tdata[2].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata3" -uniquify 0 [list [get_cells bump_array_14_5] [get_pins TLX_data_tdata[3].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata4" -uniquify 0 [list [get_cells bump_array_14_6] [get_pins TLX_data_tdata[4].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata5" -uniquify 0 [list [get_cells bump_array_14_7] [get_pins TLX_data_tdata[5].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata6" -uniquify 0 [list [get_cells bump_array_14_8] [get_pins TLX_data_tdata[6].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_clk" -uniquify 0 [list [get_cells bump_array_14_9] [get_pins u_PAD_IN_FWD_CLK/PAD]]
+create_matching_type -name "VSSIO_top" -uniquify 0 [list [get_cells bump_array_14_10] [get_pins u_PAD_VSSIO_top/VSSPST]]
+create_matching_type -name "TLX_IN_fwd_tdata7" -uniquify 0 [list [get_cells bump_array_14_11] [get_pins TLX_data_tdata[7].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tvalid" -uniquify 0 [list [get_cells bump_array_14_12] [get_pins u_PAD_TLX_IN_data_fwd_0_tvalid/PAD]]
+
+create_matching_type -name "TLX_IN_fwd_flw_tready" -uniquify 0 [list [get_cells bump_array_13_0] [get_pins u_PAD_TLX_IN_flow_fwd_0_tready/PAD]]
+create_matching_type -name "TLX_IN_fwd_flw_tdata0" -uniquify 0 [list [get_cells bump_array_13_1] [get_pins u_PAD_TLX_IN_flow_fwd_0_tdata_0/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata8" -uniquify 0 [list [get_cells bump_array_13_2] [get_pins TLX_data_tdata[8].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata9" -uniquify 0 [list [get_cells bump_array_13_3] [get_pins TLX_data_tdata[9].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata10" -uniquify 0 [list [get_cells bump_array_13_4] [get_pins TLX_data_tdata[10].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata11" -uniquify 0 [list [get_cells bump_array_13_5] [get_pins TLX_data_tdata[11].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata12" -uniquify 0 [list [get_cells bump_array_13_6] [get_pins TLX_data_tdata[12].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata13" -uniquify 0 [list [get_cells bump_array_13_7] [get_pins TLX_data_tdata[13].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata14" -uniquify 0 [list [get_cells bump_array_13_8] [get_pins TLX_data_tdata[14].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_tdata15" -uniquify 0 [list [get_cells bump_array_13_9] [get_pins TLX_data_tdata[15].u_TLX_IN_data_fwd_tdata/PAD]]
+create_matching_type -name "TLX_IN_fwd_flw_tdata1" -uniquify 0 [list [get_cells bump_array_13_10] [get_pins u_PAD_TLX_IN_flow_fwd_0_tdata_1/PAD]]
+create_matching_type -name "TLX_IN_fwd_flw_tvalid" -uniquify 0 [list [get_cells bump_array_13_11] [get_pins u_PAD_TLX_IN_flow_fwd_0_tvalid/PAD]]
+create_matching_type -name "PLL_LCK_i" -uniquify 0 [list [get_cells bump_array_13_12] [get_pins u_PAD_PLL_LOCK_i/PAD]]
+
+create_matching_type -name "VDD_top" -uniquify 0 [list [get_cells bump_array_12_0] [get_pins u_PAD_VDD_top/VDD]]
+create_matching_type -name "TLX_IN_rev_tready" -uniquify 0 [list [get_cells bump_array_12_1] [get_pins u_PAD_TLX_IN_data_rev_0_tready/PAD]]
+create_matching_type -name "TLX_IN_rev_clk" -uniquify 0 [list [get_cells bump_array_12_2] [get_pins u_PAD_IN_REV_CLK/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata0" -uniquify 0 [list [get_cells bump_array_12_3] [get_pins TLX_data_tdata[0].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata1" -uniquify 0 [list [get_cells bump_array_12_4] [get_pins TLX_data_tdata[1].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata2" -uniquify 0 [list [get_cells bump_array_12_5] [get_pins TLX_data_tdata[2].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata3" -uniquify 0 [list [get_cells bump_array_12_6] [get_pins TLX_data_tdata[3].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata4" -uniquify 0 [list [get_cells bump_array_12_7] [get_pins TLX_data_tdata[4].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata5" -uniquify 0 [list [get_cells bump_array_12_8] [get_pins TLX_data_tdata[5].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata6" -uniquify 0 [list [get_cells bump_array_12_9] [get_pins TLX_data_tdata[6].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata7" -uniquify 0 [list [get_cells bump_array_12_10] [get_pins TLX_data_tdata[7].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tvalid" -uniquify 0 [list [get_cells bump_array_12_11] [get_pins u_PAD_TLX_IN_data_rev_0_tvalid/PAD]]
+create_matching_type -name "VSS_top" -uniquify 0 [list [get_cells bump_array_12_12] [get_pins u_PAD_VSS_top/VSS]]
+
+create_matching_type -name "TLX_IN_rev_flw_tready" -uniquify 0 [list [get_cells bump_array_11_0] [get_pins u_PAD_TLX_IN_flow_rev_0_tready/PAD]]
+create_matching_type -name "TLX_IN_rev_flw_tdata0" -uniquify 0 [list [get_cells bump_array_11_1] [get_pins u_PAD_TLX_IN_flow_rev_0_tdata_0/PAD]]
+create_matching_type -name "TLX_IN_rev_flw_tdata1" -uniquify 0 [list [get_cells bump_array_11_2] [get_pins u_PAD_TLX_IN_flow_rev_0_tdata_1/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata8" -uniquify 0 [list [get_cells bump_array_11_3] [get_pins TLX_data_tdata[8].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata9" -uniquify 0 [list [get_cells bump_array_11_4] [get_pins TLX_data_tdata[9].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata10" -uniquify 0 [list [get_cells bump_array_11_5] [get_pins TLX_data_tdata[10].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata11" -uniquify 0 [list [get_cells bump_array_11_6] [get_pins TLX_data_tdata[11].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata12" -uniquify 0 [list [get_cells bump_array_11_7] [get_pins TLX_data_tdata[12].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata13" -uniquify 0 [list [get_cells bump_array_11_8] [get_pins TLX_data_tdata[13].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata14" -uniquify 0 [list [get_cells bump_array_11_9] [get_pins TLX_data_tdata[14].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_tdata15" -uniquify 0 [list [get_cells bump_array_11_10] [get_pins TLX_data_tdata[15].u_TLX_IN_data_rev_tdata/PAD]]
+create_matching_type -name "TLX_IN_rev_flw_tdata2" -uniquify 0 [list [get_cells bump_array_11_11] [get_pins u_PAD_TLX_IN_flow_rev_0_tdata_2/PAD]]
+create_matching_type -name "TLX_IN_rev_flw_tvalid" -uniquify 0 [list [get_cells bump_array_11_12] [get_pins u_PAD_TLX_IN_flow_rev_0_tvalid/PAD]]
+
+# Bottom IO
+create_matching_type -name "TLX_OUT_fwd_tready" -uniquify 0 [list [get_cells bump_array_0_0] [get_pins u_PAD_TLX_data_fwd_1_tready/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata0" -uniquify 0 [list [get_cells bump_array_0_1] [get_pins TLX_data_tdata[0].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "VDDIO_bottom" -uniquify 0 [list [get_cells bump_array_0_2] [get_pins u_PAD_VDDIO_bottom/VDDPST]]
+create_matching_type -name "TLX_OUT_fwd_tdata1" -uniquify 0 [list [get_cells bump_array_0_3] [get_pins TLX_data_tdata[1].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata2" -uniquify 0 [list [get_cells bump_array_0_4] [get_pins TLX_data_tdata[2].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata3" -uniquify 0 [list [get_cells bump_array_0_5] [get_pins TLX_data_tdata[3].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata4" -uniquify 0 [list [get_cells bump_array_0_6] [get_pins TLX_data_tdata[4].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata5" -uniquify 0 [list [get_cells bump_array_0_7] [get_pins TLX_data_tdata[5].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata6" -uniquify 0 [list [get_cells bump_array_0_8] [get_pins TLX_data_tdata[6].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_FWD_CLK" -uniquify 0 [list [get_cells bump_array_0_9] [get_pins u_PAD_OUT_FWD_CLK/PAD]]
+create_matching_type -name "VSSIO_bottom" -uniquify 0 [list [get_cells bump_array_0_10] [get_pins u_PAD_VSSIO_bottom/VSSPST]]
+create_matching_type -name "TLX_OUT_fwd_tdata7" -uniquify 0 [list [get_cells bump_array_0_11] [get_pins TLX_data_tdata[7].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tvalid" -uniquify 0 [list [get_cells bump_array_0_12] [get_pins u_PAD_TLX_data_fwd_1_tvalid/PAD]]
+
+create_matching_type -name "TLX_OUT_fwd_flw_tready" -uniquify 0 [list [get_cells bump_array_1_0] [get_pins u_PAD_TLX_flow_fwd_1_tready/PAD]]
+create_matching_type -name "TLX_OUT_fwd_flw_tdata0" -uniquify 0 [list [get_cells bump_array_1_1] [get_pins u_PAD_TLX_flow_fwd_1_tdata_0/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata8" -uniquify 0 [list [get_cells bump_array_1_2] [get_pins TLX_data_tdata[8].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata9" -uniquify 0 [list [get_cells bump_array_1_3] [get_pins TLX_data_tdata[9].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata10" -uniquify 0 [list [get_cells bump_array_1_4] [get_pins TLX_data_tdata[10].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata11" -uniquify 0 [list [get_cells bump_array_1_5] [get_pins TLX_data_tdata[11].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata12" -uniquify 0 [list [get_cells bump_array_1_6] [get_pins TLX_data_tdata[12].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata13" -uniquify 0 [list [get_cells bump_array_1_7] [get_pins TLX_data_tdata[13].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata14" -uniquify 0 [list [get_cells bump_array_1_8] [get_pins TLX_data_tdata[14].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_tdata15" -uniquify 0 [list [get_cells bump_array_1_9] [get_pins TLX_data_tdata[15].u_TLX_data_fwd_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_fwd_flw_tdata1" -uniquify 0 [list [get_cells bump_array_1_10] [get_pins u_PAD_TLX_flow_fwd_1_tdata_1/PAD]]
+create_matching_type -name "TLX_OUT_fwd_flw_tvalid" -uniquify 0 [list [get_cells bump_array_1_11] [get_pins u_PAD_TLX_flow_fwd_1_tvalid/PAD]]
+create_matching_type -name "PLL_LCK_o" -uniquify 0 [list [get_cells bump_array_1_12] [get_pins u_PAD_PLL_LOCK_o/PAD]]
+
+create_matching_type -name "VDD_bottom" -uniquify 0 [list [get_cells bump_array_2_0] [get_pins u_PAD_VDD_bottom/VDD]]
+create_matching_type -name "TLX_OUT_rev_tready" -uniquify 0 [list [get_cells bump_array_2_1] [get_pins u_PAD_TLX_data_rev_1_tready/PAD]]
+create_matching_type -name "TLX_OUT_REV_CLK" -uniquify 0 [list [get_cells bump_array_2_2] [get_pins u_PAD_OUT_REV_CLK/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata0" -uniquify 0 [list [get_cells bump_array_2_3] [get_pins TLX_data_tdata[0].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata1" -uniquify 0 [list [get_cells bump_array_2_4] [get_pins TLX_data_tdata[1].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata2" -uniquify 0 [list [get_cells bump_array_2_5] [get_pins TLX_data_tdata[2].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata3" -uniquify 0 [list [get_cells bump_array_2_6] [get_pins TLX_data_tdata[3].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata4" -uniquify 0 [list [get_cells bump_array_2_7] [get_pins TLX_data_tdata[4].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata5" -uniquify 0 [list [get_cells bump_array_2_8] [get_pins TLX_data_tdata[5].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata6" -uniquify 0 [list [get_cells bump_array_2_9] [get_pins TLX_data_tdata[6].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata7" -uniquify 0 [list [get_cells bump_array_2_10] [get_pins TLX_data_tdata[7].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tvalid" -uniquify 0 [list [get_cells bump_array_2_11] [get_pins u_PAD_TLX_data_rev_1_tvalid/PAD]]
+create_matching_type -name "VSS_bottom" -uniquify 0 [list [get_cells bump_array_2_12] [get_pins u_PAD_VSS_bottom/VSS]]
+
+create_matching_type -name "TLX_OUT_rev_flw_tready" -uniquify 0 [list [get_cells bump_array_3_0] [get_pins u_PAD_TLX_flow_rev_1_tready/PAD]]
+create_matching_type -name "TLX_OUT_rev_flw_tdata0" -uniquify 0 [list [get_cells bump_array_3_1] [get_pins u_PAD_TLX_flow_rev_1_tdata_0/PAD]]
+create_matching_type -name "TLX_OUT_rev_flw_tdata1" -uniquify 0 [list [get_cells bump_array_3_2] [get_pins u_PAD_TLX_flow_rev_1_tdata_1/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata8" -uniquify 0 [list [get_cells bump_array_3_3] [get_pins TLX_data_tdata[8].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata9" -uniquify 0 [list [get_cells bump_array_3_4] [get_pins TLX_data_tdata[9].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata10" -uniquify 0 [list [get_cells bump_array_3_5] [get_pins TLX_data_tdata[10].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata11" -uniquify 0 [list [get_cells bump_array_3_6] [get_pins TLX_data_tdata[11].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata12" -uniquify 0 [list [get_cells bump_array_3_7] [get_pins TLX_data_tdata[12].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata13" -uniquify 0 [list [get_cells bump_array_3_8] [get_pins TLX_data_tdata[13].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata14" -uniquify 0 [list [get_cells bump_array_3_9] [get_pins TLX_data_tdata[14].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_tdata15" -uniquify 0 [list [get_cells bump_array_3_10] [get_pins TLX_data_tdata[15].u_TLX_data_rev_1_tdata/PAD]]
+create_matching_type -name "TLX_OUT_rev_flw_tdata2" -uniquify 0 [list [get_cells bump_array_3_11] [get_pins u_PAD_TLX_flow_rev_1_tdata_2/PAD]]
+create_matching_type -name "TLX_OUT_rev_flw_tvalid" -uniquify 0 [list [get_cells bump_array_3_12] [get_pins u_PAD_TLX_flow_rev_1_tvalid/PAD]]
+
+
+
+
+# Left IO
+create_matching_type -name "VDD_left" -uniquify 0 [list [get_cells bump_array_10_0] [get_pins u_PAD_VDD_left/VDD]]
+create_matching_type -name "VDDIO_left" -uniquify 0 [list [get_cells bump_array_9_0] [get_pins u_PAD_VDDIO_POC_left/VDDPST]]
+create_matching_type -name "VSSIO_left" -uniquify 0 [list [get_cells bump_array_8_0] [get_pins u_PAD_VSSIO_left/VSSPST]]
+create_matching_type -name "TLX_reset" -uniquify 0 [list [get_cells bump_array_7_0] [get_pins u_PAD_DL_FWD_RESETn/PAD]]
+create_matching_type -name "aRESET" -uniquify 0 [list [get_cells bump_array_6_0] [get_pins u_PAD_aRESETn/PAD]]
+create_matching_type -name "VSS_left" -uniquify 0 [list [get_cells bump_array_5_0] [get_pins u_PAD_VSS_left/VSS]]
+create_matching_type -name "REF_CLK" -uniquify 0 [list [get_cells bump_array_4_0] [get_pins u_PAD_REF_CLK/PAD]]
+
+create_matching_type -name "AGNDHV_left" -uniquify 0 [list [get_cells bump_array_7_1 ] [get_pins u_PAD_AGNDHV_left/AVSS]]
+create_matching_type -name "AGND_left" -uniquify 0 [list [get_cells bump_array_6_1 ] [get_pins u_PAD_AGND_left/AVSS]]
+create_matching_type -name "AVDD_left" -uniquify 0 [list [get_cells bump_array_5_1 ] [get_pins u_PAD_AVDD_left/AVDD]]
+create_matching_type -name "AVDDHV_left" -uniquify 0 [list [get_cells bump_array_4_1 ] [get_pins u_PAD_AVDDHV_left/AVDD]]
+
+
+# Right IO
+create_matching_type -name "VSS_right" -uniquify 0 [list [get_cells bump_array_10_12] [get_pins u_PAD_VSS_right/VSS]]
+create_matching_type -name "addr_sel0" -uniquify 0 [list [get_cells bump_array_9_12] [get_pins gen_addr_sel[0].u_PAD_addr_sel/PAD]]
+create_matching_type -name "addr_sel1" -uniquify 0 [list [get_cells bump_array_8_12] [get_pins gen_addr_sel[1].u_PAD_addr_sel/PAD]]
+create_matching_type -name "addr_sel2" -uniquify 0 [list [get_cells bump_array_7_12] [get_pins gen_addr_sel[2].u_PAD_addr_sel/PAD]]
+create_matching_type -name "addr_sel3" -uniquify 0 [list [get_cells bump_array_6_12] [get_pins gen_addr_sel[3].u_PAD_addr_sel/PAD]]
+create_matching_type -name "VDD_right" -uniquify 0 [list [get_cells bump_array_4_12] [get_pins u_PAD_VDD_right/VDD]]
+create_matching_type -name "VDD_top_right" -uniquify 0 [list [get_cells bump_array_10_11] [get_pins u_PAD_VDD_top_right/VDD]]
+create_matching_type -name "VDDIO_right" -uniquify 0 [list [get_cells bump_array_5_12] [get_pins u_PAD_VDDIO_right/VDDPST]]
+create_matching_type -name "VSSIO_right" -uniquify 0 [list [get_cells bump_array_7_11] [get_pins u_PAD_VSSIO_right/VSSPST]]
+
+
+
+place_io
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
index 407e63e1efc3bd7abbec1e5f5b8bab07c6034a2d..49abf6cbefe13baf22f80b6ba942d02cf856e411 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
@@ -1,16 +1,61 @@
connect_pg_net -automatic
create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -horizontal_spacing {2}\
- -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+ -vertical_layer M6 -vertical_width {4} -vertical_spacing {2} -nets {AGND AVDD AVDDHV VDD VSS}
-create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
- {{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
-create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
+# 320.66 SRAM width
+create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M6} {width: 4} {pitch: 30.566} {offset: 21.5}} \
+ {{horizontal_layer: M5} {width: 4} {pitch: 30} {offset: 20}}}
+create_pg_std_cell_conn_pattern std_pattern -layers {M2} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
-set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
-set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core
+set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS AVDD AVDDHV AGND}} {offset: {3 3}}} -core
+set_pg_strategy M5M6_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core -extension {{{stop : first_target}}}
set_pg_strategy std_cell_strat -core -pattern {{name: std_pattern} {nets: {VDD VSS}}}
compile_pg -strategies core_ring
-compile_pg -strategies M5M8_mesh
+compile_pg -strategies M5M6_mesh
compile_pg -strategies std_cell_strat
+
+set_app_options -name plan.pgroute.hmpin_connection_target_layers -value M6
+create_pg_macro_conn_pattern io_to_ring_h -pin_conn_type scattered_pin \
+ -pin_layers {M2} -layers {M2 M6} -width 1.41
+set_pg_strategy h_io_to_ring -macros [list u_PAD_VDD_left u_PAD_VDD_top u_PAD_VSS_top u_PAD_VSS_left u_PAD_VDD_right u_PAD_VDD_top_right u_PAD_VSS_right u_PAD_VDD_bottom u_PAD_VSS_bottom] \
+ -pattern {{name: io_to_ring_h}{nets: VDD VSS}}
+set_pg_strategy h_io_to_ring_a -macros [list u_PAD_AVDD_left u_PAD_AVDDHV_left u_PAD_AGND_left u_PAD_AGNDHV_left]\
+ -pattern {{name: io_to_ring_h}{nets: AVDD AVDDHV AGND}}
+
+compile_pg -strategies h_io_to_ring
+compile_pg -strategies h_io_to_ring_a
+
+set_app_options -name plan.pgroute.hmpin_connection_target_layers -value M7
+create_pg_macro_conn_pattern macro_to_ring -pin_conn_type scattered_pin \
+ -pin_layers {M5} -layers {M2 M6} -width 2.4
+set_pg_strategy PLL_pins -macros u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ -pattern {{name: macro_to_ring}{nets: AVDD AVDDHV AGND}}
+compile_pg -strategies PLL_pins -ignore_drc
+
+set_app_options -name plan.pgroute.hmpin_connection_target_layers -value M5
+create_pg_macro_conn_pattern macro_to_strap -pin_conn_type scattered_pin \
+ -pin_layers {M3} -layers {M2 M7} -width 2.5
+set_pg_strategy PLL_pins_top -macros u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL \
+ -pattern {{name: macro_to_strap}{nets: VDD VSS}}
+compile_pg -strategies PLL_pins_top -ignore_drc
+
+
+
+set_app_options -name plan.pgroute.hmpin_connection_target_layers -value M7
+create_pg_macro_conn_pattern TS_to_ring -pin_conn_type scattered_pin \
+ -pin_layers {M6} -layers {M2 M6} -width 4
+set_pg_strategy TS_pins -macros u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts \
+ -pattern {{name: TS_to_ring}{nets: AVDD VDD VSS}}
+compile_pg -strategies TS_pins
+
+set_pg_strategy PD_pins -macros u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd \
+ -pattern {{name: TS_to_ring}{nets: AVDD VDD VSS}}
+compile_pg -strategies PD_pins
+
+# insert_boundary_cells
+create_boundary_cells -left_boundary_cell [get_lib_cells {cln28ht/ENDCAPTIE3_A12PP140ZTS_C35}] -right_boundary_cell [get_lib_cells {cln28ht/ENDCAPTIE3_A12PP140ZTS_C35}]
+
+# tap cells
+create_tap_cells -distance 100.0000 -lib_cell [get_lib_cells {cln28ht/FILLTIE4_A12PP140ZTS_C35}]
\ No newline at end of file
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
index d379fd0b4fff0ded225d44da82670430f3fefb3a..60de66fc2ea537346cb222b48421f5651443b510 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/synopsys_lib_conversion.tcl
@@ -1,16 +1,36 @@
+## Paths Please Edit for your system
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+set standard_cell_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0
+set pmk_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0
+set ret_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_rklo_lvt_svt_c30_c35/r1p0
+
# Technology files
-set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
-set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.tf
-set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc9mcpp140z_tech.lef
+set cln28ht_tech_file $cln28ht_tech_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.tf
+set cln28ht_lef_file $cln28ht_tech_path/lef/1p8m_5x2z_utalrdl/sc12mcpp140z_tech.lef
# Standard Cell libraries
-set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
-set sc9mcpp140z_lef_file $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
-set sc9mcpp140z_gds_file $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
-set sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
-set sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
-set sc9mcpp140z_db_file_ff_0p99v_m40C $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
-set sc9mcpp140z_antenna_file $sc9mcpp140z_base_path/milkyway/1p8m_5x2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+set standard_cell_lef_file $standard_cell_base_path/lef/sc12mcpp140z_cln28ht_base_svt_c35.lef
+set standard_cell_gds_file $standard_cell_base_path/gds2/sc12mcpp140z_cln28ht_base_svt_c35.gds2
+set standard_cell_db_file_ss_0p81v_125C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set standard_cell_db_file_tt_0p90v_25C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_tt_ctypical_max_0p90v_25c.db
+set standard_cell_db_file_ff_0p99v_m40C $standard_cell_base_path/db/sc12mcpp140z_cln28ht_base_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set standard_cell_antenna_file $standard_cell_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_base_svt_c35_antenna.clf
+
+# Power Management Kit
+set pmk_lef_file $pmk_base_path/lef/sc12mcpp140z_cln28ht_pmk_svt_c35.lef
+set pmk_gds_file $pmk_base_path/gds2/sc12mcpp140z_cln28ht_pmk_svt_c35.gds2
+set pmk_db_file_ss_0p81v_125C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set pmk_db_file_tt_0p90v_25C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_tt_ctypical_max_0p90v_25c.db
+set pmk_db_file_ff_0p99v_m40C $pmk_base_path/db/sc12mcpp140z_cln28ht_pmk_svt_c35_ffg_cbestt_min_0p99v_m40c.db
+set pmk_antenna_file $pmk_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_pmk_svt_c35_antenna.clf
+
+# Retention Kit
+set ret_lef_file $ret_base_path/lef/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.lef
+set ret_gds_file $ret_base_path/gds2/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35.gds2
+set ret_db_file_ss_0p81v_125C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ssg_cworstt_max_0p81v_125c.db
+set ret_db_file_tt_0p90v_25C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_tt_ctypical_max_0p90v_25c.db
+set ret_db_file_ff_0p99v_m40C $ret_base_path/db/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_ffg_cbestt_min_0p99v_m40c.db
+set ret_antenna_file $ret_base_path/milkyway/1p8m_5x2z_utalrdl/sc12mcpp140z_cln28ht_rklo_lvt_svt_c30_c35_antenna.clf
# SRAM files (using Arm compiler)
set sram_32k_lef_file $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.lef
@@ -32,7 +52,16 @@ set sram_16k_db_file_ss_0p81v_125c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/
set sram_16k_db_file_tt_0p90v_25c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_tt_ctypical_0p90v_0p90v_25c.db
set sram_16k_db_file_ff_0p99v_m40c $env(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c.db
+# IO Paths
+set TSMC_28NM_PDK_PATH /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28
+set tphn28hpcpgv18_lef_file $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Back_End/lef/tphn28hpcpgv18_110a/mt_2/9lm/lef/tphn28hpcpgv18_9lm.lef
+set tphn28hpcpgv18_lib_path $TSMC_28NM_PDK_PATH/CMOS/HPC+/IO1.8V/iolib/STAGGERED/tphn28hpcpgv18_170d_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tphn28hpcpgv18_170a
+set IO_TT_0p9v_1p8v_25c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18tt0p9v1p8v25c.db
+set IO_FF_0p99v_1p98v_m40c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ffg0p99v1p98vm40c.db
+set IO_SS_0p81v_1p62v_125c_db $tphn28hpcpgv18_lib_path/tphn28hpcpgv18ssg0p81v1p62v125c.db
+set pad_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/cup/8m/8M_5X2Z/lef/tpbn28v_8lm.lef
+set bump_lef_file /home/dwn1c21/SoC-Labs/phys_ip/TSMC/28/iolib/tpbn28v_160a_FE/TSMCHOME/digital/Back_End/lef/tpbn28v_160a/fc/fc_eu/MTRDL/8m/8M_Z/lef/tpbn28v_8lm.lef
# Synopsys PLL files
set Synopsys_PLL_dir /home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro
set Synopsys_PLL_lef_file $Synopsys_PLL_dir/lef/5m4x0z/dwc_z19606ts_ns_merged.lef
@@ -60,23 +89,33 @@ set Synopsys_VM_lib_file $Synopsys_VM_dir/liberty/mr74140_wc_vmin_125c.lib
set Synopsys_VM_db_file $Synopsys_VM_dir/db/mr74140_wc_vmin_125c.db
set Synopsys_VM_gds_file $Synopsys_VM_dir/gdsii/mr74140_v1r1.gds
-create_fusion_lib -dbs [list $sc9mcpp140z_db_file_ss_0p81v_125C $sc9mcpp140z_db_file_tt_0p90v_25C $sc9mcpp140z_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $sc9mcpp140z_lef_file] -technology $cln28ht_tech_file cln28ht
+# Create standard cell fusion library
+create_fusion_lib -dbs [list $standard_cell_db_file_ss_0p81v_125C $standard_cell_db_file_tt_0p90v_25C $standard_cell_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $standard_cell_lef_file] -technology $cln28ht_tech_file cln28ht
save_fusion_lib cln28ht
-
close_fusion_lib cln28ht
+# Create Power Management Kit fusion library
+create_fusion_lib -dbs [list $pmk_db_file_ss_0p81v_125C $pmk_db_file_tt_0p90v_25C $pmk_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $pmk_lef_file] -technology $cln28ht_tech_file cln28ht_pmk
+save_fusion_lib cln28ht_pmk
+close_fusion_lib cln28ht_pmk
+
+# Create Retention fusion library
+create_fusion_lib -dbs [list $ret_db_file_ss_0p81v_125C $ret_db_file_tt_0p90v_25C $ret_db_file_ff_0p99v_m40C] -lefs [list $cln28ht_lef_file $ret_lef_file] -technology $cln28ht_tech_file cln28ht_ret
+save_fusion_lib cln28ht_ret
+close_fusion_lib cln28ht_ret
+
# 32K SRAM
read_lib $sram_32k_lib_file_ss_0p81v_125c
write_lib -output $sram_32k_db_file_ss_0p81v_125c -format db sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c
-close_lib sram_32b_32k_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
read_lib $sram_32k_lib_file_tt_0p90v_25c
write_lib -output $sram_32k_db_file_tt_0p90v_25c -format db sram_32b_32k_tt_ctypical_0p90v_0p90v_25c
-close_lib sram_32b_32k_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
read_lib $sram_32k_lib_file_ff_0p99v_m40c
write_lib -output $sram_32k_db_file_ff_0p99v_m40c -format db sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c
-close_lib sram_32b_32k_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
create_fusion_lib -dbs [list $sram_32k_db_file_ss_0p81v_125c $sram_32k_db_file_tt_0p90v_25c $sram_32k_db_file_ff_0p99v_m40c] -lefs $sram_32k_lef_file -technology $cln28ht_tech_file sram_32k
save_fusion_lib sram_32k
@@ -85,15 +124,15 @@ close_fusion_lib sram_32k
# 16K SRAM
read_lib $sram_16k_lib_file_ss_0p81v_125c
write_lib -output $sram_16k_db_file_ss_0p81v_125c -format db sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c
-close_lib sram_32b_16k_ssg_cworstt_0p81v_0p81v_125c
+close_lib -all
read_lib $sram_16k_lib_file_tt_0p90v_25c
write_lib -output $sram_16k_db_file_tt_0p90v_25c -format db sram_32b_16k_tt_ctypical_0p90v_0p90v_25c
-close_lib sram_32b_16k_tt_ctypical_0p90v_0p90v_25c
+close_lib -all
read_lib $sram_16k_lib_file_ff_0p99v_m40c
write_lib -output $sram_16k_db_file_ff_0p99v_m40c -format db sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c
-close_lib sram_32b_16k_ffg_cbestt_0p99v_0p99v_m40c
+close_lib -all
create_fusion_lib -dbs [list $sram_16k_db_file_ss_0p81v_125c $sram_16k_db_file_tt_0p90v_25c $sram_16k_db_file_ff_0p99v_m40c] -lefs $sram_16k_lef_file -technology $cln28ht_tech_file sram_16k
save_fusion_lib sram_16k
@@ -128,4 +167,18 @@ create_fusion_lib -dbs $Synopsys_VM_db_file -lefs $Synopsys_VM_lef_file -technol
save_fusion_lib Synopsys_VM
close_fusion_lib Synopsys_VM
+# IO Lib
+create_fusion_lib -dbs [list $IO_SS_0p81v_1p62v_125c_db $IO_TT_0p9v_1p8v_25c_db $IO_FF_0p99v_1p98v_m40c_db] -lefs $tphn28hpcpgv18_lef_file -technology $cln28ht_tech_file io_lib
+save_fusion_lib io_lib
+close_fusion_lib io_lib
+
+# Pad Libs
+create_fusion_lib -lefs $pad_lef_file -technology $cln28ht_tech_file pad_lib
+save_fusion_lib pad_lib
+close_fusion_lib pad_lib
+
+create_fusion_lib -lefs $bump_lef_file -technology $cln28ht_tech_file bump_lib
+save_fusion_lib bump_lib
+close_fusion_lib bump_lib
+
exit
\ No newline at end of file
diff --git a/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
index 4b2202f9f4a7357788c5a96a7d3f8ace49d0fd35..c91b2baf91fb06f270439444e8a991ab4560cecc 100644
--- a/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
+++ b/ASIC/TSMC28nm_HPCP/constraints/sram_chiplet.sdc
@@ -1,14 +1,18 @@
#-----------------------------------------------------------------------------
-# SRAM Chiplet constraints for ASIC
+# SRAM Chiplet constraints for ASIC on TSMC 28nm HPC+ node
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
#
-# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
+set_units -time ns;
+set_units -capacitance pF;
+
+
#### CLOCK DEFINITION
set REF_CLK "REF_CLK";
@@ -16,18 +20,47 @@ set TLX_IN_FWD_CLK "TLX_IN_FWD_CLK"
set TLX_OUT_REV_CLK "TLX_OUT_REV_CLK"
set SYS_CLK "PLL_CLK"
-set_units -time ns;
-set_units -capacitance pF;
set REF_CLK_PERIOD 4;
set TLX_IN_FWD_CLK_PERIOD 1;
set TLX_OUT_REV_CLK_PERIOD 1;
set SYS_CLK_PERIOD 1;
-set CLK_ERROR 0.35;
-set INTER_CLOCK_UNCERTAINTY 0.1
+set REF_CLK_JITTER 0.0274; #from CDCM61001 datasheet
+set REF_CLK_TRANS 0.825;
+
+set TLX_CLK_UNCERTAINTY 0.1;
+
+create_clock -name "$REF_CLK" -period "$REF_CLK_PERIOD" [get_ports PAD_REF_CLK]
+set_clock_uncertainty $REF_CLK_JITTER $REF_CLK
+set_clock_transition $REF_CLK_TRANS [get_clocks $REF_CLK]
+
+create_clock -name "$TLX_IN_FWD_CLK" -period "$TLX_IN_FWD_CLK_PERIOD" [get_ports PAD_IN_FWD_CLK]
+set_clock_uncertainty $TLX_CLK_UNCERTAINTY $TLX_IN_FWD_CLK
+
+create_clock -name "$TLX_OUT_REV_CLK" -period "$TLX_OUT_REV_CLK_PERIOD" [get_ports PAD_OUT_REV_CLK]
+set_clock_uncertainty $TLX_CLK_UNCERTAINTY $TLX_OUT_REV_CLK
+
+create_generated_clock -name "$SYS_CLK" -source [get_ports PAD_REF_CLK] -multiply_by 4 [get_pins u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/PLL_CLK1]
+create_generated_clock -name "TLX_IN_REV_CLK" -source [get_pins u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/PLL_CLK1] -multiply_by 1 [get_pins u_PAD_IN_REV_CLK/PAD]
+
+
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_data_rev_0_tdata]
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_data_rev_0_tvalid]
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_flow_rev_0_tdata]
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_flow_rev_0_tvalid]
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_flow_fwd_0_tready]
+set_output_delay 0.1 -clock TLX_IN_REV_CLK [get_ports PAD_TLX_IN_data_fwd_0_tready]
+
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_data_rev_0_tready]
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_flow_rev_0_tready]
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_flow_fwd_0_tdata]
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_flow_fwd_0_tvalid]
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_data_fwd_0_tdata]
+set_input_delay 0.1 -clock $TLX_IN_FWD_CLK [get_ports PAD_TLX_IN_data_fwd_0_tvalid]
+
+set_max_capacitance 3 [all_outputs]
+set_max_fanout 10 [all_inputs]
+
+
-create_clock -name "$REF_CLK" -period "$REF_CLK_PERIOD" [get_ports REF_CLK]
-create_clock -name "$TLX_IN_FWD_CLK" -period "$TLX_IN_FWD_CLK_PERIOD" [get_ports IN_FWD_CLK]
-create_clock -name "$TLX_OUT_REV_CLK" -period "$TLX_OUT_REV_CLK_PERIOD" [get_ports OUT_REV_CLK]
-create_generated_clock -name "$SYS_CLK" -source [get_ports REF_CLK] -multiply_by 4 [get_pins u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/PLL_CLK1]
\ No newline at end of file
diff --git a/ASIC/TSMC28nm_HPCP/sram_chiplet.upf b/ASIC/TSMC28nm_HPCP/sram_chiplet.upf
new file mode 100644
index 0000000000000000000000000000000000000000..7a0b4a0a7fdff822f2eeaad40ae58cb058088b12
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/sram_chiplet.upf
@@ -0,0 +1,96 @@
+
+
+create_power_domain TOP
+
+# Always on VDD
+create_supply_port VDD
+create_supply_net VDD -domain TOP
+connect_supply_net VDD -ports VDD
+
+# Ground
+create_supply_port VSS
+create_supply_net VSS -domain TOP
+connect_supply_net VSS -ports VSS
+
+
+create_supply_port AVDD
+create_supply_net AVDD -domain TOP
+connect_supply_net AVDD -ports AVDD
+
+create_supply_port AVDDHV
+create_supply_net AVDDHV -domain TOP
+connect_supply_net AVDDHV -ports AVDDHV
+
+create_supply_port AGND
+create_supply_net AGND -domain TOP
+connect_supply_net AGND -ports AGND
+
+# Connect macro supplies
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[0].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[1].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/g_srams[2].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_0/u_SRAM/gen_sram.u_sram_32b_32k_N/VDDCE
+
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[0].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[1].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/g_srams[2].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_1/u_SRAM/gen_sram.u_sram_32b_32k_N/VDDCE
+
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[0].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[1].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/g_srams[2].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_2/u_SRAM/gen_sram.u_sram_32b_32k_N/VDDCE
+
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[0].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[1].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/g_srams[2].u_sram_32b_32k/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_0/VDDCE
+connect_supply_net VDD -ports u_top_sram_chiplet/u_SRAM_wrapper_3/u_SRAM/gen_split_sram.u_sram_32b_16k_1/VDDCE
+
+connect_supply_net AVDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/vp_vref
+connect_supply_net AVDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/avdd
+connect_supply_net AVDDHV -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/avddhv
+connect_supply_net VDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/dvdd
+connect_supply_net AGND -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/agnd
+connect_supply_net VSS -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PLL.u_snps_PLL/u_snps_PLL/dgnd
+
+connect_supply_net VDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts/VDD
+connect_supply_net AVDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts/VDDA
+connect_supply_net VSS -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_ts0.u_snps_PVT_ts0/u_synopsys_ts/VSS
+
+connect_supply_net VDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd/VDD
+connect_supply_net AVDD -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd/VDDA
+connect_supply_net VSS -ports u_top_sram_chiplet/u_sram_chiplet_apb_subsystem/gen_snps_PVT_pd0.u_snps_PVT_pd0/u_synopsys_pd/VSS
+
+connect_supply_net AGND -ports u_PAD_AGNDHV_left/AVSS
+connect_supply_net AGND -ports u_PAD_AGND_left/AVSS
+connect_supply_net AVDD -ports u_PAD_AVDD_left/AVDD
+connect_supply_net AVDDHV -ports u_PAD_AVDDHV_left/AVDD
+
+connect_supply_net AGND -ports bump_array_7_1/BUMP
+connect_supply_net AGND -ports bump_array_6_1/BUMP
+connect_supply_net AVDD -ports bump_array_5_1/BUMP
+connect_supply_net AVDDHV -ports bump_array_4_1/BUMP
+
+connect_supply_net VDD -ports bump_array_12_0/BUMP
+connect_supply_net VDD -ports bump_array_2_0/BUMP
+connect_supply_net VDD -ports bump_array_10_0/BUMP
+connect_supply_net VDD -ports bump_array_4_12/BUMP
+connect_supply_net VDD -ports bump_array_10_11/BUMP
+
+connect_supply_net VSS -ports bump_array_12_12/BUMP
+connect_supply_net VSS -ports bump_array_2_12/BUMP
+connect_supply_net VSS -ports bump_array_5_0/BUMP
+connect_supply_net VSS -ports bump_array_10_12/BUMP
+
+set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
+
+add_port_state VSS -state {on 0.0 0.0 0.0}
+add_port_state VDD -state {on 0.81 0.9 0.99}
+add_port_state AVDD -state {on 0.81 0.9 0.99}
+add_port_state AVDDHV -state {on 1.62 1.8 1.98}
+add_port_state AGND -state {on 0.0 0.0 0.0}
+
+create_pst pst0 -supplies {VSS AGND VDD AVDD AVDDHV}
+add_pst_state run -pst pst0 -state {on on on on on }
+
diff --git a/flist/IP/NIC400.flist b/flist/IP/NIC400.flist
index 5fdd0667c8f139d2cc9fdfe391796b49caad8483..d196c45a85e5929a75b763cf9c857cefc02866e0 100644
--- a/flist/IP/NIC400.flist
+++ b/flist/IP/NIC400.flist
@@ -1,30 +1,38 @@
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_0/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_1/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_2/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_3/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/ib_apb_group0_ib/verilog
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog
+
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi4PC
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/ApbPC
+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Apb4PC
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Ahb
-+incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/AhbPC
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_chan_slice_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_sram_chiplet.v
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_0/verilog/nic400_amib_AXI_SRAM_0_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_0/verilog/nic400_amib_AXI_SRAM_0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_1/verilog/nic400_amib_AXI_SRAM_1_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_1/verilog/nic400_amib_AXI_SRAM_1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_2/verilog/nic400_amib_AXI_SRAM_2_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_2/verilog/nic400_amib_AXI_SRAM_2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_3/verilog/nic400_amib_AXI_SRAM_3_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM_3/verilog/nic400_amib_AXI_SRAM_3_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog/nic400_amib_AXI_TLX_OUT_chan_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog/nic400_amib_AXI_TLX_OUT_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog/nic400_apb_bridge_master_domain_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/apb_bridge/verilog/nic400_apb_bridge_slave_domain_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_chan_slice_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_decode_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_maskcntl_sram_chiplet.v
@@ -35,10 +43,16 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml5_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml6_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml5_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml6_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_build_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_map_sram_chiplet.v
@@ -46,18 +60,30 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_5_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_6_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_5_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml5_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml6_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml4_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml5_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml6_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_bypass_sync_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_nosync_sram_chiplet.v
@@ -67,8 +93,6 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chip
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_or2_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_or3_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_gry_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_sram_chiplet.v
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_data_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_gry_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/cdc_blocks/verilog/nic400_cdc_random_sram_chiplet.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog/nic400_default_slave_ds_1_sram_chiplet.v
diff --git a/flist/Top/sram_chiplet.flist b/flist/Top/sram_chiplet.flist
index c14ebad05a22b225151e18ea59f55c23ec0dbb07..88a17d2fc5411c9460d006d9ef7c5640793fc910 100644
--- a/flist/Top/sram_chiplet.flist
+++ b/flist/Top/sram_chiplet.flist
@@ -25,6 +25,7 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
index cdcc0c8d83dcd0b33fda68e1eee1f3c7670a2e68..7283bdebb0761ebc849a2453eba69808e1157626 100644
--- a/flist/Top/sram_chiplet_TSMC28nm.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -21,15 +21,16 @@ $(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
// SRAM Chiplet - SRAM
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM_wrapper.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k_emulation.v
$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k_emulation.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
-// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
index ec6f82a6d0e53d8252e82c7dad3518a4c669320a..fffcd3639c86f97cc06007d64e82268d8de680c5 100644
--- a/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
+++ b/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
@@ -19,13 +19,14 @@
-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_sv.flist
// SRAM Chiplet - SRAM
-$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM_wrapper.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
// SRAM Chiplet - APB subsystem
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/synchr_clock_mux.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/PLL_integration_layer.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
$(SOCLABS_SRAM_CHIPLET_DIR)/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
diff --git a/flist/Top/sram_chiplet_TSMC28nm_GATE.flist b/flist/Top/sram_chiplet_TSMC28nm_GATE.flist
new file mode 100644
index 0000000000000000000000000000000000000000..63c423ecec896cfa35e4582d9612c2470605042c
--- /dev/null
+++ b/flist/Top/sram_chiplet_TSMC28nm_GATE.flist
@@ -0,0 +1,17 @@
+
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/interfaces
+
+// Testbench IP
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_vip.flist
+// Thin links
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/TLX400.flist
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET/sram_chiplet_gate.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_16k/sram_32b_16k.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k/sram_32b_32k.v
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0/verilog/sc12mcpp140z_cln28ht_base_svt_c35.v
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_pmk_svt_c35/r1p0/verilog/sc12mcpp140z_cln28ht_pmk_svt_c35.v
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/glib/PDDW04DGZ_V_G.v
+
+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/PLL/synopsys/dwc_pll3ghz_tsmc28hpcp/1.10a/macro/behavior/dwc_z19606ts_ns_gtech.v
\ No newline at end of file
diff --git a/flist/Top/sram_chiplet_sv.flist b/flist/Top/sram_chiplet_sv.flist
index d927cfcadac20558b6c902a148f459d615484d36..e56c1d9601e8a1935423023cbfe0658a7978accc 100644
--- a/flist/Top/sram_chiplet_sv.flist
+++ b/flist/Top/sram_chiplet_sv.flist
@@ -16,3 +16,4 @@
// SRAM Chiplet top level
$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/pad_level/glib/SRAM_chiplet.sv
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
index 6f5ce6dbc65102d7c6b59b6424ccadfcbf2a40fb..4584a3f5f49a08ff56f05b6c88f6b3f82a2c0c5f 100644
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
@@ -1,26 +1,25 @@
-module SRAM (
+module SRAM #(parameter SPLIT_SRAM =0 )(
input wire clk,
- input wire [19:0] memaddr,
+ input wire [18:0] memaddr,
input wire [31:0] memd,
output reg [31:0] memq,
input wire memcen,
input wire [3:0] memwen
);
-localparam N_MEMS = 8;
-localparam SEL_W = 3;
+localparam N_MEMS = 4;
+localparam SEL_W = 2;
reg [N_MEMS:0] CEN_i; //Active low chip select
+wire [31:0] q_i[0:N_MEMS];
wire [31:0] wena_i;
wire gwen_i;
-wire [31:0] q_i[0:N_MEMS];
assign wena_i = {{8{memwen[3]}}, {8{memwen[2]}}, {8{memwen[1]}}, {8{memwen[0]}}};
assign gwen_i = &memwen;
genvar i;
-
generate for(i=0; i<N_MEMS-1; i = i + 1) begin: g_srams
sram_32b_32k u_sram_32b_32k(
.Q(q_i[i]),
@@ -39,6 +38,8 @@ generate for(i=0; i<N_MEMS-1; i = i + 1) begin: g_srams
end endgenerate
+generate if (SPLIT_SRAM == 1) begin : gen_split_sram
+
sram_32b_16k u_sram_32b_16k_0(
.Q(q_i[N_MEMS-1]),
.CLK(clk),
@@ -76,7 +77,7 @@ always @(*) begin
else
CEN_i[j] = 1'b1;
end
- if(memaddr[SEL_W+16:17]==3'h7) begin
+ if(memaddr[SEL_W+16:17]=={SEL_W{1'b1}}) begin
if(memaddr[16]==1'b0) begin
CEN_i[N_MEMS-1]=memcen;
CEN_i[N_MEMS]=1'b1;
@@ -87,7 +88,7 @@ always @(*) begin
end
end else
CEN_i[N_MEMS:N_MEMS-1]=2'b11;
- if(memaddr[19:17]==3'h7) begin
+ if(memaddr[SEL_W+16:17]=={SEL_W{1'b1}}) begin
if(memaddr[16]==1'b1)
memq=q_i[N_MEMS];
else
@@ -95,5 +96,33 @@ always @(*) begin
end else
memq = q_i[memaddr[(SEL_W+17-1):17]];
end
+end else begin: gen_sram
+
+ sram_32b_32k u_sram_32b_32k_N(
+ .Q(q_i[N_MEMS-1]),
+ .CLK(clk),
+ .CEN(CEN_i[N_MEMS-1]),
+ .GWEN(gwen_i),
+ .A(memaddr[16:2]),
+ .D(memd),
+ .WEN(wena_i),
+ .STOV(1'b0),
+ .EMA(3'b011),
+ .EMAW(2'b01),
+ .EMAS(1'b0),
+ .RET1N(1'b1)
+ );
+
+integer j;
+always @(*) begin
+ for(j=0; j<N_MEMS; j=j+1) begin
+ if(j==memaddr[(SEL_W+17-1):17])
+ CEN_i[j] = memcen;
+ else
+ CEN_i[j] = 1'b1;
+ end
+ memq = q_i[memaddr[(SEL_W+17-1):17]];
+end
+end endgenerate
endmodule
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
deleted file mode 100644
index 08b99b142a2666bdd88925efe64c3b59f57ce17f..0000000000000000000000000000000000000000
--- a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+++ /dev/null
@@ -1,154 +0,0 @@
-//-----------------------------------------------------------------------------
-// Expansion Subsystem SRAM Wrapper
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// Daniel Newbrook (d.newbrook@soton.ac.uk)
-//
-// Copyright � 2021-4, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// Modules instantiated:
-// sie300_axi5_sram_ctrl_expansion_subsystem
-// SRAM
-
-module SRAM_wrapper #(
- parameter ID_W=12 )(
- input wire ACLK,
- input wire ARESETn,
-
- input wire AWVALID,
- output wire AWREADY,
- input wire [ID_W-1:0] AWID,
- input wire [31:0] AWADDR,
- input wire [7:0] AWLEN,
- input wire [2:0] AWSIZE,
- input wire [1:0] AWBURST,
- input wire AWLOCK,
- input wire [2:0] AWPROT,
- input wire [3:0] AWQOS,
-
- input wire WVALID,
- output wire WREADY,
- input wire [31:0] WDATA,
- input wire [3:0] WSTRB,
- input wire WLAST,
- input wire WPOISON,
-
- output wire BVALID,
- input wire BREADY,
- output wire [ID_W-1:0] BID,
- output wire [1:0] BRESP,
-
- input wire ARVALID,
- output wire ARREADY,
- input wire [ID_W-1:0] ARID,
- input wire [31:0] ARADDR,
- input wire [7:0] ARLEN,
- input wire [2:0] ARSIZE,
- input wire [1:0] ARBURST,
- input wire ARLOCK,
- input wire [2:0] ARPROT,
- input wire [3:0] ARQOS,
-
- output wire RVALID,
- input wire RREADY,
- output wire [ID_W-1:0] RID,
- output wire [31:0] RDATA,
- output wire [1:0] RRESP,
- output wire RLAST,
- output wire RPOISON,
- input wire AWAKEUP,
-
- input wire clk_qreqn,
- output wire clk_qacceptn,
- output wire clk_qdeny,
- output wire clk_qactive,
-
- input wire pwr_qreqn,
- output wire pwr_qacceptn,
- output wire pwr_qdeny,
- output wire pwr_qactive,
-
- input wire ext_gt_qreqn,
- output wire ext_gt_qacceptn,
- input wire cfg_gate_resp
-
-);
-
-
-wire [19:0] memaddr;
-wire [31:0] memd;
-wire [31:0] memq;
-wire memcen;
-wire [3:0] memwen;
-
-sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
- .aclk(ACLK),
- .aresetn(ARESETn),
- .awvalid_s(AWVALID),
- .awready_s(AWREADY),
- .awid_s(AWID),
- .awaddr_s(AWADDR[19:0]),
- .awlen_s(AWLEN),
- .awsize_s(AWSIZE),
- .awburst_s(AWBURST),
- .awlock_s(AWLOCK),
- .awprot_s(AWPROT),
- .awqos_s(AWQOS),
- .wvalid_s(WVALID),
- .wready_s(WREADY),
- .wdata_s(WDATA),
- .wstrb_s(WSTRB),
- .wlast_s(WLAST),
- .wpoison_s(WPOISON),
- .bvalid_s(BVALID),
- .bready_s(BREADY),
- .bid_s(BID),
- .bresp_s(BRESP),
- .arvalid_s(ARVALID),
- .arready_s(ARREADY),
- .arid_s(ARID),
- .araddr_s(ARADDR[19:0]),
- .arlen_s(ARLEN),
- .arsize_s(ARSIZE),
- .arburst_s(ARBURST),
- .arlock_s(ARLOCK),
- .arprot_s(ARPROT),
- .arqos_s(ARQOS),
- .rvalid_s(RVALID),
- .rready_s(RREADY),
- .rid_s(RID),
- .rdata_s(RDATA),
- .rresp_s(RRESP),
- .rlast_s(RLAST),
- .rpoison_s(RPOISON),
- .awakeup_s(AWAKEUP),
- .clk_qreqn(clk_qreqn),
- .clk_qacceptn(clk_qacceptn),
- .clk_qdeny(clk_qdeny),
- .clk_qactive(clk_qactive),
- .pwr_qreqn(pwr_qreqn),
- .pwr_qacceptn(pwr_qacceptn),
- .pwr_qdeny(pwr_qdeny),
- .pwr_qactive(pwr_qactive),
- .ext_gt_qreqn(ext_gt_qreqn),
- .ext_gt_qacceptn(ext_gt_qacceptn),
- .cfg_gate_resp(cfg_gate_resp),
- .memaddr(memaddr),
- .memd(memd),
- .memq(memq),
- .memcen(memcen),
- .memwen(memwen)
-);
-
-SRAM u_SRAM(
- .clk(ACLK),
- .memaddr(memaddr),
- .memd(memd),
- .memq(memq),
- .memcen(memcen),
- .memwen(memwen)
-);
-
-endmodule
\ No newline at end of file
diff --git a/logical/SRAM/glib/verilog/SRAM.v b/logical/SRAM/glib/verilog/SRAM.v
index d3474c4565f046fb02cb8cdc26e597cced163192..b8236b8e0ce557cfa1ce55f515eea3d44250b4e3 100644
--- a/logical/SRAM/glib/verilog/SRAM.v
+++ b/logical/SRAM/glib/verilog/SRAM.v
@@ -1,17 +1,18 @@
-module SRAM (
+module SRAM #(
+ parameter SPLIT_SRAM = 0 )(
input wire clk,
- input wire [19:0] memaddr,
+ input wire [18:0] memaddr,
input wire [31:0] memd,
output wire [31:0] memq,
input wire memcen,
input wire [3:0] memwen
);
- parameter MEM_DEPTH = 262144;
+ parameter MEM_DEPTH = 131072;
wire WriteEnable; // Write data update
- wire [17:0] Addr;
+ wire [18:0] Addr;
reg [31:0] DataAtAddress; // Current write-data at address
reg [31:0] Mask; // Write data-mask
reg [31:0] NextData; // Next write-data
@@ -19,7 +20,7 @@ module SRAM (
integer i; // Write-strobe loop variable
integer j; // Mask-bit loop variable
- assign Addr = memaddr[19:2];
+ assign Addr = memaddr[18:2];
// -------------
// Memory arrays
// -------------
diff --git a/logical/SRAM/glib/verilog/SRAM_wrapper.v b/logical/SRAM/glib/verilog/SRAM_wrapper.v
index 2df8555ed11f507b2f01c7f9efbd151e2a9f732a..a6c0770065ad1835664cb4e29ad588761968d242 100644
--- a/logical/SRAM/glib/verilog/SRAM_wrapper.v
+++ b/logical/SRAM/glib/verilog/SRAM_wrapper.v
@@ -13,7 +13,8 @@
// SRAM
module SRAM_wrapper #(
- parameter ID_W = 12
+ parameter ID_W = 12,
+ parameter SPLIT_SRAM = 0
)(
input wire ACLK,
input wire ARESETn,
@@ -78,7 +79,7 @@ module SRAM_wrapper #(
);
-wire [19:0] memaddr;
+wire [18:0] memaddr;
wire [31:0] memd;
wire [31:0] memq;
wire memcen;
@@ -90,7 +91,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.awvalid_s(AWVALID),
.awready_s(AWREADY),
.awid_s(AWID),
- .awaddr_s(AWADDR[19:0]),
+ .awaddr_s(AWADDR[18:0]),
.awlen_s(AWLEN),
.awsize_s(AWSIZE),
.awburst_s(AWBURST),
@@ -110,7 +111,7 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.arvalid_s(ARVALID),
.arready_s(ARREADY),
.arid_s(ARID),
- .araddr_s(ARADDR[19:0]),
+ .araddr_s(ARADDR[18:0]),
.arlen_s(ARLEN),
.arsize_s(ARSIZE),
.arburst_s(ARBURST),
@@ -143,7 +144,8 @@ sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
.memwen(memwen)
);
-SRAM u_SRAM(
+SRAM #(.SPLIT_SRAM(SPLIT_SRAM))
+ u_SRAM(
.clk(ACLK),
.memaddr(memaddr),
.memd(memd),
diff --git a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
index b31d6e5e52fbf9a935f1b24cf29daa61acb1208b..35fdb137333bc5915f9e5a4c0feb920d4096c416 100644
--- a/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+++ b/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
@@ -258,7 +258,7 @@ generate if(SNPS_PLL_ENABLE==1)begin: gen_snps_PLL
.out_clk2(pll_clk2_i),
.PSELx(snps_PLL_psel),
- .PADDR(PADDR_APB_PVT[11:2]),
+ .PADDR(PADDR_APB_PVT[11:0]),
.PENABLE(PENABLE_APB_PVT),
.PPROT(PPROT_APB_PVT),
.PSTRB(PSTRB_APB_PVT),
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
index 541db653889b91019a09f6adbfa17392e3407009..d6466c371fef5bbe44fd6b7ea28c6a9cab9da0c5 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
@@ -18,7 +18,7 @@
`include "tlx_interfaces.sv"
module top_sram_chiplet #(
- parameter N_ADDR_SEL_BITS = 6
+ parameter N_ADDR_SEL_BITS = 4
)(
// Clock and reset
input wire REF_CLK,
@@ -54,41 +54,150 @@ wire SYS_CLK;
// Main Bus Wires
// - SRAM AXI wires
-wire [ID_W-1:0] AWID_AXI_SRAM;
-wire [31:0] AWADDR_AXI_SRAM;
-wire [7:0] AWLEN_AXI_SRAM;
-wire [2:0] AWSIZE_AXI_SRAM;
-wire [1:0] AWBURST_AXI_SRAM;
-wire AWLOCK_AXI_SRAM;
-wire [3:0] AWCACHE_AXI_SRAM;
-wire [2:0] AWPROT_AXI_SRAM;
-wire AWVALID_AXI_SRAM;
-wire AWREADY_AXI_SRAM;
-wire [31:0] WDATA_AXI_SRAM;
-wire [3:0] WSTRB_AXI_SRAM;
-wire WLAST_AXI_SRAM;
-wire WVALID_AXI_SRAM;
-wire WREADY_AXI_SRAM;
-wire [ID_W-1:0] BID_AXI_SRAM;
-wire [1:0] BRESP_AXI_SRAM;
-wire BVALID_AXI_SRAM;
-wire BREADY_AXI_SRAM;
-wire [ID_W-1:0] ARID_AXI_SRAM;
-wire [31:0] ARADDR_AXI_SRAM;
-wire [7:0] ARLEN_AXI_SRAM;
-wire [2:0] ARSIZE_AXI_SRAM;
-wire [1:0] ARBURST_AXI_SRAM;
-wire ARLOCK_AXI_SRAM;
-wire [3:0] ARCACHE_AXI_SRAM;
-wire [2:0] ARPROT_AXI_SRAM;
-wire ARVALID_AXI_SRAM;
-wire ARREADY_AXI_SRAM;
-wire [ID_W-1:0] RID_AXI_SRAM;
-wire [31:0] RDATA_AXI_SRAM;
-wire [1:0] RRESP_AXI_SRAM;
-wire RLAST_AXI_SRAM;
-wire RVALID_AXI_SRAM;
-wire RREADY_AXI_SRAM;
+wire [ID_W-1:0] AWID_AXI_SRAM_0;
+wire [31:0] AWADDR_AXI_SRAM_0;
+wire [7:0] AWLEN_AXI_SRAM_0;
+wire [2:0] AWSIZE_AXI_SRAM_0;
+wire [1:0] AWBURST_AXI_SRAM_0;
+wire AWLOCK_AXI_SRAM_0;
+wire [3:0] AWCACHE_AXI_SRAM_0;
+wire [2:0] AWPROT_AXI_SRAM_0;
+wire AWVALID_AXI_SRAM_0;
+wire AWREADY_AXI_SRAM_0;
+wire [31:0] WDATA_AXI_SRAM_0;
+wire [3:0] WSTRB_AXI_SRAM_0;
+wire WLAST_AXI_SRAM_0;
+wire WVALID_AXI_SRAM_0;
+wire WREADY_AXI_SRAM_0;
+wire [ID_W-1:0] BID_AXI_SRAM_0;
+wire [1:0] BRESP_AXI_SRAM_0;
+wire BVALID_AXI_SRAM_0;
+wire BREADY_AXI_SRAM_0;
+wire [ID_W-1:0] ARID_AXI_SRAM_0;
+wire [31:0] ARADDR_AXI_SRAM_0;
+wire [7:0] ARLEN_AXI_SRAM_0;
+wire [2:0] ARSIZE_AXI_SRAM_0;
+wire [1:0] ARBURST_AXI_SRAM_0;
+wire ARLOCK_AXI_SRAM_0;
+wire [3:0] ARCACHE_AXI_SRAM_0;
+wire [2:0] ARPROT_AXI_SRAM_0;
+wire ARVALID_AXI_SRAM_0;
+wire ARREADY_AXI_SRAM_0;
+wire [ID_W-1:0] RID_AXI_SRAM_0;
+wire [31:0] RDATA_AXI_SRAM_0;
+wire [1:0] RRESP_AXI_SRAM_0;
+wire RLAST_AXI_SRAM_0;
+wire RVALID_AXI_SRAM_0;
+wire RREADY_AXI_SRAM_0;
+
+wire [ID_W-1:0] AWID_AXI_SRAM_1;
+wire [31:0] AWADDR_AXI_SRAM_1;
+wire [7:0] AWLEN_AXI_SRAM_1;
+wire [2:0] AWSIZE_AXI_SRAM_1;
+wire [1:0] AWBURST_AXI_SRAM_1;
+wire AWLOCK_AXI_SRAM_1;
+wire [3:0] AWCACHE_AXI_SRAM_1;
+wire [2:0] AWPROT_AXI_SRAM_1;
+wire AWVALID_AXI_SRAM_1;
+wire AWREADY_AXI_SRAM_1;
+wire [31:0] WDATA_AXI_SRAM_1;
+wire [3:0] WSTRB_AXI_SRAM_1;
+wire WLAST_AXI_SRAM_1;
+wire WVALID_AXI_SRAM_1;
+wire WREADY_AXI_SRAM_1;
+wire [ID_W-1:0] BID_AXI_SRAM_1;
+wire [1:0] BRESP_AXI_SRAM_1;
+wire BVALID_AXI_SRAM_1;
+wire BREADY_AXI_SRAM_1;
+wire [ID_W-1:0] ARID_AXI_SRAM_1;
+wire [31:0] ARADDR_AXI_SRAM_1;
+wire [7:0] ARLEN_AXI_SRAM_1;
+wire [2:0] ARSIZE_AXI_SRAM_1;
+wire [1:0] ARBURST_AXI_SRAM_1;
+wire ARLOCK_AXI_SRAM_1;
+wire [3:0] ARCACHE_AXI_SRAM_1;
+wire [2:0] ARPROT_AXI_SRAM_1;
+wire ARVALID_AXI_SRAM_1;
+wire ARREADY_AXI_SRAM_1;
+wire [ID_W-1:0] RID_AXI_SRAM_1;
+wire [31:0] RDATA_AXI_SRAM_1;
+wire [1:0] RRESP_AXI_SRAM_1;
+wire RLAST_AXI_SRAM_1;
+wire RVALID_AXI_SRAM_1;
+wire RREADY_AXI_SRAM_1;
+
+wire [ID_W-1:0] AWID_AXI_SRAM_2;
+wire [31:0] AWADDR_AXI_SRAM_2;
+wire [7:0] AWLEN_AXI_SRAM_2;
+wire [2:0] AWSIZE_AXI_SRAM_2;
+wire [1:0] AWBURST_AXI_SRAM_2;
+wire AWLOCK_AXI_SRAM_2;
+wire [3:0] AWCACHE_AXI_SRAM_2;
+wire [2:0] AWPROT_AXI_SRAM_2;
+wire AWVALID_AXI_SRAM_2;
+wire AWREADY_AXI_SRAM_2;
+wire [31:0] WDATA_AXI_SRAM_2;
+wire [3:0] WSTRB_AXI_SRAM_2;
+wire WLAST_AXI_SRAM_2;
+wire WVALID_AXI_SRAM_2;
+wire WREADY_AXI_SRAM_2;
+wire [ID_W-1:0] BID_AXI_SRAM_2;
+wire [1:0] BRESP_AXI_SRAM_2;
+wire BVALID_AXI_SRAM_2;
+wire BREADY_AXI_SRAM_2;
+wire [ID_W-1:0] ARID_AXI_SRAM_2;
+wire [31:0] ARADDR_AXI_SRAM_2;
+wire [7:0] ARLEN_AXI_SRAM_2;
+wire [2:0] ARSIZE_AXI_SRAM_2;
+wire [1:0] ARBURST_AXI_SRAM_2;
+wire ARLOCK_AXI_SRAM_2;
+wire [3:0] ARCACHE_AXI_SRAM_2;
+wire [2:0] ARPROT_AXI_SRAM_2;
+wire ARVALID_AXI_SRAM_2;
+wire ARREADY_AXI_SRAM_2;
+wire [ID_W-1:0] RID_AXI_SRAM_2;
+wire [31:0] RDATA_AXI_SRAM_2;
+wire [1:0] RRESP_AXI_SRAM_2;
+wire RLAST_AXI_SRAM_2;
+wire RVALID_AXI_SRAM_2;
+wire RREADY_AXI_SRAM_2;
+
+wire [ID_W-1:0] AWID_AXI_SRAM_3;
+wire [31:0] AWADDR_AXI_SRAM_3;
+wire [7:0] AWLEN_AXI_SRAM_3;
+wire [2:0] AWSIZE_AXI_SRAM_3;
+wire [1:0] AWBURST_AXI_SRAM_3;
+wire AWLOCK_AXI_SRAM_3;
+wire [3:0] AWCACHE_AXI_SRAM_3;
+wire [2:0] AWPROT_AXI_SRAM_3;
+wire AWVALID_AXI_SRAM_3;
+wire AWREADY_AXI_SRAM_3;
+wire [31:0] WDATA_AXI_SRAM_3;
+wire [3:0] WSTRB_AXI_SRAM_3;
+wire WLAST_AXI_SRAM_3;
+wire WVALID_AXI_SRAM_3;
+wire WREADY_AXI_SRAM_3;
+wire [ID_W-1:0] BID_AXI_SRAM_3;
+wire [1:0] BRESP_AXI_SRAM_3;
+wire BVALID_AXI_SRAM_3;
+wire BREADY_AXI_SRAM_3;
+wire [ID_W-1:0] ARID_AXI_SRAM_3;
+wire [31:0] ARADDR_AXI_SRAM_3;
+wire [7:0] ARLEN_AXI_SRAM_3;
+wire [2:0] ARSIZE_AXI_SRAM_3;
+wire [1:0] ARBURST_AXI_SRAM_3;
+wire ARLOCK_AXI_SRAM_3;
+wire [3:0] ARCACHE_AXI_SRAM_3;
+wire [2:0] ARPROT_AXI_SRAM_3;
+wire ARVALID_AXI_SRAM_3;
+wire ARREADY_AXI_SRAM_3;
+wire [ID_W-1:0] RID_AXI_SRAM_3;
+wire [31:0] RDATA_AXI_SRAM_3;
+wire [1:0] RRESP_AXI_SRAM_3;
+wire RLAST_AXI_SRAM_3;
+wire RVALID_AXI_SRAM_3;
+wire RREADY_AXI_SRAM_3;
+
// - Thin links out wires
wire [ID_W-1:0] AWID_AXI_TLX_OUT;
wire [31:0] AWADDR_AXI_TLX_OUT;
@@ -278,41 +387,149 @@ assign AWADDR_AXI_CHIPLET_IN_i = (AWADDR_AXI_CHIPLET_IN[20+:N_ADDR_SEL_BITS]==ad
assign ARADDR_AXI_CHIPLET_IN_i = (ARADDR_AXI_CHIPLET_IN[20+:N_ADDR_SEL_BITS]==addr_sel[0+:N_ADDR_SEL_BITS]) ? {ARADDR_AXI_CHIPLET_IN[31:(20+N_ADDR_SEL_BITS)],{N_ADDR_SEL_BITS{1'b0}},ARADDR_AXI_CHIPLET_IN[19:0]} : ARADDR_AXI_CHIPLET_IN;
nic400_sram_chiplet u_nic400_sram_chiplet(
- .AWID_AXI_SRAM(AWID_AXI_SRAM),
- .AWADDR_AXI_SRAM(AWADDR_AXI_SRAM),
- .AWLEN_AXI_SRAM(AWLEN_AXI_SRAM),
- .AWSIZE_AXI_SRAM(AWSIZE_AXI_SRAM),
- .AWBURST_AXI_SRAM(AWBURST_AXI_SRAM),
- .AWLOCK_AXI_SRAM(AWLOCK_AXI_SRAM),
- .AWCACHE_AXI_SRAM(AWCACHE_AXI_SRAM),
- .AWPROT_AXI_SRAM(AWPROT_AXI_SRAM),
- .AWVALID_AXI_SRAM(AWVALID_AXI_SRAM),
- .AWREADY_AXI_SRAM(AWREADY_AXI_SRAM),
- .WDATA_AXI_SRAM(WDATA_AXI_SRAM),
- .WSTRB_AXI_SRAM(WSTRB_AXI_SRAM),
- .WLAST_AXI_SRAM(WLAST_AXI_SRAM),
- .WVALID_AXI_SRAM(WVALID_AXI_SRAM),
- .WREADY_AXI_SRAM(WREADY_AXI_SRAM),
- .BID_AXI_SRAM(BID_AXI_SRAM),
- .BRESP_AXI_SRAM(BRESP_AXI_SRAM),
- .BVALID_AXI_SRAM(BVALID_AXI_SRAM),
- .BREADY_AXI_SRAM(BREADY_AXI_SRAM),
- .ARID_AXI_SRAM(ARID_AXI_SRAM),
- .ARADDR_AXI_SRAM(ARADDR_AXI_SRAM),
- .ARLEN_AXI_SRAM(ARLEN_AXI_SRAM),
- .ARSIZE_AXI_SRAM(ARSIZE_AXI_SRAM),
- .ARBURST_AXI_SRAM(ARBURST_AXI_SRAM),
- .ARLOCK_AXI_SRAM(ARLOCK_AXI_SRAM),
- .ARCACHE_AXI_SRAM(ARCACHE_AXI_SRAM),
- .ARPROT_AXI_SRAM(ARPROT_AXI_SRAM),
- .ARVALID_AXI_SRAM(ARVALID_AXI_SRAM),
- .ARREADY_AXI_SRAM(ARREADY_AXI_SRAM),
- .RID_AXI_SRAM(RID_AXI_SRAM),
- .RDATA_AXI_SRAM(RDATA_AXI_SRAM),
- .RRESP_AXI_SRAM(RRESP_AXI_SRAM),
- .RLAST_AXI_SRAM(RLAST_AXI_SRAM),
- .RVALID_AXI_SRAM(RVALID_AXI_SRAM),
- .RREADY_AXI_SRAM(RREADY_AXI_SRAM),
+ .AWID_AXI_SRAM_0(AWID_AXI_SRAM_0),
+ .AWADDR_AXI_SRAM_0(AWADDR_AXI_SRAM_0),
+ .AWLEN_AXI_SRAM_0(AWLEN_AXI_SRAM_0),
+ .AWSIZE_AXI_SRAM_0(AWSIZE_AXI_SRAM_0),
+ .AWBURST_AXI_SRAM_0(AWBURST_AXI_SRAM_0),
+ .AWLOCK_AXI_SRAM_0(AWLOCK_AXI_SRAM_0),
+ .AWCACHE_AXI_SRAM_0(AWCACHE_AXI_SRAM_0),
+ .AWPROT_AXI_SRAM_0(AWPROT_AXI_SRAM_0),
+ .AWVALID_AXI_SRAM_0(AWVALID_AXI_SRAM_0),
+ .AWREADY_AXI_SRAM_0(AWREADY_AXI_SRAM_0),
+ .WDATA_AXI_SRAM_0(WDATA_AXI_SRAM_0),
+ .WSTRB_AXI_SRAM_0(WSTRB_AXI_SRAM_0),
+ .WLAST_AXI_SRAM_0(WLAST_AXI_SRAM_0),
+ .WVALID_AXI_SRAM_0(WVALID_AXI_SRAM_0),
+ .WREADY_AXI_SRAM_0(WREADY_AXI_SRAM_0),
+ .BID_AXI_SRAM_0(BID_AXI_SRAM_0),
+ .BRESP_AXI_SRAM_0(BRESP_AXI_SRAM_0),
+ .BVALID_AXI_SRAM_0(BVALID_AXI_SRAM_0),
+ .BREADY_AXI_SRAM_0(BREADY_AXI_SRAM_0),
+ .ARID_AXI_SRAM_0(ARID_AXI_SRAM_0),
+ .ARADDR_AXI_SRAM_0(ARADDR_AXI_SRAM_0),
+ .ARLEN_AXI_SRAM_0(ARLEN_AXI_SRAM_0),
+ .ARSIZE_AXI_SRAM_0(ARSIZE_AXI_SRAM_0),
+ .ARBURST_AXI_SRAM_0(ARBURST_AXI_SRAM_0),
+ .ARLOCK_AXI_SRAM_0(ARLOCK_AXI_SRAM_0),
+ .ARCACHE_AXI_SRAM_0(ARCACHE_AXI_SRAM_0),
+ .ARPROT_AXI_SRAM_0(ARPROT_AXI_SRAM_0),
+ .ARVALID_AXI_SRAM_0(ARVALID_AXI_SRAM_0),
+ .ARREADY_AXI_SRAM_0(ARREADY_AXI_SRAM_0),
+ .RID_AXI_SRAM_0(RID_AXI_SRAM_0),
+ .RDATA_AXI_SRAM_0(RDATA_AXI_SRAM_0),
+ .RRESP_AXI_SRAM_0(RRESP_AXI_SRAM_0),
+ .RLAST_AXI_SRAM_0(RLAST_AXI_SRAM_0),
+ .RVALID_AXI_SRAM_0(RVALID_AXI_SRAM_0),
+ .RREADY_AXI_SRAM_0(RREADY_AXI_SRAM_0),
+
+ .AWID_AXI_SRAM_1(AWID_AXI_SRAM_1),
+ .AWADDR_AXI_SRAM_1(AWADDR_AXI_SRAM_1),
+ .AWLEN_AXI_SRAM_1(AWLEN_AXI_SRAM_1),
+ .AWSIZE_AXI_SRAM_1(AWSIZE_AXI_SRAM_1),
+ .AWBURST_AXI_SRAM_1(AWBURST_AXI_SRAM_1),
+ .AWLOCK_AXI_SRAM_1(AWLOCK_AXI_SRAM_1),
+ .AWCACHE_AXI_SRAM_1(AWCACHE_AXI_SRAM_1),
+ .AWPROT_AXI_SRAM_1(AWPROT_AXI_SRAM_1),
+ .AWVALID_AXI_SRAM_1(AWVALID_AXI_SRAM_1),
+ .AWREADY_AXI_SRAM_1(AWREADY_AXI_SRAM_1),
+ .WDATA_AXI_SRAM_1(WDATA_AXI_SRAM_1),
+ .WSTRB_AXI_SRAM_1(WSTRB_AXI_SRAM_1),
+ .WLAST_AXI_SRAM_1(WLAST_AXI_SRAM_1),
+ .WVALID_AXI_SRAM_1(WVALID_AXI_SRAM_1),
+ .WREADY_AXI_SRAM_1(WREADY_AXI_SRAM_1),
+ .BID_AXI_SRAM_1(BID_AXI_SRAM_1),
+ .BRESP_AXI_SRAM_1(BRESP_AXI_SRAM_1),
+ .BVALID_AXI_SRAM_1(BVALID_AXI_SRAM_1),
+ .BREADY_AXI_SRAM_1(BREADY_AXI_SRAM_1),
+ .ARID_AXI_SRAM_1(ARID_AXI_SRAM_1),
+ .ARADDR_AXI_SRAM_1(ARADDR_AXI_SRAM_1),
+ .ARLEN_AXI_SRAM_1(ARLEN_AXI_SRAM_1),
+ .ARSIZE_AXI_SRAM_1(ARSIZE_AXI_SRAM_1),
+ .ARBURST_AXI_SRAM_1(ARBURST_AXI_SRAM_1),
+ .ARLOCK_AXI_SRAM_1(ARLOCK_AXI_SRAM_1),
+ .ARCACHE_AXI_SRAM_1(ARCACHE_AXI_SRAM_1),
+ .ARPROT_AXI_SRAM_1(ARPROT_AXI_SRAM_1),
+ .ARVALID_AXI_SRAM_1(ARVALID_AXI_SRAM_1),
+ .ARREADY_AXI_SRAM_1(ARREADY_AXI_SRAM_1),
+ .RID_AXI_SRAM_1(RID_AXI_SRAM_1),
+ .RDATA_AXI_SRAM_1(RDATA_AXI_SRAM_1),
+ .RRESP_AXI_SRAM_1(RRESP_AXI_SRAM_1),
+ .RLAST_AXI_SRAM_1(RLAST_AXI_SRAM_1),
+ .RVALID_AXI_SRAM_1(RVALID_AXI_SRAM_1),
+ .RREADY_AXI_SRAM_1(RREADY_AXI_SRAM_1),
+
+ .AWID_AXI_SRAM_2(AWID_AXI_SRAM_2),
+ .AWADDR_AXI_SRAM_2(AWADDR_AXI_SRAM_2),
+ .AWLEN_AXI_SRAM_2(AWLEN_AXI_SRAM_2),
+ .AWSIZE_AXI_SRAM_2(AWSIZE_AXI_SRAM_2),
+ .AWBURST_AXI_SRAM_2(AWBURST_AXI_SRAM_2),
+ .AWLOCK_AXI_SRAM_2(AWLOCK_AXI_SRAM_2),
+ .AWCACHE_AXI_SRAM_2(AWCACHE_AXI_SRAM_2),
+ .AWPROT_AXI_SRAM_2(AWPROT_AXI_SRAM_2),
+ .AWVALID_AXI_SRAM_2(AWVALID_AXI_SRAM_2),
+ .AWREADY_AXI_SRAM_2(AWREADY_AXI_SRAM_2),
+ .WDATA_AXI_SRAM_2(WDATA_AXI_SRAM_2),
+ .WSTRB_AXI_SRAM_2(WSTRB_AXI_SRAM_2),
+ .WLAST_AXI_SRAM_2(WLAST_AXI_SRAM_2),
+ .WVALID_AXI_SRAM_2(WVALID_AXI_SRAM_2),
+ .WREADY_AXI_SRAM_2(WREADY_AXI_SRAM_2),
+ .BID_AXI_SRAM_2(BID_AXI_SRAM_2),
+ .BRESP_AXI_SRAM_2(BRESP_AXI_SRAM_2),
+ .BVALID_AXI_SRAM_2(BVALID_AXI_SRAM_2),
+ .BREADY_AXI_SRAM_2(BREADY_AXI_SRAM_2),
+ .ARID_AXI_SRAM_2(ARID_AXI_SRAM_2),
+ .ARADDR_AXI_SRAM_2(ARADDR_AXI_SRAM_2),
+ .ARLEN_AXI_SRAM_2(ARLEN_AXI_SRAM_2),
+ .ARSIZE_AXI_SRAM_2(ARSIZE_AXI_SRAM_2),
+ .ARBURST_AXI_SRAM_2(ARBURST_AXI_SRAM_2),
+ .ARLOCK_AXI_SRAM_2(ARLOCK_AXI_SRAM_2),
+ .ARCACHE_AXI_SRAM_2(ARCACHE_AXI_SRAM_2),
+ .ARPROT_AXI_SRAM_2(ARPROT_AXI_SRAM_2),
+ .ARVALID_AXI_SRAM_2(ARVALID_AXI_SRAM_2),
+ .ARREADY_AXI_SRAM_2(ARREADY_AXI_SRAM_2),
+ .RID_AXI_SRAM_2(RID_AXI_SRAM_2),
+ .RDATA_AXI_SRAM_2(RDATA_AXI_SRAM_2),
+ .RRESP_AXI_SRAM_2(RRESP_AXI_SRAM_2),
+ .RLAST_AXI_SRAM_2(RLAST_AXI_SRAM_2),
+ .RVALID_AXI_SRAM_2(RVALID_AXI_SRAM_2),
+ .RREADY_AXI_SRAM_2(RREADY_AXI_SRAM_2),
+
+ .AWID_AXI_SRAM_3(AWID_AXI_SRAM_3),
+ .AWADDR_AXI_SRAM_3(AWADDR_AXI_SRAM_3),
+ .AWLEN_AXI_SRAM_3(AWLEN_AXI_SRAM_3),
+ .AWSIZE_AXI_SRAM_3(AWSIZE_AXI_SRAM_3),
+ .AWBURST_AXI_SRAM_3(AWBURST_AXI_SRAM_3),
+ .AWLOCK_AXI_SRAM_3(AWLOCK_AXI_SRAM_3),
+ .AWCACHE_AXI_SRAM_3(AWCACHE_AXI_SRAM_3),
+ .AWPROT_AXI_SRAM_3(AWPROT_AXI_SRAM_3),
+ .AWVALID_AXI_SRAM_3(AWVALID_AXI_SRAM_3),
+ .AWREADY_AXI_SRAM_3(AWREADY_AXI_SRAM_3),
+ .WDATA_AXI_SRAM_3(WDATA_AXI_SRAM_3),
+ .WSTRB_AXI_SRAM_3(WSTRB_AXI_SRAM_3),
+ .WLAST_AXI_SRAM_3(WLAST_AXI_SRAM_3),
+ .WVALID_AXI_SRAM_3(WVALID_AXI_SRAM_3),
+ .WREADY_AXI_SRAM_3(WREADY_AXI_SRAM_3),
+ .BID_AXI_SRAM_3(BID_AXI_SRAM_3),
+ .BRESP_AXI_SRAM_3(BRESP_AXI_SRAM_3),
+ .BVALID_AXI_SRAM_3(BVALID_AXI_SRAM_3),
+ .BREADY_AXI_SRAM_3(BREADY_AXI_SRAM_3),
+ .ARID_AXI_SRAM_3(ARID_AXI_SRAM_3),
+ .ARADDR_AXI_SRAM_3(ARADDR_AXI_SRAM_3),
+ .ARLEN_AXI_SRAM_3(ARLEN_AXI_SRAM_3),
+ .ARSIZE_AXI_SRAM_3(ARSIZE_AXI_SRAM_3),
+ .ARBURST_AXI_SRAM_3(ARBURST_AXI_SRAM_3),
+ .ARLOCK_AXI_SRAM_3(ARLOCK_AXI_SRAM_3),
+ .ARCACHE_AXI_SRAM_3(ARCACHE_AXI_SRAM_3),
+ .ARPROT_AXI_SRAM_3(ARPROT_AXI_SRAM_3),
+ .ARVALID_AXI_SRAM_3(ARVALID_AXI_SRAM_3),
+ .ARREADY_AXI_SRAM_3(ARREADY_AXI_SRAM_3),
+ .RID_AXI_SRAM_3(RID_AXI_SRAM_3),
+ .RDATA_AXI_SRAM_3(RDATA_AXI_SRAM_3),
+ .RRESP_AXI_SRAM_3(RRESP_AXI_SRAM_3),
+ .RLAST_AXI_SRAM_3(RLAST_AXI_SRAM_3),
+ .RVALID_AXI_SRAM_3(RVALID_AXI_SRAM_3),
+ .RREADY_AXI_SRAM_3(RREADY_AXI_SRAM_3),
.AWID_AXI_TLX_OUT(AWID_AXI_TLX_OUT),
.AWADDR_AXI_TLX_OUT(AWADDR_AXI_TLX_OUT),
@@ -398,7 +615,6 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.RREADY_AXI_CHIPLET_IN(RREADY_AXI_CHIPLET_IN),
.clk0clk(SYS_CLK),
- .clk0clken(1'b1),
.clk0resetn(aRESETn),
.refclk(SYS_CLK),
.refclken(1'b1),
@@ -520,45 +736,222 @@ sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
assign PLL_LOCK_o = PLL_LOCK & PLL_LOCK_i;
-SRAM_wrapper u_SRAM_wrapper(
+SRAM_wrapper #(.SPLIT_SRAM(0)) u_SRAM_wrapper_0(
+ .ACLK(SYS_CLK),
+ .ARESETn(aRESETn),
+
+ .AWVALID(AWVALID_AXI_SRAM_0),
+ .AWREADY(AWREADY_AXI_SRAM_0),
+ .AWID(AWID_AXI_SRAM_0),
+ .AWADDR(AWADDR_AXI_SRAM_0),
+ .AWLEN(AWLEN_AXI_SRAM_0),
+ .AWSIZE(AWSIZE_AXI_SRAM_0),
+ .AWBURST(AWBURST_AXI_SRAM_0),
+ .AWLOCK(AWLOCK_AXI_SRAM_0),
+ .AWPROT(AWPROT_AXI_SRAM_0),
+ .AWQOS(),
+ .WVALID(WVALID_AXI_SRAM_0),
+ .WREADY(WREADY_AXI_SRAM_0),
+ .WDATA(WDATA_AXI_SRAM_0),
+ .WSTRB(WSTRB_AXI_SRAM_0),
+ .WLAST(WLAST_AXI_SRAM_0),
+ .BVALID(BVALID_AXI_SRAM_0),
+ .BREADY(BREADY_AXI_SRAM_0),
+ .BID(BID_AXI_SRAM_0),
+ .BRESP(BRESP_AXI_SRAM_0),
+ .ARVALID(ARVALID_AXI_SRAM_0),
+ .ARREADY(ARREADY_AXI_SRAM_0),
+ .ARID(ARID_AXI_SRAM_0),
+ .ARADDR(ARADDR_AXI_SRAM_0),
+ .ARLEN(ARLEN_AXI_SRAM_0),
+ .ARSIZE(ARSIZE_AXI_SRAM_0),
+ .ARBURST(ARBURST_AXI_SRAM_0),
+ .ARLOCK(ARLOCK_AXI_SRAM_0),
+ .ARPROT(ARPROT_AXI_SRAM_0),
+ .ARQOS(),
+ .RVALID(RVALID_AXI_SRAM_0),
+ .RREADY(RREADY_AXI_SRAM_0),
+ .RID(RID_AXI_SRAM_0),
+ .RDATA(RDATA_AXI_SRAM_0),
+ .RRESP(RRESP_AXI_SRAM_0),
+ .RLAST(RLAST_AXI_SRAM_0),
+ .AWAKEUP(1'b1),
+
+ .WPOISON(1'b0),
+ .RPOISON(),
+
+ .clk_qreqn(1'b1),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+
+ .pwr_qreqn(1'b1),
+ .pwr_qacceptn(),
+ .pwr_qdeny(),
+ .pwr_qactive(),
+
+ .ext_gt_qreqn(1'b1),
+ .ext_gt_qacceptn(),
+ .cfg_gate_resp(1'b0)
+);
+
+SRAM_wrapper #(.SPLIT_SRAM(0)) u_SRAM_wrapper_1(
+ .ACLK(SYS_CLK),
+ .ARESETn(aRESETn),
+
+ .AWVALID(AWVALID_AXI_SRAM_1),
+ .AWREADY(AWREADY_AXI_SRAM_1),
+ .AWID(AWID_AXI_SRAM_1),
+ .AWADDR(AWADDR_AXI_SRAM_1),
+ .AWLEN(AWLEN_AXI_SRAM_1),
+ .AWSIZE(AWSIZE_AXI_SRAM_1),
+ .AWBURST(AWBURST_AXI_SRAM_1),
+ .AWLOCK(AWLOCK_AXI_SRAM_1),
+ .AWPROT(AWPROT_AXI_SRAM_1),
+ .AWQOS(),
+ .WVALID(WVALID_AXI_SRAM_1),
+ .WREADY(WREADY_AXI_SRAM_1),
+ .WDATA(WDATA_AXI_SRAM_1),
+ .WSTRB(WSTRB_AXI_SRAM_1),
+ .WLAST(WLAST_AXI_SRAM_1),
+ .BVALID(BVALID_AXI_SRAM_1),
+ .BREADY(BREADY_AXI_SRAM_1),
+ .BID(BID_AXI_SRAM_1),
+ .BRESP(BRESP_AXI_SRAM_1),
+ .ARVALID(ARVALID_AXI_SRAM_1),
+ .ARREADY(ARREADY_AXI_SRAM_1),
+ .ARID(ARID_AXI_SRAM_1),
+ .ARADDR(ARADDR_AXI_SRAM_1),
+ .ARLEN(ARLEN_AXI_SRAM_1),
+ .ARSIZE(ARSIZE_AXI_SRAM_1),
+ .ARBURST(ARBURST_AXI_SRAM_1),
+ .ARLOCK(ARLOCK_AXI_SRAM_1),
+ .ARPROT(ARPROT_AXI_SRAM_1),
+ .ARQOS(),
+ .RVALID(RVALID_AXI_SRAM_1),
+ .RREADY(RREADY_AXI_SRAM_1),
+ .RID(RID_AXI_SRAM_1),
+ .RDATA(RDATA_AXI_SRAM_1),
+ .RRESP(RRESP_AXI_SRAM_1),
+ .RLAST(RLAST_AXI_SRAM_1),
+ .AWAKEUP(1'b1),
+
+ .WPOISON(1'b0),
+ .RPOISON(),
+
+ .clk_qreqn(1'b1),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+
+ .pwr_qreqn(1'b1),
+ .pwr_qacceptn(),
+ .pwr_qdeny(),
+ .pwr_qactive(),
+
+ .ext_gt_qreqn(1'b1),
+ .ext_gt_qacceptn(),
+ .cfg_gate_resp(1'b0)
+);
+
+SRAM_wrapper #(.SPLIT_SRAM(0)) u_SRAM_wrapper_2(
+ .ACLK(SYS_CLK),
+ .ARESETn(aRESETn),
+
+ .AWVALID(AWVALID_AXI_SRAM_2),
+ .AWREADY(AWREADY_AXI_SRAM_2),
+ .AWID(AWID_AXI_SRAM_2),
+ .AWADDR(AWADDR_AXI_SRAM_2),
+ .AWLEN(AWLEN_AXI_SRAM_2),
+ .AWSIZE(AWSIZE_AXI_SRAM_2),
+ .AWBURST(AWBURST_AXI_SRAM_2),
+ .AWLOCK(AWLOCK_AXI_SRAM_2),
+ .AWPROT(AWPROT_AXI_SRAM_2),
+ .AWQOS(),
+ .WVALID(WVALID_AXI_SRAM_2),
+ .WREADY(WREADY_AXI_SRAM_2),
+ .WDATA(WDATA_AXI_SRAM_2),
+ .WSTRB(WSTRB_AXI_SRAM_2),
+ .WLAST(WLAST_AXI_SRAM_2),
+ .BVALID(BVALID_AXI_SRAM_2),
+ .BREADY(BREADY_AXI_SRAM_2),
+ .BID(BID_AXI_SRAM_2),
+ .BRESP(BRESP_AXI_SRAM_2),
+ .ARVALID(ARVALID_AXI_SRAM_2),
+ .ARREADY(ARREADY_AXI_SRAM_2),
+ .ARID(ARID_AXI_SRAM_2),
+ .ARADDR(ARADDR_AXI_SRAM_2),
+ .ARLEN(ARLEN_AXI_SRAM_2),
+ .ARSIZE(ARSIZE_AXI_SRAM_2),
+ .ARBURST(ARBURST_AXI_SRAM_2),
+ .ARLOCK(ARLOCK_AXI_SRAM_2),
+ .ARPROT(ARPROT_AXI_SRAM_2),
+ .ARQOS(),
+ .RVALID(RVALID_AXI_SRAM_2),
+ .RREADY(RREADY_AXI_SRAM_2),
+ .RID(RID_AXI_SRAM_2),
+ .RDATA(RDATA_AXI_SRAM_2),
+ .RRESP(RRESP_AXI_SRAM_2),
+ .RLAST(RLAST_AXI_SRAM_2),
+ .AWAKEUP(1'b1),
+
+ .WPOISON(1'b0),
+ .RPOISON(),
+
+ .clk_qreqn(1'b1),
+ .clk_qacceptn(),
+ .clk_qdeny(),
+ .clk_qactive(),
+
+ .pwr_qreqn(1'b1),
+ .pwr_qacceptn(),
+ .pwr_qdeny(),
+ .pwr_qactive(),
+
+ .ext_gt_qreqn(1'b1),
+ .ext_gt_qacceptn(),
+ .cfg_gate_resp(1'b0)
+);
+
+SRAM_wrapper #(.SPLIT_SRAM(1)) u_SRAM_wrapper_3(
.ACLK(SYS_CLK),
.ARESETn(aRESETn),
- .AWVALID(AWVALID_AXI_SRAM),
- .AWREADY(AWREADY_AXI_SRAM),
- .AWID(AWID_AXI_SRAM),
- .AWADDR(AWADDR_AXI_SRAM),
- .AWLEN(AWLEN_AXI_SRAM),
- .AWSIZE(AWSIZE_AXI_SRAM),
- .AWBURST(AWBURST_AXI_SRAM),
- .AWLOCK(AWLOCK_AXI_SRAM),
- .AWPROT(AWPROT_AXI_SRAM),
+ .AWVALID(AWVALID_AXI_SRAM_3),
+ .AWREADY(AWREADY_AXI_SRAM_3),
+ .AWID(AWID_AXI_SRAM_3),
+ .AWADDR(AWADDR_AXI_SRAM_3),
+ .AWLEN(AWLEN_AXI_SRAM_3),
+ .AWSIZE(AWSIZE_AXI_SRAM_3),
+ .AWBURST(AWBURST_AXI_SRAM_3),
+ .AWLOCK(AWLOCK_AXI_SRAM_3),
+ .AWPROT(AWPROT_AXI_SRAM_3),
.AWQOS(),
- .WVALID(WVALID_AXI_SRAM),
- .WREADY(WREADY_AXI_SRAM),
- .WDATA(WDATA_AXI_SRAM),
- .WSTRB(WSTRB_AXI_SRAM),
- .WLAST(WLAST_AXI_SRAM),
- .BVALID(BVALID_AXI_SRAM),
- .BREADY(BREADY_AXI_SRAM),
- .BID(BID_AXI_SRAM),
- .BRESP(BRESP_AXI_SRAM),
- .ARVALID(ARVALID_AXI_SRAM),
- .ARREADY(ARREADY_AXI_SRAM),
- .ARID(ARID_AXI_SRAM),
- .ARADDR(ARADDR_AXI_SRAM),
- .ARLEN(ARLEN_AXI_SRAM),
- .ARSIZE(ARSIZE_AXI_SRAM),
- .ARBURST(ARBURST_AXI_SRAM),
- .ARLOCK(ARLOCK_AXI_SRAM),
- .ARPROT(ARPROT_AXI_SRAM),
+ .WVALID(WVALID_AXI_SRAM_3),
+ .WREADY(WREADY_AXI_SRAM_3),
+ .WDATA(WDATA_AXI_SRAM_3),
+ .WSTRB(WSTRB_AXI_SRAM_3),
+ .WLAST(WLAST_AXI_SRAM_3),
+ .BVALID(BVALID_AXI_SRAM_3),
+ .BREADY(BREADY_AXI_SRAM_3),
+ .BID(BID_AXI_SRAM_3),
+ .BRESP(BRESP_AXI_SRAM_3),
+ .ARVALID(ARVALID_AXI_SRAM_3),
+ .ARREADY(ARREADY_AXI_SRAM_3),
+ .ARID(ARID_AXI_SRAM_3),
+ .ARADDR(ARADDR_AXI_SRAM_3),
+ .ARLEN(ARLEN_AXI_SRAM_3),
+ .ARSIZE(ARSIZE_AXI_SRAM_3),
+ .ARBURST(ARBURST_AXI_SRAM_3),
+ .ARLOCK(ARLOCK_AXI_SRAM_3),
+ .ARPROT(ARPROT_AXI_SRAM_3),
.ARQOS(),
- .RVALID(RVALID_AXI_SRAM),
- .RREADY(RREADY_AXI_SRAM),
- .RID(RID_AXI_SRAM),
- .RDATA(RDATA_AXI_SRAM),
- .RRESP(RRESP_AXI_SRAM),
- .RLAST(RLAST_AXI_SRAM),
+ .RVALID(RVALID_AXI_SRAM_3),
+ .RREADY(RREADY_AXI_SRAM_3),
+ .RID(RID_AXI_SRAM_3),
+ .RDATA(RDATA_AXI_SRAM_3),
+ .RRESP(RRESP_AXI_SRAM_3),
+ .RLAST(RLAST_AXI_SRAM_3),
.AWAKEUP(1'b1),
.WPOISON(1'b0),
diff --git a/makefile b/makefile
index f60a4ca91e5b87a5a1953c5f82c8001839330ca6..aef9050ef6a2164b6832317eadd2a183c0245590 100644
--- a/makefile
+++ b/makefile
@@ -7,11 +7,13 @@ include ./make.cfg
# - Commonly Overloaded Variables
#-------------------------------------
# Simulator type (mti/vcs/xm)
-SIMULATOR = mti
+SIMULATOR = vcs
# IS this for an ASIC Flow?
ASIC ?= no
+GATE_SIMS ?= no
+
build_sie300_sram_ctrl:
@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
build_nic400_sram_chiplet:
@@ -45,6 +47,8 @@ SIM_DIR ?= $(SIM_TOP_DIR)
ifeq ($(ASIC),yes)
DESIGN_VC_ASIC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm_ASIC.flist
DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm.flist
+else ifeq ($(GATE_SIMS),yes)
+ DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm_GATE.flist
else
DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet.flist
endif
diff --git a/pad_level/glib/SRAM_chiplet.sv b/pad_level/glib/SRAM_chiplet.sv
new file mode 100644
index 0000000000000000000000000000000000000000..7f544ecd408ee6259eb08d351232a1bf6137f7bd
--- /dev/null
+++ b/pad_level/glib/SRAM_chiplet.sv
@@ -0,0 +1,156 @@
+//-----------------------------------------------------------------------------
+// Top pad level of SRAM chiplet for TSMC 28nm HPC+
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+`include "tlx_interfaces.sv"
+// Total pins = 106 (excluding power)
+
+module SRAM_chiplet(
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+ input wire PAD_REF_CLK,
+ input wire PAD_aRESETn,
+ input wire PAD_DL_FWD_RESETn,
+ input wire PAD_IN_FWD_CLK,
+ output wire PAD_IN_REV_CLK,
+ output wire PAD_OUT_FWD_CLK,
+ input wire PAD_OUT_REV_CLK,
+ output wire PAD_PLL_LOCK_o,
+ input wire PAD_PLL_LOCK_i,
+
+ // TLX_IN_data_rev_0 tlx out
+ output wire [15:0] PAD_TLX_IN_data_rev_0_tdata,
+ output wire PAD_TLX_IN_data_rev_0_tvalid,
+ input wire PAD_TLX_IN_data_rev_0_tready,
+
+ //TLX_IN_flow_rev_0 tlx out
+ output wire [2:0] PAD_TLX_IN_flow_rev_0_tdata,
+ output wire PAD_TLX_IN_flow_rev_0_tvalid,
+ input wire PAD_TLX_IN_flow_rev_0_tready,
+
+ //tlx in
+ input wire [1:0] PAD_TLX_IN_flow_fwd_0_tdata,
+ input wire PAD_TLX_IN_flow_fwd_0_tvalid,
+ output wire PAD_TLX_IN_flow_fwd_0_tready,
+
+ //tlx in
+ input wire [15:0] PAD_TLX_IN_data_fwd_0_tdata,
+ input wire PAD_TLX_IN_data_fwd_0_tvalid,
+ output wire PAD_TLX_IN_data_fwd_0_tready,
+
+ //tlx in
+ input wire [15:0] PAD_TLX_data_rev_1_tdata,
+ input wire PAD_TLX_data_rev_1_tvalid,
+ output wire PAD_TLX_data_rev_1_tready,
+
+ //tlx in
+ input wire [2:0] PAD_TLX_flow_rev_1_tdata,
+ input wire PAD_TLX_flow_rev_1_tvalid,
+ output wire PAD_TLX_flow_rev_1_tready,
+
+ // tlx out
+ output wire [1:0] PAD_TLX_flow_fwd_1_tdata,
+ output wire PAD_TLX_flow_fwd_1_tvalid,
+ input wire PAD_TLX_flow_fwd_1_tready,
+
+ // tlx out
+ output wire [15:0] PAD_TLX_data_fwd_1_tdata,
+ output wire PAD_TLX_data_fwd_1_tvalid,
+ input wire PAD_TLX_data_fwd_1_tready,
+
+ input wire [3:0] PAD_addr_sel
+);
+
+// Thin links from NIC_TB to SRAM_chiplet_0
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_IN_flow_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_IN_flow_fwd_0();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_fwd_0();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_1();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_1();
+
+ // TLX_IN_data_rev_0 tlx out
+assign PAD_TLX_IN_data_rev_0_tdata = TLX_IN_data_rev_0.tdata;
+assign PAD_TLX_IN_data_rev_0_tvalid = TLX_IN_data_rev_0.tvalid;
+assign TLX_IN_data_rev_0.tready = PAD_TLX_IN_data_rev_0_tready;
+
+ //TLX_IN_flow_rev_0 tlx out
+assign PAD_TLX_IN_flow_rev_0_tdata = TLX_IN_flow_rev_0.tdata;
+assign PAD_TLX_IN_flow_rev_0_tvalid = TLX_IN_flow_rev_0.tvalid;
+assign TLX_IN_flow_rev_0.tready = PAD_TLX_IN_flow_rev_0_tready;
+
+ //tlx in
+assign TLX_IN_flow_fwd_0.tdata = PAD_TLX_IN_flow_fwd_0_tdata;
+assign TLX_IN_flow_fwd_0.tvalid = PAD_TLX_IN_flow_fwd_0_tvalid;
+assign PAD_TLX_IN_flow_fwd_0_tready = TLX_IN_flow_fwd_0.tready;
+
+ //tlx in
+assign TLX_IN_data_fwd_0.tdata = PAD_TLX_IN_data_fwd_0_tdata;
+assign TLX_IN_data_fwd_0.tvalid = PAD_TLX_IN_data_fwd_0_tvalid;
+assign PAD_TLX_IN_data_fwd_0_tready = TLX_IN_data_fwd_0.tready;
+
+ //tlx in
+assign TLX_data_rev_1.tdata = PAD_TLX_data_rev_1_tdata;
+assign TLX_data_rev_1.tvalid = PAD_TLX_data_rev_1_tvalid;
+assign PAD_TLX_data_rev_1_tready = TLX_data_rev_1.tready;
+
+ //tlx in
+assign TLX_flow_rev_1.tdata = PAD_TLX_flow_rev_1_tdata;
+assign TLX_flow_rev_1.tvalid = PAD_TLX_flow_rev_1_tvalid;
+assign PAD_TLX_flow_rev_1_tready = TLX_flow_rev_1.tready;
+
+ // tlx out
+assign PAD_TLX_flow_fwd_1_tdata = TLX_flow_fwd_1.tdata;
+assign PAD_TLX_flow_fwd_1_tvalid = TLX_flow_fwd_1.tvalid;
+assign TLX_flow_fwd_1.tready = PAD_TLX_flow_fwd_1_tready;
+
+ // tlx out
+assign PAD_TLX_data_fwd_1_tdata = TLX_data_fwd_1.tdata;
+assign PAD_TLX_data_fwd_1_tvalid = TLX_data_fwd_1.tvalid;
+assign TLX_data_fwd_1.tready = PAD_TLX_data_fwd_1_tready;
+
+
+
+top_sram_chiplet #(.N_ADDR_SEL_BITS(4)) u_top_sram_chiplet (
+ .REF_CLK(PAD_REF_CLK),
+ .aRESETn(PAD_aRESETn),
+ .DL_FWD_RESETn(PAD_DL_FWD_RESETn),
+
+ .IN_FWD_CLK(PAD_IN_FWD_CLK),
+ .IN_REV_CLK(PAD_IN_REV_CLK),
+ .OUT_FWD_CLK(PAD_OUT_FWD_CLK),
+ .OUT_REV_CLK(PAD_OUT_REV_CLK),
+ .PLL_LOCK_o(PAD_PLL_LOCK_o),
+ .PLL_LOCK_i(PAD_PLL_LOCK_i),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_IN_data_rev_0),
+ .TLX_IN_flow_rev(TLX_IN_flow_rev_0),
+ .TLX_IN_flow_fwd(TLX_IN_flow_fwd_0),
+ .TLX_IN_data_fwd(TLX_IN_data_fwd_0),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_1),
+ .TLX_OUT_flow_rev(TLX_flow_rev_1),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_1),
+ .TLX_OUT_data_fwd(TLX_data_fwd_1),
+
+ // Address Select pins
+ .addr_sel(PAD_addr_sel)
+);
+
+endmodule
\ No newline at end of file
diff --git a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
index 9ff678caaffab321580f3c5aea6cf6d255971ee3..8ccf07435754a7449c0bd5f7749aae550c3af805 100644
--- a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
+++ b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.sv
@@ -10,6 +10,8 @@
//-----------------------------------------------------------------------------
`include "tlx_interfaces.sv"
+// Total pins = 106 (excluding power)
+
module SRAM_chiplet(
`ifdef POWER_PINS
inout wire VDDIO,
@@ -17,60 +19,95 @@ module SRAM_chiplet(
inout wire VDD,
inout wire VSS,
`endif
- input wire REF_CLK,
- input wire aRESETn,
- input wire DL_FWD_RESETn,
- input wire IN_FWD_CLK,
- output wire IN_REV_CLK,
- output wire OUT_FWD_CLK,
- input wire OUT_REV_CLK,
- output wire OUT_CLK,
- output wire PLL_LOCK_o,
- input wire PLL_LOCK_i,
+ input wire PAD_REF_CLK,
+ input wire PAD_aRESETn,
+ input wire PAD_DL_FWD_RESETn,
+ input wire PAD_IN_FWD_CLK,
+ output wire PAD_IN_REV_CLK,
+ output wire PAD_OUT_FWD_CLK,
+ input wire PAD_OUT_REV_CLK,
+ output wire PAD_PLL_LOCK_o,
+ input wire PAD_PLL_LOCK_i,
+
+ input wire PAD_VPREF,
// TLX_IN_data_rev_0 tlx out
- output wire [15:0] TLX_IN_data_rev_0_tdata,
- output wire TLX_IN_data_rev_0_tvalid,
- input wire TLX_IN_data_rev_0_tready,
+ output wire [15:0] PAD_TLX_IN_data_rev_0_tdata,
+ output wire PAD_TLX_IN_data_rev_0_tvalid,
+ input wire PAD_TLX_IN_data_rev_0_tready,
//TLX_IN_flow_rev_0 tlx out
- output wire [2:0] TLX_IN_flow_rev_0_tdata,
- output wire TLX_IN_flow_rev_0_tvalid,
- input wire TLX_IN_flow_rev_0_tready,
+ output wire [2:0] PAD_TLX_IN_flow_rev_0_tdata,
+ output wire PAD_TLX_IN_flow_rev_0_tvalid,
+ input wire PAD_TLX_IN_flow_rev_0_tready,
//tlx in
- input wire [1:0] TLX_IN_flow_fwd_0_tdata,
- input wire TLX_IN_flow_fwd_0_tvalid,
- output wire TLX_IN_flow_fwd_0_tready,
+ input wire [1:0] PAD_TLX_IN_flow_fwd_0_tdata,
+ input wire PAD_TLX_IN_flow_fwd_0_tvalid,
+ output wire PAD_TLX_IN_flow_fwd_0_tready,
//tlx in
- input wire [15:0] TLX_IN_data_fwd_0_tdata,
- input wire TLX_IN_data_fwd_0_tvalid,
- output wire TLX_IN_data_fwd_0_tready,
+ input wire [15:0] PAD_TLX_IN_data_fwd_0_tdata,
+ input wire PAD_TLX_IN_data_fwd_0_tvalid,
+ output wire PAD_TLX_IN_data_fwd_0_tready,
//tlx in
- input wire [15:0] TLX_data_rev_1_tdata,
- input wire TLX_data_rev_1_tvalid,
- output wire TLX_data_rev_1_tready,
+ input wire [15:0] PAD_TLX_data_rev_1_tdata,
+ input wire PAD_TLX_data_rev_1_tvalid,
+ output wire PAD_TLX_data_rev_1_tready,
//tlx in
- input wire [2:0] TLX_flow_rev_1_tdata,
- input wire TLX_flow_rev_1_tvalid,
- output wire TLX_flow_rev_1_tready,
+ input wire [2:0] PAD_TLX_flow_rev_1_tdata,
+ input wire PAD_TLX_flow_rev_1_tvalid,
+ output wire PAD_TLX_flow_rev_1_tready,
// tlx out
- output wire [1:0] TLX_flow_fwd_1_tdata,
- output wire TLX_flow_fwd_1_tvalid,
- input wire TLX_flow_fwd_1_tready,
+ output wire [1:0] PAD_TLX_flow_fwd_1_tdata,
+ output wire PAD_TLX_flow_fwd_1_tvalid,
+ input wire PAD_TLX_flow_fwd_1_tready,
// tlx out
- output wire [15:0] TLX_data_fwd_1_tdata,
- output wire TLX_data_fwd_1_tvalid,
- input wire TLX_data_fwd_1_tready,
+ output wire [15:0] PAD_TLX_data_fwd_1_tdata,
+ output wire PAD_TLX_data_fwd_1_tvalid,
+ input wire PAD_TLX_data_fwd_1_tready,
- input wire [5:0] addr_sel
+ input wire [3:0] PAD_addr_sel
);
+wire REF_CLK;
+wire aRESETn;
+wire DL_FWD_RESETn;
+wire IN_FWD_CLK;
+wire IN_REV_CLK;
+wire OUT_FWD_CLK;
+wire OUT_REV_CLK;
+wire PLL_LOCK_o;
+wire PLL_LOCK_i;
+wire [3:0] addr_sel;
+wire [15:0] TLX_IN_data_rev_0_tdata;
+wire TLX_IN_data_rev_0_tvalid;
+wire TLX_IN_data_rev_0_tready;
+wire [2:0] TLX_IN_flow_rev_0_tdata;
+wire TLX_IN_flow_rev_0_tvalid;
+wire TLX_IN_flow_rev_0_tready;
+wire [1:0] TLX_IN_flow_fwd_0_tdata;
+wire TLX_IN_flow_fwd_0_tvalid;
+wire TLX_IN_flow_fwd_0_tready;
+wire [15:0] TLX_IN_data_fwd_0_tdata;
+wire TLX_IN_data_fwd_0_tvalid;
+wire TLX_IN_data_fwd_0_tready;
+wire [15:0] TLX_data_rev_1_tdata;
+wire TLX_data_rev_1_tvalid;
+wire TLX_data_rev_1_tready;
+wire [2:0] TLX_flow_rev_1_tdata;
+wire TLX_flow_rev_1_tvalid;
+wire TLX_flow_rev_1_tready;
+wire [1:0] TLX_flow_fwd_1_tdata;
+wire TLX_flow_fwd_1_tvalid;
+wire TLX_flow_fwd_1_tready;
+wire [15:0] TLX_data_fwd_1_tdata;
+wire TLX_data_fwd_1_tvalid;
+wire TLX_data_fwd_1_tready;
// Thin links from NIC_TB to SRAM_chiplet_0
TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_0();
@@ -125,8 +162,416 @@ assign TLX_data_fwd_1_tvalid = TLX_data_fwd_1.tvalid;
assign TLX_data_fwd_1.tready = TLX_data_fwd_1_tready;
+genvar i;
+generate
+ for(i=0;i<16;i=i+1) begin : TLX_data_tdata
+ PDDW04DGZ_V_G u_TLX_IN_data_rev_tdata(
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_data_rev_0_tdata[i]),
+ .C(),
+ .PAD(PAD_TLX_IN_data_rev_0_tdata[i])
+ );
+ PDDW04DGZ_V_G u_TLX_IN_data_fwd_tdata(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_data_fwd_0_tdata[i]),
+ .PAD(PAD_TLX_IN_data_fwd_0_tdata[i])
+ );
+ PDDW04DGZ_V_G u_TLX_data_rev_1_tdata(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_data_rev_1_tdata[i]),
+ .PAD(PAD_TLX_data_rev_1_tdata[i])
+ );
+ PDDW04DGZ_V_G u_TLX_data_fwd_1_tdata(
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_data_fwd_1_tdata[i]),
+ .C(),
+ .PAD(PAD_TLX_data_fwd_1_tdata[i])
+ );
+ end
+endgenerate
+
+// Thin Links Outputs
+PDDW04DGZ_V_G u_PAD_TLX_IN_data_rev_0_tvalid(
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_data_rev_0_tvalid),
+ .C(),
+ .PAD(PAD_TLX_IN_data_rev_0_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_rev_0_tdata_0 (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_flow_rev_0_tdata[0]),
+ .C(),
+ .PAD(PAD_TLX_IN_flow_rev_0_tdata[0])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_rev_0_tdata_1 (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_flow_rev_0_tdata[1]),
+ .C(),
+ .PAD(PAD_TLX_IN_flow_rev_0_tdata[1])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_rev_0_tdata_2 (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_flow_rev_0_tdata[2]),
+ .C(),
+ .PAD(PAD_TLX_IN_flow_rev_0_tdata[2])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_rev_0_tvalid(
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_flow_rev_0_tvalid),
+ .C(),
+ .PAD(PAD_TLX_IN_flow_rev_0_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_fwd_0_tready (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_flow_fwd_0_tready),
+ .C(),
+ .PAD(PAD_TLX_IN_flow_fwd_0_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_data_fwd_0_tready (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_IN_data_fwd_0_tready),
+ .C(),
+ .PAD(PAD_TLX_IN_data_fwd_0_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_data_rev_1_tready (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_data_rev_1_tready),
+ .C(),
+ .PAD(PAD_TLX_data_rev_1_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_rev_1_tready (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_flow_rev_1_tready),
+ .C(),
+ .PAD(PAD_TLX_flow_rev_1_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_fwd_1_tdata_0 (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_flow_fwd_1_tdata[0]),
+ .C(),
+ .PAD(PAD_TLX_flow_fwd_1_tdata[0])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_fwd_1_tdata_1 (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_flow_fwd_1_tdata[1]),
+ .C(),
+ .PAD(PAD_TLX_flow_fwd_1_tdata[1])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_fwd_1_tvalid (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_flow_fwd_1_tvalid),
+ .C(),
+ .PAD(PAD_TLX_flow_fwd_1_tvalid)
+);
+
+
+PDDW04DGZ_V_G u_PAD_TLX_data_fwd_1_tvalid (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(TLX_data_fwd_1_tvalid),
+ .C(),
+ .PAD(PAD_TLX_data_fwd_1_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_IN_REV_CLK (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(IN_REV_CLK),
+ .C(),
+ .PAD(PAD_IN_REV_CLK)
+);
+
+PDDW04DGZ_V_G u_PAD_OUT_FWD_CLK (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(OUT_FWD_CLK),
+ .C(),
+ .PAD(PAD_OUT_FWD_CLK)
+);
+
+PDDW04DGZ_V_G u_PAD_PLL_LOCK_o (
+ .OEN(1'b0),
+ .REN(1'b1),
+ .I(PLL_LOCK_o),
+ .C(),
+ .PAD(PAD_PLL_LOCK_o)
+);
+
+// inputs
+PDDW04DGZ_V_G u_PAD_REF_CLK(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(REF_CLK),
+ .PAD(PAD_REF_CLK)
+);
+
+PDDW04DGZ_V_G u_PAD_aRESETn(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(aRESETn),
+ .PAD(PAD_aRESETn)
+);
+
+PDDW04DGZ_V_G u_PAD_DL_FWD_RESETn(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(DL_FWD_RESETn),
+ .PAD(PAD_DL_FWD_RESETn)
+);
+
+PDDW04DGZ_V_G u_PAD_IN_FWD_CLK(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(IN_FWD_CLK),
+ .PAD(PAD_IN_FWD_CLK)
+);
+
+PDDW04DGZ_V_G u_PAD_OUT_REV_CLK(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(OUT_REV_CLK),
+ .PAD(PAD_OUT_REV_CLK)
+);
+
+PDDW04DGZ_V_G u_PAD_PLL_LOCK_i(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(PLL_LOCK_i),
+ .PAD(PAD_PLL_LOCK_i)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_data_rev_0_tready(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_data_rev_0_tready),
+ .PAD(PAD_TLX_IN_data_rev_0_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_rev_0_tready(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_flow_rev_0_tready),
+ .PAD(PAD_TLX_IN_flow_rev_0_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_fwd_0_tdata_0(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_flow_fwd_0_tdata[0]),
+ .PAD(PAD_TLX_IN_flow_fwd_0_tdata[0])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_fwd_0_tdata_1(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_flow_fwd_0_tdata[1]),
+ .PAD(PAD_TLX_IN_flow_fwd_0_tdata[1])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_flow_fwd_0_tvalid(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_flow_fwd_0_tvalid),
+ .PAD(PAD_TLX_IN_flow_fwd_0_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_IN_data_fwd_0_tvalid(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_IN_data_fwd_0_tvalid),
+ .PAD(PAD_TLX_IN_data_fwd_0_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_data_rev_1_tvalid(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_data_rev_1_tvalid),
+ .PAD(PAD_TLX_data_rev_1_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_rev_1_tdata_0(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_flow_rev_1_tdata[0]),
+ .PAD(PAD_TLX_flow_rev_1_tdata[0])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_rev_1_tdata_1(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_flow_rev_1_tdata[1]),
+ .PAD(PAD_TLX_flow_rev_1_tdata[1])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_rev_1_tdata_2(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_flow_rev_1_tdata[2]),
+ .PAD(PAD_TLX_flow_rev_1_tdata[2])
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_rev_1_tvalid(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_flow_rev_1_tvalid),
+ .PAD(PAD_TLX_flow_rev_1_tvalid)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_flow_fwd_1_tready(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_flow_fwd_1_tready),
+ .PAD(PAD_TLX_flow_fwd_1_tready)
+);
+
+PDDW04DGZ_V_G u_PAD_TLX_data_fwd_1_tready(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(TLX_data_fwd_1_tready),
+ .PAD(PAD_TLX_data_fwd_1_tready)
+);
+
+genvar j;
+generate
+ for(j=0;j<4;j=j+1) begin : gen_addr_sel
+ PDDW04DGZ_V_G u_PAD_addr_sel(
+ .OEN(1'b1),
+ .REN(1'b1),
+ .I(1'b0),
+ .C(addr_sel[j]),
+ .PAD(PAD_addr_sel[j])
+ );
+ end
+endgenerate
+
+// Power
+ PVDD1DGZ_H_G u_PAD_VDD_top(
+
+ );
+ PVDD1DGZ_H_G u_PAD_VDD_left(
+
+ );
+ PVDD1DGZ_H_G u_PAD_VDD_right(
+
+ );
+ PVDD1DGZ_H_G u_PAD_VDD_top_right(
+
+ );
+
+ PVDD1DGZ_H_G u_PAD_VDD_bottom(
+
+ );
+
+ PVDD2POC_H_G u_PAD_VDDIO_POC_left(
+
+ );
+
+ PVDD2DGZ_H_G u_PAD_VDDIO_right(
+
+ );
+
+ PVDD2DGZ_H_G u_PAD_VDDIO_top(
+
+ );
+
+ PVDD2DGZ_H_G u_PAD_VDDIO_bottom(
+
+ );
+
+
+
+ PVSS2DGZ_H_G u_PAD_VSSIO_left(
+
+ );
+
+ PVSS2DGZ_H_G u_PAD_VSSIO_right(
+
+ );
+
+ PVSS2DGZ_H_G u_PAD_VSSIO_top(
+
+ );
+
+ PVSS2DGZ_H_G u_PAD_VSSIO_bottom(
+
+ );
+
+
+ PVSS1DGZ_H_G u_PAD_VSS_top(
+
+ );
+ PVSS1DGZ_H_G u_PAD_VSS_left(
+
+ );
+ PVSS1DGZ_H_G u_PAD_VSS_right(
+
+ );
+ PVSS1DGZ_H_G u_PAD_VSS_bottom(
+
+ );
+
+ PVDD1ANA_H_G u_PAD_AVDD_left(
+
+ );
+ PVDD2ANA_H_G u_PAD_AVDDHV_left(
+
+ );
+ PVSS1ANA_H_G u_PAD_AGND_left(
+
+ );
+ PVSS2ANA_H_G u_PAD_AGNDHV_left(
+
+ );
-top_sram_chiplet u_top_sram_chiplet(
+top_sram_chiplet #(.N_ADDR_SEL_BITS(4)) u_top_sram_chiplet (
.REF_CLK(REF_CLK),
.aRESETn(aRESETn),
.DL_FWD_RESETn(DL_FWD_RESETn),
@@ -135,7 +580,6 @@ top_sram_chiplet u_top_sram_chiplet(
.IN_REV_CLK(IN_REV_CLK),
.OUT_FWD_CLK(OUT_FWD_CLK),
.OUT_REV_CLK(OUT_REV_CLK),
- .OUT_CLK(OUT_CLK),
.PLL_LOCK_o(PLL_LOCK_o),
.PLL_LOCK_i(PLL_LOCK_i),
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index 9cf86bb26a8032e22ffbec30f4234013171a47a6..d20e167e45979905defe11889c139237035c860b 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -49,7 +49,7 @@ CONFIG_NAME: sram_chiplet
# ADDR_WIDTH: AXI5 Address Bus width
# Valid values:
# 14-24
-ADDR_WIDTH: 20
+ADDR_WIDTH: 19
#
@@ -123,14 +123,14 @@ W_BUF_SIZE: 8
# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
# Valid values:
# [BYPASS,FULL]
-REGISTER_AXI_AR: BYPASS
+REGISTER_AXI_AR: FULL
#
# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
# Valid values:
# [BYPASS,FULL]
-REGISTER_AXI_R: BYPASS
+REGISTER_AXI_R: FULL
#
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index dfaa1e18af309c64a01d7a994faae55829603368..c3232bcf67696b8ab78171fd9d13ab67532a3393 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -97,7 +97,7 @@
<LowLatency>false</LowLatency>
</SlaveInterface>
<MasterInterface>
- <Name>AXI_SRAM</Name>
+ <Name>AXI_SRAM_0</Name>
<AXI4MasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
@@ -143,6 +143,63 @@
<APBGroupRef>apb_group0</APBGroupRef>
</APB4MasterProtocol>
<GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>ref</ClockRef>
+ </MasterInterface>
+ <MasterInterface>
+ <Name>AXI_SRAM_1</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>false</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ <MasterInterface>
+ <Name>AXI_SRAM_2</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>false</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ <MasterInterface>
+ <Name>AXI_SRAM_3</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>false</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
</Interfaces>
@@ -153,15 +210,15 @@
<InterfaceRef>AXI_CHIPLET_IN</InterfaceRef>
</MemoryMapSource>
<MappedBlock>
- <InterfaceRef>AXI_SRAM</InterfaceRef>
+ <InterfaceRef>AXI_SRAM_0</InterfaceRef>
<Offset>0</Offset>
- <Range>1048576</Range>
+ <Range>524288</Range>
<Visibility>true</Visibility>
</MappedBlock>
<MappedBlock>
<InterfaceRef>AXI_TLX_OUT</InterfaceRef>
- <Offset>1048576</Offset>
- <Range>66060288</Range>
+ <Offset>2097152</Offset>
+ <Range>65011712</Range>
<Visibility>true</Visibility>
</MappedBlock>
<MappedBlock>
@@ -170,6 +227,24 @@
<Range>67108864</Range>
<Visibility>true</Visibility>
</MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>AXI_SRAM_1</InterfaceRef>
+ <Offset>524288</Offset>
+ <Range>524288</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>AXI_SRAM_2</InterfaceRef>
+ <Offset>1048576</Offset>
+ <Range>524288</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>AXI_SRAM_3</InterfaceRef>
+ <Offset>1572864</Offset>
+ <Range>524288</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
</MemoryMap>
</MemoryMaps>
<Paths>
@@ -179,7 +254,7 @@
</Source>
<Targets>
<Target>
- <InterfaceRef>AXI_SRAM</InterfaceRef>
+ <InterfaceRef>AXI_SRAM_0</InterfaceRef>
</Target>
<Target>
<InterfaceRef>AXI_TLX_OUT</InterfaceRef>
@@ -187,15 +262,25 @@
<Target>
<InterfaceRef>APB_PVT</InterfaceRef>
</Target>
+ <Target>
+ <InterfaceRef>AXI_SRAM_1</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>AXI_SRAM_2</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>AXI_SRAM_3</InterfaceRef>
+ </Target>
</Targets>
</Path>
</Paths>
<VirtualNetworks/>
</Specification>
<Architecture>
- <NICConfigFile><periph>
- <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
- <validator_version_info major_revision="22" minor_revision="1" />
+ <NICConfigFile><?xml version="1.0" encoding="iso-8859-1" ?>
+<periph>
+ <product_version_info minor_code="50000" minor_version="0" major_group="bu" minor_revision="2" major_revision="1" product_code="nic400" major_version="00" part_quality="rel"/>
+ <validator_version_info minor_revision="1" major_revision="22"/>
<global>
<address0x0 def="true">bottom</address0x0>
<aruser_width>0</aruser_width>
@@ -214,12 +299,12 @@
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
- <sas_visible def="true">false</sas_visible>
+ <sas_visible>true</sas_visible>
<start_iid>0</start_iid>
<taxonomy>masterslave</taxonomy>
<thin_links_status def="true">false</thin_links_status>
<uppercase_ext_sig>true</uppercase_ext_sig>
- <virtual_networks />
+ <virtual_networks/>
<virtual_networks_status>false</virtual_networks_status>
<wuser_width>0</wuser_width>
</global>
@@ -236,18 +321,18 @@
<address_ranges>
<name>mm0</name>
<range>
- <addr_max>0xFFFFF</addr_max>
+ <addr_max>0x7FFFF</addr_max>
<addr_min>0x0</addr_min>
<remap>
<bit>default</bit>
<present>true</present>
<region>0</region>
- <target>AXI_SRAM</target>
+ <target>AXI_SRAM_0</target>
</remap>
</range>
<range>
<addr_max>0x3FFFFFF</addr_max>
- <addr_min>0x100000</addr_min>
+ <addr_min>0x200000</addr_min>
<remap>
<bit>default</bit>
<present>true</present>
@@ -265,6 +350,36 @@
<target>APB_PVT</target>
</remap>
</range>
+ <range>
+ <addr_max>0xFFFFF</addr_max>
+ <addr_min>0x80000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_SRAM_1</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x17FFFF</addr_max>
+ <addr_min>0x100000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_SRAM_2</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x1FFFFF</addr_max>
+ <addr_min>0x180000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_SRAM_3</target>
+ </remap>
+ </range>
</address_ranges>
<apb_config>false</apb_config>
<apb_slave_no def="true">2</apb_slave_no>
@@ -336,102 +451,469 @@
<depth def="true">2</depth>
<impl def="true">absent</impl>
<location>boundary</location>
- <name>b</name>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if_addr_width>32</slave_if_addr_width>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vid_width>12</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>110</x>
+ <y>61</y>
+ <master_if_port_name>AXI_CHIPLET_IN_m</master_if_port_name>
+ <slave_if_port_name>AXI_CHIPLET_IN_s</slave_if_port_name>
+ </asib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>65</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_SRAM_0</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>890</x>
+ <y>310</y>
+ <master_if_port_name>AXI_SRAM_0_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_0_s</slave_if_port_name>
+ </amib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>64</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_TLX_OUT</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>890</x>
+ <y>116</y>
+ <master_if_port_name>AXI_TLX_OUT_m</master_if_port_name>
+ <slave_if_port_name>AXI_TLX_OUT_s</slave_if_port_name>
+ </amib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>63</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_SRAM_1</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
- <name>aw</name>
- <type def="true">full</type>
+ <name>ar</name>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
- <name>ar</name>
- <type def="true">full</type>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type>full</type>
</reg>
<reg>
+ <depth def="true">2</depth>
<impl def="true">absent</impl>
- <location>master_port</location>
+ <location>boundary</location>
<name>r</name>
- <type def="true">full</type>
+ <type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
- <location>master_port</location>
+ <impl>time_closure</impl>
+ <location>slave_port</location>
<name>w</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
+ <depth def="true">2</depth>
<impl def="true">absent</impl>
- <location>master_port</location>
- <name>b</name>
- <type def="true">full</type>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
- <name>r</name>
- <type def="true">full</type>
+ <name>b</name>
+ <type>full</type>
</reg>
<reg>
+ <depth def="true">2</depth>
<impl def="true">absent</impl>
- <location>slave_port</location>
+ <location>boundary</location>
<name>b</name>
- <type def="true">full</type>
+ <type>fifo</type>
</reg>
- <slave_if_addr_width>32</slave_if_addr_width>
<slave_if_data_width>32</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
- <vid_width>12</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>20</y>
- <master_if_port_name>AXI_CHIPLET_IN_m</master_if_port_name>
- <slave_if_port_name>AXI_CHIPLET_IN_s</slave_if_port_name>
- </asib>
+ <x>890</x>
+ <y>214</y>
+ <master_if_port_name>AXI_SRAM_1_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_1_s</slave_if_port_name>
+ </amib>
<amib>
<apb_config>false</apb_config>
- <apb_slave_no>65</apb_slave_no>
+ <apb_slave_no>62</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>false</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
<multi_region>false</multi_region>
- <name>AXI_SRAM</name>
+ <name>AXI_SRAM_2</name>
<protocol>axi4</protocol>
<qv_out>false</qv_out>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>w</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>b</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>r</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>aw</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -441,16 +923,16 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>aw</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>ar</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -460,16 +942,16 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>ar</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>r</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -479,10 +961,10 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>w</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -492,10 +974,10 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>b</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -510,49 +992,50 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>20</y>
- <master_if_port_name>AXI_SRAM_m</master_if_port_name>
- <slave_if_port_name>AXI_SRAM_s</slave_if_port_name>
+ <x>890</x>
+ <y>260</y>
+ <master_if_port_name>AXI_SRAM_2_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_2_s</slave_if_port_name>
</amib>
<amib>
<apb_config>false</apb_config>
- <apb_slave_no>64</apb_slave_no>
+ <apb_slave_no>61</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id>false</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>false</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
<multi_region>false</multi_region>
- <name>AXI_TLX_OUT</name>
+ <name>AXI_SRAM_3</name>
<protocol>axi4</protocol>
<qv_out>false</qv_out>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>w</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>b</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl>present</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>r</name>
- <type>rev</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>aw</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -562,16 +1045,16 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>aw</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>ar</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -581,16 +1064,16 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>master_port</location>
<name>ar</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>r</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -600,10 +1083,10 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>w</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -613,10 +1096,10 @@
<type>fifo</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>time_closure</impl>
<location>slave_port</location>
<name>b</name>
- <type def="true">full</type>
+ <type>full</type>
</reg>
<reg>
<depth def="true">2</depth>
@@ -631,26 +1114,27 @@
<trustzone>nsec</trustzone>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
- <x>0</x>
- <y>40</y>
- <master_if_port_name>AXI_TLX_OUT_m</master_if_port_name>
- <slave_if_port_name>AXI_TLX_OUT_s</slave_if_port_name>
+ <x>890</x>
+ <y>160</y>
+ <master_if_port_name>AXI_SRAM_3_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_3_s</slave_if_port_name>
</amib>
<amib>
<apb_config>false</apb_config>
<apb_port>
- <clock_domain>clk0</clock_domain>
+ <clock_domain>ref</clock_domain>
<name>APB_PVT</name>
<trustzone>nsec</trustzone>
- <x>0</x>
- <y>0</y>
+ <x>902</x>
+ <y>61</y>
</apb_port>
- <apb_slave_no>63</apb_slave_no>
+ <apb_slave_no>60</apb_slave_no>
<clock_boundary>async</clock_boundary>
<clock_domain_name_master_if>ref</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
<compress_id def="true">false</compress_id>
<dest_type>peripheral</dest_type>
+ <expanded>true</expanded>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
@@ -734,47 +1218,65 @@
<trustzone>nsec</trustzone>
<vn_external def="true">none</vn_external>
<vn_external_bridge def="true">none</vn_external_bridge>
- <x>0</x>
- <y>60</y>
+ <x>890</x>
+ <y>61</y>
<master_if_port_name>APB_PVT</master_if_port_name>
<slave_if_port_name>apb_group0_s</slave_if_port_name>
</amib>
<inter>
<clock_domain>clk0</clock_domain>
<data_width>32</data_width>
- <expanded>false</expanded>
- <height>60</height>
+ <expanded>true</expanded>
+ <height>320</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>63</y>
+ <x>547</x>
+ <y>116</y>
</master_if>
<master_if>
<name>axi_m_1</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>83</y>
+ <x>547</x>
+ <y>61</y>
</master_if>
<master_if>
<name>axi_m_2</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>103</y>
+ <x>547</x>
+ <y>162</y>
</master_if>
<master_if>
<name>axi_m_3</name>
<post_arb_reg>absent</post_arb_reg>
- <x>0</x>
- <y>123</y>
+ <x>547</x>
+ <y>208</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_4</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>547</x>
+ <y>254</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_5</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>547</x>
+ <y>300</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_6</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>547</x>
+ <y>346</y>
</master_if>
<name>bm0</name>
<protocol>axi4</protocol>
<slave_if>
<name>axi_s_0</name>
- <x>0</x>
- <y>63</y>
+ <x>454</x>
+ <y>61</y>
</slave_if>
<sparse>
<cds>singleslave</cds>
@@ -892,25 +1394,109 @@
<type def="true">full</type>
</reg>
</master_if_port>
+ <master_if_port>
+ <name>axi_m_4</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_5</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_6</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
</sparse>
<type>busmatrix</type>
- <width>0</width>
+ <width>94</width>
<x>500</x>
- <y>45</y>
- <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3</master_if_port_name>
+ <y>203</y>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3,axi_m_4,axi_m_5,axi_m_6</master_if_port_name>
<slave_if_port_name>axi_s_0</slave_if_port_name>
</inter>
<inter>
<name>ds_1</name>
<slave_if>
<name>axi_s_0</name>
- <x>0</x>
- <y>0</y>
+ <x>563</x>
+ <y>356</y>
</slave_if>
<type>default_slave</type>
- <x>500</x>
- <y>500</y>
- <master_if_port_name />
+ <x>577</x>
+ <y>356</y>
+ <master_if_port_name></master_if_port_name>
<slave_if_port_name>axi_s_0</slave_if_port_name>
</inter>
<connect>
@@ -934,15 +1520,15 @@
<awuser>false</awuser>
<buser>false</buser>
<dest>external</dest>
- <dest_port>AXI_SRAM</dest_port>
+ <dest_port>AXI_SRAM_0</dest_port>
<lock>false</lock>
<out_reads>8</out_reads>
<out_trans>8</out_trans>
<out_writes>8</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
- <src>AXI_SRAM</src>
- <src_port>AXI_SRAM_m</src_port>
+ <src>AXI_SRAM_0</src>
+ <src_port>AXI_SRAM_0_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -961,6 +1547,54 @@
<src_port>AXI_TLX_OUT_m</src_port>
<wuser>false</wuser>
</connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>AXI_SRAM_1</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>AXI_SRAM_1</src>
+ <src_port>AXI_SRAM_1_m</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>AXI_SRAM_2</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>AXI_SRAM_2</src>
+ <src_port>AXI_SRAM_2_m</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>AXI_SRAM_3</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>AXI_SRAM_3</src>
+ <src_port>AXI_SRAM_3_m</src_port>
+ <wuser>false</wuser>
+ </connect>
<connect>
<aruser>false</aruser>
<awuser>false</awuser>
@@ -1011,8 +1645,8 @@
<src_port>axi_m_1</src_port>
</connect>
<connect>
- <dest>AXI_SRAM</dest>
- <dest_port>AXI_SRAM_s</dest_port>
+ <dest>AXI_SRAM_3</dest>
+ <dest_port>AXI_SRAM_3_s</dest_port>
<lock>false</lock>
<out_reads>8</out_reads>
<out_trans>8</out_trans>
@@ -1021,6 +1655,39 @@
<src>bm0</src>
<src_port>axi_m_2</src_port>
</connect>
+ <connect>
+ <dest>AXI_SRAM_1</dest>
+ <dest_port>AXI_SRAM_1_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_3</src_port>
+ </connect>
+ <connect>
+ <dest>AXI_SRAM_2</dest>
+ <dest_port>AXI_SRAM_2_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_4</src_port>
+ </connect>
+ <connect>
+ <dest>AXI_SRAM_0</dest>
+ <dest_port>AXI_SRAM_0_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_5</src_port>
+ </connect>
<connect>
<dest>ds_1</dest>
<dest_port>axi_s_0</dest_port>
@@ -1030,16 +1697,19 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_3</src_port>
+ <src_port>axi_m_6</src_port>
</connect>
<architecture>
<link>
<slave_if>
<name>AXI_CHIPLET_IN</name>
- <master_if>AXI_SRAM</master_if>
- <master_if>AXI_TLX_OUT</master_if>
+ <master_if>AXI_SRAM_1</master_if>
+ <master_if>AXI_SRAM_0</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
+ <master_if>AXI_TLX_OUT</master_if>
+ <master_if>AXI_SRAM_2</master_if>
+ <master_if>AXI_SRAM_3</master_if>
<master_if>apb_group0</master_if>
</slave_if>
</link>
diff --git a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
index 6c1054168258368d0353dad6554bcd6b9539747b..13366f41af4ae4a72c51a82a6a794e8dead3c975 100644
--- a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
+++ b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
@@ -34,10 +34,10 @@
<MASTER_CLOCK>clk_m</MASTER_CLOCK>
<FW_USER_DEFINED_WIDTH>16</FW_USER_DEFINED_WIDTH>
<FW_PACKING_STRATEGY>user_def_bytes</FW_PACKING_STRATEGY>
- <FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
+ <FW_TLX_TIMING_CLOSURE>true</FW_TLX_TIMING_CLOSURE>
<REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
<REV_USER_DEFINED_WIDTH>8</REV_USER_DEFINED_WIDTH>
- <REV_TLX_TIMING_CLOSURE>false</REV_TLX_TIMING_CLOSURE>
+ <REV_TLX_TIMING_CLOSURE>true</REV_TLX_TIMING_CLOSURE>
<AWSlavePortRegister>present</AWSlavePortRegister>
<AWSlavePortRegisterType>rev</AWSlavePortRegisterType>
<AWMasterPortRegister>absent</AWMasterPortRegister>
@@ -87,8 +87,8 @@
<DBoundaryBuffering>absent</DBoundaryBuffering>
<DBoundaryBufferingDepth>2</DBoundaryBufferingDepth>
<DCreditBuffers>6</DCreditBuffers>
- <FwdChannelPLRegisterSlices>0</FwdChannelPLRegisterSlices>
- <RevChannelPLRegisterSlices>0</RevChannelPLRegisterSlices>
+ <FwdChannelPLRegisterSlices>4</FwdChannelPLRegisterSlices>
+ <RevChannelPLRegisterSlices>4</RevChannelPLRegisterSlices>
<POWER_DOMAIN_CROSSING>false</POWER_DOMAIN_CROSSING>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
@@ -239,13 +239,13 @@
<fwd_tlx>
<pl_clock_ratio>1</pl_clock_ratio>
<dll_link_user_def_width>16</dll_link_user_def_width>
- <pl_reg_stages>0</pl_reg_stages>
+ <pl_reg_stages>4</pl_reg_stages>
<dll_link_width_option>user_def_bytes</dll_link_width_option>
</fwd_tlx>
<rev_tlx>
<pl_clock_ratio>1</pl_clock_ratio>
<dll_link_user_def_width>8</dll_link_user_def_width>
- <pl_reg_stages>0</pl_reg_stages>
+ <pl_reg_stages>4</pl_reg_stages>
<dll_link_width_option>widest_div_4</dll_link_width_option>
</rev_tlx>
<tlx_enable>true</tlx_enable>
@@ -287,13 +287,13 @@
</reg>
<reg>
<type>fwd</type>
- <impl>absent</impl>
+ <impl>present</impl>
<name>d</name>
<location>tlx_fwd</location>
</reg>
<reg>
<type>fwd</type>
- <impl>absent</impl>
+ <impl>present</impl>
<name>d</name>
<location>tlx_rev</location>
</reg>
diff --git a/synopsys_28nm_slm_integration b/synopsys_28nm_slm_integration
index e88b3d4335b8416b5d78322f45e099ac9a12a1d0..9ba8cbc74e043ec6571d3ec491ce02de37264e2b 160000
--- a/synopsys_28nm_slm_integration
+++ b/synopsys_28nm_slm_integration
@@ -1 +1 @@
-Subproject commit e88b3d4335b8416b5d78322f45e099ac9a12a1d0
+Subproject commit 9ba8cbc74e043ec6571d3ec491ce02de37264e2b
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
index 3a69115a41290fb292b02c6df5955e351995ff80..6238f03fbceeed09945ba409fb8383bd36482be6 100644
--- a/verif/cocotb/makefile
+++ b/verif/cocotb/makefile
@@ -31,9 +31,10 @@ DUT = sram_chiplet_cocotb
TOPLEVEL = sram_chiplet_cocotb
MODULE = sram_chiplet_tests
-VERILOG_SOURCES += ./sram_chiplet_cocotb.sv
+VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/verif/cocotb/sram_chiplet_cocotb.sv
EXTRA_ARGS += +define+BEHAVIOURAL_SIM
EXTRA_ARGS += +define+INITIALIZE_MEMORY
+# EXTRA_ARGS += +define+ARM_UD_MODEL
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -54,6 +55,8 @@ else ifeq ($(SIM), verilator)
endif
else ifeq ($(SIM), questa)
COMPILE_ARGS += +acc
+else ifeq ($(SIM), vcs)
+ COMPILE_ARGS += -kdb
endif
include $(SOCLABS_SRAM_CHIPLET_DIR)/simulate/sim/cocotb/makefile.flist
include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/verif/cocotb/sram_chiplet_cocotb.sv b/verif/cocotb/sram_chiplet_cocotb.sv
index d21548a8a9592148843082e939060ac068c08c8d..374e0d26d892882c45a3c3bdcbe25b8c0a32453a 100644
--- a/verif/cocotb/sram_chiplet_cocotb.sv
+++ b/verif/cocotb/sram_chiplet_cocotb.sv
@@ -3,8 +3,6 @@
`include "tlx_interfaces.sv"
module sram_chiplet_cocotb(
- input wire clk_in,
- input wire aresetn,
input wire [11:0] cocotb_awid,
input wire [31:0] cocotb_awaddr,
@@ -42,8 +40,34 @@ module sram_chiplet_cocotb(
output wire cocotb_rvalid,
input wire cocotb_rready
);
-parameter N_ADDR_SEL_BITS=6;
-parameter N_CHIPLETS=8;
+
+
+wire clk_in;
+wire aresetn;
+
+reg clock_q;
+reg [32:0] shifter;
+
+initial begin
+ clock_q <= 1'b0;
+ shifter <= 32'd0;
+ #40 clock_q <= 1'b1;
+end
+
+always @(clock_q)
+ #1 clock_q <= !clock_q;
+
+assign clk_in = clock_q;
+
+always @(posedge clock_q) begin
+ if(!(&shifter))
+ shifter <= {shifter[30:0],1'b1};
+end
+
+assign aresetn = shifter[31];
+
+parameter N_ADDR_SEL_BITS=4;
+parameter N_CHIPLETS=2;
wire DL_REV_CLK[N_CHIPLETS+1];
wire DL_FWD_CLK[N_CHIPLETS+1];
@@ -54,7 +78,6 @@ TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev[N_CHIPLETS+1]();
TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd[N_CHIPLETS+1]();
TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd[N_CHIPLETS+1]();
-
wire [11:0] AWID_AXI_CHIPLET_OUT;
wire [31:0] AWADDR_AXI_CHIPLET_OUT;
wire [7:0] AWLEN_AXI_CHIPLET_OUT;
@@ -277,35 +300,57 @@ assign ref_clk[0] = clock_div[1];
wire [N_CHIPLETS:0] PLL_LOCK;
assign DL_FWD_CLK[0] = clk_in;
-
+initial begin
+ $sdf_annotate("/home/dwn1c21/SoC-Labs/TAPEOUT/jan2025/sram_chiplet/imp/ASIC/SRAM_CHIPLET/sram_chiplet_gate.sdf", gen_chiplets[0].u_top_sram_chiplet);
+end
genvar i;
generate
for(i=0; i<N_CHIPLETS;i=i+1) begin: gen_chiplets
- top_sram_chiplet u_top_sram_chiplet(
- .REF_CLK(ref_clk[0]),
-
- .aRESETn(aresetn),
- .DL_FWD_RESETn(aresetn),
- .OUT_CLK(ref_clk[i+1]),
- .PLL_LOCK_o(PLL_LOCK[i]),
- .PLL_LOCK_i(PLL_LOCK[i+1]),
- .IN_FWD_CLK(DL_FWD_CLK[i]),
- .IN_REV_CLK(DL_REV_CLK[i]),
- .OUT_FWD_CLK(DL_FWD_CLK[i+1]),
- .OUT_REV_CLK(DL_REV_CLK[i+1]),
- // Thin Links In
- .TLX_IN_data_rev(TLX_data_rev[i]),
- .TLX_IN_flow_rev(TLX_flow_rev[i]),
- .TLX_IN_flow_fwd(TLX_flow_fwd[i]),
- .TLX_IN_data_fwd(TLX_data_fwd[i]),
- // Thin Links Out
- .TLX_OUT_data_rev(TLX_data_rev[i+1]),
- .TLX_OUT_flow_rev(TLX_flow_rev[i+1]),
- .TLX_OUT_flow_fwd(TLX_flow_fwd[i+1]),
- .TLX_OUT_data_fwd(TLX_data_fwd[i+1]),
+ SRAM_chiplet u_top_sram_chiplet(
+ .PAD_REF_CLK(ref_clk[0]),
+
+ .PAD_aRESETn(aresetn),
+ .PAD_DL_FWD_RESETn(aresetn),
+ .PAD_PLL_LOCK_o(PLL_LOCK[i]),
+ .PAD_PLL_LOCK_i(PLL_LOCK[i+1]),
+ .PAD_IN_FWD_CLK(DL_FWD_CLK[i]),
+ .PAD_IN_REV_CLK(DL_REV_CLK[i]),
+ .PAD_OUT_FWD_CLK(DL_FWD_CLK[i+1]),
+ .PAD_OUT_REV_CLK(DL_REV_CLK[i+1]),
+
+ .PAD_TLX_IN_data_rev_0_tdata (TLX_data_rev[i].tdata),
+ .PAD_TLX_IN_data_rev_0_tvalid (TLX_data_rev[i].tvalid),
+ .PAD_TLX_IN_data_rev_0_tready (TLX_data_rev[i].tready),
+
+ .PAD_TLX_IN_flow_rev_0_tdata (TLX_flow_rev[i].tdata),
+ .PAD_TLX_IN_flow_rev_0_tvalid (TLX_flow_rev[i].tvalid),
+ .PAD_TLX_IN_flow_rev_0_tready (TLX_flow_rev[i].tready),
+
+ .PAD_TLX_IN_flow_fwd_0_tdata (TLX_flow_fwd[i].tdata),
+ .PAD_TLX_IN_flow_fwd_0_tvalid (TLX_flow_fwd[i].tvalid),
+ .PAD_TLX_IN_flow_fwd_0_tready (TLX_flow_fwd[i].tready),
+
+ .PAD_TLX_IN_data_fwd_0_tdata (TLX_data_fwd[i].tdata),
+ .PAD_TLX_IN_data_fwd_0_tvalid (TLX_data_fwd[i].tvalid),
+ .PAD_TLX_IN_data_fwd_0_tready (TLX_data_fwd[i].tready),
+
+ .PAD_TLX_data_rev_1_tdata (TLX_data_rev[i+1].tdata),
+ .PAD_TLX_data_rev_1_tvalid (TLX_data_rev[i+1].tvalid),
+ .PAD_TLX_data_rev_1_tready (TLX_data_rev[i+1].tready),
+
+ .PAD_TLX_flow_rev_1_tdata (TLX_flow_rev[i+1].tdata),
+ .PAD_TLX_flow_rev_1_tvalid (TLX_flow_rev[i+1].tvalid),
+ .PAD_TLX_flow_rev_1_tready (TLX_flow_rev[i+1].tready),
+
+ .PAD_TLX_flow_fwd_1_tdata (TLX_flow_fwd[i+1].tdata),
+ .PAD_TLX_flow_fwd_1_tvalid (TLX_flow_fwd[i+1].tvalid),
+ .PAD_TLX_flow_fwd_1_tready (TLX_flow_fwd[i+1].tready),
+ .PAD_TLX_data_fwd_1_tdata (TLX_data_fwd[i+1].tdata),
+ .PAD_TLX_data_fwd_1_tvalid (TLX_data_fwd[i+1].tvalid),
+ .PAD_TLX_data_fwd_1_tready (TLX_data_fwd[i+1].tready),
// Address select
- .addr_sel(i[N_ADDR_SEL_BITS-1:0])
+ .PAD_addr_sel(i[N_ADDR_SEL_BITS-1:0])
);
end
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
index e58ea83b3ed21edb035cbf139aed2695a9339a46..621fd0fc85d85dd0261248566d01c1f2476610ea 100644
--- a/verif/cocotb/sram_chiplet_tests.py
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -33,7 +33,7 @@ CHIPLET_0_PD_BASE = CHIPLET_0_APB_BASE + 6*0x1000
CHIPLET_0_VM_BASE = CHIPLET_0_APB_BASE + 7*0x1000
CHIPLET_0_PLL_BASE = CHIPLET_0_APB_BASE + 8*0x1000
-CHIPLET_0_SRAM_MAX_ADDR = 0x100000
+CHIPLET_0_SRAM_MAX_ADDR = 0x200000
class TB:
def __init__(self,dut):
@@ -42,7 +42,6 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
- cocotb.start_soon(Clock(dut.clk_in, 1, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut,"cocotb"), dut.clk_in, dut.aresetn, reset_active_level=False)
def set_idle_generator(self, generator=None):
if generator:
@@ -59,10 +58,7 @@ class TB:
self.axi_ram.write_if.w_channel.set_pause_generator(generator())
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
async def cycle_reset(self):
- self.dut.aresetn.setimmediatevalue(0)
- await Timer(time=4,units='us')
- self.dut.aresetn.value = 1
- await RisingEdge(self.dut.clk_in)
+ await RisingEdge(self.dut.aresetn)
async def delay(self, cycle):
for i in range(cycle):
await RisingEdge(self.dut.clk_in)
@@ -99,7 +95,34 @@ async def wait_for_PLL(dut, tb):
await RisingEdge(dut.PLL_LOCK[0])
await ClockCycles(dut.clk_in,20)
-
+async def PLL_enable(dut, tb):
+ tb.log.info("Set pwron and gear shift reg")
+ tmp = 1<<8
+ tmp += 1<<7
+ await tb.axi_master.write(CHIPLET_0_PLL_BASE, tmp.to_bytes(4,'little'))
+
+ tb.log.info("Wait before releasing reset...")
+ await ClockCycles(dut.clk_in, 4000)
+ tb.log.info("...release reset")
+ tmp += 1<<9
+ await tb.axi_master.write(CHIPLET_0_PLL_BASE, tmp.to_bytes(4,'little'))
+
+ tb.log.info("Wait to enable PLL")
+ await ClockCycles(dut.clk_in,4000)
+ tb.log.info("... enabling PLL")
+ tmp += 1<<4
+ tmp += 1<<5
+ await tb.axi_master.write(CHIPLET_0_PLL_BASE, tmp.to_bytes(4,'little'))
+
+ tb.log.info("Wait for PLL lock...")
+ PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
+
+ tb.log.info(PLL_LOCK.data)
+ while (PLL_LOCK.data == b'\x00'):
+ await Timer(time=100, units='ns')
+ PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
+
+
@cocotb.test()
async def PLL_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
@@ -107,27 +130,13 @@ async def PLL_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=None
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
-
- #await wait_for_PLL(dut,tb)
-
+
# Test ID of PLL Intergration layer
PLL_ID = await tb.axi_master.read(CHIPLET_0_PLL_BASE+20,4)
assert PLL_ID.data == b'LPNS'
- # Wait for PLL Lock
- PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
- tb.log.info(PLL_LOCK.data)
- while (PLL_LOCK.data == b'\x00'):
- await Timer(time=100, units='ns')
- PLL_LOCK = await tb.axi_master.read(CHIPLET_0_PLL_BASE+24,1)
- # Read write to register
- PLL_0 = await tb.axi_master.read(CHIPLET_0_PLL_BASE,4)
- tb.log.info(PLL_0.data)
- await tb.axi_master.write(CHIPLET_0_PLL_BASE, bytearray(b'\x31\x00\x00\x00'), 4)
- # Read write to PLL internal register
- PLL_800 = await tb.axi_master.read(CHIPLET_0_PLL_BASE + 0x800, 4)
- await tb.axi_master.write(CHIPLET_0_PLL_BASE + 0x800, bytearray(b'\x31\x00\x00\x00'), 4)
-
+ await PLL_enable(dut, tb)
+
@cocotb.test()
async def PD_TEST(dut,idle_insterter=None, backpressure_inserter=None, size=None):