diff --git a/.gitignore b/.gitignore
index e1b8ebdacefc51840d3ffa6c6cb2674f489d29d5..b6ee89a70b13ba9a36fd64173f0ca323313e24f6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -18,3 +18,5 @@ verif/cocotb/results.xml
verif/cocotb/*.ini
imp
+
+memories
diff --git a/.gitmodules b/.gitmodules
index 9ec29b831304e0fb42024294b07c1b9fdc353bcf..b6b5886360eaeb55af1291f235c0fa1bb193532c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
[submodule "socdebug_tech"]
path = socdebug_tech
url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
+[submodule "soctools_flow"]
+ path = soctools_flow
+ url = https://git.soton.ac.uk/soclabs/soctools_flow.git
diff --git a/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec b/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
new file mode 100644
index 0000000000000000000000000000000000000000..92253f8ea4dd860e2077acb0a1ec79dfaf57922c
--- /dev/null
+++ b/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
@@ -0,0 +1,47 @@
+# user spec file, compiler sram_sp_hde_2_svt_mvt, version r0p0
+
+EOL_guardband = 0
+activity_factor = 10
+atf = off
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+compiler_type = sp
+corners = ffg_cbestt_0p99v_0p99v_0c,ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ffg_ctypical_0p90v_0p90v_85c,ffg_ctypical_0p99v_0p99v_125c,ssg_cworstt_0p81v_0p81v_0c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,tt_ctypical_0p81v_0p81v_0c,tt_ctypical_0p90v_0p90v_125c,tt_ctypical_0p90v_0p90v_25c,tt_ctypical_0p90v_0p90v_85c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+fci_type = not_fci
+flexible_banking = 8
+frequency = 500
+instname = sram_32b_32k
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = sram_sp_hde
+lren_bankmask = off
+metal_stack =
+mux = 16
+mvt = LL
+name_case = upper
+pipeline = off
+power_gating = off
+power_type = otc
+prefix =
+pwr_gnd_rename = vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+rcols = 2
+redundancy = off
+retention = on
+right_bus_delim = ]
+rows_p_bl = 256
+rrows = 0
+scan = off
+ser = none
+site_def = off
+wa = off
+words = 32768
+wp_size = 1
+write_mask = on
+write_thru = off
diff --git a/flist/IP/NIC400.flist b/flist/IP/NIC400.flist
new file mode 100644
index 0000000000000000000000000000000000000000..fa0c1bcedca8caf3ae21281de47c3db78377036c
--- /dev/null
+++ b/flist/IP/NIC400.flist
@@ -0,0 +1,68 @@
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi4PC
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/ApbPC
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Apb4PC
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Ahb
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/AhbPC
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog/nic400_amib_AXI_TLX_OUT_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_TLX_OUT/verilog/nic400_amib_AXI_TLX_OUT_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_axi_to_itb_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.verilog
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_chan_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_decode_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_maskcntl_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_rd_ss_cdas_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_wr_ss_cdas_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_build_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_map_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml3_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog/nic400_default_slave_ds_1_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ax4_reg_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_buf_reg_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rd_reg_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_reg_slice_axi_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_wr_reg_slice_sram_chiplet.v
\ No newline at end of file
diff --git a/flist/IP/SIE300.flist b/flist/IP/SIE300.flist
new file mode 100644
index 0000000000000000000000000000000000000000..1ae456533b502ae6b408da15d1ff111adf19efe3
--- /dev/null
+++ b/flist/IP/SIE300.flist
@@ -0,0 +1,24 @@
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_addr_dec.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arb.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_awq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_axi_mux.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_bq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_clamp.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_eam.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo_core.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_lpi_ctrl.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_one_hot.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rbeat.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_resp_gen.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rq.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wbeat.sv
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wq.sv
\ No newline at end of file
diff --git a/flist/IP/TLX400.flist b/flist/IP/TLX400.flist
new file mode 100644
index 0000000000000000000000000000000000000000..a234d143a21ed82e8dd58caf704f9e2fd67228f1
--- /dev/null
+++ b/flist/IP/TLX400.flist
@@ -0,0 +1,78 @@
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi4PC
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_chan_slice_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_nosync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_and2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_gry_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_gry_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_random_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_m_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_s_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_fwd_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_rev_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_cdc_air_corrupt_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_chan_slice_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_fwd_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_rev_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_fwd_clk_buf_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_master_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_fwd_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_rev_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_rev_clk_buf_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_slave_domain_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux2_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_rd_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_sync_tlx_sram_chiplet.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_wr_tlx_sram_chiplet.v
\ No newline at end of file
diff --git a/flist/Top/sram_chiplet.flist b/flist/Top/sram_chiplet.flist
new file mode 100644
index 0000000000000000000000000000000000000000..e8c465425056c80813d17bf5b5fd5f1dfcfafe4b
--- /dev/null
+++ b/flist/Top/sram_chiplet.flist
@@ -0,0 +1,40 @@
+//-----------------------------------------------------------------------------
+// SRAM Chiplet IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/interfaces
+
+// SRAM Chiplet top level
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
+
+// SRAM Chiplet - SRAM
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM_wrapper.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/glib/verilog/SRAM.v
+
+// SRAM Chiplet - APB subsystem
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+
+// Testbench IP
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_vip.flist
+
+// Thin links
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/TLX400.flist
+
+// SRAM Chiplet - NIC400
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/NIC400.flist
+
+// SIE300 SRAM controller
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300.flist
\ No newline at end of file
diff --git a/flist/Top/sram_chiplet_TSMC28nm.flist b/flist/Top/sram_chiplet_TSMC28nm.flist
new file mode 100644
index 0000000000000000000000000000000000000000..8b11a2ad5a602dc752f7016ab9874f13e402549a
--- /dev/null
+++ b/flist/Top/sram_chiplet_TSMC28nm.flist
@@ -0,0 +1,39 @@
+//-----------------------------------------------------------------------------
+// SRAM Chiplet IP Filelist for TSMC 28nm HPC+
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// SRAM Chiplet top level
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
+
+// SRAM Chiplet - SRAM
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/memories/sram_32b_32k_emulation.v
+
+// SRAM Chiplet - APB subsystem
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
+
+// Testbench IP
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_vip.flist
+
+// Thin links
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/TLX400.flist
+
+// SRAM Chiplet - NIC400
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/NIC400.flist
+
+// SIE300 SRAM controller
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/IP/SIE300.flist
\ No newline at end of file
diff --git a/flist/Top/sram_chiplet_vip.flist b/flist/Top/sram_chiplet_vip.flist
new file mode 100644
index 0000000000000000000000000000000000000000..a5803ccf2db1984488614540b21d33e3261ef6b8
--- /dev/null
+++ b/flist/Top/sram_chiplet_vip.flist
@@ -0,0 +1,5 @@
+
+
+-f $(SOCLABS_SRAM_CHIPLET_DIR)/flist/VIP/NIC400_tb.flist
+
+
diff --git a/flist/VIP/NIC400_tb.flist b/flist/VIP/NIC400_tb.flist
new file mode 100644
index 0000000000000000000000000000000000000000..a4e50bd69ceb1445e9a27d26ccef238872ed88bd
--- /dev/null
+++ b/flist/VIP/NIC400_tb.flist
@@ -0,0 +1,45 @@
+
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi
++incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi4PC
+
+
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/nic400_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_chan_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_chan_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_decode_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_maskcntl_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_rd_ss_cdas_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_wr_ss_cdas_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_build_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_map_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog/nic400_default_slave_ds_1_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ax4_reg_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_buf_reg_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ful_regd_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_fwd_regd_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rd_reg_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_reg_slice_axi_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rev_regd_slice_tb.v
+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_wr_reg_slice_tb.v
\ No newline at end of file
diff --git a/flist/sram_chiplet_cocotb.flist b/flist/sram_chiplet_cocotb.flist
deleted file mode 100644
index 1408d4dcff2e4c31a77c114be13f4a2fecabfda9..0000000000000000000000000000000000000000
--- a/flist/sram_chiplet_cocotb.flist
+++ /dev/null
@@ -1,231 +0,0 @@
-
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/verilog/SRAM_wrapper.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SRAM/verilog/SRAM.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/sram_chiplet_apb_subsystem/verilog/sram_chiplet_apb_subsystem.v
-
-#NIC400 nic400_tb
-
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/Axi4PC
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/nic400/verilog/nic400_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_chan_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/amib_AXI_CHIPLET_OUT/verilog/nic400_amib_AXI_CHIPLET_OUT_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_chan_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_decode_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_maskcntl_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_rd_ss_cdas_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/asib_AXI_COCOTB/verilog/nic400_asib_AXI_COCOTB_wr_ss_cdas_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_build_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_map_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/default_slave_ds_1/verilog/nic400_default_slave_ds_1_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ax4_reg_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_buf_reg_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_ful_regd_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_fwd_regd_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rd_reg_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_reg_slice_axi_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_rev_regd_slice_tb.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tb/logical/nic400_tb/reg_slice/verilog/nic400_wr_reg_slice_tb.v
-#TLX Files
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/Axi4PC
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_chan_slice_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/amib_M1_m/verilog/nic400_amib_M1_m_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_nosync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_capt_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_and2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_comb_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_corrupt_gry_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_launch_gry_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/cdc_blocks/verilog/nic400_cdc_random_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_m_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_clk_s_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_fwd_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_dl_rev_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/nic400/verilog/nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_mux_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_fifo_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_ar_flow_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_mux_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_fifo_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_aw_flow_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_mux_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_fifo_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_b_flow_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_cdc_air_corrupt_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_chan_slice_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_fwd_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_dl_rev_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_fwd_clk_buf_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_master_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_fwd_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_pl_rev_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_mux_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_fifo_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_r_flow_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_rev_clk_buf_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_slave_domain_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux2_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_mux_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_fifo_wr_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_rd_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_sync_tlx_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_tlx_sram_chiplet/logical/nic400_tlx_sram_chiplet/tlx_M1_m_tlx/verilog/nic400_tlx_M1_m_tlx_w_flow_wr_tlx_sram_chiplet.v
-
-#NIC400 SRAM Chiplet
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Axi4PC
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/ApbPC
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Apb4PC
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/Ahb
-EXTRA_ARGS += +incdir+$(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/AhbPC
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/nic400/verilog/nic400_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_chan_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_AXI_SRAM/verilog/nic400_amib_AXI_SRAM_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_axi_to_itb_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/amib_apb_group0/verilog/nic400_amib_apb_group0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_ahb_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_chan_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_decode_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_itb_to_axi_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_maskcntl_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_rd_ss_cdas_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AHB_ADP/verilog/nic400_asib_AHB_ADP_wr_ss_cdas_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_chan_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_decode_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_maskcntl_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_rd_ss_cdas_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/asib_AXI_CHIPLET_IN/verilog/nic400_asib_AXI_CHIPLET_IN_wr_ss_cdas_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_arb_ml2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_lrg_arb_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_build_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_map_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_qv_cmp_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_st_tt_s1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_rd_wr_arb_1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/default_slave_ds_1/verilog/nic400_default_slave_ds_1_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ax4_reg_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_buf_reg_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_ful_regd_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_fwd_regd_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rd_reg_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_reg_slice_axi_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_rev_regd_slice_sram_chiplet.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/nic400_sram_chiplet/logical/nic400_sram_chiplet/reg_slice/verilog/nic400_wr_reg_slice_sram_chiplet.v
-
-# sie300
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_addr_dec.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arb.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_arq.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_awq.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_axi_mux.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_bq.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_clamp.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_eam.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_fifo_core.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_lpi_ctrl.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_one_hot.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rbeat.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_resp_gen.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_rq.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wbeat.sv
-VERILOG_SOURCES += $(SOCLABS_SRAM_CHIPLET_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_sram_chiplet/verilog/sie300_axi5_sram_ctrl_sram_chiplet_wq.sv
diff --git a/flows/makefile.asic b/flows/makefile.asic
new file mode 100644
index 0000000000000000000000000000000000000000..bea50adc78718f8b853aaf0bbd0aa92987abd873
--- /dev/null
+++ b/flows/makefile.asic
@@ -0,0 +1,29 @@
+
+
+
+# Location to build ASIC files
+IMP_SRAM_CHIPLET_ASIC_DIR := $(SOCLABS_SRAM_CHIPLET_DIR)/imp/ASIC/SRAM_CHIPLET
+
+# Name of generated filelist by python script
+TCL_ASIC_FLIST_DIR := $(IMP_SRAM_CHIPLET_ASIC_DIR)/flist
+TCL_ASIC_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/gen_flist.tcl
+SYNOPSYS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/synopsys_flist.tcl
+
+# Location of Macros
+MEMORIES_DIR := $(SOCLABS_SRAM_CHIPLET_DIR)/memories
+SRAM_SPEC_FILE := $(SOCLABS_SRAM_CHIPLET_DIR)/ASIC/TSMC28nm_HPCP/sram_32b_32k.spec
+
+flist_synopsys:
+ @mkdir -p $(TCL_ASIC_FLIST_DIR)
+ @(cd $(TCL_ASIC_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(SYNOPSYS_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_SRAM_CHIPLET_ASIC_DIR)/src;)
+
+gen_memories:
+ @mkdir -p $(MEMORIES_DIR)
+ echo "Generating SRAM Memory"
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt ascii -spec $(SRAM_SPEC_FILE)
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt emulation -spec $(SRAM_SPEC_FILE)
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt verilog -spec $(SRAM_SPEC_FILE)
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt liberty -spec $(SRAM_SPEC_FILE)
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_SPEC_FILE)
+ cd $(MEMORIES_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_SPEC_FILE)
diff --git a/flows/makefile.simulate b/flows/makefile.simulate
new file mode 100644
index 0000000000000000000000000000000000000000..de944165303a3e3c867160d75ec8a413c3c9c06d
--- /dev/null
+++ b/flows/makefile.simulate
@@ -0,0 +1,55 @@
+#-----------------------------------------------------------------------------
+# SRAM Chiplet Simulation Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# ------- Cocotb Variables -----------
+# Convert Simulator Name for Cocotb
+COCOTB_SIMULATOR ?= questa
+
+ifeq ($(SIMULATOR),mti)
+ COCOTB_SIMULATOR := questa
+else ifeq ($(SIMULATOR),xm)
+ COCOTB_SIMULATOR := xcelium
+else ifeq ($(SIMULATOR),vcs)
+ COCOTB_SIMULATOR := vcs
+endif
+
+# Cocotb GUI Variable
+GUI ?= 0
+
+# Cocotb Test Location
+COCOTB_TEST_DIR := $(SOCLABS_SRAM_CHIPLET_DIR)/verif/cocotb
+
+TESTCASE ?= SRAM_TEST
+
+# Cocotb Scratch Directory
+COCOTB_DIR := $(SIM_TOP_DIR)/cocotb
+COCOTB_SCRATCH_DIR := $(COCOTB_DIR)/scratch
+
+# Filelist for Cocotb
+MAKEFILE_FILELIST := $(COCOTB_DIR)/makefile.flist
+
+
+# Generate Make filelist from flists
+flist_makefile_nanosoc:
+ @mkdir -p $(COCOTB_DIR)
+ @(cd $(COCOTB_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -m -f $(DESIGN_VC) -o $(MAKEFILE_FILELIST);)
+
+run_cocotb: flist_makefile_nanosoc
+ @mkdir -p $(SIM_DIR)
+ @cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_SRAM_CHIPLET_DIR)/verif/cocotb clean SIM_BUILD=$(COCOTB_SCRATCH_DIR)
+ @cd $(SIM_DIR); $(MAKE) -C $(SOCLABS_SRAM_CHIPLET_DIR)/verif/cocotb sim SIM=$(COCOTB_SIMULATOR) GUI=$(GUI) SIM_BUILD=$(COCOTB_SCRATCH_DIR) TESTCASE=$(TESTCASE)
+
+sim_cocotb: GUI=1
+sim_cocotb: run_cocotb
+
+
diff --git a/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
new file mode 100644
index 0000000000000000000000000000000000000000..08ab779280c5e32ad127dc797ac0500ecee3f1f9
--- /dev/null
+++ b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM.v
@@ -0,0 +1,134 @@
+
+
+module SRAM (
+ input wire clk,
+ input wire [20:0] memaddr,
+ input wire [31:0] memd,
+ output reg [31:0] memq,
+ input wire memcen,
+ input wire [3:0] memwen
+);
+
+localparam N_MEMS = 8;
+
+reg [N_MEMS-1:0] CEN_i; //Active low chip select
+wire [31:0] wena_i;
+wire gwen_i;
+wire [31:0] q_i[0:N_MEMS-1];
+
+assign wena_i = {{8{memwen[3]}}, {8{memwen[2]}}, {8{memwen[1]}}, {8{memwen[0]}}};
+assign gwen_i = &memwen;
+genvar i;
+
+generate for(i=0; i<N_MEMS; i = i + 1) begin: g_srams
+ sram_32b_32k u_sram_32b_32k(
+ .Q(q_i[i]),
+ .CLK(clk),
+ .CEN(CEN_i[i]),
+ .GWEN(gwen_i),
+ .A(memaddr[14:0]),
+ .D(memd),
+ .WEN(wena_i),
+ .STOV(1'b0),
+ .EMA(3'b011),
+ .EMAW(2'b01),
+ .EMAS(1'b0),
+ .RET1N(1'b1)
+ );
+
+end endgenerate
+
+always @(*) begin
+ case(memaddr[20:15])
+ 6'h00 : begin
+ CEN_i[0]=memcen;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[0];
+ end
+ 6'h01 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=memcen;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[1];
+ end
+ 6'h02 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=memcen;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[2];
+ end
+ 6'h03 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=memcen;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[3];
+ end
+ 6'h04 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=memcen;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[4];
+ end
+ 6'h05 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=memcen;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=1'b1;
+ memq = q_i[5];
+ end
+ 6'h06 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=memcen;
+ CEN_i[7]=1'b1;
+ memq = q_i[6];
+ end
+ 6'h07 : begin
+ CEN_i[0]=1'b1;
+ CEN_i[1]=1'b1;
+ CEN_i[2]=1'b1;
+ CEN_i[3]=1'b1;
+ CEN_i[4]=1'b1;
+ CEN_i[5]=1'b1;
+ CEN_i[6]=1'b1;
+ CEN_i[7]=memcen;
+ memq = q_i[7];
+ end
+ endcase
+end
+
+endmodule
diff --git a/logical/SRAM/verilog/SRAM_wrapper.v b/logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
similarity index 100%
rename from logical/SRAM/verilog/SRAM_wrapper.v
rename to logical/SRAM/TSMC28nm_hpcp/verilog/SRAM_wrapper.v
diff --git a/logical/SRAM/verilog/SRAM.v b/logical/SRAM/glib/verilog/SRAM.v
similarity index 98%
rename from logical/SRAM/verilog/SRAM.v
rename to logical/SRAM/glib/verilog/SRAM.v
index 968446099cb43bd0298ed6da653e21725b004723..42fd655e4e5bb816d4d433c5ce55446f22a4de78 100644
--- a/logical/SRAM/verilog/SRAM.v
+++ b/logical/SRAM/glib/verilog/SRAM.v
@@ -8,7 +8,7 @@ module SRAM (
input wire memcen,
input wire [3:0] memwen
);
- parameter MEM_DEPTH = (1<<17);
+ parameter MEM_DEPTH = 253952;
wire WriteEnable; // Write data update
wire [17:0] Addr;
diff --git a/logical/SRAM/glib/verilog/SRAM_wrapper.v b/logical/SRAM/glib/verilog/SRAM_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..b5bc42582cc1defbcbd3acc26ee01ef0a3245c59
--- /dev/null
+++ b/logical/SRAM/glib/verilog/SRAM_wrapper.v
@@ -0,0 +1,153 @@
+//-----------------------------------------------------------------------------
+// Expansion Subsystem SRAM Wrapper
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+// sie300_axi5_sram_ctrl_expansion_subsystem
+// SRAM
+
+module SRAM_wrapper(
+ input wire ACLK,
+ input wire ARESETn,
+
+ input wire AWVALID,
+ output wire AWREADY,
+ input wire [3:0] AWID,
+ input wire [31:0] AWADDR,
+ input wire [7:0] AWLEN,
+ input wire [2:0] AWSIZE,
+ input wire [1:0] AWBURST,
+ input wire AWLOCK,
+ input wire [2:0] AWPROT,
+ input wire [3:0] AWQOS,
+
+ input wire WVALID,
+ output wire WREADY,
+ input wire [31:0] WDATA,
+ input wire [3:0] WSTRB,
+ input wire WLAST,
+ input wire WPOISON,
+
+ output wire BVALID,
+ input wire BREADY,
+ output wire [3:0] BID,
+ output wire [1:0] BRESP,
+
+ input wire ARVALID,
+ output wire ARREADY,
+ input wire [3:0] ARID,
+ input wire [31:0] ARADDR,
+ input wire [7:0] ARLEN,
+ input wire [2:0] ARSIZE,
+ input wire [1:0] ARBURST,
+ input wire ARLOCK,
+ input wire [2:0] ARPROT,
+ input wire [3:0] ARQOS,
+
+ output wire RVALID,
+ input wire RREADY,
+ output wire [3:0] RID,
+ output wire [31:0] RDATA,
+ output wire [1:0] RRESP,
+ output wire RLAST,
+ output wire RPOISON,
+ input wire AWAKEUP,
+
+ input wire clk_qreqn,
+ output wire clk_qacceptn,
+ output wire clk_qdeny,
+ output wire clk_qactive,
+
+ input wire pwr_qreqn,
+ output wire pwr_qacceptn,
+ output wire pwr_qdeny,
+ output wire pwr_qactive,
+
+ input wire ext_gt_qreqn,
+ output wire ext_gt_qacceptn,
+ input wire cfg_gate_resp
+
+);
+
+
+wire [20:0] memaddr;
+wire [31:0] memd;
+wire [31:0] memq;
+wire memcen;
+wire [3:0] memwen;
+
+sie300_axi5_sram_ctrl_sram_chiplet u_SMC(
+ .aclk(ACLK),
+ .aresetn(ARESETn),
+ .awvalid_s(AWVALID),
+ .awready_s(AWREADY),
+ .awid_s(AWID),
+ .awaddr_s(AWADDR[20:0]),
+ .awlen_s(AWLEN),
+ .awsize_s(AWSIZE),
+ .awburst_s(AWBURST),
+ .awlock_s(AWLOCK),
+ .awprot_s(AWPROT),
+ .awqos_s(AWQOS),
+ .wvalid_s(WVALID),
+ .wready_s(WREADY),
+ .wdata_s(WDATA),
+ .wstrb_s(WSTRB),
+ .wlast_s(WLAST),
+ .wpoison_s(WPOISON),
+ .bvalid_s(BVALID),
+ .bready_s(BREADY),
+ .bid_s(BID),
+ .bresp_s(BRESP),
+ .arvalid_s(ARVALID),
+ .arready_s(ARREADY),
+ .arid_s(ARID),
+ .araddr_s(ARADDR[20:0]),
+ .arlen_s(ARLEN),
+ .arsize_s(ARSIZE),
+ .arburst_s(ARBURST),
+ .arlock_s(ARLOCK),
+ .arprot_s(ARPROT),
+ .arqos_s(ARQOS),
+ .rvalid_s(RVALID),
+ .rready_s(RREADY),
+ .rid_s(RID),
+ .rdata_s(RDATA),
+ .rresp_s(RRESP),
+ .rlast_s(RLAST),
+ .rpoison_s(RPOISON),
+ .awakeup_s(AWAKEUP),
+ .clk_qreqn(clk_qreqn),
+ .clk_qacceptn(clk_qacceptn),
+ .clk_qdeny(clk_qdeny),
+ .clk_qactive(clk_qactive),
+ .pwr_qreqn(pwr_qreqn),
+ .pwr_qacceptn(pwr_qacceptn),
+ .pwr_qdeny(pwr_qdeny),
+ .pwr_qactive(pwr_qactive),
+ .ext_gt_qreqn(ext_gt_qreqn),
+ .ext_gt_qacceptn(ext_gt_qacceptn),
+ .cfg_gate_resp(cfg_gate_resp),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+SRAM u_SRAM(
+ .clk(ACLK),
+ .memaddr(memaddr),
+ .memd(memd),
+ .memq(memq),
+ .memcen(memcen),
+ .memwen(memwen)
+);
+
+endmodule
\ No newline at end of file
diff --git a/logical/interfaces/tlx_interfaces.sv b/logical/interfaces/tlx_interfaces.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3efe5fe441c78c8a1119858c635437714df0344b
--- /dev/null
+++ b/logical/interfaces/tlx_interfaces.sv
@@ -0,0 +1,8 @@
+interface TLX_AXI_stream #(parameter DATA_WIDTH = 16);
+ logic [DATA_WIDTH-1:0] tdata;
+ logic tvalid;
+ logic tready;
+ modport in(input tdata, input tvalid, output tready);
+ modport out(output tdata, output tvalid, input tready);
+endinterface
+
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.v b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
similarity index 53%
rename from logical/top_sram_chiplet/verilog/top_sram_chiplet.v
rename to logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
index fdc45e0334c77c548d6c3fa7cc95b09ddd74943b..9c80679566790455b7e92579b6bd35c8a3f4c53c 100644
--- a/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
+++ b/logical/top_sram_chiplet/verilog/top_sram_chiplet.sv
@@ -15,40 +15,39 @@
// sram_chiplet_apb_subsystem
// SRAM_wrapper
+`include "tlx_interfaces.sv"
module top_sram_chiplet(
// Clock and reset
input wire SYS_CLK,
input wire DL_FWD_CLK,
output wire DL_REV_CLK,
-
input wire aRESETn,
input wire DL_FWD_RESETn,
- // Thin links interface
- output wire tvalid_pl_rev_m1_m_tlx_m_stream,
- input wire tready_pl_rev_m1_m_tlx_m_stream,
- output wire [15:0] tdata_pl_rev_m1_m_tlx_m_stream,
-
- output wire tvalid_pl_rev_m1_m_tlx_m_flow,
- input wire tready_pl_rev_m1_m_tlx_m_flow,
- output wire [2:0] tdata_pl_rev_m1_m_tlx_m_flow,
-
- input wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
- output wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
- input wire [1:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow,
+ // Thin links interface Input
+ TLX_AXI_stream.out TLX_IN_data_rev,
+ TLX_AXI_stream.out TLX_IN_flow_rev,
+ TLX_AXI_stream.in TLX_IN_flow_fwd,
+ TLX_AXI_stream.in TLX_IN_data_fwd,
+
+ // Thin links interface output
+ TLX_AXI_stream.in TLX_OUT_data_rev,
+ TLX_AXI_stream.in TLX_OUT_flow_rev,
+ TLX_AXI_stream.out TLX_OUT_flow_fwd,
+ TLX_AXI_stream.out TLX_OUT_data_fwd,
+
+ // FT1248
- input wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data,
- output wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_data,
- input wire [15:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data
- // FT1248
+ // Address Select pins
+ input wire [2:0] addr_sel
);
// Main Bus Wires
// - SRAM AXI wires
-wire [4:0] AWID_AXI_SRAM;
+wire [3:0] AWID_AXI_SRAM;
wire [31:0] AWADDR_AXI_SRAM;
wire [7:0] AWLEN_AXI_SRAM;
wire [2:0] AWSIZE_AXI_SRAM;
@@ -63,11 +62,11 @@ wire [3:0] WSTRB_AXI_SRAM;
wire WLAST_AXI_SRAM;
wire WVALID_AXI_SRAM;
wire WREADY_AXI_SRAM;
-wire [4:0] BID_AXI_SRAM;
+wire [3:0] BID_AXI_SRAM;
wire [1:0] BRESP_AXI_SRAM;
wire BVALID_AXI_SRAM;
wire BREADY_AXI_SRAM;
-wire [4:0] ARID_AXI_SRAM;
+wire [3:0] ARID_AXI_SRAM;
wire [31:0] ARADDR_AXI_SRAM;
wire [7:0] ARLEN_AXI_SRAM;
wire [2:0] ARSIZE_AXI_SRAM;
@@ -77,12 +76,48 @@ wire [3:0] ARCACHE_AXI_SRAM;
wire [2:0] ARPROT_AXI_SRAM;
wire ARVALID_AXI_SRAM;
wire ARREADY_AXI_SRAM;
-wire [4:0] RID_AXI_SRAM;
+wire [3:0] RID_AXI_SRAM;
wire [31:0] RDATA_AXI_SRAM;
wire [1:0] RRESP_AXI_SRAM;
wire RLAST_AXI_SRAM;
wire RVALID_AXI_SRAM;
wire RREADY_AXI_SRAM;
+// - Thin links out wires
+wire [3:0] AWID_AXI_TLX_OUT;
+wire [31:0] AWADDR_AXI_TLX_OUT;
+wire [7:0] AWLEN_AXI_TLX_OUT;
+wire [2:0] AWSIZE_AXI_TLX_OUT;
+wire [1:0] AWBURST_AXI_TLX_OUT;
+wire AWLOCK_AXI_TLX_OUT;
+wire [3:0] AWCACHE_AXI_TLX_OUT;
+wire [2:0] AWPROT_AXI_TLX_OUT;
+wire AWVALID_AXI_TLX_OUT;
+wire AWREADY_AXI_TLX_OUT;
+wire [31:0] WDATA_AXI_TLX_OUT;
+wire [3:0] WSTRB_AXI_TLX_OUT;
+wire WLAST_AXI_TLX_OUT;
+wire WVALID_AXI_TLX_OUT;
+wire WREADY_AXI_TLX_OUT;
+wire [3:0] BID_AXI_TLX_OUT;
+wire [1:0] BRESP_AXI_TLX_OUT;
+wire BVALID_AXI_TLX_OUT;
+wire BREADY_AXI_TLX_OUT;
+wire [3:0] ARID_AXI_TLX_OUT;
+wire [31:0] ARADDR_AXI_TLX_OUT;
+wire [7:0] ARLEN_AXI_TLX_OUT;
+wire [2:0] ARSIZE_AXI_TLX_OUT;
+wire [1:0] ARBURST_AXI_TLX_OUT;
+wire ARLOCK_AXI_TLX_OUT;
+wire [3:0] ARCACHE_AXI_TLX_OUT;
+wire [2:0] ARPROT_AXI_TLX_OUT;
+wire ARVALID_AXI_TLX_OUT;
+wire ARREADY_AXI_TLX_OUT;
+wire [3:0] RID_AXI_TLX_OUT;
+wire [31:0] RDATA_AXI_TLX_OUT;
+wire [1:0] RRESP_AXI_TLX_OUT;
+wire RLAST_AXI_TLX_OUT;
+wire RVALID_AXI_TLX_OUT;
+wire RREADY_AXI_TLX_OUT;
// - PVT (silicon lifetime monitoring) APB wires
wire [31:0] PADDR_APB_PVT;
wire [31:0] PWDATA_APB_PVT;
@@ -94,19 +129,6 @@ wire PSELx_APB_PVT;
wire [31:0] PRDATA_APB_PVT;
wire PSLVERR_APB_PVT;
wire PREADY_APB_PVT;
-// - ADP AHB wires
-wire [31:0] HADDR_AHB_ADP;
-wire [1:0] HTRANS_AHB_ADP;
-wire HWRITE_AHB_ADP;
-wire [2:0] HSIZE_AHB_ADP;
-wire [2:0] HBURST_AHB_ADP;
-wire [3:0] HPROT_AHB_ADP;
-wire [31:0] HWDATA_AHB_ADP;
-wire HSELx_AHB_ADP;
-wire [31:0] HRDATA_AHB_ADP;
-wire HREADY_AHB_ADP;
-wire HREADYOUT_AHB_ADP;
-wire HRESP_AHB_ADP;
// - Chiplet In AXI port
wire [3:0] AWID_AXI_CHIPLET_IN;
wire [31:0] AWADDR_AXI_CHIPLET_IN;
@@ -145,34 +167,29 @@ wire RVALID_AXI_CHIPLET_IN;
wire RREADY_AXI_CHIPLET_IN;
// Thin links internal wires
-wire tvalid_pl_rev_m1_m_tlx_s_stream;
-wire tready_pl_rev_m1_m_tlx_s_stream;
-wire [15:0] tdata_pl_rev_m1_m_tlx_s_stream;
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_pl();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_IN_flow_rev_pl();
-
-wire tvalid_pl_rev_m1_m_tlx_s_flow;
-wire tready_pl_rev_m1_m_tlx_s_flow;
-wire [2:0] tdata_pl_rev_m1_m_tlx_s_flow;
nic400_cd_pl_rev_M1_m_tlx_tlx_sram_chiplet u_cd_pl_rev_M1_m_tlx(
// (tdata out)
- .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
- .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
- .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
+ .tvalid_pl_rev_m1_m_tlx_m_stream(TLX_IN_data_rev.tvalid),
+ .tready_pl_rev_m1_m_tlx_m_stream(TLX_IN_data_rev.tready),
+ .tdata_pl_rev_m1_m_tlx_m_stream(TLX_IN_data_rev.tdata),
// (tdata in)
- .tvalid_pl_rev_m1_m_tlx_s_stream(tvalid_pl_rev_m1_m_tlx_s_stream),
- .tready_pl_rev_m1_m_tlx_s_stream(tready_pl_rev_m1_m_tlx_s_stream),
- .tdata_pl_rev_m1_m_tlx_s_stream(tdata_pl_rev_m1_m_tlx_s_stream),
+ .tvalid_pl_rev_m1_m_tlx_s_stream(TLX_IN_data_rev_pl.tvalid),
+ .tready_pl_rev_m1_m_tlx_s_stream(TLX_IN_data_rev_pl.tready),
+ .tdata_pl_rev_m1_m_tlx_s_stream(TLX_IN_data_rev_pl.tdata),
// (tdata out)
- .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
- .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
- .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+ .tvalid_pl_rev_m1_m_tlx_m_flow(TLX_IN_flow_rev.tvalid),
+ .tready_pl_rev_m1_m_tlx_m_flow(TLX_IN_flow_rev.tready),
+ .tdata_pl_rev_m1_m_tlx_m_flow(TLX_IN_flow_rev.tdata),
// (tdata in)
- .tvalid_pl_rev_m1_m_tlx_s_flow(tvalid_pl_rev_m1_m_tlx_s_flow),
- .tready_pl_rev_m1_m_tlx_s_flow(tready_pl_rev_m1_m_tlx_s_flow),
- .tdata_pl_rev_m1_m_tlx_s_flow(tdata_pl_rev_m1_m_tlx_s_flow),
+ .tvalid_pl_rev_m1_m_tlx_s_flow(TLX_IN_flow_rev_pl.tvalid),
+ .tready_pl_rev_m1_m_tlx_s_flow(TLX_IN_flow_rev_pl.tready),
+ .tdata_pl_rev_m1_m_tlx_s_flow(TLX_IN_flow_rev_pl.tdata),
.pl_rev_M1_m_tlxclk(SYS_CLK),
.pl_rev_M1_m_tlxresetn(aRESETn)
@@ -217,24 +234,24 @@ nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
.rready_m1_m_m(RREADY_AXI_CHIPLET_IN),
// Thin links data reverse to PL (tdata out)
- .tvalid_m1_m_tlx_tlx_m_to_pl_rev_data(tvalid_pl_rev_m1_m_tlx_s_stream),
- .tready_m1_m_tlx_tlx_m_to_pl_rev_data(tready_pl_rev_m1_m_tlx_s_stream),
- .tdata_m1_m_tlx_tlx_m_to_pl_rev_data(tdata_pl_rev_m1_m_tlx_s_stream),
+ .tvalid_m1_m_tlx_tlx_m_to_pl_rev_data(TLX_IN_data_rev_pl.tvalid),
+ .tready_m1_m_tlx_tlx_m_to_pl_rev_data(TLX_IN_data_rev_pl.tready),
+ .tdata_m1_m_tlx_tlx_m_to_pl_rev_data(TLX_IN_data_rev_pl.tdata),
// Thin links flow reverse to PL (tdata out)
- .tvalid_m1_m_tlx_tlx_m_to_pl_rev_flow(tvalid_pl_rev_m1_m_tlx_s_flow),
- .tready_m1_m_tlx_tlx_m_to_pl_rev_flow(tready_pl_rev_m1_m_tlx_s_flow),
- .tdata_m1_m_tlx_tlx_m_to_pl_rev_flow(tdata_pl_rev_m1_m_tlx_s_flow),
+ .tvalid_m1_m_tlx_tlx_m_to_pl_rev_flow(TLX_IN_flow_rev_pl.tvalid),
+ .tready_m1_m_tlx_tlx_m_to_pl_rev_flow(TLX_IN_flow_rev_pl.tready),
+ .tdata_m1_m_tlx_tlx_m_to_pl_rev_flow(TLX_IN_flow_rev_pl.tdata),
// Thin links data forward from PL (tdata in)
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(TLX_IN_flow_fwd.tvalid),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(TLX_IN_flow_fwd.tready),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(TLX_IN_flow_fwd.tdata),
// Thin links flow forward from PL (tdata in)
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(TLX_IN_data_fwd.tvalid),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(TLX_IN_data_fwd.tready),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(TLX_IN_data_fwd.tdata),
// Master clock
.clk_mclk(SYS_CLK),
@@ -244,6 +261,13 @@ nic400_master_pwr_M1_m_tlx_tlx_sram_chiplet u_master_pwr_M1_m_tlx(
.dl_fwd_M1_m_tlxresetn(DL_FWD_RESETn)
);
+// Address select logic
+wire [31:0] AWADDR_AXI_CHIPLET_IN_i;
+wire [31:0] ARADDR_AXI_CHIPLET_IN_i;
+
+assign AWADDR_AXI_CHIPLET_IN_i = (AWADDR_AXI_CHIPLET_IN[23:21]==addr_sel[2:0]) ? {11'h000,AWADDR_AXI_CHIPLET_IN[20:0]} : AWADDR_AXI_CHIPLET_IN;
+assign ARADDR_AXI_CHIPLET_IN_i = (ARADDR_AXI_CHIPLET_IN[23:21]==addr_sel[2:0]) ? {11'h000,ARADDR_AXI_CHIPLET_IN[20:0]} : ARADDR_AXI_CHIPLET_IN;
+
nic400_sram_chiplet u_nic400_sram_chiplet(
.AWID_AXI_SRAM(AWID_AXI_SRAM),
.AWADDR_AXI_SRAM(AWADDR_AXI_SRAM),
@@ -281,6 +305,42 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.RVALID_AXI_SRAM(RVALID_AXI_SRAM),
.RREADY_AXI_SRAM(RREADY_AXI_SRAM),
+ .AWID_AXI_TLX_OUT(AWID_AXI_TLX_OUT),
+ .AWADDR_AXI_TLX_OUT(AWADDR_AXI_TLX_OUT),
+ .AWLEN_AXI_TLX_OUT(AWLEN_AXI_TLX_OUT),
+ .AWSIZE_AXI_TLX_OUT(AWSIZE_AXI_TLX_OUT),
+ .AWBURST_AXI_TLX_OUT(AWBURST_AXI_TLX_OUT),
+ .AWLOCK_AXI_TLX_OUT(AWLOCK_AXI_TLX_OUT),
+ .AWCACHE_AXI_TLX_OUT(AWCACHE_AXI_TLX_OUT),
+ .AWPROT_AXI_TLX_OUT(AWPROT_AXI_TLX_OUT),
+ .AWVALID_AXI_TLX_OUT(AWVALID_AXI_TLX_OUT),
+ .AWREADY_AXI_TLX_OUT(AWREADY_AXI_TLX_OUT),
+ .WDATA_AXI_TLX_OUT(WDATA_AXI_TLX_OUT),
+ .WSTRB_AXI_TLX_OUT(WSTRB_AXI_TLX_OUT),
+ .WLAST_AXI_TLX_OUT(WLAST_AXI_TLX_OUT),
+ .WVALID_AXI_TLX_OUT(WVALID_AXI_TLX_OUT),
+ .WREADY_AXI_TLX_OUT(WREADY_AXI_TLX_OUT),
+ .BID_AXI_TLX_OUT(BID_AXI_TLX_OUT),
+ .BRESP_AXI_TLX_OUT(BRESP_AXI_TLX_OUT),
+ .BVALID_AXI_TLX_OUT(BVALID_AXI_TLX_OUT),
+ .BREADY_AXI_TLX_OUT(BREADY_AXI_TLX_OUT),
+ .ARID_AXI_TLX_OUT(ARID_AXI_TLX_OUT),
+ .ARADDR_AXI_TLX_OUT(ARADDR_AXI_TLX_OUT),
+ .ARLEN_AXI_TLX_OUT(ARLEN_AXI_TLX_OUT),
+ .ARSIZE_AXI_TLX_OUT(ARSIZE_AXI_TLX_OUT),
+ .ARBURST_AXI_TLX_OUT(ARBURST_AXI_TLX_OUT),
+ .ARLOCK_AXI_TLX_OUT(ARLOCK_AXI_TLX_OUT),
+ .ARCACHE_AXI_TLX_OUT(ARCACHE_AXI_TLX_OUT),
+ .ARPROT_AXI_TLX_OUT(ARPROT_AXI_TLX_OUT),
+ .ARVALID_AXI_TLX_OUT(ARVALID_AXI_TLX_OUT),
+ .ARREADY_AXI_TLX_OUT(ARREADY_AXI_TLX_OUT),
+ .RID_AXI_TLX_OUT(RID_AXI_TLX_OUT),
+ .RDATA_AXI_TLX_OUT(RDATA_AXI_TLX_OUT),
+ .RRESP_AXI_TLX_OUT(RRESP_AXI_TLX_OUT),
+ .RLAST_AXI_TLX_OUT(RLAST_AXI_TLX_OUT),
+ .RVALID_AXI_TLX_OUT(RVALID_AXI_TLX_OUT),
+ .RREADY_AXI_TLX_OUT(RREADY_AXI_TLX_OUT),
+
.PADDR_APB_PVT(PADDR_APB_PVT),
.PWDATA_APB_PVT(PWDATA_APB_PVT),
.PWRITE_APB_PVT(PWRITE_APB_PVT),
@@ -292,21 +352,8 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.PSLVERR_APB_PVT(PSLVERR_APB_PVT),
.PREADY_APB_PVT(PREADY_APB_PVT),
- .HADDR_AHB_ADP(HADDR_AHB_ADP),
- .HTRANS_AHB_ADP(HTRANS_AHB_ADP),
- .HWRITE_AHB_ADP(HWRITE_AHB_ADP),
- .HSIZE_AHB_ADP(HSIZE_AHB_ADP),
- .HBURST_AHB_ADP(HBURST_AHB_ADP),
- .HPROT_AHB_ADP(HPROT_AHB_ADP),
- .HWDATA_AHB_ADP(HWDATA_AHB_ADP),
- .HSELx_AHB_ADP(HSELx_AHB_ADP),
- .HRDATA_AHB_ADP(HRDATA_AHB_ADP),
- .HREADY_AHB_ADP(HREADY_AHB_ADP),
- .HREADYOUT_AHB_ADP(HREADYOUT_AHB_ADP),
- .HRESP_AHB_ADP(HRESP_AHB_ADP),
-
.AWID_AXI_CHIPLET_IN(AWID_AXI_CHIPLET_IN),
- .AWADDR_AXI_CHIPLET_IN(AWADDR_AXI_CHIPLET_IN),
+ .AWADDR_AXI_CHIPLET_IN(AWADDR_AXI_CHIPLET_IN_i),
.AWLEN_AXI_CHIPLET_IN(AWLEN_AXI_CHIPLET_IN),
.AWSIZE_AXI_CHIPLET_IN(AWSIZE_AXI_CHIPLET_IN),
.AWBURST_AXI_CHIPLET_IN(AWBURST_AXI_CHIPLET_IN),
@@ -325,7 +372,7 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.BVALID_AXI_CHIPLET_IN(BVALID_AXI_CHIPLET_IN),
.BREADY_AXI_CHIPLET_IN(BREADY_AXI_CHIPLET_IN),
.ARID_AXI_CHIPLET_IN(ARID_AXI_CHIPLET_IN),
- .ARADDR_AXI_CHIPLET_IN(ARADDR_AXI_CHIPLET_IN),
+ .ARADDR_AXI_CHIPLET_IN(ARADDR_AXI_CHIPLET_IN_i),
.ARLEN_AXI_CHIPLET_IN(ARLEN_AXI_CHIPLET_IN),
.ARSIZE_AXI_CHIPLET_IN(ARSIZE_AXI_CHIPLET_IN),
.ARBURST_AXI_CHIPLET_IN(ARBURST_AXI_CHIPLET_IN),
@@ -346,6 +393,100 @@ nic400_sram_chiplet u_nic400_sram_chiplet(
.clk0resetn(aRESETn)
);
+// Thin links output
+// Thin links internal wires
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_OUT_data_fwd_pl();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_OUT_flow_fwd_pl();
+
+nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
+ .awid_m1_m_s(AWID_AXI_TLX_OUT),
+ .awaddr_m1_m_s(AWADDR_AXI_TLX_OUT),
+ .awlen_m1_m_s(AWLEN_AXI_TLX_OUT),
+ .awsize_m1_m_s(AWSIZE_AXI_TLX_OUT),
+ .awburst_m1_m_s(AWBURST_AXI_TLX_OUT),
+ .awlock_m1_m_s(AWLOCK_AXI_TLX_OUT),
+ .awcache_m1_m_s(AWCACHE_AXI_TLX_OUT),
+ .awprot_m1_m_s(AWPROT_AXI_TLX_OUT),
+ .awvalid_m1_m_s(AWVALID_AXI_TLX_OUT),
+ .awready_m1_m_s(AWREADY_AXI_TLX_OUT),
+ .wdata_m1_m_s(WDATA_AXI_TLX_OUT),
+ .wstrb_m1_m_s(WSTRB_AXI_TLX_OUT),
+ .wlast_m1_m_s(WLAST_AXI_TLX_OUT),
+ .wvalid_m1_m_s(WVALID_AXI_TLX_OUT),
+ .wready_m1_m_s(WREADY_AXI_TLX_OUT),
+ .bid_m1_m_s(BID_AXI_TLX_OUT),
+ .bresp_m1_m_s(BRESP_AXI_TLX_OUT),
+ .bvalid_m1_m_s(BVALID_AXI_TLX_OUT),
+ .bready_m1_m_s(BREADY_AXI_TLX_OUT),
+ .arid_m1_m_s(ARID_AXI_TLX_OUT),
+ .araddr_m1_m_s(ARADDR_AXI_TLX_OUT),
+ .arlen_m1_m_s(ARLEN_AXI_TLX_OUT),
+ .arsize_m1_m_s(ARSIZE_AXI_TLX_OUT),
+ .arburst_m1_m_s(ARBURST_AXI_TLX_OUT),
+ .arlock_m1_m_s(ARLOCK_AXI_TLX_OUT),
+ .arcache_m1_m_s(ARCACHE_AXI_TLX_OUT),
+ .arprot_m1_m_s(ARPROT_AXI_TLX_OUT),
+ .arvalid_m1_m_s(ARVALID_AXI_TLX_OUT),
+ .arready_m1_m_s(ARREADY_AXI_TLX_OUT),
+ .rid_m1_m_s(RID_AXI_TLX_OUT),
+ .rdata_m1_m_s(RDATA_AXI_TLX_OUT),
+ .rresp_m1_m_s(RRESP_AXI_TLX_OUT),
+ .rlast_m1_m_s(RLAST_AXI_TLX_OUT),
+ .rvalid_m1_m_s(RVALID_AXI_TLX_OUT),
+ .rready_m1_m_s(RREADY_AXI_TLX_OUT),
+
+ // Axi Stream master (tdata out) data stream
+ .tvalid_m1_m_tlx_fwd_ib_axi_stream(TLX_OUT_data_fwd_pl.tvalid),
+ .tready_m1_m_tlx_fwd_ib_axi_stream(TLX_OUT_data_fwd_pl.tready),
+ .tdata_m1_m_tlx_fwd_ib_axi_stream(TLX_OUT_data_fwd_pl.tdata),
+
+ // Axi Stream master (tdata out) data flow
+ .tvalid_m1_m_tlx_fwd_ib_flow(TLX_OUT_flow_fwd_pl.tvalid),
+ .tready_m1_m_tlx_fwd_ib_flow(TLX_OUT_flow_fwd_pl.tready),
+ .tdata_m1_m_tlx_fwd_ib_flow(TLX_OUT_flow_fwd_pl.tdata),
+
+ // Axi Stream slave (tdata in) rev flow from SRAM chiplet PL
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_OUT_flow_rev.tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_OUT_flow_rev.tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_OUT_flow_rev.tdata),
+
+ // Axi stream slave (tdata in) rev data from SRAM chiplet PL
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_OUT_data_rev.tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_OUT_data_rev.tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_OUT_data_rev.tdata),
+
+ .clk_sclk(SYS_CLK),
+ .clk_sresetn(aRESETn),
+ .dl_rev_M1_m_tlxclk(SYS_CLK),
+ .dl_rev_M1_m_tlxresetn(aRESETn)
+);
+
+nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
+ // axi sream master (tdata out)
+ .tvalid_pl_fwd_m1_m_tlx_m_stream(TLX_OUT_data_fwd.tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_stream(TLX_OUT_data_fwd.tready),
+ .tdata_pl_fwd_m1_m_tlx_m_stream(TLX_OUT_data_fwd.tdata),
+
+ // axi stream slave (tdata in)
+ .tvalid_pl_fwd_m1_m_tlx_s_stream(TLX_OUT_data_fwd_pl.tvalid),
+ .tready_pl_fwd_m1_m_tlx_s_stream(TLX_OUT_data_fwd_pl.tready),
+ .tdata_pl_fwd_m1_m_tlx_s_stream(TLX_OUT_data_fwd_pl.tdata),
+
+ // axi stream master (tdata out)
+ .tvalid_pl_fwd_m1_m_tlx_m_flow(TLX_OUT_flow_fwd.tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_flow(TLX_OUT_flow_fwd.tready),
+ .tdata_pl_fwd_m1_m_tlx_m_flow(TLX_OUT_flow_fwd.tdata),
+
+ // axi stream slave (tdata in)
+ .tvalid_pl_fwd_m1_m_tlx_s_flow(TLX_OUT_flow_fwd_pl.tvalid),
+ .tready_pl_fwd_m1_m_tlx_s_flow(TLX_OUT_flow_fwd_pl.tready),
+ .tdata_pl_fwd_m1_m_tlx_s_flow(TLX_OUT_flow_fwd_pl.tdata),
+
+ .pl_fwd_M1_m_tlxclk(SYS_CLK),
+ .pl_fwd_M1_m_tlxresetn(aRESETn)
+
+);
+
sram_chiplet_apb_subsystem u_sram_chiplet_apb_subsystem(
);
diff --git a/makefile b/makefile
index 50054b37d6aec6a6eb5a081fa49087b949990154..c3895676b4c0d091913585ce699409316b0fe224 100644
--- a/makefile
+++ b/makefile
@@ -3,6 +3,14 @@
include ./make.cfg
+#-------------------------------------
+# - Commonly Overloaded Variables
+#-------------------------------------
+# Simulator type (mti/vcs/xm)
+SIMULATOR = mti
+
+# IS this for an ASIC Flow?
+ASIC ?= no
build_sie300_sram_ctrl:
@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
@@ -21,3 +29,25 @@ build_ip: build_sie300_sram_ctrl build_nic400_sram_chiplet build_nic400_tb build
first_time_setup: make_project build_sie300_sram_ctrl build_nic400_sram_chiplet build_nic400_tb build_tlx_sram_chiplet
+
+
+#-------------------------------------
+# - Directory Setups
+#-------------------------------------
+# Project System Directory
+ASIC_IMP_DIR := $(SOCLABS_PSOCLABS_SRAM_CHIPLET_DIRROJECT_DIR)/imp/asic
+
+# Directory to put simulation files
+SIM_TOP_DIR ?= $(SOCLABS_SRAM_CHIPLET_DIR)/simulate/sim
+SIM_DIR ?= $(SIM_TOP_DIR)
+
+
+ifeq ($(ASIC),yes)
+ DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet_TSMC28nm.flist
+else
+ DESIGN_VC ?= $(SOCLABS_SRAM_CHIPLET_DIR)/flist/Top/sram_chiplet.flist
+endif
+
+#Include flows
+include ./flows/makefile.simulate
+include ./flows/makefile.asic
\ No newline at end of file
diff --git a/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v
new file mode 100644
index 0000000000000000000000000000000000000000..3dadbfec62aa11cceb692ccef3242fa68b1a4d1c
--- /dev/null
+++ b/pad_level/tsmc28nm_hpcp/SRAM_chiplet.v
@@ -0,0 +1,53 @@
+//-----------------------------------------------------------------------------
+// Top pad level of SRAM chiplet for TSMC 28nm HPC+
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SRAM_chiplet(
+`ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+`endif
+
+);
+
+
+
+top_sram_chiplet u_top_sram_chiplet(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Axi stream master (tdata out) from PL
+ .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
+ .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
+ .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
+
+ // Axi Stream master (tdata out) from PL
+ .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
+ .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
+ .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+
+ // Axi Stream Slave (tdata in) to DL
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+
+ // Axi Stream slave (tdata in) to DL
+ .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data)
+);
+
+endmodule
\ No newline at end of file
diff --git a/set_sram_chiplet_env.sh b/set_sram_chiplet_env.sh
index 2944029ba69efb9ed183074588532a7f7aaa3da8..0e573bbaad214f353e19b671485755e8ed0eb525 100644
--- a/set_sram_chiplet_env.sh
+++ b/set_sram_chiplet_env.sh
@@ -1 +1,2 @@
-export SOCLABS_SRAM_CHIPLET_DIR=$(pwd)
\ No newline at end of file
+export SOCLABS_SRAM_CHIPLET_DIR=$(pwd)
+export SOCLABS_SOCTOOLS_FLOW_DIR=$SOCLABS_SRAM_CHIPLET_DIR/soctools_flow
\ No newline at end of file
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
index 2f6d055d00f3315893135d8584820584a4750ce7..ec3ef9fb85d9f7000461193298c47c97cd4537ad 100644
--- a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -63,7 +63,7 @@ DATA_WIDTH: 32
# ID_WIDTH: AXI5 ID width for all channels
# Valid values:
# 2-32
-ID_WIDTH: 5
+ID_WIDTH: 4
#
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
index 5079c85d9ef71abad9ee14367f9ea7b325903565..b34056ce3ad240b4902a96dda21556c901c53de4 100644
--- a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -15,7 +15,7 @@
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
- <GlobalIDWidth>5</GlobalIDWidth>
+ <GlobalIDWidth>4</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
@@ -96,7 +96,7 @@
<WriteIssuing>8</WriteIssuing>
<TotalIssuing>8</TotalIssuing>
<MultiPorted>false</MultiPorted>
- <IDWidthReduction>true</IDWidthReduction>
+ <IDWidthReduction>false</IDWidthReduction>
<OutputSignals>false</OutputSignals>
<VNExternal>false</VNExternal>
</AXI4MasterProtocol>
@@ -114,31 +114,25 @@
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
</MasterInterface>
- <SlaveInterface>
- <Name>AHB_ADP</Name>
- <AHBLiteTargetSlaveProtocol>
+ <MasterInterface>
+ <Name>AXI_TLX_OUT</Name>
+ <AXI4MasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
- <RUSEREnabled>false</RUSEREnabled>
- <WUSEREnabled>false</WUSEREnabled>
- <LockSupport>false</LockSupport>
- <TrustZoneSlaveAHB>non_secure</TrustZoneSlaveAHB>
- <ReadAcceptanceAHB>1</ReadAcceptanceAHB>
- <WriteAcceptance>4</WriteAcceptance>
- <QoSTypeAHB>fixed</QoSTypeAHB>
- <QoSValue>0</QoSValue>
- <TransactionRateRegulation>false</TransactionRateRegulation>
- <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
- <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
- <EnableEarlyWriteResponse>true</EnableEarlyWriteResponse>
- <BrokenBursts>false</BrokenBursts>
- </AHBLiteTargetSlaveProtocol>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>8</ReadIssuing>
+ <WriteIssuing>8</WriteIssuing>
+ <TotalIssuing>8</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>false</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
<GeographicDomainRef>gd0</GeographicDomainRef>
<ClockRef>clk0</ClockRef>
- <MultiPorted>false</MultiPorted>
- <CyclicDependencyAvoidanceScheme>single_slave</CyclicDependencyAvoidanceScheme>
- <LowLatency>false</LowLatency>
- </SlaveInterface>
+ </MasterInterface>
</Interfaces>
<MemoryMaps>
<MemoryMap>
@@ -146,9 +140,6 @@
<MemoryMapSource>
<InterfaceRef>AXI_CHIPLET_IN</InterfaceRef>
</MemoryMapSource>
- <MemoryMapSource>
- <InterfaceRef>AHB_ADP</InterfaceRef>
- </MemoryMapSource>
<MappedBlock>
<InterfaceRef>AXI_SRAM</InterfaceRef>
<Offset>0</Offset>
@@ -161,6 +152,12 @@
<Range>65536</Range>
<Visibility>true</Visibility>
</MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
+ <Offset>2097152</Offset>
+ <Range>16777216</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
</MemoryMap>
</MemoryMaps>
<Paths>
@@ -175,18 +172,8 @@
<Target>
<InterfaceRef>APB_PVT</InterfaceRef>
</Target>
- </Targets>
- </Path>
- <Path>
- <Source>
- <InterfaceRef>AHB_ADP</InterfaceRef>
- </Source>
- <Targets>
<Target>
- <InterfaceRef>APB_PVT</InterfaceRef>
- </Target>
- <Target>
- <InterfaceRef>AXI_SRAM</InterfaceRef>
+ <InterfaceRef>AXI_TLX_OUT</InterfaceRef>
</Target>
</Targets>
</Path>
@@ -211,7 +198,7 @@
<hcg_en>false</hcg_en>
<license_status>unlicensed_nic</license_status>
<periph_id3 def="true">0</periph_id3>
- <pl_id_width>5</pl_id_width>
+ <pl_id_width>4</pl_id_width>
<qos_status>false</qos_status>
<rsb_arch_central_ring>false</rsb_arch_central_ring>
<ruser_width>0</ruser_width>
@@ -250,6 +237,16 @@
<target>APB_PVT</target>
</remap>
</range>
+ <range>
+ <addr_max>0x11FFFFF</addr_max>
+ <addr_min>0x200000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_TLX_OUT</target>
+ </remap>
+ </range>
</address_ranges>
<apb_config>false</apb_config>
<apb_slave_no def="true">2</apb_slave_no>
@@ -379,147 +376,140 @@
<master_if_port_name>AXI_CHIPLET_IN_m</master_if_port_name>
<slave_if_port_name>AXI_CHIPLET_IN_s</slave_if_port_name>
</asib>
- <asib>
- <address_ranges>
- <name>mm0</name>
- <range>
- <addr_max>0x1EFFFF</addr_max>
- <addr_min>0x0</addr_min>
- <remap>
- <bit>default</bit>
- <present>true</present>
- <region>0</region>
- <target>AXI_SRAM</target>
- </remap>
- </range>
- <range>
- <addr_max>0x1FFFFF</addr_max>
- <addr_min>0x1F0000</addr_min>
- <remap>
- <bit>default</bit>
- <present>true</present>
- <region>0</region>
- <target>APB_PVT</target>
- </remap>
- </range>
- </address_ranges>
+ <amib>
<apb_config>false</apb_config>
- <apb_slave_no def="true">2</apb_slave_no>
- <broken_bursts>false</broken_bursts>
- <cds>singleslave</cds>
+ <apb_slave_no>65</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
- <ewr_incr_promotion>true</ewr_incr_promotion>
+ <compress_id>false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
<multi_region>false</multi_region>
- <name>AHB_ADP</name>
- <protocol>ahb_s</protocol>
- <qos_config>
- <hard>disable</hard>
- <lqv>disable</lqv>
- <pot>disable</pot>
- </qos_config>
- <qv>
- <type>fixed</type>
- <value>0</value>
- </qv>
+ <name>AXI_SRAM</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
<reg>
<impl>present</impl>
- <location>slave_port</location>
+ <location>master_port</location>
<name>w</name>
<type>rev</type>
</reg>
<reg>
- <impl def="true">absent</impl>
+ <impl>present</impl>
<location>master_port</location>
+ <name>b</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
<name>aw</name>
<type def="true">full</type>
</reg>
<reg>
+ <depth def="true">2</depth>
<impl def="true">absent</impl>
- <location>master_port</location>
- <name>ar</name>
- <type def="true">full</type>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
</reg>
<reg>
<impl def="true">absent</impl>
<location>master_port</location>
- <name>r</name>
+ <name>aw</name>
<type def="true">full</type>
</reg>
<reg>
<impl def="true">absent</impl>
- <location>master_port</location>
- <name>w</name>
+ <location>slave_port</location>
+ <name>ar</name>
<type def="true">full</type>
</reg>
<reg>
+ <depth def="true">2</depth>
<impl def="true">absent</impl>
- <location>master_port</location>
- <name>b</name>
- <type def="true">full</type>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
</reg>
<reg>
<impl def="true">absent</impl>
- <location>slave_port</location>
- <name>a</name>
+ <location>master_port</location>
+ <name>ar</name>
<type def="true">full</type>
</reg>
<reg>
<impl def="true">absent</impl>
<location>slave_port</location>
- <name>d</name>
+ <name>r</name>
<type def="true">full</type>
</reg>
<reg>
<depth def="true">2</depth>
<impl def="true">absent</impl>
<location>boundary</location>
- <name>a</name>
+ <name>r</name>
<type>fifo</type>
</reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
<reg>
<depth def="true">2</depth>
<impl def="true">absent</impl>
<location>boundary</location>
- <name>d</name>
+ <name>w</name>
<type>fifo</type>
</reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
<reg>
<depth def="true">2</depth>
<impl def="true">absent</impl>
<location>boundary</location>
- <name>w</name>
+ <name>b</name>
<type>fifo</type>
</reg>
- <slave_if_addr_width>32</slave_if_addr_width>
<slave_if_data_width>32</slave_if_data_width>
<token_prerequest def="true">false</token_prerequest>
<token_prerequest_bridge def="true">false</token_prerequest_bridge>
<trustzone>nsec</trustzone>
- <vid_width>0</vid_width>
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
- <y>40</y>
- <master_if_port_name>AHB_ADP_m</master_if_port_name>
- <slave_if_port_name>AHB_ADP_s</slave_if_port_name>
- </asib>
+ <y>20</y>
+ <master_if_port_name>AXI_SRAM_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_s</slave_if_port_name>
+ </amib>
<amib>
<apb_config>false</apb_config>
- <apb_slave_no>65</apb_slave_no>
+ <apb_slave_no>64</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
- <compress_id>true</compress_id>
+ <compress_id>false</compress_id>
<dest_type>peripheral</dest_type>
<master_if_addr_width>32</master_if_addr_width>
<master_if_data_width>32</master_if_data_width>
<multi_ported>false</multi_ported>
<multi_region>false</multi_region>
- <name>AXI_SRAM</name>
+ <name>AXI_TLX_OUT</name>
<protocol>axi4</protocol>
<qv_out>false</qv_out>
<reg>
@@ -624,9 +614,9 @@
<vn_external>none</vn_external>
<vn_external_bridge>none</vn_external_bridge>
<x>0</x>
- <y>20</y>
- <master_if_port_name>AXI_SRAM_m</master_if_port_name>
- <slave_if_port_name>AXI_SRAM_s</slave_if_port_name>
+ <y>40</y>
+ <master_if_port_name>AXI_TLX_OUT_m</master_if_port_name>
+ <slave_if_port_name>AXI_TLX_OUT_s</slave_if_port_name>
</amib>
<amib>
<apb_config>false</apb_config>
@@ -637,7 +627,7 @@
<x>0</x>
<y>0</y>
</apb_port>
- <apb_slave_no>64</apb_slave_no>
+ <apb_slave_no>63</apb_slave_no>
<clock_boundary>none</clock_boundary>
<clock_domain_name_master_if>clk0</clock_domain_name_master_if>
<clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
@@ -726,7 +716,7 @@
<vn_external def="true">none</vn_external>
<vn_external_bridge def="true">none</vn_external_bridge>
<x>0</x>
- <y>40</y>
+ <y>60</y>
<master_if_port_name>APB_PVT</master_if_port_name>
<slave_if_port_name>apb_group0_s</slave_if_port_name>
</amib>
@@ -734,7 +724,7 @@
<clock_domain>clk0</clock_domain>
<data_width>32</data_width>
<expanded>false</expanded>
- <height>40</height>
+ <height>60</height>
<impl>mlayer</impl>
<master_if>
<name>axi_m_0</name>
@@ -754,6 +744,12 @@
<x>0</x>
<y>103</y>
</master_if>
+ <master_if>
+ <name>axi_m_3</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>123</y>
+ </master_if>
<name>bm0</name>
<protocol>axi4</protocol>
<slave_if>
@@ -761,11 +757,6 @@
<x>0</x>
<y>63</y>
</slave_if>
- <slave_if>
- <name>axi_s_1</name>
- <x>0</x>
- <y>83</y>
- </slave_if>
<sparse>
<cds>singleslave</cds>
<sas def="true">false</sas>
@@ -854,69 +845,8 @@
<type def="true">full</type>
</reg>
</master_if_port>
- </sparse>
- <sparse>
- <cds>singleslave</cds>
- <sas def="true">false</sas>
- <slave_if_port>axi_s_1</slave_if_port>
- <master_if_port>
- <name>axi_m_0</name>
- <reg>
- <impl def="true">absent</impl>
- <name>aw</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>ar</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>r</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>w</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>b</name>
- <type def="true">full</type>
- </reg>
- </master_if_port>
- <master_if_port>
- <name>axi_m_1</name>
- <reg>
- <impl def="true">absent</impl>
- <name>aw</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>ar</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>r</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>w</name>
- <type def="true">full</type>
- </reg>
- <reg>
- <impl def="true">absent</impl>
- <name>b</name>
- <type def="true">full</type>
- </reg>
- </master_if_port>
<master_if_port>
- <name>axi_m_2</name>
+ <name>axi_m_3</name>
<reg>
<impl def="true">absent</impl>
<name>aw</name>
@@ -948,8 +878,8 @@
<width>0</width>
<x>500</x>
<y>45</y>
- <master_if_port_name>axi_m_0,axi_m_1,axi_m_2</master_if_port_name>
- <slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2,axi_m_3</master_if_port_name>
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
</inter>
<inter>
<name>ds_1</name>
@@ -984,16 +914,16 @@
<aruser>false</aruser>
<awuser>false</awuser>
<buser>false</buser>
- <dest>AHB_ADP</dest>
- <dest_port>AHB_ADP_s</dest_port>
+ <dest>external</dest>
+ <dest_port>AXI_SRAM</dest_port>
<lock>false</lock>
- <out_reads>1</out_reads>
- <out_trans>5</out_trans>
- <out_writes>4</out_writes>
- <protocol>ahb_s</protocol>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
<ruser>false</ruser>
- <src>external</src>
- <src_port>AHB_ADP</src_port>
+ <src>AXI_SRAM</src>
+ <src_port>AXI_SRAM_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -1001,15 +931,15 @@
<awuser>false</awuser>
<buser>false</buser>
<dest>external</dest>
- <dest_port>AXI_SRAM</dest_port>
+ <dest_port>AXI_TLX_OUT</dest_port>
<lock>false</lock>
<out_reads>8</out_reads>
<out_trans>8</out_trans>
<out_writes>8</out_writes>
<protocol>axi4</protocol>
<ruser>false</ruser>
- <src>AXI_SRAM</src>
- <src_port>AXI_SRAM_m</src_port>
+ <src>AXI_TLX_OUT</src>
+ <src_port>AXI_TLX_OUT_m</src_port>
<wuser>false</wuser>
</connect>
<connect>
@@ -1039,6 +969,17 @@
<src>AXI_CHIPLET_IN</src>
<src_port>AXI_CHIPLET_IN_m</src_port>
</connect>
+ <connect>
+ <dest>AXI_TLX_OUT</dest>
+ <dest_port>AXI_TLX_OUT_s</dest_port>
+ <lock>false</lock>
+ <out_reads>8</out_reads>
+ <out_trans>8</out_trans>
+ <out_writes>8</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
<connect>
<dest>apb_group0</dest>
<dest_port>apb_group0_s</dest_port>
@@ -1048,7 +989,7 @@
<out_writes def="true">2</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_0</src_port>
+ <src_port>axi_m_1</src_port>
</connect>
<connect>
<dest>AXI_SRAM</dest>
@@ -1059,18 +1000,7 @@
<out_writes>8</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_1</src_port>
- </connect>
- <connect>
- <dest>bm0</dest>
- <dest_port>axi_s_1</dest_port>
- <lock>false</lock>
- <out_reads def="true">1</out_reads>
- <out_trans>5</out_trans>
- <out_writes def="true">4</out_writes>
- <protocol>axi4</protocol>
- <src>AHB_ADP</src>
- <src_port>AHB_ADP_m</src_port>
+ <src_port>axi_m_2</src_port>
</connect>
<connect>
<dest>ds_1</dest>
@@ -1081,21 +1011,13 @@
<out_writes>1</out_writes>
<protocol>axi4</protocol>
<src>bm0</src>
- <src_port>axi_m_2</src_port>
+ <src_port>axi_m_3</src_port>
</connect>
<architecture>
<link>
<slave_if>
<name>AXI_CHIPLET_IN</name>
- <master_if>AXI_SRAM</master_if>
- <master_if>APB_PVT<parent>apb_group0</parent>
- </master_if>
- <master_if>apb_group0</master_if>
- </slave_if>
- </link>
- <link>
- <slave_if>
- <name>AHB_ADP</name>
+ <master_if>AXI_TLX_OUT</master_if>
<master_if>AXI_SRAM</master_if>
<master_if>APB_PVT<parent>apb_group0</parent>
</master_if>
diff --git a/socrates/nic400_tb/nic400_tb.xml b/socrates/nic400_tb/nic400_tb.xml
index 6142c38fa060e0388a8333335f3af302de15bd74..5798eafa7dffdc535d4ba13cb6a037cfbda097a7 100644
--- a/socrates/nic400_tb/nic400_tb.xml
+++ b/socrates/nic400_tb/nic400_tb.xml
@@ -104,7 +104,7 @@
<MappedBlock>
<InterfaceRef>AXI_CHIPLET_OUT</InterfaceRef>
<Offset>0</Offset>
- <Range>2097152</Range>
+ <Range>16777216</Range>
<Visibility>true</Visibility>
<Region>0</Region>
</MappedBlock>
@@ -162,7 +162,7 @@
<address_ranges>
<name>mm0</name>
<range>
- <addr_max>0x1FFFFF</addr_max>
+ <addr_max>0xFFFFFF</addr_max>
<addr_min>0x0</addr_min>
<remap>
<bit>default</bit>
diff --git a/soctools_flow b/soctools_flow
new file mode 160000
index 0000000000000000000000000000000000000000..3e339941d8b4536f4bd096fc4191a4e36e38978a
--- /dev/null
+++ b/soctools_flow
@@ -0,0 +1 @@
+Subproject commit 3e339941d8b4536f4bd096fc4191a4e36e38978a
diff --git a/verif/cocotb/makefile b/verif/cocotb/makefile
index 00ee7c3e5018472de0170f2c6e913560272f61f2..b18864536786760e48e4ebb28b3574a5265b4624 100644
--- a/verif/cocotb/makefile
+++ b/verif/cocotb/makefile
@@ -31,7 +31,7 @@ DUT = sram_chiplet_cocotb
TOPLEVEL = sram_chiplet_cocotb
MODULE = sram_chiplet_tests
-VERILOG_SOURCES += ./sram_chiplet_cocotb.v
+VERILOG_SOURCES += ./sram_chiplet_cocotb.sv
ifeq ($(SIM), icarus)
@@ -51,8 +51,10 @@ else ifeq ($(SIM), verilator)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
endif
+else ifeq ($(SIM), questa)
+ COMPILE_ARGS += +acc
endif
-include $(SOCLABS_SRAM_CHIPLET_DIR)/flist/sram_chiplet_cocotb.flist
+include $(SOCLABS_SRAM_CHIPLET_DIR)/simulate/sim/cocotb/makefile.flist
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
diff --git a/verif/cocotb/sram_chiplet_cocotb.v b/verif/cocotb/sram_chiplet_cocotb.sv
similarity index 55%
rename from verif/cocotb/sram_chiplet_cocotb.v
rename to verif/cocotb/sram_chiplet_cocotb.sv
index c07106c9ffc8d3a6a6fdef3c84ab9f5b5e7c1eb1..5bb4a2dcc7a16c0edde4faa4fc317438b0284004 100644
--- a/verif/cocotb/sram_chiplet_cocotb.v
+++ b/verif/cocotb/sram_chiplet_cocotb.sv
@@ -1,5 +1,7 @@
`timescale 1ns/1ps
+`include "tlx_interfaces.sv"
+
module sram_chiplet_cocotb(
input wire clk_in,
input wire aresetn,
@@ -44,18 +46,62 @@ module sram_chiplet_cocotb(
wire DL_REV_CLK;
-wire tvalid_pl_rev_m1_m_tlx_m_stream;
-wire tready_pl_rev_m1_m_tlx_m_stream;
-wire [15:0] tdata_pl_rev_m1_m_tlx_m_stream;
-wire tvalid_pl_rev_m1_m_tlx_m_flow;
-wire tready_pl_rev_m1_m_tlx_m_flow;
-wire [2:0] tdata_pl_rev_m1_m_tlx_m_flow;
-wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
-wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
-wire [1:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow;
-wire tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data;
-wire tready_m1_m_tlx_pl_fwd_to_dl_fwd_data;
-wire [15:0] tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data;
+
+// Thin links from NIC_TB to SRAM_chiplet_0
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_IN_flow_rev_0();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_IN_flow_fwd_0();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_IN_data_fwd_0();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_1();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_1();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_1();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_2();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_2();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_2();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_2();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_3();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_3();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_3();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_3();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_4();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_4();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_4();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_4();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_5();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_5();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_5();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_5();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_6();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_6();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_6();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_6();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_7();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_7();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_7();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_7();
+
+// Thin links from SRAM_chiplet_0 to SRAM_chiplet_1
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_rev_8();
+TLX_AXI_stream #(.DATA_WIDTH(3)) TLX_flow_rev_8();
+TLX_AXI_stream #(.DATA_WIDTH(2)) TLX_flow_fwd_8();
+TLX_AXI_stream #(.DATA_WIDTH(16)) TLX_data_fwd_8();
+
+
wire [3:0] AWID_AXI_CHIPLET_OUT;
@@ -227,14 +273,14 @@ nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
.tdata_m1_m_tlx_fwd_ib_flow(tdata_m1_m_tlx_fwd_ib_flow),
// Axi Stream slave (tdata in) rev flow from SRAM chiplet PL
- .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
- .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(tready_pl_rev_m1_m_tlx_m_flow),
- .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(tdata_pl_rev_m1_m_tlx_m_flow),
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_flow(TLX_IN_flow_rev_0.tdata),
// Axi stream slave (tdata in) rev data from SRAM chiplet PL
- .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(tvalid_pl_rev_m1_m_tlx_m_stream),
- .tready_m1_m_tlx_pl_rev_to_dl_rev_data(tready_pl_rev_m1_m_tlx_m_stream),
- .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(tdata_pl_rev_m1_m_tlx_m_stream),
+ .tvalid_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tvalid),
+ .tready_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tready),
+ .tdata_m1_m_tlx_pl_rev_to_dl_rev_data(TLX_IN_data_rev_0.tdata),
.clk_sclk(clk_in),
.clk_sresetn(aresetn),
@@ -244,9 +290,9 @@ nic400_slave_pwr_M1_m_tlx_tlx_sram_chiplet u_slave_pwd_M1_m_tlx(
nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
// axi sream master (tdata out)
- .tvalid_pl_fwd_m1_m_tlx_m_stream(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tready_pl_fwd_m1_m_tlx_m_stream(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tdata_pl_fwd_m1_m_tlx_m_stream(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data),
+ .tvalid_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tready),
+ .tdata_pl_fwd_m1_m_tlx_m_stream(TLX_IN_data_fwd_0.tdata),
// axi stream slave (tdata in)
.tvalid_pl_fwd_m1_m_tlx_s_stream(tvalid_m1_m_tlx_fwd_ib_axi_stream),
@@ -254,9 +300,9 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
.tdata_pl_fwd_m1_m_tlx_s_stream(tdata_m1_m_tlx_fwd_ib_axi_stream),
// axi stream master (tdata out)
- .tvalid_pl_fwd_m1_m_tlx_m_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tready_pl_fwd_m1_m_tlx_m_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tdata_pl_fwd_m1_m_tlx_m_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
+ .tvalid_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tvalid),
+ .tready_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tready),
+ .tdata_pl_fwd_m1_m_tlx_m_flow(TLX_IN_flow_fwd_0.tdata),
// axi stream slave (tdata in)
.tvalid_pl_fwd_m1_m_tlx_s_flow(tvalid_m1_m_tlx_fwd_ib_flow),
@@ -267,7 +313,123 @@ nic400_cd_pl_fwd_M1_m_tlx_tlx_sram_chiplet u_pl_fwd_M1_m_tlx_m(
.pl_fwd_M1_m_tlxresetn(aresetn)
);
-top_sram_chiplet u_top_sram_chiplet(
+top_sram_chiplet u_top_sram_chiplet_0(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_IN_data_rev_0),
+ .TLX_IN_flow_rev(TLX_IN_flow_rev_0),
+ .TLX_IN_flow_fwd(TLX_IN_flow_fwd_0),
+ .TLX_IN_data_fwd(TLX_IN_data_fwd_0),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_1),
+ .TLX_OUT_flow_rev(TLX_flow_rev_1),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_1),
+ .TLX_OUT_data_fwd(TLX_data_fwd_1),
+
+ // Address select
+ .addr_sel(3'h0)
+);
+
+top_sram_chiplet u_top_sram_chiplet_1(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_1),
+ .TLX_IN_flow_rev(TLX_flow_rev_1),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_1),
+ .TLX_IN_data_fwd(TLX_data_fwd_1),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_2),
+ .TLX_OUT_flow_rev(TLX_flow_rev_2),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_2),
+ .TLX_OUT_data_fwd(TLX_data_fwd_2),
+
+ // Address select
+ .addr_sel(3'h1)
+);
+
+top_sram_chiplet u_top_sram_chiplet_2(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_2),
+ .TLX_IN_flow_rev(TLX_flow_rev_2),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_2),
+ .TLX_IN_data_fwd(TLX_data_fwd_2),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_3),
+ .TLX_OUT_flow_rev(TLX_flow_rev_3),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_3),
+ .TLX_OUT_data_fwd(TLX_data_fwd_3),
+
+ // Address select
+ .addr_sel(3'h2)
+);
+
+
+top_sram_chiplet u_top_sram_chiplet_3(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_3),
+ .TLX_IN_flow_rev(TLX_flow_rev_3),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_3),
+ .TLX_IN_data_fwd(TLX_data_fwd_3),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_4),
+ .TLX_OUT_flow_rev(TLX_flow_rev_4),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_4),
+ .TLX_OUT_data_fwd(TLX_data_fwd_4),
+
+ // Address select
+ .addr_sel(3'h3)
+);
+
+top_sram_chiplet u_top_sram_chiplet_4(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_4),
+ .TLX_IN_flow_rev(TLX_flow_rev_4),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_4),
+ .TLX_IN_data_fwd(TLX_data_fwd_4),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_5),
+ .TLX_OUT_flow_rev(TLX_flow_rev_5),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_5),
+ .TLX_OUT_data_fwd(TLX_data_fwd_5),
+
+ // Address select
+ .addr_sel(3'h4)
+);
+
+top_sram_chiplet u_top_sram_chiplet_5(
.SYS_CLK(clk_in),
.DL_FWD_CLK(clk_in),
.DL_REV_CLK(DL_REV_CLK),
@@ -275,25 +437,65 @@ top_sram_chiplet u_top_sram_chiplet(
.aRESETn(aresetn),
.DL_FWD_RESETn(aresetn),
- // Axi stream master (tdata out) from PL
- .tvalid_pl_rev_m1_m_tlx_m_stream(tvalid_pl_rev_m1_m_tlx_m_stream),
- .tready_pl_rev_m1_m_tlx_m_stream(tready_pl_rev_m1_m_tlx_m_stream),
- .tdata_pl_rev_m1_m_tlx_m_stream(tdata_pl_rev_m1_m_tlx_m_stream),
-
- // Axi Stream master (tdata out) from PL
- .tvalid_pl_rev_m1_m_tlx_m_flow(tvalid_pl_rev_m1_m_tlx_m_flow),
- .tready_pl_rev_m1_m_tlx_m_flow(tready_pl_rev_m1_m_tlx_m_flow),
- .tdata_pl_rev_m1_m_tlx_m_flow(tdata_pl_rev_m1_m_tlx_m_flow),
-
- // Axi Stream Slave (tdata in) to DL
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tready_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_flow),
-
- // Axi Stream slave (tdata in) to DL
- .tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data(tvalid_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tready_m1_m_tlx_pl_fwd_to_dl_fwd_data(tready_m1_m_tlx_pl_fwd_to_dl_fwd_data),
- .tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data(tdata_m1_m_tlx_pl_fwd_to_dl_fwd_data)
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_5),
+ .TLX_IN_flow_rev(TLX_flow_rev_5),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_5),
+ .TLX_IN_data_fwd(TLX_data_fwd_5),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_6),
+ .TLX_OUT_flow_rev(TLX_flow_rev_6),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_6),
+ .TLX_OUT_data_fwd(TLX_data_fwd_6),
+
+ // Address select
+ .addr_sel(3'h5)
+);
+
+top_sram_chiplet u_top_sram_chiplet_6(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_6),
+ .TLX_IN_flow_rev(TLX_flow_rev_6),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_6),
+ .TLX_IN_data_fwd(TLX_data_fwd_6),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_7),
+ .TLX_OUT_flow_rev(TLX_flow_rev_7),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_7),
+ .TLX_OUT_data_fwd(TLX_data_fwd_7),
+
+ // Address select
+ .addr_sel(3'h6)
+);
+
+top_sram_chiplet u_top_sram_chiplet_7(
+ .SYS_CLK(clk_in),
+ .DL_FWD_CLK(clk_in),
+ .DL_REV_CLK(DL_REV_CLK),
+
+ .aRESETn(aresetn),
+ .DL_FWD_RESETn(aresetn),
+
+ // Thin Links In
+ .TLX_IN_data_rev(TLX_data_rev_7),
+ .TLX_IN_flow_rev(TLX_flow_rev_7),
+ .TLX_IN_flow_fwd(TLX_flow_fwd_7),
+ .TLX_IN_data_fwd(TLX_data_fwd_7),
+ // Thin Links Out
+ .TLX_OUT_data_rev(TLX_data_rev_8),
+ .TLX_OUT_flow_rev(TLX_flow_rev_8),
+ .TLX_OUT_flow_fwd(TLX_flow_fwd_8),
+ .TLX_OUT_data_fwd(TLX_data_fwd_8),
+
+ // Address select
+ .addr_sel(3'h7)
);
endmodule
\ No newline at end of file
diff --git a/verif/cocotb/sram_chiplet_tests.py b/verif/cocotb/sram_chiplet_tests.py
index 3b108f617ff84bbacff6c841070835a1dcc4a890..429d9464d1cb9dd2ccc7a86049d16b5c4d63d4ad 100644
--- a/verif/cocotb/sram_chiplet_tests.py
+++ b/verif/cocotb/sram_chiplet_tests.py
@@ -68,7 +68,7 @@ async def init_sram(dut, tb, base_addr, size=0x8000):
async def SRAM_test_write(dut, tb, base_addr, byte_lanes, size):
for length in list(range(1, byte_lanes*2))+[8192]:
- for offset in list(range(byte_lanes))+list(range(8192-byte_lanes, 8192)):
+ for offset in list(range(byte_lanes))+list(range(0x1EE000-byte_lanes, 0x1EE000)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset + base_addr
test_data = bytearray([x % 256 for x in range(length)])
@@ -95,3 +95,41 @@ async def SRAM_TEST(dut,idle_inserter=None, backpressure_inserter=None, size=Non
await init_sram(dut, tb, 0x00000000)
await init_sram(dut, tb, 0x1F0000 - 0x8000, size=0x8000)
await SRAM_test_write(dut, tb, 0x0, byte_lanes, size)
+
+@cocotb.test()
+async def SRAM_TEST_MULTI_CHIPLET(dut,idle_inserter=None, backpressure_inserter=None, size=None):
+ tb = TB(dut)
+ byte_lanes = tb.axi_master.write_if.byte_lanes
+ max_burst_size = tb.axi_master.write_if.max_burst_size
+
+ if size is None:
+ size = max_burst_size
+
+ await tb.cycle_reset()
+ tb.set_idle_generator(idle_inserter)
+ tb.set_backpressure_generator(backpressure_inserter)
+
+ N=13824
+ data = bytearray([x % 256 for x in range(N)])
+
+ addresses = [0x000000, 0x200000, 0x400000, 0x600000, 0x800000, 0xA00000, 0xC00000, 0xE00000]
+ BW_write = []
+ BW_read = []
+
+ for addr in addresses:
+ start_time = cocotb.utils.get_sim_time()
+ await tb.axi_master.write(addr, data, size=size)
+ end_time = cocotb.utils.get_sim_time()
+ BW_write.append(1e3*N*8/(end_time-start_time))
+
+ start_time = cocotb.utils.get_sim_time()
+ d_read = await tb.axi_master.read(addr,N)
+ end_time = cocotb.utils.get_sim_time()
+ BW_read.append(1e3*N*8/(end_time-start_time))
+
+ assert d_read.data == data
+
+ tb.log.info("Chiplet number \t Bandwidth write (Gbps) \t Bandwidth read (Gbps)")
+
+ for x in range(len(addresses)):
+ tb.log.info("%d \t\t %f \t\t\t %f",x, BW_write[x], BW_read[x])