From ce9edaa78fac0d09ad9466e4bc159e999483fd12 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 12:27:19 +0100
Subject: [PATCH] Changed Incdir syntax
---
bin/filelist_compile.py | 6 +++---
bin/htmlgen/v2html/v2html | 4 ++--
bin/htmlgen/v2html/v2html.1 | 4 ++--
bin/htmlgen/v2html/v2html.man.html | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/bin/filelist_compile.py b/bin/filelist_compile.py
index 0aa21c4..5f2d5fd 100755
--- a/bin/filelist_compile.py
+++ b/bin/filelist_compile.py
@@ -72,11 +72,11 @@ def read_list(filelist):
if file.endswith(verilog_extensions):
compiled_filelist.append(env_var_substitute(line_list[1])+"/"+str(file))
- elif line_list[0].startswith("+incdir+"):
+ elif line_list[0].startswith("-incdir "):
# Append to filelist
- for file in os.listdir(env_var_substitute(line_list[0].lstrip("+incdir+"))):
+ for file in os.listdir(env_var_substitute(line_list[0].lstrip("-incdir "))):
if file.endswith(verilog_extensions):
- compiled_filelist.append(env_var_substitute(line_list[0].lstrip("+incdir+"))+"/"+str(file))
+ compiled_filelist.append(env_var_substitute(line_list[0].lstrip("-incdir "))+"/"+str(file))
# If file list a verilog file
elif line_list[0].endswith(verilog_extensions):
diff --git a/bin/htmlgen/v2html/v2html b/bin/htmlgen/v2html/v2html
index 6e0f8c7..da1872e 100755
--- a/bin/htmlgen/v2html/v2html
+++ b/bin/htmlgen/v2html/v2html
@@ -547,7 +547,7 @@ Verilog like options:
+define: Specify a define for use when processing, can be either:
+define+NAME or +define+NAME=VALUE
- +incdir: Specify a directory to search for includes +incdir+DIR_NAME
+ +incdir: Specify a directory to search for includes -incdir DIR_NAME
-y : Specify a library to search for modules eg: -y DIR_NAME
+libext: Specify a the extension for libraries eg: +libext+.v or +libext+.v+.V
-v : Specify a library file (same as putting the file without -v)
@@ -599,7 +599,7 @@ Ignored options:
example:
v2html -hc "Our Chip" -o /users/www/p/html -m Joe_Blogs\@jb.com
- +incdir+/p/includes -y /p/verilog +libext+.v+.V /p/verilog/chip_top.v
+ -incdir /p/includes -y /p/verilog +libext+.v+.V /p/verilog/chip_top.v
See http://www.burbleland.com/v2html/v2html.html for more details
diff --git a/bin/htmlgen/v2html/v2html.1 b/bin/htmlgen/v2html/v2html.1
index ea1b360..d3423a8 100644
--- a/bin/htmlgen/v2html/v2html.1
+++ b/bin/htmlgen/v2html/v2html.1
@@ -199,8 +199,8 @@ Pre-define a value. This is just the same as putting:
at the top of each of your input files. The rather strange syntax is the
same as VerilogXL's. This option is useful for controlling which ifdefs appear
true to \fBv2html\fR.
-.IP "\fB+incdir+DIR\fR" 5
-.IX Item "+incdir+DIR"
+.IP "\fB-incdir DIR\fR" 5
+.IX Item "-incdir DIR"
Specify a directory to search for include files (just like VerilogXL).
.IP "\fB\-y\fR\ \s-1DIR\s0" 5
.IX Item "-yDIR"
diff --git a/bin/htmlgen/v2html/v2html.man.html b/bin/htmlgen/v2html/v2html.man.html
index f50978a..1a943c7 100644
--- a/bin/htmlgen/v2html/v2html.man.html
+++ b/bin/htmlgen/v2html/v2html.man.html
@@ -95,7 +95,7 @@ it is doing.</p>
same as VerilogXL's. This option is useful for controlling which ifdefs appear
true to <strong>v2html</strong>.</p>
</dd>
-<dt><strong><a name="item__2bincdir_2bdir"><strong>+incdir+DIR</strong></a></strong></dt>
+<dt><strong><a name="item__2bincdir_2bdir"><strong>-incdir DIR</strong></a></strong></dt>
<dd>
<p>Specify a directory to search for include files (just like VerilogXL).</p>
--
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