//-----------------------------------------------------------------------------
// SoCDebug Top-level FT1248-AHB Debug Controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------

module socdebug_ahb #(
    parameter PROMPT_CHAR = "]"
)(  
    // AHB-lite Master Interface
    input  wire        HCLK,
    input  wire        HRESETn,
    output wire [31:0] HADDR32_o,
    output wire [ 2:0] HBURST3_o,
    output wire        HMASTLOCK_o,
    output wire [ 3:0] HPROT4_o,
    output wire [ 2:0] HSIZE3_o,
    output wire [ 1:0] HTRANS2_o,
    output wire [31:0] HWDATA32_o,
    output wire        HWRITE_o,
    input  wire [31:0] HRDATA32_i,
    input  wire        HREADY_i,
    input  wire        HRESP_i,
    
    // APB Slave Interface
    input  wire        PCLK,     // Clock
    input  wire        PCLKG,    // Gated Clock
    input  wire        PRESETn,  // Reset

    input  wire        PSEL,     // Device select
    input  wire [11:2] PADDR,    // Address
    input  wire        PENABLE,  // Transfer control
    input  wire        PWRITE,   // Write control
    input  wire [31:0] PWDATA,   // Write data
    
    output wire [31:0] PRDATA,   // Read data
    output wire        PREADY,   // Device ready
    output wire        PSLVERR,  // Device error response
    
    // GPIO interface
    output wire [ 7:0] GPO8_o,
    input  wire [ 7:0] GPI8_i
);

    // COMIO interface
    wire [ 7:0] COMRX_TDATA_i;
    wire        COMRX_TVALID_i;
    wire        COMRX_TREADY_o;
    wire [ 7:0] COMTX_TDATA_o;
    wire        COMTX_TVALID_o;
    wire        COMTX_TREADY_i;

    // STDIO interface
    wire [ 7:0] STDRX_TDATA_i;
    wire        STDRX_TVALID_i;
    wire        STDRX_TREADY_o;
    wire [ 7:0] STDTX_TDATA_o;
    wire        STDTX_TVALID_o;
    wire        STDTX_TREADY_i;
    
    // Instantiation of USRT Device
    socdebug_apb_usrt u_apb_usrt_com (
        .PCLK              (PCLK),     // Peripheral clock
        .PCLKG             (PCLKG),    // Gated PCLK for bus
        .PRESETn           (PRESETn),  // Reset

        .PSEL              (PSEL),     // APB interface inputs
        .PADDR             (PADDR),
        .PENABLE           (PENABLE),
        .PWRITE            (PWRITE),
        .PWDATA            (PWDATA),

        .PRDATA            (PRDATA),   // APB interface outputs
        .PREADY            (PREADY),
        .PSLVERR           (PSLVERR),

        .ECOREVNUM         (4'h0),     // Engineering-change-order revision bits

        .TX_VALID_o        (stdio_rx_valid),
        .TX_DATA8_o        (stdio_rx_data8),
        .TX_READY_i        (stdio_rx_ready),

        .RX_VALID_i        (stdio_tx_valid),
        .RX_DATA8_i        (stdio_tx_data8),
        .RX_READY_o        (stdio_tx_ready),

        .TXINT             ( ),       // Transmit Interrupt
        .RXINT             ( ),       // Receive  Interrupt
        .TXOVRINT          ( ),       // Transmit Overrun Interrupt
        .RXOVRINT          ( ),       // Receive  Overrun Interrupt
        .UARTINT           ( )        // Combined Interrupt
    );

    // Instantiation of FT1248 Bus Master

    // Instantiation of ADP AHB Controller

    
endmodule