<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>soclabs.org</spirit:vendor>
<spirit:library>slip</spirit:library>
<spirit:name>extio8x4_axis_target</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>axis_rx0</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx0_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx0_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx0_tdata8</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>axis_rx1</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx1_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx1_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_rx1_tdata8</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>axis_tx0</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx0_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx0_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx0_tdata8</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>axis_tx1</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx1_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx1_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>axis_tx1_tdata8</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>resetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>resetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">axis_rx0:axis_rx1:axis_tx0:axis_tx1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">resetn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName>extio8x4_axis_target</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>42b891ef</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName>extio8x4_axis_target</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>42b891ef</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f92e9879</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>archive_project</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>archive_project_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>b0c1c61e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>resetn</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>testmode</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx0_tready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx0_tvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx0_tdata8</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx1_tready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx1_tvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_rx1_tdata8</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx0_tready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx0_tvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx0_tdata8</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx1_tready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx1_tvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>axis_tx1_tdata8</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>iodata4_i</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>iodata4_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>iodata4_e</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>iodata4_t</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ioreq1_a</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ioreq2_a</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ioack_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/extio8x4_target.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/extio8x4_sync.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/extio8x4_tfsm.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/extio8x4_axis_target.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_15edbcd4</spirit:userFileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/extio8x4_sync.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/extio8x4_tfsm.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/extio8x4_axis_target.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/extio8x4_axis_target_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>archive_project_view_fileset</spirit:name>
<spirit:file>
<spirit:name>ip_project_archive.zip</spirit:name>
<spirit:userFileType>zip</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>extio8x4_axis_target_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">extio8x4_axis_target_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/soclabsIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>extio8x4_axis_target_v1_0</xilinx:displayName>
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-10-08T16:30:59Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.df@247831ce_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@3e3d1f50_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@3c1d5142_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@7af2b751_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@6d2b230e_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@6fcfda9d_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@384b91c2_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@779d5616_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2788228d_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@44a80b53_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@6bb013c9_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@4ec3d82_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@48dc1b5f_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@3f9bd21a_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@5b916f18_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@5e60f731_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@737a2f6c_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2be947d1_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@3d3abef3_ARCHIVE_LOCATION">/home/dwf1m12/work/extio_merge/main/accelerator-project/nanosoc_tech/fpga/pynq_z2_xio/pynq_z2_xio.tmp/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@f992813_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@2bbbb719_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@531b8297_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@380be242_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@5a97ffa7_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.df@6c94eefd_ARCHIVE_LOCATION">/home/dwf1m12/work/tmp/accelerator-project/nanosoc_tech/nanosoc/socdebug_tech/socket/vivado_packages/extio8x4_axis_target_1.0/extio8x4_axis_target_v1_0_project/tmp_edit_project/tmp_edit_project.srcs/sources_1/imports/vivado_packages</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="574beea2"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="df8a00f1"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="d4879326"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="06f7268c"/>
<xilinx:targetDRCs>
<xilinx:targetDRC xilinx:tool="ipi">
<xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="false"/>
</xilinx:targetDRC>
</xilinx:targetDRCs>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>