From ee1f184e8a7df3e6e461b7a331e88d0fe9be58cd Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Thu, 22 Jun 2023 09:26:43 +0100 Subject: [PATCH] Added SoCDebug Controller IP Filelist --- flist/socdebug_controller_ip.flist | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 flist/socdebug_controller_ip.flist diff --git a/flist/socdebug_controller_ip.flist b/flist/socdebug_controller_ip.flist new file mode 100644 index 0000000..6c86da0 --- /dev/null +++ b/flist/socdebug_controller_ip.flist @@ -0,0 +1,23 @@ +//----------------------------------------------------------------------------- +// SoCDebug Controller IP Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Bus Matrix IP +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= SoCDebug IP search path ============= + +$(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_adp_control.v +$(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_ahb.v +$(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_ft1248_control.v +$(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_usrt_control.v \ No newline at end of file -- GitLab