From ec5a60835a6ed8b44c084f701411914eeda75a4e Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 22 Jun 2023 09:14:11 +0100
Subject: [PATCH] Fixed io stream instantiation wiring and changed clock
dividing to a parameter
---
controller/verilog/socdebug_ahb.v | 8 ++++++--
socket/verilog/axi_stream_io_v1_0.v | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/controller/verilog/socdebug_ahb.v b/controller/verilog/socdebug_ahb.v
index 32b880d..cb071de 100644
--- a/controller/verilog/socdebug_ahb.v
+++ b/controller/verilog/socdebug_ahb.v
@@ -12,7 +12,8 @@
module socdebug_ahb #(
parameter PROMPT_CHAR = "]",
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_CLKON = 1 // FTDI clock always on - else quiet when no access
+ parameter integer FT1248_CLKON = 1, // FTDI clock always on - else quiet when no access
+ parameter [7:0] FT1248_CLKDIV = 8'd03 // Clock Division Ratio
)(
// AHB-lite Master Interface - ADP
input wire HCLK,
@@ -52,7 +53,6 @@ module socdebug_ahb #(
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
- input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
output wire [7:0] GPO8_o,
@@ -79,6 +79,10 @@ module socdebug_ahb #(
wire [ 7:0] ADP_USRT_TDATA;
wire ADP_USRT_TREADY;
+ // Clock Divsion Ratio
+ wire [7:0] FT_CLKDIV;
+ assign FT_CLKDIV = FT1248_CLKDIV;
+
// Instantiation of USRT Controller
socdebug_usrt_control u_usrt_control (
// APB Clock and Reset Signals
diff --git a/socket/verilog/axi_stream_io_v1_0.v b/socket/verilog/axi_stream_io_v1_0.v
index 0c52be8..f017669 100755
--- a/socket/verilog/axi_stream_io_v1_0.v
+++ b/socket/verilog/axi_stream_io_v1_0.v
@@ -81,7 +81,7 @@
.rx_tdata(rx_tdata),
// input wire [0 : 0] tx_tstrb,
// input wire tx_tlast,
- .tx_tready(rx_tready),
+ .rx_tready(rx_tready),
.interrupt(interrupt),
.S_AXI_AWADDR(axi_awaddr),
.S_AXI_AWPROT(axi_awprot),
--
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