diff --git a/controller/verilog/socdebug_adp_control.v b/controller/verilog/socdebug_adp_control.v
index 46991aa43e5831a1a9f5002b7f3123bc295d8635..ca27b5b85fcd03b44fa24e162c2555ae2e3daecd 100755
--- a/controller/verilog/socdebug_adp_control.v
+++ b/controller/verilog/socdebug_adp_control.v
@@ -67,7 +67,7 @@ wire STD_RXE_i = !STDRX_TVALID_i;
localparam BANNERHEX = 32'h50c1ab04;
`endif
-localparam CMD_bad = 4'b0000;
+//localparam CMD_NUL = 4'b0000;
localparam CMD_A = 4'b0001; // set Address
localparam CMD_C = 4'b0010; // Control
localparam CMD_R = 4'b0011; // Read word, addr++
@@ -116,7 +116,7 @@ case (char8[7:0])
"v": FNvalid_cmd = CMD_V;
`endif
default:
- FNvalid_cmd = 0;
+ FNvalid_cmd = 4'b0000;
endcase
endfunction
@@ -125,10 +125,10 @@ input [7:0] char8;
FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09));
endfunction
-function FNnull; // space or tab char
-input [7:0] char8;
- FNnull = (char8[7:0] == 8'h00);
-endfunction
+//function FNnull; // space or tab char
+//input [7:0] char8;
+// FNnull = (char8[7:0] == 8'h00);
+//endfunction
function FNexit; // EOF
input [7:0] char8;
@@ -140,11 +140,6 @@ input [7:0] char8;
FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d));
endfunction
-function FNuppercase;
-input [7:0] char8;
- FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8);
-endfunction
-
function [2:0] FNsize_inc;
// top 2 bits encode 01 (byte), 10 (halfword), 11 (word) 00 - no parameter
@@ -175,10 +170,10 @@ function [34:0] FNBuild_size3_param32_hexdigit;
input [34:0] param32;
input [7:0] char8;
case (char8[7:0])
-"\t":FNBuild_size3_param32_hexdigit = 35'b0; // tab starts new (zeroed) param32
-" ": FNBuild_size3_param32_hexdigit = 35'b0; // space starts new (zeroed) param32
-"x": FNBuild_size3_param32_hexdigit = 35'b0; // hex prefix starts new (zeroed) param32
-"X": FNBuild_size3_param32_hexdigit = 35'b0; // hex prefix starts new (zeroed) param32
+"\t":FNBuild_size3_param32_hexdigit = {35{1'b0}}; // tab starts new (zeroed) param32
+" ": FNBuild_size3_param32_hexdigit = {35{1'b0}}; // space starts new (zeroed) param32
+"x": FNBuild_size3_param32_hexdigit = {35{1'b0}}; // hex prefix starts new (zeroed) param32
+"X": FNBuild_size3_param32_hexdigit = {35{1'b0}}; // hex prefix starts new (zeroed) param32
"0": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0000};
"1": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0001};
"2": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0010};
@@ -209,23 +204,23 @@ endfunction
function [7:0] FNmap_hex_digit;
input [3:0] nibble;
case (nibble[3:0])
-4'b0000: FNmap_hex_digit = "0";
-4'b0001: FNmap_hex_digit = "1";
-4'b0010: FNmap_hex_digit = "2";
-4'b0011: FNmap_hex_digit = "3";
-4'b0100: FNmap_hex_digit = "4";
-4'b0101: FNmap_hex_digit = "5";
-4'b0110: FNmap_hex_digit = "6";
-4'b0111: FNmap_hex_digit = "7";
-4'b1000: FNmap_hex_digit = "8";
-4'b1001: FNmap_hex_digit = "9";
-4'b1010: FNmap_hex_digit = "a";
-4'b1011: FNmap_hex_digit = "b";
-4'b1100: FNmap_hex_digit = "c";
-4'b1101: FNmap_hex_digit = "d";
-4'b1110: FNmap_hex_digit = "e";
-4'b1111: FNmap_hex_digit = "f";
-default: FNmap_hex_digit = "0";
+4'b0000: FNmap_hex_digit = "0" & 8'hff;
+4'b0001: FNmap_hex_digit = "1" & 8'hff;
+4'b0010: FNmap_hex_digit = "2" & 8'hff;
+4'b0011: FNmap_hex_digit = "3" & 8'hff;
+4'b0100: FNmap_hex_digit = "4" & 8'hff;
+4'b0101: FNmap_hex_digit = "5" & 8'hff;
+4'b0110: FNmap_hex_digit = "6" & 8'hff;
+4'b0111: FNmap_hex_digit = "7" & 8'hff;
+4'b1000: FNmap_hex_digit = "8" & 8'hff;
+4'b1001: FNmap_hex_digit = "9" & 8'hff;
+4'b1010: FNmap_hex_digit = "a" & 8'hff;
+4'b1011: FNmap_hex_digit = "b" & 8'hff;
+4'b1100: FNmap_hex_digit = "c" & 8'hff;
+4'b1101: FNmap_hex_digit = "d" & 8'hff;
+4'b1110: FNmap_hex_digit = "e" & 8'hff;
+4'b1111: FNmap_hex_digit = "f" & 8'hff;
+//default: FNmap_hex_digit = "0" & 8'hff;
endcase
endfunction
@@ -339,12 +334,11 @@ reg adp_bus_req ;
reg adp_bus_write ;
reg adp_bus_err ;
reg [7:0] adp_cmd ;
-reg [7:0] adp_cmdwid ;
reg [34:0] adp_param ;
reg [31:0] adp_addr ;
reg [1:0] adp_size ;
reg adp_addr_inc;
-reg [31:0] adp_sys ;
+reg [ 7:0] adp_sys ;
assign GPO8_o = adp_sys[7:0];
@@ -371,10 +365,12 @@ wire ahb_aphase = adp_bus_req & !ahb_dphase;
wire adp_bus_ack = ahb_dphase & HREADY_i;
// control pipe
always @(posedge HCLK or negedge HRESETn)
+begin
if(!HRESETn)
- ahb_dphase <= 0;
+ begin ahb_dphase <= 1'b0; end
else if (HREADY_i)
- ahb_dphase <= (ahb_aphase);
+ begin ahb_dphase <= (ahb_aphase); end
+end
wire [1:0] byteaddr;
@@ -396,17 +392,10 @@ assign HWRITE_o = adp_bus_write;
`ifndef ADPBASIC
reg [34:0] adp_val;
reg [31:0] adp_mask;
-reg [31:0] adp_poll;
reg [31:0] adp_count;
reg adp_count_dec ;
-wire adp_delay_done;
-wire poll2_loop_next;
`endif
-// ADP_control flags in the 'C' control field
-wire adp_disable;
-wire adp_stdin_wait;
-
// commnon interface handshake terms
wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o;
wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i;
@@ -416,132 +405,132 @@ wire adp_bus_done = (adp_bus_req & adp_bus_ack);
// common task to set up for next state
task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner)
-// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end
- begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
-endtask
-task ADP_PROMPT_next; // prepare prompt TX
- begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end
+ begin com_tx_req <= 1'b1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
endtask
task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion
- begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end
+ begin adp_bus_req <= 1'b1; adp_bus_write <= 1'b1; adp_addr_inc <= 1'b1; end
endtask
task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion
- begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end
+ begin adp_bus_req <= 1'b1; adp_bus_write <= 1'b0; adp_addr_inc <= 1'b1; end
endtask
task ADP_hexdigit_next; // output nibble
input [3:0] nibble;
- begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
+ begin com_tx_req <= 1'b1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
endtask
task ADP_txchar_next; // output char
input [7:0] octet;
- begin com_tx_req<= 1; com_tx_byte <= octet; end
+ begin com_tx_req <= 1'b1; com_tx_byte <= octet; end
endtask
-task com_rx_nxt; com_rx_ack <=1; endtask
-
function FNcount_down_zero_next; // param about to be zero
input [31:0] counter;
- FNcount_down_zero_next = !(|counter[31:1]);
+ FNcount_down_zero_next = (counter[31:0] >> 1) == 32'h00000000;
endfunction
always @(posedge HCLK or negedge HRESETn)
+begin
if(!HRESETn) begin
adp_state <= ADP_WRITEHEX ;
- adp_bus_data <= BANNERHEX;
- banner <= 1; // start-up HEX message
- com_tx_req <= 0; // default no TX req
- com_rx_ack <= 0; // default no RX ack
- std_tx_req <= 0; // default no TX req
- std_rx_ack <= 0; // default no RX ack
- adp_bus_req <= 0; // default no bus transaction
- adp_bus_err <= 0; // default no bus error
- adp_cmd <= 0;
- adp_param <= 0;
- adp_size <= 2'b10; // default to 32-bit word size
- adp_addr <= 0;
- adp_addr_inc <= 0;
- adp_bus_write<= 0;
+ adp_bus_data <= {32{1'b0}};
+ banner <= 1'b1; // start-up HEX message
+ com_tx_req <= 1'b0; // default no TX req
+ com_rx_ack <= 1'b0; // default no RX ack
+ std_tx_req <= 1'b0; // default no TX req
+ std_rx_ack <= 1'b0; // default no RX ack
+ com_tx_byte <= 8'h00;
+ std_tx_byte <= 8'h00;
+ adp_bus_req <= 1'b0; // default no bus transaction
+ adp_bus_err <= 1'b0; // default no bus error
+ adp_cmd <= {8{1'b0}};
+ adp_param <= {35{1'b0}};
+ adp_size <= 2'b00; // default to 32-bit word size
+ adp_addr <= {32{1'b0}};
+ adp_addr_inc <= 1'b0;
+ adp_bus_write<= 1'b0;
`ifndef ADPBASIC
- adp_count <= 0;
- adp_count_dec<= 0;
- adp_val <= 0;
- adp_mask <= 0;
- adp_sys <= 0;
+ adp_count <= {32{1'b0}};
+ adp_count_dec<= 1'b0;
+ adp_val <= {35{1'b0}};
+ adp_mask <= {32{1'b0}};
+ adp_sys <= {8{1'b0}};
`endif
end else begin // default states
+ if (banner) begin adp_bus_data <= BANNERHEX; adp_size <= 2'b10; end
adp_state <= adp_state; // default to hold current state
- com_tx_req <= 0; // default no TX req
- com_rx_ack <= 0; // default no RX ack
- std_tx_req <= 0; // default no TX req
- std_rx_ack <= 0; // default no RX ack
- adp_bus_req <= 0; // default no bus transaction
- adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + (1 << adp_size) : adp_addr; // address++
- adp_addr_inc <= 0;
+ com_tx_req <= 1'b0; // default no TX req
+ com_rx_ack <= 1'b0; // default no RX ack
+ std_tx_req <= 1'b0; // default no TX req
+ std_rx_ack <= 1'b0; // default no RX ack
+ adp_bus_req <= 1'b0; // default no bus transaction
+ adp_addr <= (adp_addr_inc && adp_bus_done) ? adp_addr + (1 << adp_size) : adp_addr; // address++
+ adp_addr_inc <= 1'b0;
`ifndef ADPBASIC
- adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param--
- adp_count_dec<= 0;
+ adp_count <= (adp_count_dec && adp_bus_done && (adp_count[31:0] != 32'h00000000)) ? (adp_count - 32'h00000001) : adp_count; // param--
+ adp_count_dec<= 1'b0;
`endif
case (adp_state)
// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>>
STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
- if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN
-// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
- else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending
+ if (com_rx_req) begin com_rx_ack <= 1'b1; adp_state <= STD_RXD1; end // input char pending for STDIN
+// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1'b1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
+ else if (std_rx_req) begin std_rx_ack <= 1'b1; adp_state <= STD_TXD1; end // STDOUT char pending
STD_TXD1: // get STD out char
if (std_rx_done)
- begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end
- else std_rx_ack <= 1; // extend
+ begin com_tx_byte <= std_rx_byte; com_tx_req <= 1'b1; adp_state <= STD_TXD2; end
+ else begin std_rx_ack <= 1'b1; end // extend
STD_TXD2: // output char to ADP channel
if (com_tx_done) begin adp_state <= STD_IOCHK; end
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
STD_RXD1: // read rx char and check for ADP entry else STDIN **
if (com_rx_done) begin
if (FNvalid_adp_entry(com_rx_byte))
begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt
else if (std_tx_ack)
- begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end
- else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked
- end else com_rx_ack <= 1; // extend
+ begin std_tx_byte <= com_rx_byte; std_tx_req <= 1'b1; adp_state <= STD_RXD2; end
+ else begin adp_state <= STD_IOCHK; end // otherwise discard STDIN char and process OP data if blocked
+ end else begin com_rx_ack <= 1'b1; end // extend
STD_RXD2: // get STD in char
if (std_tx_done) begin adp_state <= STD_IOCHK; end
- else std_tx_req <= 1; // extend
+ else begin std_tx_req <= 1'b1; end // extend
// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>>
ADP_PROMPT: // transition after reset deassertion
if (com_tx_done) begin adp_state <= ADP_IOCHK; end
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
- if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
- else if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+ if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1'b1; adp_state <= ADP_STDOUT; end
+ else if (com_rx_req) begin com_rx_ack <= 1'b1; adp_state <= ADP_RXCMD; end
// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>>
ADP_STDOUT: // output "<"
- if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end
- else com_tx_req <= 1; // extend stream request if not ready
+ if (com_tx_done) begin std_rx_ack <= 1'b1; adp_state <= ADP_STDOUT1; end
+ else begin com_tx_req <= 1'b1; end // extend stream request if not ready
ADP_STDOUT1: // get STD out char
- if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end
- else std_rx_ack <= 1; // else extend
+ if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1'b1; adp_state <= ADP_STDOUT2; end
+ else begin std_rx_ack <= 1'b1; end // else extend
ADP_STDOUT2: // output char
- if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end
- else com_tx_req <= 1; // else extend
+ if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1'b1; adp_state <= ADP_STDOUT3; end
+ else begin com_tx_req <= 1'b1; end // else extend
ADP_STDOUT3: // output ">"
- if (com_tx_done) begin if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end else adp_state <= ADP_IOCHK; end
- else com_tx_req <= 1; // else extend
+ if (com_tx_done) begin
+ if (com_rx_req) begin com_rx_ack <= 1'b1; adp_state <= ADP_RXCMD; end else begin adp_state <= ADP_IOCHK; end
+ end
+ else begin com_tx_req <= 1'b1; end // else extend
// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>>
ADP_RXCMD: // read and save ADP command
if (com_rx_done) begin
- if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit
- else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command
+ if (FNexit(com_rx_byte)) begin adp_state <= STD_IOCHK; end // immediate exit
+ else if (FNvalid_space(com_rx_byte)) begin com_rx_ack <= 1'b1; end // retry for a command
else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_LINEACK; end // no command, skip param
- else begin adp_cmd <= com_rx_byte; adp_param <= 35'h0_00000000; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter
+ else begin adp_cmd <= com_rx_byte; adp_param <= 35'h0_00000000; com_rx_ack <= 1'b1; adp_state <= ADP_RXPARAM; end // get optional parameter
end
- else com_rx_ack <= 1; // extend stream request if not ready
+ else begin com_rx_ack <= 1'b1; end // extend stream request if not ready
ADP_RXPARAM: // read and build hex parameter
if (com_rx_done) begin // RX byte
- if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit
+ if (FNexit(com_rx_byte)) begin adp_state <= STD_IOCHK; end // exit
else if (FNvalid_EOL(com_rx_byte))
`ifndef ADPBASIC
begin adp_count <= adp_param[31:0]; adp_state <= ADP_ACTION;
@@ -551,24 +540,24 @@ always @(posedge HCLK or negedge HRESETn)
adp_size <= FNparam2size(adp_param[34:33]); end // parameter complete on EOL
`endif
else
- begin adp_param <= FNBuild_size3_param32_hexdigit(adp_param[34:0], com_rx_byte); com_rx_ack <= 1; end // build parameter
+ begin adp_param <= FNBuild_size3_param32_hexdigit(adp_param[34:0], com_rx_byte); com_rx_ack <= 1'b1; end // build parameter
end
- else com_rx_ack <= 1;
+ else begin com_rx_ack <= 1'b1; end
ADP_ACTION: // parse command and action with parameter
if (FNexit(com_rx_byte))
- adp_state <= STD_IOCHK;
+ begin adp_state <= STD_IOCHK; end
else if (FNvalid_cmd(adp_cmd) == CMD_A)
- begin if (|adp_param[34:32]) adp_addr <= adp_param[31:0]; else adp_param <= {3'b111, adp_addr} ;
+ begin if (|adp_param[34:32]) begin adp_addr <= adp_param[31:0]; end else begin adp_param <= {3'b111, adp_addr}; end
adp_state <= ADP_ECHOCMD; end
else if (FNvalid_cmd(adp_cmd) == CMD_C) begin
if (|adp_param[34:32] == 1'b0) // report GPO
begin adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 1) // clear selected bits in GPO
+ else if (adp_param[31:8] == 24'h000001) // clear selected bits in GPO
begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 2) // set selected bits in GPO
+ else if (adp_param[31:8] == 24'h000002) // set selected bits in GPO
begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 3) // overwrite bits in GPO
+ else if (adp_param[31:8] == 24'h000003) // overwrite bits in GPO
begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end
else // 4 etc, report GPO
begin adp_state <= ADP_SYSCTL; end
@@ -584,21 +573,26 @@ always @(posedge HCLK or negedge HRESETn)
else if (FNvalid_cmd(adp_cmd) == CMD_W)
begin adp_size <= FNparam2size(adp_param[34:33]); adp_bus_data <= adp_param[31:0]; ADP_BUSWRITEINC_next; adp_state <= ADP_WRITE; end
else if (FNvalid_cmd(adp_cmd) == CMD_X)
- begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end
+ begin com_tx_byte <= 8'h0a; com_tx_req <= 1'b1; adp_state <= ADP_EXIT; end
`ifndef ADPBASIC
- else if (FNvalid_cmd(adp_cmd) == CMD_U)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_UCTRL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_U) begin
+ if (FNcount_down_zero_next(adp_param[31:0])) begin adp_state <= ADP_ECHOCMD; end else begin adp_state <= ADP_UCTRL; end// non-zero count
+ end
else if (FNvalid_cmd(adp_cmd) == CMD_M)
- begin if (|adp_param[34:32]) adp_mask <= adp_param[31:0]; else adp_param <= {3'b111,adp_mask};
+ begin if (|adp_param[34:32]) begin adp_mask <= adp_param[31:0]; end else begin adp_param <= {3'b111,adp_mask}; end
adp_state <= ADP_ECHOCMD; end
else if (FNvalid_cmd(adp_cmd) == CMD_P)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL0; // non-zero count
+ begin
+ if (FNcount_down_zero_next(adp_param[31:0])) begin adp_state <= ADP_ECHOCMD; end else begin adp_state <= ADP_POLL0; end// non-zero count
+ end
else if (FNvalid_cmd(adp_cmd) == CMD_V)
begin if (|adp_param[34:32]) begin adp_size <= FNparam2size(adp_param[34:33]); adp_val <= adp_param[34:0]; end
- else adp_param <= adp_val;
+ else begin adp_param <= adp_val; end
adp_state <= ADP_ECHOCMD; end
else if (FNvalid_cmd(adp_cmd) == CMD_F)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_FCTRL; // non-zero count
+ begin
+ if (FNcount_down_zero_next(adp_param[31:0])) begin adp_state <= ADP_ECHOCMD; end else begin adp_state <= ADP_FCTRL; end // non-zero count
+ end
`endif
else
begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald
@@ -627,54 +621,55 @@ always @(posedge HCLK or negedge HRESETn)
// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>>
ADP_UCTRL: // set control value
- begin com_rx_ack <= 1; adp_size <= 2'b00; adp_state <= ADP_UREADB; end // read next byte
+ begin com_rx_ack <= 1'b1; adp_size <= 2'b00; adp_state <= ADP_UREADB; end // read next byte
ADP_UREADB: // read raw binary byte
if (com_rx_done)
- begin adp_bus_data[31:0] <= {4{com_rx_byte}}; ADP_BUSWRITEINC_next; adp_count_dec <= 1; adp_state <= ADP_UWRITE; end
- else com_rx_ack <= 1; // extend stream request if not ready
+ begin adp_bus_data[31:0] <= {4{com_rx_byte}}; ADP_BUSWRITEINC_next; adp_count_dec <= 1'b1; adp_state <= ADP_UWRITE; end
+ else begin com_rx_ack <= 1'b1; end // extend stream request if not ready
ADP_UWRITE: // Write word to Addr++
if (adp_bus_done) begin // auto address++, count--
- if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_UREADB; adp_bus_err <= adp_bus_err | HRESP_i; end
- end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1; end // extend request
+ if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; end else begin adp_state <= ADP_UREADB; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1'b1; end // extend request
// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>>
ADP_POLL0: // set poll value
- begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end
+ begin adp_bus_req <= 1'b1; adp_bus_write <= 1'b0; adp_state <= ADP_POLL1; end
ADP_POLL1: // wait for read data, no addr++
- if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; adp_bus_err <= adp_bus_err | HRESP_i; end
- else begin adp_bus_req <= 1; adp_count_dec <=1; end
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <= 1'b1; adp_state <= ADP_POLL2; adp_bus_err <= adp_bus_err | HRESP_i; end
+ else begin adp_bus_req <= 1'b1; adp_count_dec <= 1'b1; end
ADP_POLL2:
if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= 1'b1; end // timeout
- else if (((adp_bus_data & adp_mask) ^ adp_val[31:0]) == 0) begin adp_state <= ADP_ECHOCMD; adp_param <= {1'b0, (adp_param[31:0] - adp_count)}; end // exact match
- else adp_state <= ADP_POLL0;
+ else if (((adp_bus_data & adp_mask) ^ adp_val[31:0]) == 0)
+ begin adp_state <= ADP_ECHOCMD; adp_param[34:32] <= 3'b000; adp_param[31:0] <= (adp_param[31:0] - adp_count); end // exact match
+ else begin adp_state <= ADP_POLL0; end
// >>>>>>>>>>>>>>>> ADP (ZERO) FILL MEMORY >>>>>>>>>>>>>>>>>>>>>>
ADP_FCTRL: // set control value
- begin adp_size <= FNparam2size(adp_val[34:33]); adp_bus_data <= adp_val[31:0]; ADP_BUSWRITEINC_next; adp_count_dec <= 1; adp_state <= ADP_FWRITE; end
+ begin adp_size <= FNparam2size(adp_val[34:33]); adp_bus_data <= adp_val[31:0]; ADP_BUSWRITEINC_next; adp_count_dec <= 1'b1; adp_state <= ADP_FWRITE; end
ADP_FWRITE: // Write word to Addr++
if (adp_bus_done) begin // auto address++, count--
- if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_FCTRL; adp_bus_err <= adp_bus_err | HRESP_i; end
- end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1; end // extend request
+ if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; end else begin adp_state <= ADP_FCTRL; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1'b1; end // extend request
`endif
// >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>>
ADP_UNKNOWN: // output "?"
if (com_tx_done) begin ADP_LINEACK_next; end
- else com_tx_req <= 1; // extend stream request if not ready
+ else begin com_tx_req <= 1'b1; end // extend stream request if not ready
ADP_EXIT: // exit ADP mode
- if (com_tx_done) adp_state <= STD_IOCHK;
- else com_tx_req <= 1; // extend stream request if not ready
+ if (com_tx_done) begin adp_state <= STD_IOCHK; end
+ else begin com_tx_req <= 1'b1; end // extend stream request if not ready
ADP_SYSCHK: // check STDIN fifo
begin // no upper flags so STDIN char
- if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
+ if (std_tx_ack) begin std_tx_req <= 1'b1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
else begin adp_bus_err <= 1'b1; adp_state <= ADP_ECHOCMD; end // signal error then echo comand
end
ADP_STDIN: // push char into STDIN
- if (std_tx_done) begin adp_bus_data <= {24'b0,adp_param[7:0]}; ADP_txchar_next("S"); adp_state <= ADP_ECHOBUS; end
- else std_tx_req <= 1; // extend
+ if (std_tx_done) begin adp_bus_data <= {{24{1'b0}},adp_param[7:0]}; ADP_txchar_next("S"); adp_state <= ADP_ECHOBUS; end
+ else begin std_tx_req <= 1'b1; end // extend
ADP_SYSCTL: // read current status - and report in hex
begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); adp_state <= ADP_ECHOBUS; end
@@ -683,66 +678,69 @@ always @(posedge HCLK or negedge HRESETn)
begin ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param[31:0]; adp_state <= ADP_ECHOBUS; end // output command char
ADP_ECHOBUS: // output command space and (bus) data
if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX: // output hex word with prefix
begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
ADP_WRITEHEXS:
if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX9:
- if (com_tx_done & adp_size[1]) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix
- else if (com_tx_done & adp_size[0]) begin adp_state <= ADP_WRITEHEX4; ADP_txchar_next("x"); end // output "x" hex prefix
- else if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_txchar_next("x"); end // output "x" hex prefix
- else com_tx_req <= 1; // extend
+ if (com_tx_done) begin
+ ADP_txchar_next("x"); // output "x" hex prefix
+ adp_state <= (adp_size[1]) ? ADP_WRITEHEX8
+ : (adp_size[0]) ? ADP_WRITEHEX4
+ : ADP_WRITEHEX2;
+ end else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX8:
if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX7: // output hex nibble 7
if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX6: // output hex nibble 6
if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX5: // output hex nibble 5
if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX4: // output hex nibble 4
if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX3: // output hex nibble 3
if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX2: // output hex nibble 2
if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX1: // output hex nibble 1
if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0
- else com_tx_req <= 1; // extend
+ else begin com_tx_req <= 1'b1; end // extend
ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack
if (com_tx_done) begin
adp_bus_err <= 1'b0; // clear sticky bus error flag
if (banner) begin ADP_LINEACK_next; end
- else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
- end else com_tx_req <= 1; // extend
+ else begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // newline and prompt
+ end else begin com_tx_req <= 1'b1; end // extend
ADP_LINEACK: // write EOLN
if (com_tx_done) begin
begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end
- end else com_tx_req <= 1; // extend
+ end else begin com_tx_req <= 1'b1; end // extend
ADP_LINEACK2: // CR
if (com_tx_done) begin
- if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end
+ if (banner) begin banner <= 1'b0; adp_state <= STD_IOCHK; end
`ifndef ADPBASIC
- else if ((FNvalid_cmd(adp_cmd) == CMD_R) & |adp_count) //// non-zero count
+ else if ((FNvalid_cmd(adp_cmd) == CMD_R) && (adp_count != 32'h00000000)) //// non-zero count
begin ADP_BUSREADINC_next; adp_count_dec <= 1'b1; adp_state <= ADP_READ; end //
`endif
else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end
- end else com_tx_req <= 1; // extend
+ end else begin com_tx_req <= 1'b1; end // extend
default:
begin ADP_txchar_next("#"); adp_state <= ADP_UNKNOWN; end // default error
endcase
end
+end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/controller/verilog/socdebug_ft1248_control.v b/controller/verilog/socdebug_ft1248_control.v
index 69bd9753d28f6832a3682e72628ec8223581957f..14fc26a75ca941cf26aa353b8041626dec5d5a8d 100755
--- a/controller/verilog/socdebug_ft1248_control.v
+++ b/controller/verilog/socdebug_ft1248_control.v
@@ -110,13 +110,13 @@ module socdebug_ft1248_control #(
generate
if (FT1248_WIDTH == 1) begin
- assign ft_rdmasked[7:1] = 7'b1111111;
+ assign ft_rdmasked[7:1] = {7{1'b1}};
end
endgenerate
assign ft_rdmasked[0] = ft_miosio_i[0];
assign ft_miosio_o[0] = ft_reg[0];
- assign ft_miosio_e[0] = ft_state[1];
+ assign ft_miosio_e[0] = ft_state[1];
assign ft_miosio_z[0] = ~ft_state[1];
assign ft_clk_o = ft_state[0];
@@ -139,12 +139,12 @@ module socdebug_ft1248_control #(
always @(posedge clk or negedge resetn )
begin
if (!resetn) begin
- ft_clkcnt_r <= 0;
- ft_clken <= 0;
+ ft_clkcnt_r <= 8'h00;
+ ft_clken <= 1'b0;
end
else begin
ft_clken <= (ft_clkcnt_r == ft_clkdiv);
- ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 0 : (ft_clkcnt_r +1);
+ ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 8'h00 : ((ft_clkcnt_r + 8'h01) & 8'hff);
end
end
@@ -161,10 +161,10 @@ module socdebug_ft1248_control #(
always @(posedge clk or negedge resetn )
begin
if (!resetn) begin
- ft_miso_i_sync_1 <= 1;
- ft_miosio_i0_sync_1 <= 1;
- ft_miso_i_sync <= 1;
- ft_miosio_i0_sync <= 1;
+ ft_miso_i_sync_1 <= 1'b1;
+ ft_miosio_i0_sync_1 <= 1'b1;
+ ft_miso_i_sync <= 1'b1;
+ ft_miosio_i0_sync <= 1'b1;
end
else begin
ft_miso_i_sync_1 <= ft_miso_i;
@@ -213,35 +213,49 @@ module socdebug_ft1248_control #(
reg ssn_del;
always @(posedge clk or negedge resetn)
- if (!resetn)
+ begin
+ if (!resetn) begin
ssn_del <= 1'b1;
- else if (ft_clken)
+ end
+ else if (ft_clken) begin
ssn_del <= ft_ssn_o;
+ end
+ end
wire ssn_start = ft_ssn_o & ssn_del;
// FTDI1248 state machine
always @(posedge clk or negedge resetn)
+ begin
if (!resetn) begin
ft_state <= FT_0_IDLE;
- ft_reg <= 0;
- txdata <= 0;
- rxdone <= 0;
- ft_wcyc <= 0;
- ft_txf <= 1; // ftdi channel TXE# ('1' full)
- ft_rxe <= 1; // ftdi channel RXF# ('1' empty)
- ft_nak <= 0;
+ ft_reg <= {9{1'b0}};
+ txdata <= {9{1'b0}};
+ rxdone <= 1'b0;
+ ft_wcyc <= 1'b0;
+ ft_txf <= 1'b1; // ftdi channel TXE# ('1' full)
+ ft_rxe <= 1'b1; // ftdi channel RXF# ('1' empty)
+ ft_nak <= 1'b0;
end else begin
ft_txf <= (ft_state==FT_0_IDLE) ? (ft_miosio_i[0] | ft_miosio_i0_sync) : 1'b1; //ft_txf & !( ft_wcyc &(ft_state==FT_ZBT_CLKHI) & ft_miso_i);
ft_rxe <= (ft_state==FT_0_IDLE) ? (ft_miso_i | ft_miso_i_sync) : 1'b1; //ft_rxe & !(!ft_wcyc & (ft_state==FT_ZBT_CLKHI) & ft_miso_i);
txdata[8] <= txdata[8] & !txd_tready; // tx_valid handshake
rxdone <= (ft_clken & (ft_state==FT_ZWD_CLKLO) & !ft_nak) | (rxdone & !rxd_tvalid); // hold until acknowledged
- if (ft_clken)
+ if (ft_clken) begin
case (ft_state)
FT_0_IDLE: begin // RX req priority
- if (ssn_start & ft_rxreq) begin ft_reg <= rcmdpatt; ft_state <= FT_ZCMD_CLKLO; end
- else if (ssn_start & ft_txreq) begin ft_reg <= wcmdpatt; ft_state <= FT_ZCMD_CLKLO; ft_wcyc <= 1; end
- else ft_state <= (!ft_txf | !ft_rxe | (FT1248_CLKON!=0)) ? FT_1_IDLE : FT_0_IDLE;
+ if (ssn_start && ft_rxreq) begin
+ ft_reg <= rcmdpatt;
+ ft_state <= FT_ZCMD_CLKLO;
+ end
+ else if (ssn_start && ft_txreq) begin
+ ft_reg <= wcmdpatt;
+ ft_state <= FT_ZCMD_CLKLO;
+ ft_wcyc <= 1'b1;
+ end
+ else begin
+ ft_state <= (!ft_txf || !ft_rxe || (FT1248_CLKON != 0)) ? FT_1_IDLE : FT_0_IDLE;
+ end
end
FT_1_IDLE:
ft_state <= FT_0_IDLE;
@@ -250,42 +264,115 @@ module socdebug_ft1248_control #(
FT_CMD_CLKHI:
ft_state <= FT_CMD_CLKLO;
FT_CMD_CLKLO: // 2, 4 or 7 shifts
- if (bwid8) begin ft_reg <= FT_ZBT_CLKHI; end
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
+ if (bwid8) begin
+ ft_state <= FT_ZBT_CLKHI;
+ end
+ else if (bwid4) begin
+ ft_reg <= {4'b0000,ft_reg[8:4]};
+ ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
+ else if (bwid2) begin
+ ft_reg <= { 2'b00,ft_reg[8:2]};
+ ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
+ else begin
+ ft_reg <= { 1'b0,ft_reg[8:1]};
+ ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
FT_ZBT_CLKHI:
ft_state <= FT_ZBT_CLKLO;
FT_ZBT_CLKLO:
- if (ft_wcyc) begin ft_reg <= {1'b1,rxd_tdata}; ft_state <= FT_WD_CLKHI; end
- else begin ft_reg <= 9'b011111111; ft_state <= FT_RD_CLKHI; end
+ if (ft_wcyc) begin
+ ft_reg <= {1'b1,rxd_tdata};
+ ft_state <= FT_WD_CLKHI;
+ end
+ else begin
+ ft_reg <= 9'b011111111;
+ ft_state <= FT_RD_CLKHI;
+ end
FT_WD_CLKHI:
- if (ft_miso_i & ft_reg[8]) begin ft_nak <= 1'b1; ft_state <= FT_ZWD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
- else if (bwid4) ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else if (bwid2) ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ if (ft_miso_i && ft_reg[8]) begin
+ ft_nak <= 1'b1;
+ ft_state <= FT_ZWD_CLKLO;
+ end // NAK terminate on first cycle
+ else if (bwid8) begin
+ ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
+ end
+ else if (bwid4) begin
+ ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
+ else if (bwid2) begin
+ ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
+ else begin
+ ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
FT_WD_CLKLO:
- if (bwid8) begin ft_reg <= { 1'b0,ft_reg[7:0]}; ft_state <= FT_WD_CLKHI; end // clear top flag
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= FT_WD_CLKHI; end // shift 4 bits right
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= FT_WD_CLKHI; end // shift 2 bits right
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= FT_WD_CLKHI; end // shift 1 bit right
+ if (bwid8) begin
+ ft_reg <= { 1'b0,ft_reg[7:0]};
+ ft_state <= FT_WD_CLKHI;
+ end // clear top flag
+ else if (bwid4) begin
+ ft_reg <= {4'b0000,ft_reg[8:4]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 4 bits right
+ else if (bwid2) begin
+ ft_reg <= { 2'b00,ft_reg[8:2]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 2 bits right
+ else begin
+ ft_reg <= { 1'b0,ft_reg[8:1]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 1 bit right
FT_ZWD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end // terminate without TX handshake
- else begin ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end
+ if (ft_nak) begin
+ ft_nak<= 1'b0;
+ ft_state <= FT_0_IDLE;
+ ft_wcyc <= 1'b0;
+ end // terminate without TX handshake
+ else begin
+ ft_state <= FT_0_IDLE;
+ ft_wcyc <= 1'b0;
+ end
FT_RD_CLKHI: // capture iodata pins end of CLKHI phase
- if (ft_miso_i & (&ft_reg[7:0])) begin ft_nak <= 1'b1; ft_state <= FT_RD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) begin ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0}; ft_state <= FT_RD_CLKLO; end // 8-bit read twice
- else if (bwid4) begin ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]}; ft_state <= FT_RD_CLKLO; end
- else if (bwid2) begin ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]}; ft_state <= FT_RD_CLKLO; end
- else begin ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]}; ft_state <= FT_RD_CLKLO; end
+ if (ft_miso_i && (&ft_reg[7:0])) begin
+ ft_nak <= 1'b1;
+ ft_state <= FT_RD_CLKLO;
+ end // NAK terminate on first cycle
+ else if (bwid8) begin
+ ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0};
+ ft_state <= FT_RD_CLKLO;
+ end // 8-bit read twice
+ else if (bwid4) begin
+ ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]};
+ ft_state <= FT_RD_CLKLO;
+ end
+ else if (bwid2) begin
+ ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]};
+ ft_state <= FT_RD_CLKLO;
+ end
+ else begin
+ ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]};
+ ft_state <= FT_RD_CLKLO;
+ end
FT_RD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; txdata <= 9'b0; end // terminate without TX handshake
- else if (ft_reg[0]) begin ft_state <= FT_RD_CLKHI; ft_reg[0] <= !(bwid8); end // loop until all 8 bits shifted in (or 8-bit read repeated)
- else begin ft_state <= FT_0_IDLE; txdata <= {1'b1,ft_reg[8:1]}; end
+ if (ft_nak) begin
+ ft_nak<= 1'b0;
+ ft_state <= FT_0_IDLE;
+ txdata <= 9'b000000000;
+ end // terminate without TX handshake
+ else if (ft_reg[0]) begin
+ ft_state <= FT_RD_CLKHI;
+ ft_reg[0] <= !(bwid8);
+ end // loop until all 8 bits shifted in (or 8-bit read repeated)
+ else begin
+ ft_state <= FT_0_IDLE;
+ txdata <= {1'b1,ft_reg[8:1]};
+ end
default:
ft_state <= FT_0_IDLE;
endcase
+ end
end
-
+ end
endmodule
diff --git a/hal/socdebug_controller_ip.waive b/hal/socdebug_controller_ip.waive
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..47c71fbc412bb056f03bb73407d888fddfbd0d4c 100644
--- a/hal/socdebug_controller_ip.waive
+++ b/hal/socdebug_controller_ip.waive
@@ -0,0 +1,52 @@
+
+lint_checking designunit = socdebug_adp_control
+{
+ // Not Top-level in design_info
+ TPOUNR off;
+
+ // waivers for some legacy FT245 stream handshake signals
+ URDWIR off;
+ INFNOT off;
+
+ // Multi-statement per line permitted for ease of maintenance
+ SEPLIN off;
+
+ // specifically support task global vaariable assignments to reuse tasks
+ TSETGV off;
+
+ // excuse FSM multiple non-blocking assigns (priority design)
+ MULNBA off;
+
+ // support async FSM registers
+ FFASRT off;
+
+ // coding allow multi-bit changes in next-state transitions
+ TRNMBT off;
+
+ // FSM coding waivers - explicitly coded, >40 states with non-standard state assignment
+ SYNASN off;
+ DNSTIF off;
+ LMTSTS off;
+ FSMIDN off;
+ BADFSM off;
+ EXTFSM off;
+
+ // Allow specific AHB controller outputs to be driven as constants
+ TIELOG off;
+
+ // clock domain crossing handled explicitly - HCLK and PCLK balanced
+ CLKDMN off;
+ FLSYNC off;
+ INSYNC off;
+
+}
+
+lint_checking designunit = socdebug_ft1248_control
+{
+ // Not Top-level in design_info
+ TPOUNR off;
+
+ // single bit bus configuration permitted
+ ONPNSG off;
+
+}
diff --git a/makefile b/makefile
index 73b6378362a81b590391f70e64fd26d28184e2b3..4efba84ff06680c305c80408a648d50b8bdff5b7 100644
--- a/makefile
+++ b/makefile
@@ -12,7 +12,7 @@
include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/socdebug
-LINT_INFO_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
+LINT_INFO_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
# Core Design Filelist
DESIGN_VC ?= $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist