From aa64ace1bb88e1c396f6bae6fb34de2af57a980f Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Mon, 10 Jul 2023 20:20:14 +0100
Subject: [PATCH] fix floating RX stream ready output
---
controller/verilog/socdebug_usrt_control.v | 3 +++
1 file changed, 3 insertions(+)
diff --git a/controller/verilog/socdebug_usrt_control.v b/controller/verilog/socdebug_usrt_control.v
index 121855c..7222fbd 100644
--- a/controller/verilog/socdebug_usrt_control.v
+++ b/controller/verilog/socdebug_usrt_control.v
@@ -547,6 +547,9 @@ assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
// --------------------------------------------
// Receive
+assign RX_READY_o = !rx_buf_full;
+
+
// Increment TickCounter
assign nxt_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) ? 5'h08 :
rx_tick_cnt + {{3{1'b0}},reg_baud_tick};
--
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