diff --git a/controller/verilog/socdebug_usrt_control.v b/controller/verilog/socdebug_usrt_control.v
index 121855cff1c493d27759947887e2ed27dbfb1f66..7222fbd5e53c54c49c71aaf66bbedf184d3d8aa2 100644
--- a/controller/verilog/socdebug_usrt_control.v
+++ b/controller/verilog/socdebug_usrt_control.v
@@ -547,6 +547,9 @@ assign  write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
 // --------------------------------------------
 // Receive
 
+assign RX_READY_o = !rx_buf_full;
+
+
   // Increment TickCounter
   assign nxt_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) ? 5'h08 :
                         rx_tick_cnt + {{3{1'b0}},reg_baud_tick};