diff --git a/fpga/makefile b/fpga/makefile
index 987f8bff4207dbe2e9aa01cd15b8d2ecd8a20be2..0e13191f667427275c89982198c3854de80ecc00 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -11,33 +11,32 @@
#-----------------------------------------------------------------------------
IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
-TEMP_RTL_SOCKET_DIR := $(IMPLEMENTATION_DIR)/socket
-
-RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_lib
+IMP_SOCKET_DIR ?= $(IMPLEMENTATION_DIR)/socket
+RTL_SOCKET_DIR ?= $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
+# Temporary Make recipies until actual package flow for components is implemented
package_adp_control:
@echo Packaging Uart To AXI Master
- @mkdir -p $(TEMP_RTL_SOCKET_DIR)
- @cp -r $(RTL_SOCKET_DIR)/ADPcontrol_1.0 $(TEMP_RTL_SOCKET_DIR)/ADPcontrol_1.0
+ @mkdir -p $(IMP_SOCKET_DIR)
+ @cp -r $(RTL_SOCKET_DIR)/ADPcontrol_1.0 $(IMP_SOCKET_DIR)/ADPcontrol_1.0
package_axi_stream_io:
@echo Packaging Uart To AXI Master
- @mkdir -p $(TEMP_RTL_SOCKET_DIR)
- @cp -r $(RTL_SOCKET_DIR)/axi_stream_io_1.0 $(TEMP_RTL_SOCKET_DIR)/axi_stream_io_1.0
+ @mkdir -p $(IMP_SOCKET_DIR)
+ @cp -r $(RTL_SOCKET_DIR)/axi_stream_io_1.0 $(IMP_SOCKET_DIR)/axi_stream_io_1.0
package_ft1248_to_stream:
@echo Packaging FT1248 to AXI Stream
- @mkdir -p $(TEMP_RTL_SOCKET_DIR)
- @cp -r $(RTL_SOCKET_DIR)/ft1248x1_to_stream8_1.0 $(TEMP_RTL_SOCKET_DIR)/ft1248x1_to_stream8_1.0
- @cp -r $(RTL_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0 $(TEMP_RTL_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0
+ @mkdir -p $(IMP_SOCKET_DIR)
+ @cp -r $(RTL_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0 $(IMP_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0
package_uart_to_axi:
@echo Packaging Uart To AXI Master
- @mkdir -p $(TEMP_RTL_SOCKET_DIR)
- @cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(TEMP_RTL_SOCKET_DIR)/uart_to_AXI_master_1.0
+ @mkdir -p $(IMP_SOCKET_DIR)
+ @cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(IMP_SOCKET_DIR)/uart_to_AXI_master_1.0
package_socket: clean_socket package_uart_to_axi package_ft1248_to_stream package_axi_stream_io package_adp_control
clean_socket:
@echo Cleaning FPGA Implementation Socket Directory
- @rm -rf $(TEMP_RTL_SOCKET_DIR)
\ No newline at end of file
+ @rm -rf $(IMP_SOCKET_DIR)
\ No newline at end of file
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/component.xml b/socket/vivado_lib/ft1248x1_to_stream8_1.0/component.xml
deleted file mode 100644
index c9d8d6e573fef4d3a7f1d643e634a02f82032d93..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/component.xml
+++ /dev/null
@@ -1,127 +0,0 @@
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- <spirit:file>
- <spirit:name>src/ft1248x1_to_stream8.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
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- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:taxonomies>
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diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix b/socket/vivado_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix
deleted file mode 100644
index 1b2410ad1ecde98574e898028f41ad55c1c8f3b1..0000000000000000000000000000000000000000
Binary files a/socket/vivado_lib/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix and /dev/null differ
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v b/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
deleted file mode 100644
index 822ab4cd47a344ec599d082d80384686bdb6360d..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
+++ /dev/null
@@ -1,75 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module ft1248x1_to_stream8_v1_0 #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
-
- // Parameters of Axi Slave Bus Interface RXD8
- parameter integer C_RXD8_TDATA_WIDTH = 32,
-
- // Parameters of Axi Master Bus Interface TXD8
- parameter integer C_TXD8_TDATA_WIDTH = 32,
- parameter integer C_TXD8_START_COUNT = 32
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
-
- // Ports of Axi Slave Bus Interface RXD8
- input wire rxd8_aclk,
- input wire rxd8_aresetn,
- output wire rxd8_tready,
- input wire [C_RXD8_TDATA_WIDTH-1 : 0] rxd8_tdata,
- input wire [(C_RXD8_TDATA_WIDTH/8)-1 : 0] rxd8_tstrb,
- input wire rxd8_tlast,
- input wire rxd8_tvalid,
-
- // Ports of Axi Master Bus Interface TXD8
- input wire txd8_aclk,
- input wire txd8_aresetn,
- output wire txd8_tvalid,
- output wire [C_TXD8_TDATA_WIDTH-1 : 0] txd8_tdata,
- output wire [(C_TXD8_TDATA_WIDTH/8)-1 : 0] txd8_tstrb,
- output wire txd8_tlast,
- input wire txd8_tready
- );
-// Instantiation of Axi Bus Interface RXD8
- ft1248x1_to_stream8_v1_0_RXD8 # (
- .C_S_AXIS_TDATA_WIDTH(C_RXD8_TDATA_WIDTH)
- ) ft1248x1_to_stream8_v1_0_RXD8_inst (
- .S_AXIS_ACLK(rxd8_aclk),
- .S_AXIS_ARESETN(rxd8_aresetn),
- .S_AXIS_TREADY(rxd8_tready),
- .S_AXIS_TDATA(rxd8_tdata),
- .S_AXIS_TSTRB(rxd8_tstrb),
- .S_AXIS_TLAST(rxd8_tlast),
- .S_AXIS_TVALID(rxd8_tvalid)
- );
-
-// Instantiation of Axi Bus Interface TXD8
- ft1248x1_to_stream8_v1_0_TXD8 # (
- .C_M_AXIS_TDATA_WIDTH(C_TXD8_TDATA_WIDTH),
- .C_M_START_COUNT(C_TXD8_START_COUNT)
- ) ft1248x1_to_stream8_v1_0_TXD8_inst (
- .M_AXIS_ACLK(txd8_aclk),
- .M_AXIS_ARESETN(txd8_aresetn),
- .M_AXIS_TVALID(txd8_tvalid),
- .M_AXIS_TDATA(txd8_tdata),
- .M_AXIS_TSTRB(txd8_tstrb),
- .M_AXIS_TLAST(txd8_tlast),
- .M_AXIS_TREADY(txd8_tready)
- );
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v b/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
deleted file mode 100644
index 9b39ac62c1aa1246d5b566160b5bd7b5dd1d07ad..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
+++ /dev/null
@@ -1,167 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module ft1248x1_to_stream8_v1_0_RXD8 #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- // AXI4Stream sink: Data Width
- parameter integer C_S_AXIS_TDATA_WIDTH = 32
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // AXI4Stream sink: Clock
- input wire S_AXIS_ACLK,
- // AXI4Stream sink: Reset
- input wire S_AXIS_ARESETN,
- // Ready to accept data in
- output wire S_AXIS_TREADY,
- // Data in
- input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
- // Byte qualifier
- input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
- // Indicates boundary of last packet
- input wire S_AXIS_TLAST,
- // Data is in valid
- input wire S_AXIS_TVALID
- );
- // function called clogb2 that returns an integer which has the
- // value of the ceiling of the log base 2.
- function integer clogb2 (input integer bit_depth);
- begin
- for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
- bit_depth = bit_depth >> 1;
- end
- endfunction
-
- // Total number of input data.
- localparam NUMBER_OF_INPUT_WORDS = 8;
- // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
- localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
- // Define the states of state machine
- // The control state machine oversees the writing of input streaming data to the FIFO,
- // and outputs the streaming data from the FIFO
- parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
-
- WRITE_FIFO = 1'b1; // In this state FIFO is written with the
- // input stream data S_AXIS_TDATA
- wire axis_tready;
- // State variable
- reg mst_exec_state;
- // FIFO implementation signals
- genvar byte_index;
- // FIFO write enable
- wire fifo_wren;
- // FIFO full flag
- reg fifo_full_flag;
- // FIFO write pointer
- reg [bit_num-1:0] write_pointer;
- // sink has accepted all the streaming data and stored in FIFO
- reg writes_done;
- // I/O Connections assignments
-
- assign S_AXIS_TREADY = axis_tready;
- // Control state machine implementation
- always @(posedge S_AXIS_ACLK)
- begin
- if (!S_AXIS_ARESETN)
- // Synchronous reset (active low)
- begin
- mst_exec_state <= IDLE;
- end
- else
- case (mst_exec_state)
- IDLE:
- // The sink starts accepting tdata when
- // there tvalid is asserted to mark the
- // presence of valid streaming data
- if (S_AXIS_TVALID)
- begin
- mst_exec_state <= WRITE_FIFO;
- end
- else
- begin
- mst_exec_state <= IDLE;
- end
- WRITE_FIFO:
- // When the sink has accepted all the streaming input data,
- // the interface swiches functionality to a streaming master
- if (writes_done)
- begin
- mst_exec_state <= IDLE;
- end
- else
- begin
- // The sink accepts and stores tdata
- // into FIFO
- mst_exec_state <= WRITE_FIFO;
- end
-
- endcase
- end
- // AXI Streaming Sink
- //
- // The example design sink is always ready to accept the S_AXIS_TDATA until
- // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
- assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
-
- always@(posedge S_AXIS_ACLK)
- begin
- if(!S_AXIS_ARESETN)
- begin
- write_pointer <= 0;
- writes_done <= 1'b0;
- end
- else
- if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
- begin
- if (fifo_wren)
- begin
- // write pointer is incremented after every write to the FIFO
- // when FIFO write signal is enabled.
- write_pointer <= write_pointer + 1;
- writes_done <= 1'b0;
- end
- if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
- begin
- // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
- // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
- writes_done <= 1'b1;
- end
- end
- end
-
- // FIFO write enable generation
- assign fifo_wren = S_AXIS_TVALID && axis_tready;
-
- // FIFO Implementation
- generate
- for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
- begin:FIFO_GEN
-
- reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
-
- // Streaming input data is stored in FIFO
-
- always @( posedge S_AXIS_ACLK )
- begin
- if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
- begin
- stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
- end
- end
- end
- endgenerate
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v b/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
deleted file mode 100644
index 3abf9f8a3c52a9a6716e09c985c2a15faa383be5..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
+++ /dev/null
@@ -1,228 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module ft1248x1_to_stream8_v1_0_TXD8 #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
- parameter integer C_M_AXIS_TDATA_WIDTH = 32,
- // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
- parameter integer C_M_START_COUNT = 32
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // Global ports
- input wire M_AXIS_ACLK,
- //
- input wire M_AXIS_ARESETN,
- // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
- output wire M_AXIS_TVALID,
- // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
- output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
- // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
- output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
- // TLAST indicates the boundary of a packet.
- output wire M_AXIS_TLAST,
- // TREADY indicates that the slave can accept a transfer in the current cycle.
- input wire M_AXIS_TREADY
- );
- // Total number of output data
- localparam NUMBER_OF_OUTPUT_WORDS = 8;
-
- // function called clogb2 that returns an integer which has the
- // value of the ceiling of the log base 2.
- function integer clogb2 (input integer bit_depth);
- begin
- for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
- bit_depth = bit_depth >> 1;
- end
- endfunction
-
- // WAIT_COUNT_BITS is the width of the wait counter.
- localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
-
- // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
- localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
-
- // Define the states of state machine
- // The control state machine oversees the writing of input streaming data to the FIFO,
- // and outputs the streaming data from the FIFO
- parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
-
- INIT_COUNTER = 2'b01, // This state initializes the counter, once
- // the counter reaches C_M_START_COUNT count,
- // the state machine changes state to SEND_STREAM
- SEND_STREAM = 2'b10; // In this state the
- // stream data is output through M_AXIS_TDATA
- // State variable
- reg [1:0] mst_exec_state;
- // Example design FIFO read pointer
- reg [bit_num-1:0] read_pointer;
-
- // AXI Stream internal signals
- //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
- reg [WAIT_COUNT_BITS-1 : 0] count;
- //streaming data valid
- wire axis_tvalid;
- //streaming data valid delayed by one clock cycle
- reg axis_tvalid_delay;
- //Last of the streaming data
- wire axis_tlast;
- //Last of the streaming data delayed by one clock cycle
- reg axis_tlast_delay;
- //FIFO implementation signals
- reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
- wire tx_en;
- //The master has issued all the streaming data stored in FIFO
- reg tx_done;
-
-
- // I/O Connections assignments
-
- assign M_AXIS_TVALID = axis_tvalid_delay;
- assign M_AXIS_TDATA = stream_data_out;
- assign M_AXIS_TLAST = axis_tlast_delay;
- assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
-
-
- // Control state machine implementation
- always @(posedge M_AXIS_ACLK)
- begin
- if (!M_AXIS_ARESETN)
- // Synchronous reset (active low)
- begin
- mst_exec_state <= IDLE;
- count <= 0;
- end
- else
- case (mst_exec_state)
- IDLE:
- // The slave starts accepting tdata when
- // there tvalid is asserted to mark the
- // presence of valid streaming data
- //if ( count == 0 )
- // begin
- mst_exec_state <= INIT_COUNTER;
- // end
- //else
- // begin
- // mst_exec_state <= IDLE;
- // end
-
- INIT_COUNTER:
- // The slave starts accepting tdata when
- // there tvalid is asserted to mark the
- // presence of valid streaming data
- if ( count == C_M_START_COUNT - 1 )
- begin
- mst_exec_state <= SEND_STREAM;
- end
- else
- begin
- count <= count + 1;
- mst_exec_state <= INIT_COUNTER;
- end
-
- SEND_STREAM:
- // The example design streaming master functionality starts
- // when the master drives output tdata from the FIFO and the slave
- // has finished storing the S_AXIS_TDATA
- if (tx_done)
- begin
- mst_exec_state <= IDLE;
- end
- else
- begin
- mst_exec_state <= SEND_STREAM;
- end
- endcase
- end
-
-
- //tvalid generation
- //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
- //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
- assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
-
- // AXI tlast generation
- // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
- // (0 to NUMBER_OF_OUTPUT_WORDS-1)
- assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
-
-
- // Delay the axis_tvalid and axis_tlast signal by one clock cycle
- // to match the latency of M_AXIS_TDATA
- always @(posedge M_AXIS_ACLK)
- begin
- if (!M_AXIS_ARESETN)
- begin
- axis_tvalid_delay <= 1'b0;
- axis_tlast_delay <= 1'b0;
- end
- else
- begin
- axis_tvalid_delay <= axis_tvalid;
- axis_tlast_delay <= axis_tlast;
- end
- end
-
-
- //read_pointer pointer
-
- always@(posedge M_AXIS_ACLK)
- begin
- if(!M_AXIS_ARESETN)
- begin
- read_pointer <= 0;
- tx_done <= 1'b0;
- end
- else
- if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
- begin
- if (tx_en)
- // read pointer is incremented after every read from the FIFO
- // when FIFO read signal is enabled.
- begin
- read_pointer <= read_pointer + 1;
- tx_done <= 1'b0;
- end
- end
- else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
- begin
- // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
- // has been out.
- tx_done <= 1'b1;
- end
- end
-
-
- //FIFO read enable generation
-
- assign tx_en = M_AXIS_TREADY && axis_tvalid;
-
- // Streaming output data is read from FIFO
- always @( posedge M_AXIS_ACLK )
- begin
- if(!M_AXIS_ARESETN)
- begin
- stream_data_out <= 1;
- end
- else if (tx_en)// && M_AXIS_TSTRB[byte_index]
- begin
- stream_data_out <= read_pointer + 32'b1;
- end
- end
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/ip_project_archive.zip b/socket/vivado_lib/ft1248x1_to_stream8_1.0/ip_project_archive.zip
deleted file mode 100755
index e67e74bbc9ca5ffffb895c6ce630825d07197fa2..0000000000000000000000000000000000000000
Binary files a/socket/vivado_lib/ft1248x1_to_stream8_1.0/ip_project_archive.zip and /dev/null differ
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip b/socket/vivado_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip
deleted file mode 100644
index bd8f20f74f0cc9c44da89578d526ab1afbd7f276..0000000000000000000000000000000000000000
Binary files a/socket/vivado_lib/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip and /dev/null differ
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v b/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
deleted file mode 100755
index 6c55abc8d956769a1ca142d910603d780445a4ca..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
+++ /dev/null
@@ -1,187 +0,0 @@
-//-----------------------------------------------------------------------------
-// FT1248 1-bit-data to 8-bit AXI-Stream IO
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
-//-----------------------------------------------------------------------------
-
-
-module ft1248x1_to_stream8
- (
- input wire ft_clk_i, // SCLK
- input wire ft_ssn_i, // SS_N
- output wire ft_miso_o, // MISO
-// inout wire ft_miosio_io, // MIOSIO tristate output control
- input wire ft_miosio_i,
- output wire ft_miosio_o,
- output wire ft_miosio_z,
-// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO
-//
-// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
-
- input wire clk, // external primary clock
- input wire resetn, // external reset (active low)
-
- // Ports of Axi stream Bus Interface TXD
- output wire txd_tvalid_o,
- output wire [7 : 0] txd_tdata8_o,
- input wire txd_tready_i,
-
- // Ports of Axi stream Bus Interface RXD
- output wire rxd_tready_o,
- input wire [7 : 0] rxd_tdata8_i,
- input wire rxd_tvalid_i
-
- );
-
-//wire ft_clk;
-wire ft_clk_rising;
-wire ft_clk_falling;
-
-wire ft_ssn;
-//wire ft_ssn_rising;
-//wire ft_ssn_falling;
-
-SYNCHRONIZER_EDGES u_xync_ft_clk (
- .testmode_i(1'b0),
- .clk_i(clk),
- .reset_n_i(resetn),
- .asyn_i(ft_clk_i),
- .syn_o(),
- .posedge_o(ft_clk_rising),
- .negedge_o(ft_clk_falling)
- );
-
-SYNCHRONIZER_EDGES u_xync_ft_ssn (
- .testmode_i(1'b0),
- .clk_i(clk),
- .reset_n_i(resetn),
- .asyn_i(ft_ssn_i),
- .syn_o(ft_ssn),
- .posedge_o( ),
- .negedge_o( )
- );
-
-//----------------------------------------------
-//-- FT1248 1-bit protocol State Machine
-//----------------------------------------------
-
-reg [4:0] ft_state; // 17-state for bit-serial
-wire [4:0] ft_nextstate = ft_state + 5'b00001;
-
-// advance state count on rising edge of ft_clk
-always @(posedge clk or negedge resetn)
- if (!resetn)
- ft_state <= 5'b11111;
- else if (ft_ssn) // sync reset
- ft_state <= 5'b11111;
- else if (ft_clk_rising) // loop if multi-data
-// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
- ft_state <= ft_nextstate;
-
-// 16: bus turnaround (or bit[5])
-// 0 for CMD3
-// 3 for CMD2
-// 5 for CMD1
-// 6 for CMD0
-// 7 for cmd turnaround
-// 8 for data bit0
-// 9 for data bit1
-// 10 for data bit2
-// 11 for data bit3
-// 12 for data bit4
-// 13 for data bit5
-// 14 for data bit6
-// 15 for data bit7
-
-// capture 7-bit CMD on falling edge of clock (mid-data)
-reg [7:0] ft_cmd;
-// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
-always @(posedge clk or negedge resetn)
- if (!resetn)
- ft_cmd <= 8'b00000001;
- else if (ft_ssn) // sync reset
- ft_cmd <= 8'b00000001;
- else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
- ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
-
-wire ft_cmd_valid = ft_cmd[7];
-wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
-wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
-
-// tristate enable for miosio (deselected status or serialized data for read command)
-wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
-assign ft_miosio_z = !ft_miosio_e;
-
-// capture (ft_cmd_txd) serial data out on falling edge of clock
-// bit [0] indicated byte valid
-reg [7:0] rxd_sr;
-always @(posedge clk or negedge resetn)
- if (!resetn)
- rxd_sr <= 8'b00000000;
- else if (ft_ssn) // sync reset
- rxd_sr <= 8'b00000000;
- else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
- rxd_sr <= {ft_miosio_i, rxd_sr[7:1]};
-
-// AXI STREAM handshake interfaces
-// TX stream delivers valid FT1248 read data transfer
-// 8-bit write port with extra top-bit used as valid qualifer
-reg [8:0] txstream;
-always @(posedge clk or negedge resetn)
- if (!resetn)
- txstream <= 9'b000000000;
- else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
- txstream[8] <= 1'b0;
- else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
- txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]};
-
-assign txd_tvalid_o = txstream[8];
-assign txd_tdata8_o = txstream[7:0];
-
-
-// AXI STREAM handshake interfaces
-// RX stream accepts 8-bit data to transfer over FT1248 channel
-// 8-bit write port with extra top-bit used as valid qualifer
-reg [8:0] rxstream;
-always @(posedge clk or negedge resetn)
- if (!resetn)
- rxstream <= 9'b000000000;
- else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
- rxstream[8:0] <= {1'b1,rxd_tdata8_i};
- else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
- rxstream[8] <= 1'b0;
-assign rxd_tready_o = !rxstream[8]; // ready until loaded
-
-// shift TXD on rising edge of clock
-reg [7:0] txd_sr;
-// rewrite for clocked
-always @(posedge clk or negedge resetn)
- if (!resetn)
- txd_sr <= 8'b00000000;
- else if (ft_ssn) // sync reset
- txd_sr <= 8'b00000000;
- else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111))
- txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000;
- else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
- txd_sr <= {1'b0,txd_sr[7:1]};
-
-
-//FT1248 FIFO status signals
-
-// ft_miso_o reflects TXF when deselected
-assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0];
-
-// ft_miso_o reflects RXE when deselected
-assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
-
-
-endmodule
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/synclib.v b/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/synclib.v
deleted file mode 100755
index 1daf61f27dffed42591278f8e46a4239a46554a2..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/src/synclib.v
+++ /dev/null
@@ -1,139 +0,0 @@
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module SYNCHRONIZER (
- input wire testmode_i
- ,input wire clk_i
- ,input wire reset_n_i
- ,input wire asyn_i
- ,output wire syn_o
- );
-
-reg sync_stage1;
-reg sync_stage2;
-
- always @(posedge clk_i or negedge reset_n_i)
- if(~reset_n_i) begin
- sync_stage1 <= 1'b0;
- sync_stage2 <= 1'b0;
- end
- else begin
- sync_stage1 <= asyn_i;
- sync_stage2 <= sync_stage1;
- end
-
-assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
-
-endmodule
-
-module SYNCHRONIZER_EDGES (
- input wire testmode_i
- ,input wire clk_i
- ,input wire reset_n_i
- ,input wire asyn_i
- ,output wire syn_o
- ,output wire posedge_o
- ,output wire negedge_o
- );
-
-reg sync_stage1;
-reg sync_stage2;
-reg sync_stage3;
-
- always @(posedge clk_i or negedge reset_n_i)
- if(~reset_n_i) begin
- sync_stage1 <= 1'b0;
- sync_stage2 <= 1'b0;
- sync_stage3 <= 1'b0;
- end
- else begin
- sync_stage1 <= asyn_i;
- sync_stage2 <= sync_stage1;
- sync_stage3 <= sync_stage2;
- end
-
-assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
-assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
-assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
-
-endmodule
-
-module SYNCHRONIZER_RST_LO (
- input wire reset_n_i
- ,input wire testmode_i
- ,input wire clk_i
- ,input wire asyn_i
- ,output wire syn_o
- );
-
-reg sync_stage1;
-reg sync_stage2;
-
- always @(posedge clk_i or negedge reset_n_i)
- if(~reset_n_i) begin
- sync_stage1 <= 1'b0;
- sync_stage2 <= 1'b0;
- end
- else begin
- sync_stage1 <= asyn_i;
- sync_stage2 <= sync_stage1;
- end
-assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
-
-endmodule
-
-module SYNCHRONIZER_RST_HI (
- input wire reset_n_i
- ,input wire testmode_i
- ,input wire clk_i
- ,input wire asyn_i
- ,output wire syn_o
- );
-
-reg sync_stage1;
-reg sync_stage2;
-
- always @(posedge clk_i or negedge reset_n_i)
- if(~reset_n_i) begin
- sync_stage1 <= 1'b1;
- sync_stage2 <= 1'b1;
- end
- else begin
- sync_stage1 <= asyn_i;
- sync_stage2 <= sync_stage1;
- end
-
-assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
-
-endmodule
-
-
-module NRST_SYNCHRONIZER_LO (
- input wire reset_n_i
- ,input wire testmode_i
- ,input wire clk_i
- ,output wire synreset_n_o
- );
-
-reg sync_stage1;
-reg sync_stage2;
-
- always @(posedge clk_i or negedge reset_n_i)
- if(~reset_n_i) begin
- sync_stage1 <= 1'b0;
- sync_stage2 <= 1'b0;
- end
- else begin
- sync_stage1 <= 1'b1;
- sync_stage2 <= sync_stage1;
- end
-
-assign synreset_n_o = (testmode_i) ? reset_n_i : sync_stage2;
-
-endmodule
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl b/socket/vivado_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
deleted file mode 100644
index 0db18e9a9d18f3e4b14481f7664b048781110ca3..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
+++ /dev/null
@@ -1,10 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
- ipgui::add_param $IPINST -name "Component_Name"
- #Adding Page
- ipgui::add_page $IPINST -name "Page 0"
-
-
-}
-
-
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/bd/bd.tcl b/socket/vivado_lib/uart_to_AXI_master_1.0/bd/bd.tcl
deleted file mode 100644
index 4804aeba807dc4c53516378f9a0796c29f028d13..0000000000000000000000000000000000000000
--- a/socket/vivado_lib/uart_to_AXI_master_1.0/bd/bd.tcl
+++ /dev/null
@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
- set full_sbusif_list [list ]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
- set busif_param_list [list]
- set busif_name [get_property NAME $busif]
- if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
- continue
- }
- foreach tparam $axi_standard_param_list {
- lappend busif_param_list "C_${busif_name}_${tparam}"
- }
- bd::mark_propagate_only $cell_handle $busif_param_list
- }
- }
-}
-
-
-proc pre_propagate {cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
- continue
- }
- if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
- continue
- }
-
- set busif_name [get_property NAME $busif]
- foreach tparam $axi_standard_param_list {
- set busif_param_name "C_${busif_name}_${tparam}"
-
- set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
- set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
-
- if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
- if { $val_on_cell != "" } {
- set_property CONFIG.${tparam} $val_on_cell $busif
- }
- }
- }
- }
-}
-
-
-proc propagate {cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
- continue
- }
- if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
- continue
- }
-
- set busif_name [get_property NAME $busif]
- foreach tparam $axi_standard_param_list {
- set busif_param_name "C_${busif_name}_${tparam}"
-
- set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
- set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
-
- if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
- #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
- if { $val_on_cell_intf_pin != "" } {
- set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
- }
- }
- }
- }
-}
-
diff --git a/socket/vivado_lib/ADPcontrol_1.0/bd/bd.tcl b/socket/vivado_packages/ADPcontrol_1.0/bd/bd.tcl
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/bd/bd.tcl
rename to socket/vivado_packages/ADPcontrol_1.0/bd/bd.tcl
diff --git a/socket/vivado_lib/ADPcontrol_1.0/component.xml b/socket/vivado_packages/ADPcontrol_1.0/component.xml
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/component.xml
rename to socket/vivado_packages/ADPcontrol_1.0/component.xml
diff --git a/socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
rename to socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
rename to socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
rename to socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
rename to socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
rename to socket/vivado_packages/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/socket/vivado_packages/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
rename to socket/vivado_packages/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
diff --git a/socket/vivado_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/socket/vivado_packages/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
rename to socket/vivado_packages/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/src/ADPmanager.v b/socket/vivado_packages/ADPcontrol_1.0/src/ADPmanager.v
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/src/ADPmanager.v
rename to socket/vivado_packages/ADPcontrol_1.0/src/ADPmanager.v
diff --git a/socket/vivado_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/socket/vivado_packages/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
similarity index 100%
rename from socket/vivado_lib/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
rename to socket/vivado_packages/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
diff --git a/socket/vivado_lib/axi_stream_io_1.0/bd/bd.tcl b/socket/vivado_packages/axi_stream_io_1.0/bd/bd.tcl
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/bd/bd.tcl
rename to socket/vivado_packages/axi_stream_io_1.0/bd/bd.tcl
diff --git a/socket/vivado_lib/axi_stream_io_1.0/component.xml b/socket/vivado_packages/axi_stream_io_1.0/component.xml
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/component.xml
rename to socket/vivado_packages/axi_stream_io_1.0/component.xml
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
diff --git a/socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c b/socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
rename to socket/vivado_packages/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
diff --git a/socket/vivado_lib/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/socket/vivado_packages/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
rename to socket/vivado_packages/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
diff --git a/socket/vivado_lib/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/socket/vivado_packages/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
rename to socket/vivado_packages/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
diff --git a/socket/vivado_lib/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl b/socket/vivado_packages/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
similarity index 100%
rename from socket/vivado_lib/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
rename to socket/vivado_packages/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/component.xml b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/component.xml
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/component.xml
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/component.xml
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
diff --git a/socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
rename to socket/vivado_packages/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
diff --git a/socket/vivado_lib/ft1248x1_to_stream8_1.0/bd/bd.tcl b/socket/vivado_packages/uart_to_AXI_master_1.0/bd/bd.tcl
similarity index 100%
rename from socket/vivado_lib/ft1248x1_to_stream8_1.0/bd/bd.tcl
rename to socket/vivado_packages/uart_to_AXI_master_1.0/bd/bd.tcl
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/component.xml b/socket/vivado_packages/uart_to_AXI_master_1.0/component.xml
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/component.xml
rename to socket/vivado_packages/uart_to_AXI_master_1.0/component.xml
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v b/socket/vivado_packages/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
rename to socket/vivado_packages/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v b/socket/vivado_packages/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
rename to socket/vivado_packages/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge.v b/socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge.v
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge.v
rename to socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge.v
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v b/socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
rename to socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v b/socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
rename to socket/vivado_packages/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
diff --git a/socket/vivado_lib/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl b/socket/vivado_packages/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
similarity index 100%
rename from socket/vivado_lib/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
rename to socket/vivado_packages/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl