From 5a418341e7a2362b375c1c323a7243ac56c6c948 Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Sat, 3 Jun 2023 21:48:45 +0100
Subject: [PATCH] Restructured Debug Controller
---
controller/verilog/nanosoc_stream_adp_io.v | 89 -------
controller/verilog/socdebug_adp_control.v | 4 +-
controller/verilog/socdebug_ahb.v | 223 ++++++++++++------
...248_stream.v => socdebug_ft1248_control.v} | 8 +-
...bug_apb_usrt.v => socdebug_usrt_control.v} | 2 +-
5 files changed, 164 insertions(+), 162 deletions(-)
delete mode 100755 controller/verilog/nanosoc_stream_adp_io.v
rename controller/verilog/{socdebug_ft1248_stream.v => socdebug_ft1248_control.v} (95%)
rename controller/verilog/{socdebug_apb_usrt.v => socdebug_usrt_control.v} (99%)
diff --git a/controller/verilog/nanosoc_stream_adp_io.v b/controller/verilog/nanosoc_stream_adp_io.v
deleted file mode 100755
index 0b27e18..0000000
--- a/controller/verilog/nanosoc_stream_adp_io.v
+++ /dev/null
@@ -1,89 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC ASCII Debug Protocol Controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021-2, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-// TODO: DM - I think this file is redundant if we move to nanosoc_manager_adp
-
-module nanosoc_stream_adp_io #(
- parameter PROMPT_CHAR = "]"
- )(
- // Ports of Axi Slave Bus Interface com_rx
- input wire ahb_hclk,
- input wire ahb_hresetn,
-
- output wire com_rx_tready,
- input wire [7:0] com_rx_tdata,
- input wire com_rx_tvalid,
-
- // Ports of Axi Master Bus Interface com_tx
- output wire com_tx_tvalid,
- output wire [7:0] com_tx_tdata,
- input wire com_tx_tready,
-
- // Ports of Axi Slave Bus Interface stdio_rx
- output wire stdio_rx_tready,
- input wire [7:0] stdio_rx_tdata,
- input wire stdio_rx_tvalid,
-
- // Ports of Axi Master Bus Interface stdio_tx
- output wire stdio_tx_tvalid,
- output wire [7:0] stdio_tx_tdata,
- input wire stdio_tx_tready,
-
- output wire [7 : 0] gpo8,
- input wire [7 : 0] gpi8,
-
- output wire [31:0] ahb_haddr,
- output wire [ 2:0] ahb_hburst,
- output wire ahb_hmastlock,
- output wire [ 3:0] ahb_hprot,
- output wire [ 2:0] ahb_hsize,
- output wire [ 1:0] ahb_htrans,
- output wire [31:0] ahb_hwdata,
- output wire ahb_hwrite,
- input wire [31:0] ahb_hrdata,
- input wire ahb_hready,
- input wire ahb_hresp
- );
-
- nanosoc_adp_control #(
- .PROMPT_CHAR (PROMPT_CHAR)
- ) u_adp_control (
- .HCLK (ahb_hclk ),
- .HRESETn (ahb_hresetn ),
- .HADDR32_o (ahb_haddr ),
- .HBURST3_o (ahb_hburst ),
- .HMASTLOCK_o (ahb_hmastlock ),
- .HPROT4_o (ahb_hprot ),
- .HSIZE3_o (ahb_hsize ),
- .HTRANS2_o (ahb_htrans ),
- .HWDATA32_o (ahb_hwdata ),
- .HWRITE_o (ahb_hwrite ),
- .HRDATA32_i (ahb_hrdata ),
- .HREADY_i (ahb_hready ),
- .HRESP_i (ahb_hresp ),
- .GPO8_o (gpo8 ),
- .GPI8_i (gpi8 ),
- .COMRX_TREADY_o(com_rx_tready),
- .COMRX_TDATA_i(com_rx_tdata),
- .COMRX_TVALID_i(com_rx_tvalid),
- .STDRX_TREADY_o(stdio_rx_tready),
- .STDRX_TDATA_i(stdio_rx_tdata),
- .STDRX_TVALID_i(stdio_rx_tvalid),
- .COMTX_TVALID_o(com_tx_tvalid),
- .COMTX_TDATA_o(com_tx_tdata),
- .COMTX_TREADY_i(com_tx_tready),
- .STDTX_TVALID_o(stdio_tx_tvalid),
- .STDTX_TDATA_o(stdio_tx_tdata),
- .STDTX_TREADY_i(stdio_tx_tready)
- );
-
-
-endmodule
diff --git a/controller/verilog/socdebug_adp_control.v b/controller/verilog/socdebug_adp_control.v
index c4b9cf6..e6282ec 100755
--- a/controller/verilog/socdebug_adp_control.v
+++ b/controller/verilog/socdebug_adp_control.v
@@ -30,9 +30,11 @@ module socdebug_adp_control #(
input wire HREADY_i,
input wire HRESP_i,
- // COMIO interface
+ // GPIO Interface
output wire [ 7:0] GPO8_o,
input wire [ 7:0] GPI8_i,
+
+ // COMIO interface
input wire [ 7:0] COMRX_TDATA_i,
input wire COMRX_TVALID_i,
output wire COMRX_TREADY_o,
diff --git a/controller/verilog/socdebug_ahb.v b/controller/verilog/socdebug_ahb.v
index edeb5ba..b361c5e 100644
--- a/controller/verilog/socdebug_ahb.v
+++ b/controller/verilog/socdebug_ahb.v
@@ -10,85 +10,105 @@
//-----------------------------------------------------------------------------
module socdebug_ahb #(
- parameter PROMPT_CHAR = "]"
+ parameter PROMPT_CHAR = "]",
+ parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_CLKON = 0 // FTDI clock always on - else quiet when no access
)(
- // AHB-lite Master Interface
- input wire HCLK,
- input wire HRESETn,
- output wire [31:0] HADDR32_o,
- output wire [ 2:0] HBURST3_o,
- output wire HMASTLOCK_o,
- output wire [ 3:0] HPROT4_o,
- output wire [ 2:0] HSIZE3_o,
- output wire [ 1:0] HTRANS2_o,
- output wire [31:0] HWDATA32_o,
- output wire HWRITE_o,
- input wire [31:0] HRDATA32_i,
- input wire HREADY_i,
- input wire HRESP_i,
+ // AHB-lite Master Interface - ADP
+ input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR32_o,
+ output wire [ 2:0] HBURST3_o,
+ output wire HMASTLOCK_o,
+ output wire [ 3:0] HPROT4_o,
+ output wire [ 2:0] HSIZE3_o,
+ output wire [ 1:0] HTRANS2_o,
+ output wire [31:0] HWDATA32_o,
+ output wire HWRITE_o,
+ input wire [31:0] HRDATA32_i,
+ input wire HREADY_i,
+ input wire HRESP_i,
- // APB Slave Interface
- input wire PCLK, // Clock
- input wire PCLKG, // Gated Clock
- input wire PRESETn, // Reset
+ // APB Slave Interface - USRT
+ input wire PCLK, // Clock
+ input wire PCLKG, // Gated Clock
+ input wire PRESETn, // Reset
- input wire PSEL, // Device select
- input wire [11:2] PADDR, // Address
- input wire PENABLE, // Transfer control
- input wire PWRITE, // Write control
- input wire [31:0] PWDATA, // Write data
+ input wire PSEL_i, // Device select
+ input wire [11:2] PADDR_i, // Address
+ input wire PENABLE_i, // Transfer control
+ input wire PWRITE_i, // Write control
+ input wire [31:0] PWDATA_i, // Write data
+
+ output wire [31:0] PRDATA_o, // Read data
+ output wire PREADY_o, // Device ready
+ output wire PSLVERR_o, // Device error response
- output wire [31:0] PRDATA, // Read data
- output wire PREADY, // Device ready
- output wire PSLVERR, // Device error response
+ // FT1248 Interace - FT1248
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
+ input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
// GPIO interface
- output wire [ 7:0] GPO8_o,
- input wire [ 7:0] GPI8_i
+ output wire [7:0] GPO8_o,
+ input wire [7:0] GPI8_i
);
- // COMIO interface
- wire [ 7:0] COMRX_TDATA_i;
- wire COMRX_TVALID_i;
- wire COMRX_TREADY_o;
- wire [ 7:0] COMTX_TDATA_o;
- wire COMTX_TVALID_o;
- wire COMTX_TREADY_i;
+ // FT1248 to ADP Bus
+ wire FT1248_ADP_TVALID;
+ wire [ 7:0] FT1248_ADP_TDATA;
+ wire FT1248_ADP_TREADY;
+
+ // ADP to FT1248 Bus
+ wire ADP_FT1248_TVALID;
+ wire [ 7:0] ADP_FT1248_TDATA;
+ wire ADP_FT1248_TREADY;
- // STDIO interface
- wire [ 7:0] STDRX_TDATA_i;
- wire STDRX_TVALID_i;
- wire STDRX_TREADY_o;
- wire [ 7:0] STDTX_TDATA_o;
- wire STDTX_TVALID_o;
- wire STDTX_TREADY_i;
+ // USRT to ADP Bus
+ wire USRT_ADP_TVALID;
+ wire [ 7:0] USRT_ADP_TDATA;
+ wire USRT_ADP_TREADY;
+
+ // ADP to USRT Bus
+ wire ADP_USRT_TVALID;
+ wire [ 7:0] ADP_USRT_TDATA;
+ wire ADP_USRT_TREADY;
- // Instantiation of USRT Device
- socdebug_apb_usrt u_apb_usrt_com (
- .PCLK (PCLK), // Peripheral clock
+ // Instantiation of USRT Controller
+ socdebug_usrt_control u_usrt_control (
+ // APB Clock and Reset Signals
+ .PCLK (PCLK),
.PCLKG (PCLKG), // Gated PCLK for bus
- .PRESETn (PRESETn), // Reset
-
- .PSEL (PSEL), // APB interface inputs
- .PADDR (PADDR),
- .PENABLE (PENABLE),
- .PWRITE (PWRITE),
- .PWDATA (PWDATA),
-
- .PRDATA (PRDATA), // APB interface outputs
- .PREADY (PREADY),
- .PSLVERR (PSLVERR),
+ .PRESETn (PRESETn),
+
+ // APB Interface Signals
+ .PSEL (PSEL_i),
+ .PADDR (PADDR_i),
+ .PENABLE (PENABLE_i),
+ .PWRITE (PWRITE_i),
+ .PWDATA (PWDATA_i),
+ .PRDATA (PRDATA_o),
+ .PREADY (PREADY_o),
+ .PSLVERR (PSLVERR_o),
- .ECOREVNUM (4'h0), // Engineering-change-order revision bits
-
- .TX_VALID_o (stdio_rx_valid),
- .TX_DATA8_o (stdio_rx_data8),
- .TX_READY_i (stdio_rx_ready),
-
- .RX_VALID_i (stdio_tx_valid),
- .RX_DATA8_i (stdio_tx_data8),
- .RX_READY_o (stdio_tx_ready),
+ .ECOREVNUM (4'h0),
+
+ // ADP Interface - From USRT to ADP
+ .TX_VALID_o (USRT_ADP_TVALID),
+ .TX_DATA8_o (USRT_ADP_TDATA),
+ .TX_READY_i (USRT_ADP_TREADY),
+ // ADP Interface - From ADP to USRT
+ .RX_VALID_i (ADP_USRT_TVALID),
+ .RX_DATA8_i (ADP_USRT_TDATA),
+ .RX_READY_o (ADP_USRT_TREADY),
+
+ // Interrupt Interfaces
.TXINT ( ), // Transmit Interrupt
.RXINT ( ), // Receive Interrupt
.TXOVRINT ( ), // Transmit Overrun Interrupt
@@ -96,9 +116,78 @@ module socdebug_ahb #(
.UARTINT ( ) // Combined Interrupt
);
- // Instantiation of FT1248 Bus Master
+ // Instantiation of FT1248 Controller
+ socdebug_ft1248_control #(
+ .FT1248_WIDTH (FT1248_WIDTH),
+ .FT1248_CLKON (FT1248_CLKON)
+ ) u_ft1248_control (
+ .clk (HCLK),
+ .resetn (HRESETn),
+ .ft_clkdiv (FT_CLKDIV),
+ .ft_clk_o (FT_CLK_O),
+ .ft_ssn_o (FT_SSN_O),
+ .ft_miso_i (FT_MISO_I),
+ .ft_miosio_o (FT_MIOSIO_O),
+ .ft_miosio_e (FT_MIOSIO_E),
+ .ft_miosio_z (FT_MIOSIO_Z),
+ .ft_miosio_i (FT_MIOSIO_I),
+
+ // ADP Interface - FT1248 to ADP
+ .txd_tvalid (FT1248_ADP_TVALID),
+ .txd_tdata (FT1248_ADP_TDATA),
+ .txd_tready (FT1248_ADP_TREADY),
+ .txd_tlast ( ),
+
+ // ADP Interface - ADP to FT1248
+ .rxd_tvalid (ADP_FT1248_TVALID),
+ .rxd_tdata (ADP_FT1248_TDATA),
+ .rxd_tready (ADP_FT1248_TREADY),
+ .rxd_tlast (1'b0)
+ );
// Instantiation of ADP AHB Controller
+ socdebug_adp_control #(
+ .PROMPT_CHAR (PROMPT_CHAR)
+ ) u_adp_control (
+ // AHB Interface
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HADDR32_o (HADDR32_o),
+ .HBURST3_o (HBURST3_o),
+ .HMASTLOCK_o (HMASTLOCK_o),
+ .HPROT4_o (HPROT4_o),
+ .HSIZE3_o (HSIZE3_o),
+ .HTRANS2_o (HTRANS2_o),
+ .HWDATA32_o (HWDATA32_o),
+ .HWRITE_o (HWRITE_o),
+ .HRDATA32_i (HRDATA32_i),
+ .HREADY_i (HREADY_i),
+ .HRESP_i (HRESP_i),
+
+ // GPIO Interface
+ .GPO8_o (GPO8_o),
+ .GPI8_i (GPI8_i),
+
+ // USRT Interface - From ADP to USRT
+ .STDTX_TVALID_o (ADP_USRT_TVALID),
+ .STDTX_TDATA_o (ADP_USRT_TDATA),
+ .STDTX_TREADY_i (ADP_USRT_TREADY),
+
+ // USRT Interface - From USRT to ADP
+ .STDRX_TVALID_i (USRT_ADP_TVALID),
+ .STDRX_TDATA_i (USRT_ADP_TDATA),
+ .STDRX_TREADY_o (USRT_ADP_TREADY),
+
+ // FT1248 Interface - From FT1248 to ADP
+ .COMRX_TVALID_i (FT1248_ADP_TVALID),
+ .COMRX_TDATA_i (FT1248_ADP_TDATA),
+ .COMRX_TREADY_o (FT1248_ADP_TREADY),
+
+ // FT1248 Interface - From ADP to FT1248
+ .COMTX_TVALID_o (ADP_FT1248_TVALID),
+ .COMTX_TDATA_o (ADP_FT1248_TDATA),
+ .COMTX_TREADY_i (ADP_FT1248_TREADY)
+ );
endmodule
\ No newline at end of file
diff --git a/controller/verilog/socdebug_ft1248_stream.v b/controller/verilog/socdebug_ft1248_control.v
similarity index 95%
rename from controller/verilog/socdebug_ft1248_stream.v
rename to controller/verilog/socdebug_ft1248_control.v
index 1e43d4c..69bd975 100755
--- a/controller/verilog/socdebug_ft1248_stream.v
+++ b/controller/verilog/socdebug_ft1248_control.v
@@ -9,14 +9,14 @@
// Copyright � 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module socdebug_ft1248_stream #(
+module socdebug_ft1248_control #(
parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
parameter integer FT1248_CLKON = 1 // FTDI clock always on - else quiet when no access
)(
// IO pad interface - to FT232R configured in 1/2/4/8 mode
- output wire ft_clk_o, // SCLK
- output wire ft_ssn_o, // SS_N
- input wire ft_miso_i, // MISO
+ output wire ft_clk_o, // SCLK
+ output wire ft_ssn_o, // SS_N
+ input wire ft_miso_i, // MISO
output wire [FT1248_WIDTH-1:0] ft_miosio_o, // MIOSIO tristate output when enabled
output wire [FT1248_WIDTH-1:0] ft_miosio_e, // MIOSIO tristate output enable (active hi)
output wire [FT1248_WIDTH-1:0] ft_miosio_z, // MIOSIO tristate output enable (active lo)
diff --git a/controller/verilog/socdebug_apb_usrt.v b/controller/verilog/socdebug_usrt_control.v
similarity index 99%
rename from controller/verilog/socdebug_apb_usrt.v
rename to controller/verilog/socdebug_usrt_control.v
index b056810..121855c 100644
--- a/controller/verilog/socdebug_apb_usrt.v
+++ b/controller/verilog/socdebug_usrt_control.v
@@ -61,7 +61,7 @@
// 0x3E0 - 0x3FC ID registers
//-------------------------------------
-module socdebug_apb_usrt (
+module socdebug_usrt_control (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
--
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