diff --git a/controller/verilog/socdebug_ft1248_control.v b/controller/verilog/socdebug_ft1248_control.v
index 69bd9753d28f6832a3682e72628ec8223581957f..14fc26a75ca941cf26aa353b8041626dec5d5a8d 100755
--- a/controller/verilog/socdebug_ft1248_control.v
+++ b/controller/verilog/socdebug_ft1248_control.v
@@ -110,13 +110,13 @@ module socdebug_ft1248_control #(
generate
if (FT1248_WIDTH == 1) begin
- assign ft_rdmasked[7:1] = 7'b1111111;
+ assign ft_rdmasked[7:1] = {7{1'b1}};
end
endgenerate
assign ft_rdmasked[0] = ft_miosio_i[0];
assign ft_miosio_o[0] = ft_reg[0];
- assign ft_miosio_e[0] = ft_state[1];
+ assign ft_miosio_e[0] = ft_state[1];
assign ft_miosio_z[0] = ~ft_state[1];
assign ft_clk_o = ft_state[0];
@@ -139,12 +139,12 @@ module socdebug_ft1248_control #(
always @(posedge clk or negedge resetn )
begin
if (!resetn) begin
- ft_clkcnt_r <= 0;
- ft_clken <= 0;
+ ft_clkcnt_r <= 8'h00;
+ ft_clken <= 1'b0;
end
else begin
ft_clken <= (ft_clkcnt_r == ft_clkdiv);
- ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 0 : (ft_clkcnt_r +1);
+ ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 8'h00 : ((ft_clkcnt_r + 8'h01) & 8'hff);
end
end
@@ -161,10 +161,10 @@ module socdebug_ft1248_control #(
always @(posedge clk or negedge resetn )
begin
if (!resetn) begin
- ft_miso_i_sync_1 <= 1;
- ft_miosio_i0_sync_1 <= 1;
- ft_miso_i_sync <= 1;
- ft_miosio_i0_sync <= 1;
+ ft_miso_i_sync_1 <= 1'b1;
+ ft_miosio_i0_sync_1 <= 1'b1;
+ ft_miso_i_sync <= 1'b1;
+ ft_miosio_i0_sync <= 1'b1;
end
else begin
ft_miso_i_sync_1 <= ft_miso_i;
@@ -213,35 +213,49 @@ module socdebug_ft1248_control #(
reg ssn_del;
always @(posedge clk or negedge resetn)
- if (!resetn)
+ begin
+ if (!resetn) begin
ssn_del <= 1'b1;
- else if (ft_clken)
+ end
+ else if (ft_clken) begin
ssn_del <= ft_ssn_o;
+ end
+ end
wire ssn_start = ft_ssn_o & ssn_del;
// FTDI1248 state machine
always @(posedge clk or negedge resetn)
+ begin
if (!resetn) begin
ft_state <= FT_0_IDLE;
- ft_reg <= 0;
- txdata <= 0;
- rxdone <= 0;
- ft_wcyc <= 0;
- ft_txf <= 1; // ftdi channel TXE# ('1' full)
- ft_rxe <= 1; // ftdi channel RXF# ('1' empty)
- ft_nak <= 0;
+ ft_reg <= {9{1'b0}};
+ txdata <= {9{1'b0}};
+ rxdone <= 1'b0;
+ ft_wcyc <= 1'b0;
+ ft_txf <= 1'b1; // ftdi channel TXE# ('1' full)
+ ft_rxe <= 1'b1; // ftdi channel RXF# ('1' empty)
+ ft_nak <= 1'b0;
end else begin
ft_txf <= (ft_state==FT_0_IDLE) ? (ft_miosio_i[0] | ft_miosio_i0_sync) : 1'b1; //ft_txf & !( ft_wcyc &(ft_state==FT_ZBT_CLKHI) & ft_miso_i);
ft_rxe <= (ft_state==FT_0_IDLE) ? (ft_miso_i | ft_miso_i_sync) : 1'b1; //ft_rxe & !(!ft_wcyc & (ft_state==FT_ZBT_CLKHI) & ft_miso_i);
txdata[8] <= txdata[8] & !txd_tready; // tx_valid handshake
rxdone <= (ft_clken & (ft_state==FT_ZWD_CLKLO) & !ft_nak) | (rxdone & !rxd_tvalid); // hold until acknowledged
- if (ft_clken)
+ if (ft_clken) begin
case (ft_state)
FT_0_IDLE: begin // RX req priority
- if (ssn_start & ft_rxreq) begin ft_reg <= rcmdpatt; ft_state <= FT_ZCMD_CLKLO; end
- else if (ssn_start & ft_txreq) begin ft_reg <= wcmdpatt; ft_state <= FT_ZCMD_CLKLO; ft_wcyc <= 1; end
- else ft_state <= (!ft_txf | !ft_rxe | (FT1248_CLKON!=0)) ? FT_1_IDLE : FT_0_IDLE;
+ if (ssn_start && ft_rxreq) begin
+ ft_reg <= rcmdpatt;
+ ft_state <= FT_ZCMD_CLKLO;
+ end
+ else if (ssn_start && ft_txreq) begin
+ ft_reg <= wcmdpatt;
+ ft_state <= FT_ZCMD_CLKLO;
+ ft_wcyc <= 1'b1;
+ end
+ else begin
+ ft_state <= (!ft_txf || !ft_rxe || (FT1248_CLKON != 0)) ? FT_1_IDLE : FT_0_IDLE;
+ end
end
FT_1_IDLE:
ft_state <= FT_0_IDLE;
@@ -250,42 +264,115 @@ module socdebug_ft1248_control #(
FT_CMD_CLKHI:
ft_state <= FT_CMD_CLKLO;
FT_CMD_CLKLO: // 2, 4 or 7 shifts
- if (bwid8) begin ft_reg <= FT_ZBT_CLKHI; end
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
+ if (bwid8) begin
+ ft_state <= FT_ZBT_CLKHI;
+ end
+ else if (bwid4) begin
+ ft_reg <= {4'b0000,ft_reg[8:4]};
+ ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
+ else if (bwid2) begin
+ ft_reg <= { 2'b00,ft_reg[8:2]};
+ ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
+ else begin
+ ft_reg <= { 1'b0,ft_reg[8:1]};
+ ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI;
+ end
FT_ZBT_CLKHI:
ft_state <= FT_ZBT_CLKLO;
FT_ZBT_CLKLO:
- if (ft_wcyc) begin ft_reg <= {1'b1,rxd_tdata}; ft_state <= FT_WD_CLKHI; end
- else begin ft_reg <= 9'b011111111; ft_state <= FT_RD_CLKHI; end
+ if (ft_wcyc) begin
+ ft_reg <= {1'b1,rxd_tdata};
+ ft_state <= FT_WD_CLKHI;
+ end
+ else begin
+ ft_reg <= 9'b011111111;
+ ft_state <= FT_RD_CLKHI;
+ end
FT_WD_CLKHI:
- if (ft_miso_i & ft_reg[8]) begin ft_nak <= 1'b1; ft_state <= FT_ZWD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
- else if (bwid4) ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else if (bwid2) ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ if (ft_miso_i && ft_reg[8]) begin
+ ft_nak <= 1'b1;
+ ft_state <= FT_ZWD_CLKLO;
+ end // NAK terminate on first cycle
+ else if (bwid8) begin
+ ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
+ end
+ else if (bwid4) begin
+ ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
+ else if (bwid2) begin
+ ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
+ else begin
+ ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
+ end
FT_WD_CLKLO:
- if (bwid8) begin ft_reg <= { 1'b0,ft_reg[7:0]}; ft_state <= FT_WD_CLKHI; end // clear top flag
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= FT_WD_CLKHI; end // shift 4 bits right
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= FT_WD_CLKHI; end // shift 2 bits right
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= FT_WD_CLKHI; end // shift 1 bit right
+ if (bwid8) begin
+ ft_reg <= { 1'b0,ft_reg[7:0]};
+ ft_state <= FT_WD_CLKHI;
+ end // clear top flag
+ else if (bwid4) begin
+ ft_reg <= {4'b0000,ft_reg[8:4]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 4 bits right
+ else if (bwid2) begin
+ ft_reg <= { 2'b00,ft_reg[8:2]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 2 bits right
+ else begin
+ ft_reg <= { 1'b0,ft_reg[8:1]};
+ ft_state <= FT_WD_CLKHI;
+ end // shift 1 bit right
FT_ZWD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end // terminate without TX handshake
- else begin ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end
+ if (ft_nak) begin
+ ft_nak<= 1'b0;
+ ft_state <= FT_0_IDLE;
+ ft_wcyc <= 1'b0;
+ end // terminate without TX handshake
+ else begin
+ ft_state <= FT_0_IDLE;
+ ft_wcyc <= 1'b0;
+ end
FT_RD_CLKHI: // capture iodata pins end of CLKHI phase
- if (ft_miso_i & (&ft_reg[7:0])) begin ft_nak <= 1'b1; ft_state <= FT_RD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) begin ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0}; ft_state <= FT_RD_CLKLO; end // 8-bit read twice
- else if (bwid4) begin ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]}; ft_state <= FT_RD_CLKLO; end
- else if (bwid2) begin ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]}; ft_state <= FT_RD_CLKLO; end
- else begin ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]}; ft_state <= FT_RD_CLKLO; end
+ if (ft_miso_i && (&ft_reg[7:0])) begin
+ ft_nak <= 1'b1;
+ ft_state <= FT_RD_CLKLO;
+ end // NAK terminate on first cycle
+ else if (bwid8) begin
+ ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0};
+ ft_state <= FT_RD_CLKLO;
+ end // 8-bit read twice
+ else if (bwid4) begin
+ ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]};
+ ft_state <= FT_RD_CLKLO;
+ end
+ else if (bwid2) begin
+ ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]};
+ ft_state <= FT_RD_CLKLO;
+ end
+ else begin
+ ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]};
+ ft_state <= FT_RD_CLKLO;
+ end
FT_RD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; txdata <= 9'b0; end // terminate without TX handshake
- else if (ft_reg[0]) begin ft_state <= FT_RD_CLKHI; ft_reg[0] <= !(bwid8); end // loop until all 8 bits shifted in (or 8-bit read repeated)
- else begin ft_state <= FT_0_IDLE; txdata <= {1'b1,ft_reg[8:1]}; end
+ if (ft_nak) begin
+ ft_nak<= 1'b0;
+ ft_state <= FT_0_IDLE;
+ txdata <= 9'b000000000;
+ end // terminate without TX handshake
+ else if (ft_reg[0]) begin
+ ft_state <= FT_RD_CLKHI;
+ ft_reg[0] <= !(bwid8);
+ end // loop until all 8 bits shifted in (or 8-bit read repeated)
+ else begin
+ ft_state <= FT_0_IDLE;
+ txdata <= {1'b1,ft_reg[8:1]};
+ end
default:
ft_state <= FT_0_IDLE;
endcase
+ end
end
-
+ end
endmodule
diff --git a/hal/socdebug_controller_ip.waive b/hal/socdebug_controller_ip.waive
index 1aafd2125bb6c8a60e85f389e807ea4d95625121..47c71fbc412bb056f03bb73407d888fddfbd0d4c 100644
--- a/hal/socdebug_controller_ip.waive
+++ b/hal/socdebug_controller_ip.waive
@@ -40,3 +40,13 @@ lint_checking designunit = socdebug_adp_control
INSYNC off;
}
+
+lint_checking designunit = socdebug_ft1248_control
+{
+ // Not Top-level in design_info
+ TPOUNR off;
+
+ // single bit bus configuration permitted
+ ONPNSG off;
+
+}
diff --git a/makefile b/makefile
index 73b6378362a81b590391f70e64fd26d28184e2b3..4efba84ff06680c305c80408a648d50b8bdff5b7 100644
--- a/makefile
+++ b/makefile
@@ -12,7 +12,7 @@
include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/socdebug
-LINT_INFO_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
+LINT_INFO_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
# Core Design Filelist
DESIGN_VC ?= $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist