diff --git a/README.md b/README.md
index a71c0afda8d889bd43115725b0b98342853946f2..609bd5d3bb86023a22eaa916a68f293951188f90 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,8 @@
-# SoCShute Tech
+# SoCDebug Tech
 ---
 
 ## Introduction
-SoCShute is a Debug Controller to enable low-level debug within SoCs. SoCShute runs over both FT1248 and USRT allowing for access to the internal system bus. Currently we have only supported an AHB interface but we may expand this in the future.
+SoCDebug is a Debug Controller to enable low-level debug within SoCs. SoCDebug runs over both FT1248 and USRT allowing for access to the internal system bus. Currently we have only supported an AHB interface but we may expand this in the future.
 
 ## RTL Structure
 This repo will contain the Verilog RTL for the USRT, FT1248 Controller and the ADP Controller. These components communicate with each other over AXI-Stream Interfaces which allow for the addition of other AXI-Stream compatable Debug Communication interfaces to interact with the ADP Controller.
diff --git a/controller/verilog/socshute_adp_control.v b/controller/verilog/socdebug_adp_control.v
similarity index 99%
rename from controller/verilog/socshute_adp_control.v
rename to controller/verilog/socdebug_adp_control.v
index 27b51296b3ba78eda6bedd582a375004b862315c..c4b9cf696ccf798669cb10ca3542cdf21f64da35 100755
--- a/controller/verilog/socshute_adp_control.v
+++ b/controller/verilog/socdebug_adp_control.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// SoCShute ASCII Debug Protocol Controller
+// SoCDebug ASCII Debug Protocol Controller
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -12,7 +12,7 @@
 //`define ADPBASIC 1
 `define ADPFSMDESIGN 1
 
-module socshute_adp_control #(
+module socdebug_adp_control #(
   parameter PROMPT_CHAR = "]"
 )(  
   // AHB-lite interface
diff --git a/controller/verilog/socshute_ahb.v b/controller/verilog/socdebug_ahb.v
similarity index 96%
rename from controller/verilog/socshute_ahb.v
rename to controller/verilog/socdebug_ahb.v
index a8c97312ab5d71ecc3aa331008b20899bf5afa26..edeb5bad04e8e3c64f0536876f0f93ca9a03129e 100644
--- a/controller/verilog/socshute_ahb.v
+++ b/controller/verilog/socdebug_ahb.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// SoCShute Top-level FT1248-AHB Debug Controller
+// SoCDebug Top-level FT1248-AHB Debug Controller
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,7 +9,7 @@
 // Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
-module socshute_ahb #(
+module socdebug_ahb #(
     parameter PROMPT_CHAR = "]"
 )(  
     // AHB-lite Master Interface
@@ -64,7 +64,7 @@ module socshute_ahb #(
     wire        STDTX_TREADY_i;
     
     // Instantiation of USRT Device
-    socshute_apb_usrt u_apb_usrt_com (
+    socdebug_apb_usrt u_apb_usrt_com (
         .PCLK              (PCLK),     // Peripheral clock
         .PCLKG             (PCLKG),    // Gated PCLK for bus
         .PRESETn           (PRESETn),  // Reset
diff --git a/controller/verilog/socshute_apb_usrt.v b/controller/verilog/socdebug_apb_usrt.v
similarity index 99%
rename from controller/verilog/socshute_apb_usrt.v
rename to controller/verilog/socdebug_apb_usrt.v
index 8da2951ba09e63ecb71a8638f6899c72f2d3d1d1..b056810bd7dfd14f3c88348569fae4c431c55253 100644
--- a/controller/verilog/socshute_apb_usrt.v
+++ b/controller/verilog/socdebug_apb_usrt.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// SoCShute APB USRT adapted from Arm CMSDK APB UART
+// SoCDebug APB USRT adapted from Arm CMSDK APB UART
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -61,7 +61,7 @@
 // 0x3E0 - 0x3FC  ID registers
 //-------------------------------------
 
-module socshute_apb_usrt (
+module socdebug_apb_usrt (
 // --------------------------------------------------------------------------
 // Port Definitions
 // --------------------------------------------------------------------------
diff --git a/controller/verilog/socshute_ft1248_stream.v b/controller/verilog/socdebug_ft1248_stream.v
similarity index 96%
rename from controller/verilog/socshute_ft1248_stream.v
rename to controller/verilog/socdebug_ft1248_stream.v
index 1030636ae197d099430a22fac96eecd400e0723c..1e43d4cf10608bbb1f2b5fd473b93306873c77fd 100755
--- a/controller/verilog/socshute_ft1248_stream.v
+++ b/controller/verilog/socdebug_ft1248_stream.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// SoCShute FTDI FT1248 Interface to AXI-Stream Controller
+// SoCDebug FTDI FT1248 Interface to AXI-Stream Controller
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
@@ -9,7 +9,7 @@
 // Copyright � 2022, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
-module socshute_ft1248_stream #(
+module socdebug_ft1248_stream #(
   parameter integer FT1248_WIDTH	= 1, // FTDI Interface 1,2,4 width supported
   parameter integer FT1248_CLKON	= 1  // FTDI clock always on - else quiet when no access
 )(