diff --git a/.gitmodules b/.gitmodules
index 619739672f5636a9995fc3c62d65ebfaa1ca08ef..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "socket/uart_axi_master"]
- path = socket/uart_axi_master
- url = https://github.com/ultraembedded/core_dbg_bridge.git
diff --git a/flist/axi_stream_io_ip.flist b/flist/axi_stream_io_ip.flist
new file mode 100644
index 0000000000000000000000000000000000000000..db995a6857885b008ee70d5a7f5f0109941cce8e
--- /dev/null
+++ b/flist/axi_stream_io_ip.flist
@@ -0,0 +1,15 @@
+//-----------------------------------------------------------------------------
+// SoCDebug AXI Stream IO Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for SoCLabs AXI Stream IO IP
+//-----------------------------------------------------------------------------
+
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/axi_stream_io/verilog/axi_stream_io.v
\ No newline at end of file
diff --git a/flist/f232h_ft1248_stream_ip.flist b/flist/f232h_ft1248_stream_ip.flist
index 81fb7d49f071a268444232dcb7e2bd7a2c63fa4a..072b26c4406e8efb100f16db3870759107ce20bc 100644
--- a/flist/f232h_ft1248_stream_ip.flist
+++ b/flist/f232h_ft1248_stream_ip.flist
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// SoCDebug UART to AXI Master Filelist
+// SoCDebug F232H FT1248 to AXI Stream Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,7 +9,7 @@
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
+// Abstract : Verilog Command File for SoCLabs F232H FT1248 to AXI Stream IP
//-----------------------------------------------------------------------------
$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v
diff --git a/fpga/makefile b/fpga/makefile
index 7fe1dc05cae341f6e80a9df81ff072f58b986931..52adf574327d163c1a7023327f304be8e1d1932f 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -65,14 +65,14 @@ flist_uart:
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR);)
-# Environment Variables for Packaging NanoSoC
+# Environment Variables for Packaging UART to AXI Master
package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST)
package_uart: export FPGA_COMPONENT_LIB = $(UART_IMP_DIR)
package_uart: export FPGA_COMPONENT_TOP = $(UART_TOP)
package_uart: export FPGA_VENDOR = $(VENDUART_VENDOROR)
package_uart: export FPGA_CORE_REV = $(UART_CORE_REV)
-# Package NanoSoC IP
+# Package UART to AXI Master IP
package_uart: flist_uart
@echo Packaging UART to AXI Master Component
@mkdir -p $(RUN_DIR)
@@ -81,7 +81,7 @@ package_uart: flist_uart
@cp $(RUN_DIR)/vivado.log $(UART_IMP_DIR)/logs
@echo UART to AXI Master Packaged
-# UART Packaging
+# F232H Emulator Packaging
F232H_FLIST := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/f232h_ft1248_stream_ip.flist
F232H_IMP_DIR := $(IMP_SOCKET_DIR)/f232h_ft1248_stream
@@ -97,18 +97,50 @@ flist_f232h:
@(cd $(F232H_TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR);)
-# Environment Variables for Packaging NanoSoC
+# Environment Variables for Packaging F232H Emulator
package_f232h: export FPGA_COMPONENT_FILELIST = $(F232H_TCL_OUTPUT_FILELIST)
package_f232h: export FPGA_COMPONENT_LIB = $(F232H_IMP_DIR)
package_f232h: export FPGA_COMPONENT_TOP = $(F232H_TOP)
package_f232h: export FPGA_VENDOR = $(F232H_VENDOR)
package_f232h: export FPGA_CORE_REV = $(F232H_CORE_REV)
-# Package NanoSoC IP
+# Package F232H Emulator IP
package_f232h: flist_f232h
@echo Packaging F232H FT1248 to AXI Stream Component
@mkdir -p $(RUN_DIR)
@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
@mkdir -p $(F232H_IMP_DIR)/logs
@cp $(RUN_DIR)/vivado.log $(F232H_IMP_DIR)/logs
- @echo F232H FT1248 to AXI Stream Packaged
\ No newline at end of file
+ @echo F232H FT1248 to AXI Stream Packaged
+
+# STREAMIO Emulator Packaging
+STREAMIO_FLIST := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/axi_stream_io_ip.flist
+STREAMIO_IMP_DIR := $(IMP_SOCKET_DIR)/axi_stream_io
+
+STREAMIO_TCL_FLIST_DIR := $(STREAMIO_IMP_DIR)/flist
+STREAMIO_TCL_OUTPUT_FILELIST := $(STREAMIO_TCL_FLIST_DIR)/gen_flist.tcl
+
+STREAMIO_TOP := axi_stream_io
+STREAMIO_VENDOR := soclabs.org
+STREAMIO_CORE_REV ?= 1
+
+flist_streamio:
+ @mkdir -p $(STREAMIO_TCL_FLIST_DIR)
+ @(cd $(STREAMIO_TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(STREAMIO_FLIST) -o $(STREAMIO_TCL_OUTPUT_FILELIST) -r $(STREAMIO_IMP_DIR);)
+
+# Environment Variables for Packaging NanoSoC
+package_streamio: export FPGA_COMPONENT_FILELIST = $(STREAMIO_TCL_OUTPUT_FILELIST)
+package_streamio: export FPGA_COMPONENT_LIB = $(STREAMIO_IMP_DIR)
+package_streamio: export FPGA_COMPONENT_TOP = $(STREAMIO_TOP)
+package_streamio: export FPGA_VENDOR = $(STREAMIO_VENDOR)
+package_streamio: export FPGA_CORE_REV = $(STREAMIO_CORE_REV)
+
+# Package NanoSoC IP
+package_streamio: flist_streamio
+ @echo Packaging AXI Stream Interface Component
+ @mkdir -p $(RUN_DIR)
+ @cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
+ @mkdir -p $(STREAMIO_IMP_DIR)/logs
+ @cp $(RUN_DIR)/vivado.log $(STREAMIO_IMP_DIR)/logs
+ @echo AXI Stream Interface Packaged
\ No newline at end of file
diff --git a/socket/verilog/axi_stream_io_v1_0_axi_s.v b/socket/axi_stream_io/verilog/axi_stream_io.v
similarity index 87%
rename from socket/verilog/axi_stream_io_v1_0_axi_s.v
rename to socket/axi_stream_io/verilog/axi_stream_io.v
index 303780efefce184c1f353751c71280794b5348bd..231944e85bd17ee23d1a329a3b681db6a450c353 100755
--- a/socket/verilog/axi_stream_io_v1_0_axi_s.v
+++ b/socket/axi_stream_io/verilog/axi_stream_io.v
@@ -1,7 +1,18 @@
+//-----------------------------------------------------------------------------
+// SoCLabs AXI Stream Interface
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
`timescale 1 ns / 1 ps
- module axi_stream_io_v1_0_axi_s #
+ module axi_stream_io #
(
// Users to add parameters here
@@ -133,25 +144,19 @@
integer byte_index;
reg aw_en;
- wire tx_req = tx_reg[8]; // request to transmit
- wire tx_ack = tx_tready; // acknowledge when stream ready
- wire tx_rdy = !tx_reg[8];
- wire rx_req = rx_tvalid; // request to receive
- wire rx_ack = !rx_reg[8];
- wire rx_rdy = rx_reg[8];
+ wire tx_empty = !tx_reg[8]; // request to transmit
+ wire rx_full = rx_reg[8];
- //assign rx_reg[7:0] <= rx_tdata;
-
// I/O Connections assignments
- assign interrupt = ctrl_reg[4] & (!tx_req | rx_req);
+ assign interrupt = ctrl_reg[4] & (tx_empty | rx_full);
// TX stream interface
assign tx_tdata = tx_reg[7:0];
- assign tx_tvalid = tx_req;
+ assign tx_tvalid = tx_reg[8];
// RX stream interface
- assign rx_tready = rx_ack;
+ assign rx_tready = !rx_reg[8];
//AXI Slave
assign S_AXI_AWREADY = axi_awready;
@@ -257,27 +262,27 @@
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
- rx_reg <= 0;
- else if ((ctrl_reg[1] == 1'b1))
- rx_reg <= 0;
- else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ rx_reg <= 0;
+ else if ((ctrl_reg[1] == 1'b1)) // RX flush
+ rx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // SW test write
rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
- else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
+ else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // Read and clear RX valid pending
rx_reg[8] <= 1'b0;
- else if (rx_req & rx_ack) // check precedence (rx_req)
- rx_reg[8:0] <= {1'b1, rx_tdata[7:0]};
+ else if (rx_tvalid & rx_tready) //(!rx_reg[8]) // new RX data
+ rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; // valid rx data (= clear rx_tready inverted bit[8])
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
tx_reg <= 0;
- else if ((ctrl_reg[0] == 1'b1))
- tx_reg <= 0;
- else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1))
+ else if ((ctrl_reg[0] == 1'b1)) // TX flush
+ tx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) // Write and set valid pending
tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
- else if (tx_req & tx_ack)
- tx_reg[8] <= 1'b0;
+ else if (tx_tready & tx_tvalid) //& tx_reg[8]) // clear TX valid pending when req and ack
+ tx_reg[8] <= 1'b0; // clear valid when TX data acknowledged
end
always @( posedge S_AXI_ACLK )
@@ -392,7 +397,7 @@
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= rx_reg[7:0];
2'h1 : reg_data_out <= tx_reg[7:0];
- 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_rdy, tx_rdy, rx_rdy, rx_rdy};
+ 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_empty, tx_empty, rx_full, rx_full};
2'h3 : reg_data_out <= ctrl_reg;
default : reg_data_out <= 0;
endcase
diff --git a/socket/uart_axi_master b/socket/uart_axi_master
deleted file mode 160000
index 3ea8f99cb458acf3f6cfe27862afe77d560caf08..0000000000000000000000000000000000000000
--- a/socket/uart_axi_master
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 3ea8f99cb458acf3f6cfe27862afe77d560caf08
diff --git a/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v b/socket/uart_axi_master/wrapper/verilog/uart_axi_master.v
similarity index 100%
rename from socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
rename to socket/uart_axi_master/wrapper/verilog/uart_axi_master.v
diff --git a/socket/wrappers/uart_axi_master/verilog/uart_axi_master_M00_AXI.v b/socket/uart_axi_master/wrapper/verilog/uart_axi_master_M00_AXI.v
similarity index 100%
rename from socket/wrappers/uart_axi_master/verilog/uart_axi_master_M00_AXI.v
rename to socket/uart_axi_master/wrapper/verilog/uart_axi_master_M00_AXI.v
diff --git a/socket/verilog/axi_stream_io_v1_0.v b/socket/verilog/axi_stream_io_v1_0.v
deleted file mode 100755
index f017669bcee76c6ab4fb74c53ceff56eb2ac5522..0000000000000000000000000000000000000000
--- a/socket/verilog/axi_stream_io_v1_0.v
+++ /dev/null
@@ -1,114 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module axi_stream_io_v1_0 #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
-
- // Parameters of Axi Slave Bus Interface axi
- parameter integer C_axi_DATA_WIDTH = 32,
- parameter integer C_axi_ADDR_WIDTH = 4,
-
- // Parameters of Axi Master Bus Interface tx
- parameter integer C_tx_TDATA_WIDTH = 8,
- parameter integer C_tx_START_COUNT = 3,
-
- // Parameters of Axi Slave Bus Interface rx
- parameter integer C_rx_TDATA_WIDTH = 8
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
-
- // Ports of Axi Slave Bus Interface axi
- input wire axi_aclk,
- input wire axi_aresetn,
- input wire [C_axi_ADDR_WIDTH-1 : 0] axi_awaddr,
- input wire [2 : 0] axi_awprot,
- input wire axi_awvalid,
- output wire axi_awready,
- input wire [C_axi_DATA_WIDTH-1 : 0] axi_wdata,
- input wire [(C_axi_DATA_WIDTH/8)-1 : 0] axi_wstrb,
- input wire axi_wvalid,
- output wire axi_wready,
- output wire [1 : 0] axi_bresp,
- output wire axi_bvalid,
- input wire axi_bready,
- input wire [C_axi_ADDR_WIDTH-1 : 0] axi_araddr,
- input wire [2 : 0] axi_arprot,
- input wire axi_arvalid,
- output wire axi_arready,
- output wire [C_axi_DATA_WIDTH-1 : 0] axi_rdata,
- output wire [1 : 0] axi_rresp,
- output wire axi_rvalid,
- input wire axi_rready,
-
- output wire interrupt,
- // Ports of Axi Master Bus Interface tx
- output wire tx_tvalid,
- output wire [C_tx_TDATA_WIDTH-1 : 0] tx_tdata,
- output wire [(C_tx_TDATA_WIDTH/8)-1 : 0] tx_tstrb,
- output wire tx_tlast,
- input wire tx_tready,
-
- // Ports of Axi Slave Bus Interface rx
- output wire rx_tready,
- input wire [C_rx_TDATA_WIDTH-1 : 0] rx_tdata,
- input wire [(C_rx_TDATA_WIDTH/8)-1 : 0] rx_tstrb,
- input wire rx_tlast,
- input wire rx_tvalid
- );
-// Instantiation of Axi Bus Interface axi
- iostream_v1_0_axi # (
- .C_S_AXI_DATA_WIDTH(C_axi_DATA_WIDTH),
- .C_S_AXI_ADDR_WIDTH(C_axi_ADDR_WIDTH)
- ) iostream_v1_0_axi_inst (
- .S_AXI_ACLK(axi_aclk),
- .S_AXI_ARESETN(axi_aresetn),
- .tx_tvalid(tx_tvalid),
- .tx_tdata(tx_tdata),
-// output wire [0 : 0] tx_tstrb,
-// output wire tx_tlast,
- .tx_tready(tx_tready),
- .rx_tvalid(rx_tvalid),
- .rx_tdata(rx_tdata),
-// input wire [0 : 0] tx_tstrb,
-// input wire tx_tlast,
- .rx_tready(rx_tready),
- .interrupt(interrupt),
- .S_AXI_AWADDR(axi_awaddr),
- .S_AXI_AWPROT(axi_awprot),
- .S_AXI_AWVALID(axi_awvalid),
- .S_AXI_AWREADY(axi_awready),
- .S_AXI_WDATA(axi_wdata),
- .S_AXI_WSTRB(axi_wstrb),
- .S_AXI_WVALID(axi_wvalid),
- .S_AXI_WREADY(axi_wready),
- .S_AXI_BRESP(axi_bresp),
- .S_AXI_BVALID(axi_bvalid),
- .S_AXI_BREADY(axi_bready),
- .S_AXI_ARADDR(axi_araddr),
- .S_AXI_ARPROT(axi_arprot),
- .S_AXI_ARVALID(axi_arvalid),
- .S_AXI_ARREADY(axi_arready),
- .S_AXI_RDATA(axi_rdata),
- .S_AXI_RRESP(axi_rresp),
- .S_AXI_RVALID(axi_rvalid),
- .S_AXI_RREADY(axi_rready)
- );
-
-assign tx_tstrb[0:0] = tx_tvalid;
-assign tx_tlast = 1'b0;
-
- // Add user logic here
-
- // User logic ends
-
- endmodule