diff --git a/flist/uart_axi_master.flist b/flist/f232h_ft1248_stream_ip.flist
similarity index 90%
rename from flist/uart_axi_master.flist
rename to flist/f232h_ft1248_stream_ip.flist
index 001dd6376e09e08515d9fee24ec8739f0ee29f0d..36e5e360ca877b5531aa937571cc80d10f0ff458 100644
--- a/flist/uart_axi_master.flist
+++ b/flist/f232h_ft1248_stream_ip.flist
@@ -15,4 +15,4 @@
$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/uart_axi_master.v
\ No newline at end of file
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
\ No newline at end of file
diff --git a/flist/uart_axi_master_ip.flist b/flist/uart_axi_master_ip.flist
new file mode 100644
index 0000000000000000000000000000000000000000..36e5e360ca877b5531aa937571cc80d10f0ff458
--- /dev/null
+++ b/flist/uart_axi_master_ip.flist
@@ -0,0 +1,18 @@
+//-----------------------------------------------------------------------------
+// SoCDebug UART to AXI Master Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
+//-----------------------------------------------------------------------------
+
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
\ No newline at end of file
diff --git a/fpga/makefile b/fpga/makefile
index d5d8592a9f8b619b875678a710392adeb61b9cc3..0f30b53cf4b3ff70ecb459562d6e43abe6767c6a 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -43,7 +43,7 @@ clean_socket:
# UART Packaging
-DESIGN_VC := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/uart_axi_master.flist
+DESIGN_VC := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/uart_axi_master_ip.flist
IMPLEMENTATION_DIR ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
RUN_DIR := $(IMPLEMENTATION_DIR)/run
diff --git a/socket/ft232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v b/socket/ft232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v
new file mode 100644
index 0000000000000000000000000000000000000000..0f0940346406398686958b63782030b470569ed0
--- /dev/null
+++ b/socket/ft232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v
@@ -0,0 +1,43 @@
+//-----------------------------------------------------------------------------
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire syn_del_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign syn_del_o = (testmode_i) ? asyn_i : sync_stage3;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
diff --git a/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v
new file mode 100644
index 0000000000000000000000000000000000000000..ba0a04636bb69ad0535867cdb85f8edc8e7936fa
--- /dev/null
+++ b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v
@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2022-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+ module ft232h_ft1248_stream #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Stream Bus Interface rxd8
+ parameter integer C_rxd8_TDATA_WIDTH = 8,
+
+ // Parameters of Axi Stream Bus Interface txd8
+ parameter integer C_txd8_TDATA_WIDTH = 8
+ )
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+
+ input wire aclk, // external primary clock
+ input wire aresetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+wire ft_miosio_i_del;
+
+SYNCHRONIZER_EDGES u_sync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .syn_del_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .syn_del_o(),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_din (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_miosio_i),
+ .syn_o( ),
+ .syn_del_o(ft_miosio_i_del),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i_del, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, ft_miosio_i_del, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+
+/*
+reg [8:0] rxstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+*/
+
+// shift TXD on rising edge of clock
+reg [8:0] txd_sr;
+// rewrite for clocked
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & rxd_tvalid_i & (ft_state == 5'b00111))
+ txd_sr <= rxd_tdata8_i;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+assign rxd_tready_o = (ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01110)); // hold until final shift
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+//assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+assign ft_miso_o = (ft_ssn_i) ? !rxd_tvalid_i : ((ft_state == 5'b00111) & ((ft_cmd_txd) ? txstream[8]: !rxd_tvalid_i));
+
+endmodule
diff --git a/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_rxd8.v b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_rxd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..2ade9d77928377891fdd358e64d35f2a9e514850
--- /dev/null
+++ b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_rxd8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft232h_ft1248_stream_rxd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_txd8.v b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_txd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..bd7b9601ba4ad582d547736094a7dde7223fc593
--- /dev/null
+++ b/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream_txd8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft232h_ft1248_stream_txd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/socket/verilog/ft232h_ft1248_x1.v b/socket/verilog/ft232h_ft1248_x1.v
deleted file mode 100644
index e125ea3a0ca03bce2fccdd816606fb5c2017438c..0000000000000000000000000000000000000000
--- a/socket/verilog/ft232h_ft1248_x1.v
+++ /dev/null
@@ -1,157 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC FT1248 ADP UART file logging
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
-// and allows cmsdk_uart_capture testbench models to log ADP ip, op streams
-//-----------------------------------------------------------------------------
-
-
-module ft232h_ft1248_x1 #(
- parameter ADPFILENAME = "adp.cmd",
- parameter VERBOSE = 0
-)(
- input wire ft_clk_i, // SCLK
- input wire ft_ssn_i, // SS_N
- output wire ft_miso_o, // MISO
- inout wire ft_miosio_io, // MIOSIO tristate output when enabled
-
- output wire FTDI_CLK2UART_o, // Clock (baud rate)
- output wire FTDI_OP2UART_o, // Received data to UART capture
- output wire FTDI_IP2UART_o // Transmitted data to UART capture
-);
-
-
- //----------------------------------------------
- //-- File I/O
- //----------------------------------------------
-
-
- integer fdcmd; // channel descriptor for cmd file input
- integer ch;
-`define EOF -1
-
- reg ft_rxreq;
- wire ft_rxack;
- reg [7:0] ft_adpbyte;
-
- initial
- begin
- ft_rxreq <= 0;
- $timeformat(-9, 0, " ns", 14);
- fdcmd= $fopen(ADPFILENAME,"r");
- if (fdcmd == 0)
- $write("** FT1248x1 : no command file **\n");
- else begin
- ch = $fgetc(fdcmd);
- while (ch != `EOF) begin
- ft_adpbyte <= (ch & 8'hff);
- ft_rxreq <= 1'b1;
- while (ft_ssn_i == 1'b0)
- @(posedge ft_ssn_i);
- @(posedge ft_rxack);
- ft_rxreq <=0;
- @(negedge ft_rxack);
- ch = $fgetc(fdcmd);
- end
- end
- $fclose(fdcmd);
- ft_rxreq <= 0;
- end
-
-
-//----------------------------------------------
-//-- State Machine
-//----------------------------------------------
-
-wire ft_miosio_i;
-wire ft_miosio_o;
-wire ft_miosio_z;
-
-// tri-state pad control for MIOSIO
-assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-// add notinal delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
-assign #1 ft_miosio_i = ft_miosio_io;
-
-reg [4:0] ft_state; // 17-state for bit-serial
-wire [5:0] ft_nextstate = ft_state + 5'b00001;
-
-always @(posedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_state <= 5'b11111;
- else // loop if multi-data
-// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
- ft_state <= ft_nextstate;
-
-// 16: bus turnaround (or bit[5])
-// 0 for CMD3
-// 3 for CMD2
-// 5 for CMD1
-// 6 for CMD0
-// 7 for cmd turnaround
-// 8 for data bit0
-// 9 for data bit1
-// 10 for data bit2
-// 11 for data bit3
-// 12 for data bit4
-// 13 for data bit5
-// 14 for data bit6
-// 15 for data bit7
-
-// ft_miso_o reflects RXE when deselected
-assign ft_miso_o = (ft_ssn_i) ? !ft_rxreq : (ft_state == 5'b00111);
-
-// capture CMD on falling edge of clock (mid-data)
-// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
-reg [7:0] ft_cmd;
-always @(negedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_cmd <= 8'b00000001;
- else // shift in data
- ft_cmd <= (!ft_state[3] & !ft_nextstate[3]) ? {ft_cmd[6:0],ft_miosio_i} : ft_cmd;
-
-wire ft_cmd_valid = ft_cmd[7];
-wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
-wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
-
-// tristate enable for miosio (deselected status or serialized data for read command)
-wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
-assign ft_miosio_z = !ft_miosio_e;
-
-// serial data formatted with start bit for UART capture (on rising uart-clock)
-assign FTDI_CLK2UART_o = !ft_clk_i;
-// suitable for CMSDK UART capture IO
-// inject a start bit low else mark high
-assign FTDI_OP2UART_o = (ft_cmd_txd & (ft_state[4:3]) == 2'b01) ? ft_miosio_i : !(ft_cmd_txd & (ft_state == 5'b00111));
-assign FTDI_IP2UART_o = (ft_cmd_rxd & (ft_state[4:3]) == 2'b01) ? ft_miosio_io : !(ft_cmd_rxd & (ft_state == 5'b00111));
-
-// capture RXD on falling edge of clock
-reg [8:0] ft_rxd;
-always @(negedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_rxd <= 9'b111111111;
- else if (ft_cmd_txd & !(ft_miosio_i & (&ft_rxd[8:0]))) //only on valid start-bit
- ft_rxd <= {ft_miosio_i, ft_rxd[8:1]};
-
-// shift TXD on rising edge of clock
-reg [8:0] ft_txd;
-always @(posedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_txd <= {1'b1,ft_adpbyte};
- else if (ft_rxreq & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //valid TX shift
- ft_txd <= {1'b0,ft_txd[8:1]};
-
-assign ft_rxack = (ft_cmd_rxd & (ft_state==5'b01111));
-
-// ft_miso_o reflects TXF when deselected (never full for simulation output)
-assign ft_miosio_o = (ft_ssn_i) ? 1'b0 : ft_txd[0];
-
-endmodule
diff --git a/socket/wrappers/uart_axi_master/uart_axi_master.v b/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
similarity index 100%
rename from socket/wrappers/uart_axi_master/uart_axi_master.v
rename to socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
diff --git a/socket/wrappers/uart_axi_master/uart_to_AXI_master_v1_0_M00_AXI.v b/socket/wrappers/uart_axi_master/verilog/uart_axi_master_M00_AXI.v
similarity index 99%
rename from socket/wrappers/uart_axi_master/uart_to_AXI_master_v1_0_M00_AXI.v
rename to socket/wrappers/uart_axi_master/verilog/uart_axi_master_M00_AXI.v
index ac7d45594a28cc78c48e2852cb8f6e1070be8813..ed5ef5674af51b52bddbfac9e826a96100653339 100644
--- a/socket/wrappers/uart_axi_master/uart_to_AXI_master_v1_0_M00_AXI.v
+++ b/socket/wrappers/uart_axi_master/verilog/uart_axi_master_M00_AXI.v
@@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
- module uart_to_AXI_master_v1_0_M00_AXI #
+ module uart_axi_master_0_M00_AXI #
(
// Users to add parameters here