From d3a9db1014315bda22e9025b24fc9cda7b064a10 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 5 Dec 2023 17:19:40 +0000
Subject: [PATCH] add 3rd stream to wrapper
---
flist/dma350_ahb_big_ip.flist | 12 ++++++++++
flist/sldma350_ahb_big.flist | 41 ++++++++++++++++++++++++++++++++++
flist/sldma350_ahb_small.flist | 41 ++++++++++++++++++++++++++++++++++
wrapper/logical/sldma350_ahb.v | 33 ++++++++++++++++++++++++++-
4 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 flist/sldma350_ahb_big.flist
create mode 100644 flist/sldma350_ahb_small.flist
diff --git a/flist/dma350_ahb_big_ip.flist b/flist/dma350_ahb_big_ip.flist
index 1e796b9..505480b 100644
--- a/flist/dma350_ahb_big_ip.flist
+++ b/flist/dma350_ahb_big_ip.flist
@@ -69,6 +69,10 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_chan
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
@@ -88,6 +92,10 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_chan
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
@@ -107,6 +115,10 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_chan
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_slave_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_master_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_bypass_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv
diff --git a/flist/sldma350_ahb_big.flist b/flist/sldma350_ahb_big.flist
new file mode 100644
index 0000000..85d8e65
--- /dev/null
+++ b/flist/sldma350_ahb_big.flist
@@ -0,0 +1,41 @@
+//-----------------------------------------------------------------------------
+// MegaSoC DMA-350 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-350
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/dma350_ahb_big_ip.flist
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_or.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_xor.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_flop.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_sync.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_bypass_regd_slice_empty.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice_empty.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_xin.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_h_xout.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_xreg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_hreg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_r.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_b.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_lpi.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_strbgen.sv
+
+
+$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_ahb_small.v
+$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_trig_converter.v
diff --git a/flist/sldma350_ahb_small.flist b/flist/sldma350_ahb_small.flist
new file mode 100644
index 0000000..e3a56b5
--- /dev/null
+++ b/flist/sldma350_ahb_small.flist
@@ -0,0 +1,41 @@
+//-----------------------------------------------------------------------------
+// MegaSoC DMA-350 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-350
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/dma350_ahb_small_ip.flist
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_or.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_xor.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_flop.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_sync.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_bypass_regd_slice_empty.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice_empty.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_xin.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_h_xout.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_xreg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_hreg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_r.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_b.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_lpi.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_strbgen.sv
+
+
+$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_ahb_small.v
+$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_trig_converter.v
diff --git a/wrapper/logical/sldma350_ahb.v b/wrapper/logical/sldma350_ahb.v
index f63fefc..6d8bb07 100644
--- a/wrapper/logical/sldma350_ahb.v
+++ b/wrapper/logical/sldma350_ahb.v
@@ -88,6 +88,23 @@ module sldma350_ahb #(
input wire DMAC_STR_IN_1_TLAST,
output wire DMAC_STR_IN_1_FLUSH,
`endif
+`ifdef DMA350_STREAM_3
+// DMAC Channel 1 AXI Stream out
+ output wire DMAC_STR_OUT_2_TVALID,
+ input wire DMAC_STR_OUT_2_TREADY,
+ output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_2_TDATA,
+ output wire [4-1:0] DMAC_STR_OUT_2_TSTRB,
+ output wire DMAC_STR_OUT_2_TLAST,
+
+ // DMAC Channel 1 AXI Stream out
+ input wire DMAC_STR_IN_2_TVALID,
+ output wire DMAC_STR_IN_2_TREADY,
+ input wire [SYS_DATA_W-1:0] DMAC_STR_IN_2_TDATA,
+ input wire [4-1:0] DMAC_STR_IN_2_TSTRB,
+ input wire DMAC_STR_IN_2_TLAST,
+ output wire DMAC_STR_IN_2_FLUSH,
+`endif
+
// DMA Request and Status Port
input wire [CHANNEL_NUM-1:0] DMA_REQ, // DMA transfer request
output wire [CHANNEL_NUM-1:0] DMA_DONE, // DMA transfer done
@@ -392,7 +409,21 @@ ada_top_sldma350 u_dmac_0(
.str_in_1_tlast(DMAC_STR_IN_1_TLAST),
.str_in_1_flush(DMAC_STR_IN_1_FLUSH),
`endif
-
+`ifdef DMA350_STREAM_3
+ // AXI Stream 1 out
+ .str_out_2_tvalid(DMAC_STR_OUT_2_TVALID),
+ .str_out_2_tready(DMAC_STR_OUT_2_TREADY),
+ .str_out_2_tdata(DMAC_STR_OUT_2_TDATA),
+ .str_out_2_tstrb(DMAC_STR_OUT_2_TSTRB),
+ .str_out_2_tlast(DMAC_STR_OUT_2_TLAST),
+ // AXI Stream 1 in
+ .str_in_2_tvalid(DMAC_STR_IN_2_TVALID),
+ .str_in_2_tready(DMAC_STR_IN_2_TREADY),
+ .str_in_2_tdata(DMAC_STR_IN_2_TDATA),
+ .str_in_2_tstrb(DMAC_STR_IN_2_TSTRB),
+ .str_in_2_tlast(DMAC_STR_IN_2_TLAST),
+ .str_in_2_flush(DMAC_STR_IN_2_FLUSH),
+`endif
.allch_stop_req_nonsec(1'b0),
.allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC),
.allch_pause_req_nonsec(1'b0),
--
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