diff --git a/wrapper/logical/sldma350_trig_converter.v b/wrapper/logical/sldma350_trig_converter.v
index b27936def97fc7d8bd14226863fa6b5de5541ff7..f2cbe08d24dee8ef26a7d6de4e9e74d5f333de1d 100644
--- a/wrapper/logical/sldma350_trig_converter.v
+++ b/wrapper/logical/sldma350_trig_converter.v
@@ -37,11 +37,28 @@ assign DMAC_DMA_REQ_ERR = dma_err;
 assign trig_in_req_type = 2'b10;
 assign DMAC_DMA_DONE = out_ack;
 
+reg         req_0;
+reg         req_1;
+reg         DMAC_DMA_REQ_EDGE;
+
+always @(posedge clk) begin
+    req_0<=DMAC_DMA_REQ;
+    req_1<=req_0;
+    if (req_0&~req_1) begin
+        DMAC_DMA_REQ_EDGE<=1'b1;
+    end else begin
+        DMAC_DMA_REQ_EDGE<=1'b0;
+    end
+end
+
 always @(negedge resetn or posedge clk) begin
     if(~resetn) begin
         state <= IDLE;
         dma_err<= 1'b0;
         out_ack <= 1'b0;
+        req_0 <= 1'b0;
+        req_1 <= 1'b0;
+        DMAC_DMA_REQ_EDGE <= 1'b0;
     end else begin
         state <= next_state;
     end
@@ -59,7 +76,7 @@ always @* begin
 case(state)
     IDLE: begin
         trig_req = 1'b0;
-        if (DMAC_DMA_REQ) begin
+        if (DMAC_DMA_REQ_EDGE & ~trig_in_ack) begin
             req_err = 1'b0;
             next_state = START_REQ;
         end