diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..a70a9ae377981f74351af0db162efa9e1782d7c1
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+# Configured DMA IP files
+/src/*
\ No newline at end of file
diff --git a/config/cfg_dma_ahb.yaml b/config/cfg_dma_ahb.yaml
new file mode 100755
index 0000000000000000000000000000000000000000..99b33376d8e17321cad475c6b0d56c7330fca7e3
--- /dev/null
+++ b/config/cfg_dma_ahb.yaml
@@ -0,0 +1,166 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Release Information : DMA350-r0p0-00rel0
+#
+# -----------------------------------------------------------------------------
+# Abstract : User Configuration file for ADA DMA
+# -----------------------------------------------------------------------------
+
+#
+# CONFIG_NAME: Name of the configuration.
+# Each unifiqued element and top is suffixed with
+# _${CONFIG_NAME}
+#
+CONFIG_NAME: sldma350
+
+#
+# ADDR_WIDTH: Address Bus width
+#
+# Valid values:
+# 32-64
+ADDR_WIDTH: 32
+
+#
+# DATA_WIDTH: Data Bus width
+#
+# Valid values:
+# [32,64,128]
+DATA_WIDTH: 32
+
+#
+# CHID_WIDTH: Width of the configurable channel ID user signal.
+# When set to 0, then the archid and awchid ports are not present on the module.
+#
+# Valid values:
+# 0-16
+CHID_WIDTH: 0
+
+#
+# GPO_WIDTH: Width of GPO output for every channel. When multiple channels have GPOs
+# then the width must be set to the maximum number of GPOs a channel can have,
+# and unused GPO ports need to be left unconnected. When all bits of CH_GPO_MASK
+# is 0, this parameter is not relevant.
+#
+# Valid values:
+# 1-32
+GPO_WIDTH: 1
+
+#
+# CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
+# bitmask is NUM_CHANNELS-1. When bit n is set to 1 then the GPO is enabled for
+# channel n and the gpo_ch_n[GPO_WIDTH-1:0] port appears on the module.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_GPO_MASK: 0x0
+
+#
+# CH_STREAM_MASK: A bitmask for enabling the stream interfaces for each channel.
+# The width of the bitmask is NUM_CHANNELS-1. When bit n is set to 1 then
+# the stream interfaces are enabled for channel n and the relevant ports
+# appears on the module. NOTE: When streaming interface is enabled the actual
+# FIFO size of the channel will be the double of CH_<N>_FIFO_DEPTH
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_STREAM_MASK: 0x3
+
+#
+# CH_<N>_FIFO_DEPTH: Sets the FIFO depth for channel <N> that defines the number of
+# DATA_WIDTH size entries a channel can hold for a transfer. N goes from 0 to
+# NUM_CHANNELS-1. In combination with the TRANSIZE setting of the command, the
+# FIFO depth defines the maximum burst size a channel can support. This setting
+# needs to be aligned with the bandwidth requirements of the channel but it
+# highly affects the area of the design.
+#
+# Valid values:
+# [1,2,4,8,16,32,64]
+CH_0_FIFO_DEPTH: 2
+CH_1_FIFO_DEPTH: 2
+
+#
+# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
+# The extension contains 2D, WRAP, TMPLT features. Default value enables it for
+# the number of channels.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_EXT_FEAT_MASK: 0x3
+
+#
+# NUM_CHANNELS: Number of configurable DMA channels.
+#
+# Valid values:
+# 1-8
+NUM_CHANNELS: 2
+
+#
+# NUM_TRIGGER_IN: Number of trigger input ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_IN: 2
+
+#
+# NUM_TRIGGER_OUT: Number of trigger output ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_OUT: 2
+
+#
+# TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_IN-1.
+# When bit n is set to 1 then the trigger in interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_IN-1)
+TRIG_IN_SYNC_EN_MASK: 0x0
+
+#
+# TRIG_OUT_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger out
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_OUT-1.
+# When bit n is set to 1 then the trigger out interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_OUT-1)
+TRIG_OUT_SYNC_EN_MASK: 0x0
+
+#
+# AXI5_M1_PRESENT: Enables an additional master port. When set the m1 master port is
+# present on the top level port list and additional include file can be used with
+# a System Verilog function that defines which address ranges are mapped to the m1
+# interface.
+#
+# Valid values:
+# [0,1]
+AXI5_M1_PRESENT: 0
+
+#
+# SECEXT_PRESENT: Enables TrustZone security support.
+#
+# Valid values:
+# [0,1]
+SECEXT_PRESENT: 0
+
+
+#
+# AXI5_M1_ADDR_MAP: Select AXI M1 master.
+#
+# Valid values:
+# relative path to logical
+AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_example1.sv
diff --git a/config/cfg_dma_axi.yaml b/config/cfg_dma_axi.yaml
new file mode 100755
index 0000000000000000000000000000000000000000..1522fc392a753ebfe434cd31b111f7f92e82b47a
--- /dev/null
+++ b/config/cfg_dma_axi.yaml
@@ -0,0 +1,166 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Release Information : DMA350-r0p0-00rel0
+#
+# -----------------------------------------------------------------------------
+# Abstract : User Configuration file for ADA DMA
+# -----------------------------------------------------------------------------
+
+#
+# CONFIG_NAME: Name of the configuration.
+# Each unifiqued element and top is suffixed with
+# _${CONFIG_NAME}
+#
+CONFIG_NAME: sldma350
+
+#
+# ADDR_WIDTH: Address Bus width
+#
+# Valid values:
+# 32-64
+ADDR_WIDTH: 32
+
+#
+# DATA_WIDTH: Data Bus width
+#
+# Valid values:
+# [32,64,128]
+DATA_WIDTH: 128
+
+#
+# CHID_WIDTH: Width of the configurable channel ID user signal.
+# When set to 0, then the archid and awchid ports are not present on the module.
+#
+# Valid values:
+# 0-16
+CHID_WIDTH: 0
+
+#
+# GPO_WIDTH: Width of GPO output for every channel. When multiple channels have GPOs
+# then the width must be set to the maximum number of GPOs a channel can have,
+# and unused GPO ports need to be left unconnected. When all bits of CH_GPO_MASK
+# is 0, this parameter is not relevant.
+#
+# Valid values:
+# 1-32
+GPO_WIDTH: 1
+
+#
+# CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
+# bitmask is NUM_CHANNELS-1. When bit n is set to 1 then the GPO is enabled for
+# channel n and the gpo_ch_n[GPO_WIDTH-1:0] port appears on the module.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_GPO_MASK: 0x0
+
+#
+# CH_STREAM_MASK: A bitmask for enabling the stream interfaces for each channel.
+# The width of the bitmask is NUM_CHANNELS-1. When bit n is set to 1 then
+# the stream interfaces are enabled for channel n and the relevant ports
+# appears on the module. NOTE: When streaming interface is enabled the actual
+# FIFO size of the channel will be the double of CH_<N>_FIFO_DEPTH
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_STREAM_MASK: 0x3
+
+#
+# CH_<N>_FIFO_DEPTH: Sets the FIFO depth for channel <N> that defines the number of
+# DATA_WIDTH size entries a channel can hold for a transfer. N goes from 0 to
+# NUM_CHANNELS-1. In combination with the TRANSIZE setting of the command, the
+# FIFO depth defines the maximum burst size a channel can support. This setting
+# needs to be aligned with the bandwidth requirements of the channel but it
+# highly affects the area of the design.
+#
+# Valid values:
+# [1,2,4,8,16,32,64]
+CH_0_FIFO_DEPTH: 2
+CH_1_FIFO_DEPTH: 2
+
+#
+# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
+# The extension contains 2D, WRAP, TMPLT features. Default value enables it for
+# the number of channels.
+#
+# Valid values:
+# 0-(2^NUM_CHANNELS-1)
+CH_EXT_FEAT_MASK: 0x3
+
+#
+# NUM_CHANNELS: Number of configurable DMA channels.
+#
+# Valid values:
+# 1-8
+NUM_CHANNELS: 2
+
+#
+# NUM_TRIGGER_IN: Number of trigger input ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_IN: 2
+
+#
+# NUM_TRIGGER_OUT: Number of trigger output ports.
+#
+# Valid values:
+# 0-32
+NUM_TRIGGER_OUT: 2
+
+#
+# TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_IN-1.
+# When bit n is set to 1 then the trigger in interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_IN-1)
+TRIG_IN_SYNC_EN_MASK: 0x0
+
+#
+# TRIG_OUT_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger out
+# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_OUT-1.
+# When bit n is set to 1 then the trigger out interface is considered asynchronous
+# and the synchronizer logic is placed on the selected input ports.
+#
+# Valid values:
+# 0-(2^NUM_TRIGGER_OUT-1)
+TRIG_OUT_SYNC_EN_MASK: 0x0
+
+#
+# AXI5_M1_PRESENT: Enables an additional master port. When set the m1 master port is
+# present on the top level port list and additional include file can be used with
+# a System Verilog function that defines which address ranges are mapped to the m1
+# interface.
+#
+# Valid values:
+# [0,1]
+AXI5_M1_PRESENT: 0
+
+#
+# SECEXT_PRESENT: Enables TrustZone security support.
+#
+# Valid values:
+# [0,1]
+SECEXT_PRESENT: 0
+
+
+#
+# AXI5_M1_ADDR_MAP: Select AXI M1 master.
+#
+# Valid values:
+# relative path to logical
+AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_example1.sv
diff --git a/flist/dma350_ip.flist b/flist/dma350_ip.flist
new file mode 100644
index 0000000000000000000000000000000000000000..c94e2fa14096c287942de199b8f53664b2b680ae
--- /dev/null
+++ b/flist/dma350_ip.flist
@@ -0,0 +1,126 @@
+//-----------------------------------------------------------------------------
+// MegaSoC DMA-350 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-350
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= DMA-350 search path =============
++incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_interface_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_flop.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_sync.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_mux2.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_or.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_idbit_v1.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_ecorevnum.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
diff --git a/makefile b/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1096f37e655951c78637377df88a4aba0173cfc5
--- /dev/null
+++ b/makefile
@@ -0,0 +1,46 @@
+#-----------------------------------------------------------------------------
+# MegaSoC Top-Level Makefile
+# - Includes other Makefiles in flow directory
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Flynn (d.w.flynn@soton.ac.uk)
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#-------------------------------------
+# - Commonly Overloaded Variables
+#-------------------------------------
+# Name of test directory - Default Test is Hello World
+TESTNAME ?= hello
+
+# Simulator type (mti/vcs/xm)
+SIMULATOR = mti
+
+# Is an accelerator subsystem present in the design?
+ACCELERATOR ?= yes
+
+#-------------------------------------
+# - Directory Setups
+#-------------------------------------
+# Directory of Testcodes
+TESTCODES_DIR := $(SOCLABS_MEGASOC_TECH_DIR)/testcodes
+
+# Project System Directory
+FPGA_IMP_DIR := $(SOCLABS_PROJECT_DIR)/imp/fpga
+PROJ_SYS_DIR := $(SOCLABS_PROJECT_DIR)/system
+PROJ_SW_DIR ?= $(PROJ_SYS_DIR)/testcodes
+
+# Directory to put simulation files
+SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
+SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
+
+config_dma_axi:
+ @$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_axi.yaml --output ./src/
+config_dma_ahb:
+ @$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb.yaml --output ./src/
+
+clean_ip:
+ @rm -rf ./src/*
\ No newline at end of file
diff --git a/wrapper/logical/sldma350_ahb.v b/wrapper/logical/sldma350_ahb.v
new file mode 100644
index 0000000000000000000000000000000000000000..90317a37bc50ed789c22a4ed8d955f838971d917
--- /dev/null
+++ b/wrapper/logical/sldma350_ahb.v
@@ -0,0 +1,423 @@
+//-----------------------------------------------------------------------------
+// DMA350 wrapper - Contains DMA Controllers with AHB interface
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access l
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+
+module sldma350_ahb #(
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 32,
+ parameter CFG_ADDR_W = 12, // Configuration Port Address Width
+ parameter CHANNEL_NUM = 2 // Number of DMA Channels
+
+ )(
+ // AHB Clocks and Resets
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB Lite Port
+ output wire [SYS_ADDR_W-1:0] HADDR, // Address bus
+ output wire [1:0] HTRANS, // Transfer type
+ output wire HWRITE, // Transfer direction
+ output wire [2:0] HSIZE, // Transfer size
+ output wire [2:0] HBURST, // Burst type
+ output wire [3:0] HPROT, // Protection control
+ output wire [SYS_DATA_W-1:0] HWDATA, // Write data
+ output wire HMASTLOCK, // Locked Sequence
+ input wire [SYS_DATA_W-1:0] HRDATA, // Read data bus
+ input wire HREADY, // HREADY feedback
+ input wire HRESP, // Transfer response
+
+ // APB Configurtation Port
+ input wire PCLKEN, // APB clock enable
+ input wire PSEL, // APB peripheral select
+ input wire PEN, // APB transfer enable
+ input wire PWRITE, // APB transfer direction
+ input wire [CFG_ADDR_W-1:0] PADDR, // APB address
+ input wire [SYS_DATA_W-1:0] PWDATA, // APB write data
+ output wire [SYS_DATA_W-1:0] PRDATA, // APB read data
+
+ // DMA Request and Status Port
+ input wire [CHANNEL_NUM-1:0] DMA_REQ, // DMA transfer request
+ output wire [CHANNEL_NUM-1:0] DMA_DONE, // DMA transfer done
+ output wire DMA_ERR // DMA slave response not OK
+);
+
+
+wire SYS_HRESETn,
+wire DMAC_PCLKen,
+wire DMAC_ACLKen,
+
+// Q Channel Signals
+wire DMAC_CLK_QREQN,
+wire DMAC_CLK_QACCEPTN,
+wire DMAC_CLK_QDENY,
+wire DMAC_CLK_QACTIVE,
+
+// P Channel Signals
+wire DMAC_PREQ,
+wire [3:0] DMAC_PSTATE,
+wire DMAC_PACCEPT,
+wire DMAC_PDENY,
+wire [9:0] DMAC_PACTIVE,
+wire DMAC_PWAKEUP,
+wire DMAC_PDEBUG,
+wire DMAC_PSEL,
+wire DMAC_PENABLE,
+wire [2:0] DMAC_PPROT,
+wire DMAC_PWRITE,
+wire [12:0] DMAC_PADDR,
+wire [31:0] DMAC_PWDATA,
+wire [3:0] DMAC_PSTRB,
+wire DMAC_PREADY,
+wire DMAC_PSLVERR,
+wire [31:0] DMAC_PRDATA,
+// DMAC AXI Port
+wire DMAC_AWAKEUP,
+wire DMAC_AWVALID,
+wire [SYS_ADDR_W-1:0] DMAC_AWADDR,
+wire [1:0] DMAC_AWBURST,
+wire [7:0] DMAC_AWLEN,
+wire [2:0] DMAC_AWSIZE,
+wire [3:0] DMAC_AWQOS,
+wire [2:0] DMAC_AWPROT,
+wire DMAC_AWREADY,
+wire [3:0] DMAC_AWCACHE,
+wire [3:0] DMAC_AWINNER,
+wire [1:0] DMAC_AWDOMAIN,
+
+wire DMAC_ARVALID,
+wire [SYS_ADDR_W-1:0] DMAC_ARADDR,
+wire [1:0] DMAC_ARBURST,
+wire [7:0] DMAC_ARLEN,
+wire [2:0] DMAC_ARSIZE,
+wire [3:0] DMAC_ARQOS,
+wire [2:0] DMAC_ARPROT,
+wire DMAC_ARREADY,
+wire [3:0] DMAC_ARCACHE,
+wire [3:0] DMAC_ARINNER,
+wire [1:0] DMAC_ARDOMAIN,
+wire DMAC_ARCMDLINK,
+
+wire DMAC_WVALID,
+wire DMAC_WLAST,
+wire [16-1:0] DMAC_WSTRB,
+wire [SYS_DATA_W-1:0] DMAC_WDATA,
+wire DMAC_WREADY,
+wire DMAC_RVALID,
+wire DMAC_RLAST,
+wire [SYS_DATA_W-1:0] DMAC_RDATA,
+wire [2-1:0] DMAC_RPOISON,
+wire [1:0] DMAC_RRESP,
+wire DMAC_RREADY,
+
+wire DMAC_BVALID,
+wire [1:0] DMAC_BRESP,
+wire DMAC_BREADY,
+
+// Trigger 0 in
+wire DMAC_TRIG_IN_0_REQ,
+wire [1:0] DMAC_TRIG_IN_0_REQ_TYPE,
+wire DMAC_TRIG_IN_0_ACK,
+wire [1:0] DMAC_TRIG_IN_0_ACK_TYPE,
+wire DMAC_TRIG_IN_1_REQ,
+wire [1:0] DMAC_TRIG_IN_1_REQ_TYPE,
+wire DMAC_TRIG_IN_1_ACK,
+wire [1:0] DMAC_TRIG_IN_1_ACK_TYPE,
+wire DMAC_TRIG_OUT_0_REQ,
+wire DMAC_TRIG_OUT_0_ACK,
+wire DMAC_TRIG_OUT_1_REQ,
+wire DMAC_TRIG_OUT_1_ACK,
+wire [2-1:0] DMAC_IRQ_CHANNEL,
+wire DMAC_IRQ_COMB_NONSEC,
+
+// DMAC Channel 0 AXI stream out
+wire DMAC_STR_OUT_0_TVALID,
+wire DMAC_STR_OUT_0_TREADY,
+wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA,
+wire [16-1:0] DMAC_STR_OUT_0_TSTRB,
+wire DMAC_STR_OUT_0_TLAST,
+
+// DMAC Channel 0 AXI Stream in
+wire DMAC_STR_IN_0_TVALID,
+wire DMAC_STR_IN_0_TREADY,
+wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA,
+wire [16-1:0] DMAC_STR_IN_0_TSTRB,
+wire DMAC_STR_IN_0_TLAST,
+wire DMAC_STR_IN_0_FLUSH,
+
+// DMAC Channel 1 AXI Stream out
+wire DMAC_STR_OUT_1_TVALID,
+wire DMAC_STR_OUT_1_TREADY,
+wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA,
+wire [16-1:0] DMAC_STR_OUT_1_TSTRB,
+wire DMAC_STR_OUT_1_TLAST,
+
+// DMAC Channel 1 AXI Stream out
+wire DMAC_STR_IN_1_TVALID,
+wire DMAC_STR_IN_1_TREADY,
+wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA,
+wire [16-1:0] DMAC_STR_IN_1_TSTRB,
+wire DMAC_STR_IN_1_TLAST,
+wire DMAC_STR_IN_1_FLUSH,
+wire DMAC_ALLCH_STOP_REQ_NONSEC,
+wire DMAC_ALLCH_STOP_ACK_NONSEC,
+wire DMAC_ALLCH_PAUSE_REQ_NONSEC,
+wire DMAC_ALLCH_PAUSE_ACK_NONSEC,
+wire [2-1:0] DMAC_CH_ENABLED,
+wire [2-1:0] DMAC_CH_ERR,
+wire [2-1:0] DMAC_CH_STOPPED,
+wire [2-1:0] DMAC_CH_PAUSED,
+wire [2-1:0] DMAC_CH_PRIV,
+
+wire DMAC_HALT_REQ,
+wire DMAC_RESTART_REQ,
+wire DMAC_HALTED,
+wire DMAC_BOOT_EN,
+wire [32-1:2] DMAC_BOOT_ADDR,
+wire [ 7:0] DMAC_BOOT_MEMATTR,
+wire [ 1:0] DMAC_BOOT_SHAREATTR
+
+// -------------------------------
+// DMA Controller Instantiation
+// -------------------------------
+ada_top_sldma350 u_dmac_0(
+ // Clock and Reset signals
+ .clk(HCLK),
+ .resetn(HRESETn),
+ .aclken_m0(DMAC_ACLKen),
+ .pclken(PCLKEN),
+ // Q Channel signals
+ .clk_qreqn(DMAC_CLK_QREQN),
+ .clk_qacceptn(DMAC_CLK_QACCEPTN),
+ .clk_qdeny(DMAC_CLK_QDENY),
+ .clk_qactive(DMAC_CLK_QACTIVE),
+ // P Channel Signals
+ .preq(DMAC_PREQ),
+ .pstate(DMAC_PSTATE),
+ .paccept(DMAC_PACCEPT),
+ .pdeny(DMAC_PDENY),
+ .pactive(DMAC_PACTIVE),
+
+ .pwakeup(DMAC_PWAKEUP),
+ .pdebug(DMAC_PDEBUG),
+ .psel(PSEL),
+ .penable(PEN),
+ .pprot(DMAC_PPROT),
+ .pwrite(PWRITE),
+ .paddr(PADDR),
+ .pwdata(PWDATA),
+ .pstrb(DMAC_PSTRB),
+ .pready(DMAC_PREADY),
+ .pslverr(DMAC_PSLVERR),
+ .prdata(PRDATA),
+ // AXI Write Channel Signals
+ .awakeup_m0(DMAC_AWAKEUP),
+ .awvalid_m0(DMAC_AWVALID),
+ .awaddr_m0(DMAC_AWADDR),
+ .awburst_m0(DMAC_AWBURST),
+ .awid_m0(),
+ .awlen_m0(DMAC_AWLEN),
+ .awsize_m0(DMAC_AWSIZE),
+ .awqos_m0(DMAC_AWQOS),
+ .awprot_m0(DMAC_AWPROT),
+ .awready_m0(DMAC_AWREADY),
+ .awcache_m0(DMAC_AWCACHE),
+ .awinner_m0(DMAC_AWINNER),
+ .awdomain_m0(DMAC_AWDOMAIN),
+ // AXI Read Channel Signals
+ .arvalid_m0(DMAC_ARVALID),
+ .araddr_m0(DMAC_ARADDR),
+ .arburst_m0(DMAC_ARBURST),
+ .arid_m0(),
+ .arlen_m0(DMAC_ARLEN),
+ .arsize_m0(DMAC_ARSIZE),
+ .arqos_m0(DMAC_ARQOS),
+ .arprot_m0(DMAC_ARPROT),
+ .arready_m0(DMAC_ARREADY),
+ .arcache_m0(DMAC_ARCACHE),
+ .arinner_m0(DMAC_ARINNER),
+ .ardomain_m0(DMAC_ARDOMAIN),
+ .arcmdlink_m0(DMAC_ARCMDLINK),
+ // AXI Write Data Signals
+ .wvalid_m0(DMAC_WVALID),
+ .wlast_m0(DMAC_WLAST),
+ .wstrb_m0(DMAC_WSTRB),
+ .wdata_m0(DMAC_WDATA),
+ .wready_m0(DMAC_WREADY),
+ // AXI Read Data Signals
+ .rvalid_m0(DMAC_RVALID),
+ .rid_m0(),
+ .rlast_m0(DMAC_RLAST),
+ .rdata_m0(DMAC_RDATA),
+ .rpoison_m0(DMAC_RPOISON),
+ .rresp_m0(DMAC_RRESP),
+ .rready_m0(DMAC_RREADY),
+ // AXI Write response signals
+ .bvalid_m0(DMAC_BVALID),
+ .bid_m0(),
+ .bresp_m0(DMAC_BRESP),
+ .bready_m0(DMAC_BREADY),
+ // Trigger 0 in
+ .trig_in_0_req(DMAC_TRIG_IN_0_REQ),
+ .trig_in_0_req_type(DMAC_TRIG_IN_0_REQ_TYPE),
+ .trig_in_0_ack(DMAC_TRIG_IN_0_ACK),
+ .trig_in_0_ack_type(DMAC_TRIG_IN_0_ACK_TYPE),
+ // Trigger 1 in
+ .trig_in_1_req(DMAC_TRIG_IN_1_REQ),
+ .trig_in_1_req_type(DMAC_TRIG_IN_1_REQ_TYPE),
+ .trig_in_1_ack(DMAC_TRIG_IN_1_ACK),
+ .trig_in_1_ack_type(DMAC_TRIG_IN_1_ACK_TYPE),
+ // Trigger 0 out
+ .trig_out_0_req(DMAC_TRIG_OUT_0_REQ),
+ .trig_out_0_ack(DMAC_TRIG_OUT_0_ACK),
+ // Trigger 1 out
+ .trig_out_1_req(DMAC_TRIG_OUT_1_REQ),
+ .trig_out_1_ack(DMAC_TRIG_OUT_1_ACK),
+ // Interrupt Signals
+ .irq_channel(DMAC_IRQ_CHANNEL),
+ .irq_comb_nonsec(DMAC_IRQ_COMB_NONSEC),
+ // AXI Stream 0 out
+ .str_out_0_tvalid(DMAC_STR_OUT_0_TVALID),
+ .str_out_0_tready(DMAC_STR_OUT_0_TREADY),
+ .str_out_0_tdata(DMAC_STR_OUT_0_TDATA),
+ .str_out_0_tstrb(DMAC_STR_OUT_0_TSTRB),
+ .str_out_0_tlast(DMAC_STR_OUT_0_TLAST),
+ // AXI Stream 0 In
+ .str_in_0_tvalid(DMAC_STR_IN_0_TVALID),
+ .str_in_0_tready(DMAC_STR_IN_0_TREADY),
+ .str_in_0_tdata(DMAC_STR_IN_0_TDATA),
+ .str_in_0_tstrb(DMAC_STR_IN_0_TSTRB),
+ .str_in_0_tlast(DMAC_STR_IN_0_TLAST),
+ .str_in_0_flush(DMAC_STR_IN_0_FLUSH),
+ // AXI Stream 1 out
+ .str_out_1_tvalid(DMAC_STR_OUT_1_TVALID),
+ .str_out_1_tready(DMAC_STR_OUT_1_TREADY),
+ .str_out_1_tdata(DMAC_STR_OUT_1_TDATA),
+ .str_out_1_tstrb(DMAC_STR_OUT_1_TSTRB),
+ .str_out_1_tlast(DMAC_STR_OUT_1_TLAST),
+ // AXI Stream 1 in
+ .str_in_1_tvalid(DMAC_STR_IN_1_TVALID),
+ .str_in_1_tready(DMAC_STR_IN_1_TREADY),
+ .str_in_1_tdata(DMAC_STR_IN_1_TDATA),
+ .str_in_1_tstrb(DMAC_STR_IN_1_TSTRB),
+ .str_in_1_tlast(DMAC_STR_IN_1_TLAST),
+ .str_in_1_flush(DMAC_STR_IN_1_FLUSH),
+
+ .allch_stop_req_nonsec(DMAC_ALLCH_STOP_REQ_NONSEC),
+ .allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC),
+ .allch_pause_req_nonsec(DMAC_ALLCH_PAUSE_REQ_NONSEC),
+ .allch_pause_ack_nonsec(DMAC_ALLCH_PAUSE_ACK_NONSEC),
+ .ch_enabled(DMAC_CH_ENABLED),
+ .ch_err(DMAC_CH_ERR),
+ .ch_stopped(DMAC_CH_STOPPED),
+ .ch_paused(DMAC_CH_PAUSED),
+ .ch_priv(DMAC_CH_PRIV),
+ .halt_req(DMAC_HALT_REQ),
+ .restart_req(DMAC_RESTART_REQ),
+ .halted(DMAC_HALTED),
+ .boot_en(DMAC_BOOT_EN),
+ .boot_addr(DMAC_BOOT_ADDR),
+ .boot_memattr(DMAC_BOOT_MEMATTR),
+ .boot_shareattr(DMAC_BOOT_SHAREATTR)
+);
+
+xhb400 #(.DATA_WIDTH(SYS_DATA_W))
+(
+ //-----------------------------------------------------------------------------
+ // Clock and Reset
+ //-----------------------------------------------------------------------------
+
+ .CLK(HCLK),
+ .nSYSRESET(HRESETn),
+ //-----------------------------------------------------------------------------
+ // AXI Master Interface
+ //-----------------------------------------------------------------------------
+
+ // Write Address Channel signals
+ .AWADDR(DMAC_AWADDR),
+ .AWBURST(DMAC_AWBURST),
+ .AWID(),
+ .AWLEN(DMAC_AWLEN),
+ .AWSIZE(DMAC_AWSIZE),
+ .AWLOCK(),
+ .AWPROT(DMAC_AWPROT),
+ .AWCACHE(DMAC_AWCACHE),
+ .AWUSER(),
+ .AWSPARSE(),
+ .AWVALID(DMAC_AWVALID),
+ .AWREADY(DMAC_AWREADY),
+
+// Read Address Channel signals
+ .ARADDR(DMAC_ARADDR),
+ .ARBURST(DMAC_ARBURST),
+ .ARID(),
+ .ARLEN(DMAC_ARLEN),
+ .ARSIZE(DMAC_ARSIZE),
+ .ARLOCK(),
+ .ARPROT(DMAC_ARPROT),
+ .ARCACHE(DMAC_ARCACHE),
+ .ARUSER(),
+ .ARVALID(DMAC_ARVALID),
+ .ARREADY(DMAC_ARREADY),
+
+// Write Data Channel signals
+ .WLAST(DMAC_WLAST),
+ .WSTRB(DMAC_WSTRB),
+ .WDATA(DMAC_WDATA),
+ .WUSER(),
+ .WVALID(DMAC_WVALID),
+ .WREADY(DMAC_WREADY),
+
+// Read Data Channel signals
+ .RREADY(DMAC_RREADY),
+ .RVALID(DMAC_RVALID),
+ .RID(),
+ .RLAST(DMAC_RLAST),
+ .RDATA(DMAC_RDATA),
+ .RUSER(),
+ .RRESP(DMAC_RRESP),
+
+// Write Response Channel signals
+ .BREADY(DMAC_BREADY),
+ .BVALID(DMAC_BVALID),
+ .BID(),
+ .BRESP(DMAC_BRESP),
+
+
+//-----------------------------------------------------------------------------
+// AHB-Lite Slave Interface
+//-----------------------------------------------------------------------------
+
+// AHB-Lite Master signals
+ .HTRANS(HTRANS),
+ .HBURST(HBURST),
+ .HADDR(HADDR),
+ .HWRITE(HWRITE),
+ .HSIZE(HSIZE),
+ .HWDATA(HWDATA),
+ .HPROT(HPROT),
+ .HMASTLOCK(HMASTLOCK),
+
+// AHB-Lite Slave Response signals
+ .HREADY(HREADY),
+ .HRDATA(HRDATA),
+ .HRESP(HRESP),
+
+// Non-standard Exclusive Access signals
+ .EXREQ,
+ .EXRESP,
+
+// Sideband AHB USER signals
+ .HAUSER,
+ .HWUSER,
+ .HRUSER
+);
+
+endmodule
diff --git a/wrapper/logical/sldma350_axi.v b/wrapper/logical/sldma350_axi.v
new file mode 100644
index 0000000000000000000000000000000000000000..b384777096713491d086d6468cfcb54cda7e26a1
--- /dev/null
+++ b/wrapper/logical/sldma350_axi.v
@@ -0,0 +1,301 @@
+//-----------------------------------------------------------------------------
+// DMA350 wrapper - Contains DMA Controllers with AXI interface
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access l
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module sldma350_axi #(
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 128
+)(
+ input wire SYS_HCLK,
+ input wire SYS_HRESETn,
+ input wire DMAC_PCLKen,
+ input wire DMAC_ACLKen,
+
+ // Q Channel Signals
+ input wire DMAC_CLK_QREQN,
+ output wire DMAC_CLK_QACCEPTN,
+ output wire DMAC_CLK_QDENY,
+ output wire DMAC_CLK_QACTIVE,
+
+ // P Channel Signals
+ input wire DMAC_PREQ,
+ input wire [3:0] DMAC_PSTATE,
+ output wire DMAC_PACCEPT,
+ output wire DMAC_PDENY,
+ output wire [9:0] DMAC_PACTIVE,
+ input wire DMAC_PWAKEUP,
+ input wire DMAC_PDEBUG,
+ input wire DMAC_PSEL,
+ input wire DMAC_PENABLE,
+ input wire [2:0] DMAC_PPROT,
+ input wire DMAC_PWRITE,
+ input wire [12:0] DMAC_PADDR,
+ input wire [31:0] DMAC_PWDATA,
+ input wire [3:0] DMAC_PSTRB,
+ output wire DMAC_PREADY,
+ output wire DMAC_PSLVERR,
+ output wire [31:0] DMAC_PRDATA,
+ // DMAC AXI Port
+ output wire DMAC_AWAKEUP,
+ output wire DMAC_AWVALID,
+ output wire [SYS_ADDR_W-1:0] DMAC_AWADDR,
+ output wire [1:0] DMAC_AWBURST,
+ output wire [7:0] DMAC_AWLEN,
+ output wire [2:0] DMAC_AWSIZE,
+ output wire [3:0] DMAC_AWQOS,
+ output wire [2:0] DMAC_AWPROT,
+ input wire DMAC_AWREADY,
+ output wire [3:0] DMAC_AWCACHE,
+ output wire [3:0] DMAC_AWINNER,
+ output wire [1:0] DMAC_AWDOMAIN,
+
+ output wire DMAC_ARVALID,
+ output wire [SYS_ADDR_W-1:0] DMAC_ARADDR,
+ output wire [1:0] DMAC_ARBURST,
+ output wire [7:0] DMAC_ARLEN,
+ output wire [2:0] DMAC_ARSIZE,
+ output wire [3:0] DMAC_ARQOS,
+ output wire [2:0] DMAC_ARPROT,
+ input wire DMAC_ARREADY,
+ output wire [3:0] DMAC_ARCACHE,
+ output wire [3:0] DMAC_ARINNER,
+ output wire [1:0] DMAC_ARDOMAIN,
+ output wire DMAC_ARCMDLINK,
+
+ output wire DMAC_WVALID,
+ output wire DMAC_WLAST,
+ output wire [16-1:0] DMAC_WSTRB,
+ output wire [SYS_DATA_W-1:0] DMAC_WDATA,
+ input wire DMAC_WREADY,
+
+ input wire DMAC_RVALID,
+ input wire DMAC_RLAST,
+ input wire [SYS_DATA_W-1:0] DMAC_RDATA,
+ input wire [2-1:0] DMAC_RPOISON,
+ input wire [1:0] DMAC_RRESP,
+ output wire DMAC_RREADY,
+
+ input wire DMAC_BVALID,
+ input wire [1:0] DMAC_BRESP,
+ output wire DMAC_BREADY,
+
+ // Trigger 0 in
+ input wire DMAC_TRIG_IN_0_REQ,
+ input wire [1:0] DMAC_TRIG_IN_0_REQ_TYPE,
+ output wire DMAC_TRIG_IN_0_ACK,
+ output wire [1:0] DMAC_TRIG_IN_0_ACK_TYPE,
+ input wire DMAC_TRIG_IN_1_REQ,
+ input wire [1:0] DMAC_TRIG_IN_1_REQ_TYPE,
+ output wire DMAC_TRIG_IN_1_ACK,
+ output wire [1:0] DMAC_TRIG_IN_1_ACK_TYPE,
+ output wire DMAC_TRIG_OUT_0_REQ,
+ input wire DMAC_TRIG_OUT_0_ACK,
+ output wire DMAC_TRIG_OUT_1_REQ,
+ input wire DMAC_TRIG_OUT_1_ACK,
+ output wire [2-1:0] DMAC_IRQ_CHANNEL,
+ output wire DMAC_IRQ_COMB_NONSEC,
+
+ // DMAC Channel 0 AXI stream out
+ output wire DMAC_STR_OUT_0_TVALID,
+ input wire DMAC_STR_OUT_0_TREADY,
+ output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA,
+ output wire [16-1:0] DMAC_STR_OUT_0_TSTRB,
+ output wire DMAC_STR_OUT_0_TLAST,
+
+ // DMAC Channel 0 AXI Stream in
+ input wire DMAC_STR_IN_0_TVALID,
+ output wire DMAC_STR_IN_0_TREADY,
+ input wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA,
+ input wire [16-1:0] DMAC_STR_IN_0_TSTRB,
+ input wire DMAC_STR_IN_0_TLAST,
+ output wire DMAC_STR_IN_0_FLUSH,
+
+ // DMAC Channel 1 AXI Stream out
+ output wire DMAC_STR_OUT_1_TVALID,
+ input wire DMAC_STR_OUT_1_TREADY,
+ output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA,
+ output wire [16-1:0] DMAC_STR_OUT_1_TSTRB,
+ output wire DMAC_STR_OUT_1_TLAST,
+
+ // DMAC Channel 1 AXI Stream out
+ input wire DMAC_STR_IN_1_TVALID,
+ output wire DMAC_STR_IN_1_TREADY,
+ input wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA,
+ input wire [16-1:0] DMAC_STR_IN_1_TSTRB,
+ input wire DMAC_STR_IN_1_TLAST,
+ output wire DMAC_STR_IN_1_FLUSH,
+
+ input wire DMAC_ALLCH_STOP_REQ_NONSEC,
+ output wire DMAC_ALLCH_STOP_ACK_NONSEC,
+ input wire DMAC_ALLCH_PAUSE_REQ_NONSEC,
+ output wire DMAC_ALLCH_PAUSE_ACK_NONSEC,
+ output wire [2-1:0] DMAC_CH_ENABLED,
+ output wire [2-1:0] DMAC_CH_ERR,
+ output wire [2-1:0] DMAC_CH_STOPPED,
+ output wire [2-1:0] DMAC_CH_PAUSED,
+ output wire [2-1:0] DMAC_CH_PRIV,
+
+ input wire DMAC_HALT_REQ,
+ input wire DMAC_RESTART_REQ,
+ output wire DMAC_HALTED,
+
+ input wire DMAC_BOOT_EN,
+ input wire [32-1:2] DMAC_BOOT_ADDR,
+ input wire [ 7:0] DMAC_BOOT_MEMATTR,
+ input wire [ 1:0] DMAC_BOOT_SHAREATTR
+);
+
+// -------------------------------
+// DMA Controller Instantiation
+// -------------------------------
+ada_top_sldma350 u_dmac_0(
+ // Clock and Reset signals
+ .clk(SYS_HCLK),
+ .resetn(SYS_HRESETn),
+ .aclken_m0(DMAC_ACLKen),
+ .pclken(DMAC_PCLKen),
+ // Q Channel signals
+ .clk_qreqn(DMAC_CLK_QREQN),
+ .clk_qacceptn(DMAC_CLK_QACCEPTN),
+ .clk_qdeny(DMAC_CLK_QDENY),
+ .clk_qactive(DMAC_CLK_QACTIVE),
+ // P Channel Signals
+ .preq(DMAC_PREQ),
+ .pstate(DMAC_PSTATE),
+ .paccept(DMAC_PACCEPT),
+ .pdeny(DMAC_PDENY),
+ .pactive(DMAC_PACTIVE),
+
+ .pwakeup(DMAC_PWAKEUP),
+ .pdebug(DMAC_PDEBUG),
+ .psel(DMAC_PSEL),
+ .penable(DMAC_PENABLE),
+ .pprot(DMAC_PPROT),
+ .pwrite(DMAC_PWRITE),
+ .paddr(DMAC_PADDR),
+ .pwdata(DMAC_PWDATA),
+ .pstrb(DMAC_PSTRB),
+ .pready(DMAC_PREADY),
+ .pslverr(DMAC_PSLVERR),
+ .prdata(DMAC_PRDATA),
+ // AXI Write Channel Signals
+ .awakeup_m0(DMAC_AWAKEUP),
+ .awvalid_m0(DMAC_AWVALID),
+ .awaddr_m0(DMAC_AWADDR),
+ .awburst_m0(DMAC_AWBURST),
+ .awid_m0(),
+ .awlen_m0(DMAC_AWLEN),
+ .awsize_m0(DMAC_AWSIZE),
+ .awqos_m0(DMAC_AWQOS),
+ .awprot_m0(DMAC_AWPROT),
+ .awready_m0(DMAC_AWREADY),
+ .awcache_m0(DMAC_AWCACHE),
+ .awinner_m0(DMAC_AWINNER),
+ .awdomain_m0(DMAC_AWDOMAIN),
+ // AXI Read Channel Signals
+ .arvalid_m0(DMAC_ARVALID),
+ .araddr_m0(DMAC_ARADDR),
+ .arburst_m0(DMAC_ARBURST),
+ .arid_m0(),
+ .arlen_m0(DMAC_ARLEN),
+ .arsize_m0(DMAC_ARSIZE),
+ .arqos_m0(DMAC_ARQOS),
+ .arprot_m0(DMAC_ARPROT),
+ .arready_m0(DMAC_ARREADY),
+ .arcache_m0(DMAC_ARCACHE),
+ .arinner_m0(DMAC_ARINNER),
+ .ardomain_m0(DMAC_ARDOMAIN),
+ .arcmdlink_m0(DMAC_ARCMDLINK),
+ // AXI Write Data Signals
+ .wvalid_m0(DMAC_WVALID),
+ .wlast_m0(DMAC_WLAST),
+ .wstrb_m0(DMAC_WSTRB),
+ .wdata_m0(DMAC_WDATA),
+ .wready_m0(DMAC_WREADY),
+ // AXI Read Data Signals
+ .rvalid_m0(DMAC_RVALID),
+ .rid_m0(),
+ .rlast_m0(DMAC_RLAST),
+ .rdata_m0(DMAC_RDATA),
+ .rpoison_m0(DMAC_RPOISON),
+ .rresp_m0(DMAC_RRESP),
+ .rready_m0(DMAC_RREADY),
+ // AXI Write response signals
+ .bvalid_m0(DMAC_BVALID),
+ .bid_m0(),
+ .bresp_m0(DMAC_BRESP),
+ .bready_m0(DMAC_BREADY),
+ // Trigger 0 in
+ .trig_in_0_req(DMAC_TRIG_IN_0_REQ),
+ .trig_in_0_req_type(DMAC_TRIG_IN_0_REQ_TYPE),
+ .trig_in_0_ack(DMAC_TRIG_IN_0_ACK),
+ .trig_in_0_ack_type(DMAC_TRIG_IN_0_ACK_TYPE),
+ // Trigger 1 in
+ .trig_in_1_req(DMAC_TRIG_IN_1_REQ),
+ .trig_in_1_req_type(DMAC_TRIG_IN_1_REQ_TYPE),
+ .trig_in_1_ack(DMAC_TRIG_IN_1_ACK),
+ .trig_in_1_ack_type(DMAC_TRIG_IN_1_ACK_TYPE),
+ // Trigger 0 out
+ .trig_out_0_req(DMAC_TRIG_OUT_0_REQ),
+ .trig_out_0_ack(DMAC_TRIG_OUT_0_ACK),
+ // Trigger 1 out
+ .trig_out_1_req(DMAC_TRIG_OUT_1_REQ),
+ .trig_out_1_ack(DMAC_TRIG_OUT_1_ACK),
+ // Interrupt Signals
+ .irq_channel(DMAC_IRQ_CHANNEL),
+ .irq_comb_nonsec(DMAC_IRQ_COMB_NONSEC),
+ // AXI Stream 0 out
+ .str_out_0_tvalid(DMAC_STR_OUT_0_TVALID),
+ .str_out_0_tready(DMAC_STR_OUT_0_TREADY),
+ .str_out_0_tdata(DMAC_STR_OUT_0_TDATA),
+ .str_out_0_tstrb(DMAC_STR_OUT_0_TSTRB),
+ .str_out_0_tlast(DMAC_STR_OUT_0_TLAST),
+ // AXI Stream 0 In
+ .str_in_0_tvalid(DMAC_STR_IN_0_TVALID),
+ .str_in_0_tready(DMAC_STR_IN_0_TREADY),
+ .str_in_0_tdata(DMAC_STR_IN_0_TDATA),
+ .str_in_0_tstrb(DMAC_STR_IN_0_TSTRB),
+ .str_in_0_tlast(DMAC_STR_IN_0_TLAST),
+ .str_in_0_flush(DMAC_STR_IN_0_FLUSH),
+ // AXI Stream 1 out
+ .str_out_1_tvalid(DMAC_STR_OUT_1_TVALID),
+ .str_out_1_tready(DMAC_STR_OUT_1_TREADY),
+ .str_out_1_tdata(DMAC_STR_OUT_1_TDATA),
+ .str_out_1_tstrb(DMAC_STR_OUT_1_TSTRB),
+ .str_out_1_tlast(DMAC_STR_OUT_1_TLAST),
+ // AXI Stream 1 in
+ .str_in_1_tvalid(DMAC_STR_IN_1_TVALID),
+ .str_in_1_tready(DMAC_STR_IN_1_TREADY),
+ .str_in_1_tdata(DMAC_STR_IN_1_TDATA),
+ .str_in_1_tstrb(DMAC_STR_IN_1_TSTRB),
+ .str_in_1_tlast(DMAC_STR_IN_1_TLAST),
+ .str_in_1_flush(DMAC_STR_IN_1_FLUSH),
+
+ .allch_stop_req_nonsec(DMAC_ALLCH_STOP_REQ_NONSEC),
+ .allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC),
+ .allch_pause_req_nonsec(DMAC_ALLCH_PAUSE_REQ_NONSEC),
+ .allch_pause_ack_nonsec(DMAC_ALLCH_PAUSE_ACK_NONSEC),
+ .ch_enabled(DMAC_CH_ENABLED),
+ .ch_err(DMAC_CH_ERR),
+ .ch_stopped(DMAC_CH_STOPPED),
+ .ch_paused(DMAC_CH_PAUSED),
+ .ch_priv(DMAC_CH_PRIV),
+ .halt_req(DMAC_HALT_REQ),
+ .restart_req(DMAC_RESTART_REQ),
+ .halted(DMAC_HALTED),
+ .boot_en(DMAC_BOOT_EN),
+ .boot_addr(DMAC_BOOT_ADDR),
+ .boot_memattr(DMAC_BOOT_MEMATTR),
+ .boot_shareattr(DMAC_BOOT_SHAREATTR)
+);
+
+
+
+endmodule
\ No newline at end of file