diff --git a/flist/cortexm0_ip.flist b/flist/cortexm0_ip.flist
index 24db235510cc31983e41e89302a80b70eefacec3..b189b983be630103e4d5bebe627960f5f89f1a57 100644
--- a/flist/cortexm0_ip.flist
+++ b/flist/cortexm0_ip.flist
@@ -16,12 +16,12 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+-incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
 
 // Cortex-M0 Core IP
 // -y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog