diff --git a/src/verilog/slcorem0_integration.v b/src/verilog/slcorem0_integration.v
index 4698c15a70ee50a73a70a191fce5d53fd40f8740..78748de652ae44e46ef52becc1f3c92dce3c264d 100644
--- a/src/verilog/slcorem0_integration.v
+++ b/src/verilog/slcorem0_integration.v
@@ -170,7 +170,11 @@ module slcorem0_integration
      input  wire        SE,
      input  wire        RSTBYPASS
      );
-
+   // ------------------------------------------------------------
+   // ROM Table Value Calculation
+   // ------------------------------------------------------------
+   wire    [31:0] ROMTABLE_VAL;
+   assign         ROMTABLE_VAL = {ROMTABLE_BASE[31:2],2'd3};
    // ------------------------------------------------------------
    // Configurability
    // ------------------------------------------------------------
@@ -379,7 +383,7 @@ module slcorem0_integration
           .SLVRDATA                       (slv_rdata_dap[31:0]),
           .SLVREADY                       (slv_ready_dap),
           .SLVRESP                        (slv_resp_dap),
-          .BASEADDR                       (ROMTABLE_BASE + 32'h00000003),
+          .BASEADDR                       (ROMTABLE_VAL),
           .ECOREVNUM                      (ECOREVNUM[27:20]),
           .SE                             (SE)
           );