From 8d4d1ca205c942d1676180055dd93f5a49f4f7f7 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 15 Jun 2023 10:17:26 +0100
Subject: [PATCH] SOC1-230: Created SLCore repo and added core wrappers to this
repo
---
README.md | 92 +----------
flist/slcorem0.flist | 22 +++
src/verilog/slcorem0.v | 264 +++++++++++++++++++++++++++++++
src/verilog/slcorem0_prmu.v | 155 ++++++++++++++++++
src/verilog/slcorem0_rstctrl.v | 138 ++++++++++++++++
src/verilog/slcorem0_stclkctrl.v | 89 +++++++++++
6 files changed, 670 insertions(+), 90 deletions(-)
create mode 100644 flist/slcorem0.flist
create mode 100644 src/verilog/slcorem0.v
create mode 100644 src/verilog/slcorem0_prmu.v
create mode 100644 src/verilog/slcorem0_rstctrl.v
create mode 100644 src/verilog/slcorem0_stclkctrl.v
diff --git a/README.md b/README.md
index f33d023..9952a98 100644
--- a/README.md
+++ b/README.md
@@ -1,92 +1,4 @@
# SLCore M0 Tech
-
-
-## Getting started
-
-To make it easy for you to get started with GitLab, here's a list of recommended next steps.
-
-Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
-
-## Add your files
-
-- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
-- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
-
-```
-cd existing_repo
-git remote add origin https://git.soton.ac.uk/soclabs/slcore_m0_tech.git
-git branch -M main
-git push -uf origin main
-```
-
-## Integrate with your tools
-
-- [ ] [Set up project integrations](https://git.soton.ac.uk/soclabs/slcore_m0_tech/-/settings/integrations)
-
-## Collaborate with your team
-
-- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
-- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
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-- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
-- [ ] [Automatically merge when pipeline succeeds](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
-
-## Test and Deploy
-
-Use the built-in continuous integration in GitLab.
-
-- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
-- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing(SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
-- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
-- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
-- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
-
-***
-
-# Editing this README
-
-When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thank you to [makeareadme.com](https://www.makeareadme.com/) for this template.
-
-## Suggestions for a good README
-Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
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-## Name
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-## Description
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-## Badges
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-
-## Installation
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-
-## Usage
-Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README.
-
-## Support
-Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc.
-
-## Roadmap
-If you have ideas for releases in the future, it is a good idea to list them in the README.
-
-## Contributing
-State if you are open to contributions and what your requirements are for accepting them.
-
-For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self.
-
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-
-## Authors and acknowledgment
-Show your appreciation to those who have contributed to the project.
-
-## License
-For open source projects, say how it is licensed.
-
-## Project status
-If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
+## SLCore-M0
+SLCore M0 is a SoCLabs custom wrapper around the Arm Cortex-M0 designed to be integrated within the NanoSoC SoC.
\ No newline at end of file
diff --git a/flist/slcorem0.flist b/flist/slcorem0.flist
new file mode 100644
index 0000000..2512ee2
--- /dev/null
+++ b/flist/slcorem0.flist
@@ -0,0 +1,22 @@
+//-----------------------------------------------------------------------------
+// SLCore-M0 IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Bus Matrix IP search path =============
+$(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0.v
+$(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_prmu.v
+$(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_stclkctrl.v
+$(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_rstctrl.v
\ No newline at end of file
diff --git a/src/verilog/slcorem0.v b/src/verilog/slcorem0.v
new file mode 100644
index 0000000..caea7c2
--- /dev/null
+++ b/src/verilog/slcorem0.v
@@ -0,0 +1,264 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 - Basic Cortex-M0 CPU Subsystem
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module slcorem0 #(
+ parameter CLKGATE_PRESENT = 0,
+ parameter BE = 0, // 1: Big endian 0: little endian
+ parameter BKPT = 4, // Number of breakpoint comparators
+ parameter DBG = 1, // Debug configuration
+ parameter NUMIRQ = 32, // NUM of IRQ
+ parameter SMUL = 0, // Multiplier configuration
+ parameter SYST = 1, // SysTick
+ parameter WIC = 1, // Wake-up interrupt controller support
+ parameter WICLINES = 34, // Supported WIC lines
+ parameter WPT = 2, // Number of DWT comparators
+ parameter RESET_ALL_REGS = 0, // Do not reset all registers
+ parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
+)(
+ // System Input Clocks and Resets
+ input wire SYS_FCLK, // Free running clock
+ input wire SYS_SYSRESETn, // System Reset
+ input wire SYS_SCANENABLE, // Scan Mode Enable
+ input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // System Reset Request Signals
+ input wire SYS_SYSRESETREQ, // System Request from System Managers
+ output wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
+
+ // Generated Clocks and Resets
+ output wire SYS_PORESETn, // System Power On Reset
+ output wire SYS_HCLK, // AHB Clock
+ output wire SYS_HRESETn, // AHB and System reset
+
+ // Power Management Signals
+ input wire SYS_PMUENABLE, // Power Management Enable
+ output wire SYS_PMUDBGRESETREQ, // Power Management Debug Reset Req
+
+ // AHB Lite port
+ output wire [31:0] HADDR, // Address bus
+ output wire [1:0] HTRANS, // Transfer type
+ output wire HWRITE, // Transfer direction
+ output wire [2:0] HSIZE, // Transfer size
+ output wire [2:0] HBURST, // Burst type
+ output wire [3:0] HPROT, // Protection control
+ output wire [31:0] HWDATA, // Write data
+ output wire HMASTLOCK, // Locked Sequence
+ input wire [31:0] HRDATA, // Read data bus
+ input wire HREADY, // HREADY feedback
+ input wire HRESP, // Transfer response
+
+ // Sideband CPU signalling
+ input wire CORE_NMI, // Non-Maskable Interrupt request
+ input wire [31:0] CORE_IRQ, // Maskable Interrupt requests
+ output wire CORE_TXEV, // Send Event (SEV) output
+ input wire CORE_RXEV, // Receive Event input
+ output wire CORE_LOCKUP, // Wake up request from WIC
+ output wire CORE_SYSRESETREQ, // System reset request
+
+ output wire CORE_SLEEPING, // Processor status - sleeping
+ output wire CORE_SLEEPDEEP, // Processor status - deep sleep
+
+ // Serial-Wire Debug
+ input wire CORE_SWDI, // SWD data input
+ input wire CORE_SWCLK, // SWD clock
+ output wire CORE_SWDO, // SWD data output
+ output wire CORE_SWDOEN // SWD data output enable
+);
+
+ // ---------------------------------------------------
+ // Cortex-M0 Power Management and Reset Control Unit
+ // ---------------------------------------------------
+ // Cortex-M0 Control to Core Connectivity
+ wire CORE_GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
+ wire CORE_WAKEUP; // Wake-up Signaling from Core
+ wire CORE_CDBGPWRUPREQ; // Core Debug Power Up Request
+ wire CORE_CDBGPWRUPACK; // Core Debug Power Up Acknowledge
+ wire CORE_WICENREQ; // WIC enable request from PMU
+ wire CORE_WICENACK; // Wake-on-Interrupt Enable ACK from Core
+ wire CORE_SLEEPHOLDREQn; // Core Sleep Hold Request
+ wire CORE_SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
+
+ // Internal Clock Signals
+ wire CORE_HCLK; // AHB Clock
+ wire CORE_HRESETn; // AHB and System reset
+ wire CORE_SCLK; // System clock
+ wire CORE_DCLK; // Debug clock
+ wire CORE_DBGRESETn; // Debug reset
+
+ // Cortex-M0 Control Instantiation
+ slcorem0_prmu #(
+ .CLKGATE_PRESENT(CLKGATE_PRESENT)
+ ) u_core_prmu (
+ // Input Clocks and Resets
+ .SYS_FCLK (SYS_FCLK), // Free running clock
+ .SYS_SYSRESETn (SYS_SYSRESETn), // System Reset
+ .SYS_SCANENABLE (SYS_SCANENABLE), // Scan Mode Enable
+ .SYS_TESTMODE (SYS_TESTMODE), // Test Mode Enable (Override Synchronisers)
+
+ // Core Generated Clocks and Resets
+ .CORE_SCLK (CORE_SCLK), // Core-Subsystem clock
+ .CORE_HCLK (CORE_HCLK), // Core AHB Clock
+ .CORE_HRESETn (CORE_HRESETn), // Core AHB Reset
+ .CORE_DCLK (CORE_DCLK), // Core Debug clock
+ .CORE_DBGRESETn (CORE_DBGRESETn), // Core Debug reset
+
+ // System Generated Clocks and Resets
+ .SYS_HCLK (SYS_HCLK), // System AHB Clock
+ .SYS_HRESETn (SYS_HRESETn), // System AHB Reset
+ .SYS_PORESETn (SYS_PORESETn), // System Power on reset
+
+ // System Reset Request
+ .SYS_SYSRESETREQ (SYS_SYSRESETREQ), // System Reset Request
+
+ // Power Management Control Signals
+ .SYS_PMUENABLE (SYS_PMUENABLE), // PMU Enable from System Register
+ .CORE_WAKEUP (CORE_WAKEUP), // Wake-up Signaling from Core
+ .CORE_SLEEPDEEP (CORE_SLEEPDEEP), // Debug Power Up Request
+ .CORE_GATEHCLK (CORE_GATEHCLK), // Control Signal from Core to Control Clock Gating of HCLK
+
+ // Power Management Request signals
+ .CORE_CDBGPWRUPREQ (CORE_CDBGPWRUPREQ), // Core Debug Power Up Request
+ .CORE_WICENREQ (CORE_WICENREQ), // Core WIC enable request from PMU
+ .CORE_SLEEPHOLDREQn (CORE_SLEEPHOLDREQn), // Core Sleep Hold Request
+
+ .SYS_PRMURESETREQ (SYS_PRMURESETREQ), // Core Control System Reset Request
+ .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ), // Core Power Management Unit Debug Reset Request
+
+ // Power Management Ackowledge signals
+ .CORE_WICENACK (CORE_WICENACK), // Wake-on-Interrupt Enable ACK from Core
+ .CORE_SLEEPHOLDACKn (CORE_SLEEPHOLDACKn), // Sleep Hold Acknowledgement
+ .CORE_CDBGPWRUPACK (CORE_CDBGPWRUPACK) // Core Debug Power Up Acknowledge
+ );
+
+ // -------------------------------
+ // SysTick signals
+ // -------------------------------
+ // SysTick Timer Signals
+ wire CORE_STCLKEN;
+ wire [25:0] CORE_STCALIB;
+
+ // SysTick Control Instantiation
+ slcorem0_stclkctrl #(
+ .DIV_RATIO (18'd01000)
+ ) u_stclkctrl (
+ .FCLK (SYS_FCLK),
+ .SYSRESETn (SYS_SYSRESETn),
+
+ .STCLKEN (CORE_STCLKEN),
+ .STCALIB (CORE_STCALIB)
+ );
+
+ // -------------------------------
+ // Cortex-M0 CPU Instantiation
+ // -------------------------------
+ // Processor status
+ wire [2:0] CORE_CODEHINTDE;
+ wire CORE_SPECHTRANS;
+ wire CORE_CODENSEQ;
+ wire CORE_SHAREABLE;
+
+ // Cortex-M0 Logic Instantiation
+ CORTEXM0INTEGRATION #(
+ .ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT) // Number of DWT comparators
+ ) u_cortex_m0_integration (
+ // System inputs
+ .FCLK (SYS_FCLK), // FCLK
+ .SCLK (CORE_SCLK), // SCLK generated from PMU
+ .HCLK (CORE_HCLK), // HCLK generated from PMU
+ .DCLK (CORE_DCLK), // DCLK generated from PMU
+ .PORESETn (SYS_PORESETn),
+ .HRESETn (CORE_HRESETn),
+ .DBGRESETn (CORE_DBGRESETn),
+ .RSTBYPASS (SYS_TESTMODE),
+ .SE (SYS_SCANENABLE),
+
+ // Power management inputs
+ .SLEEPHOLDREQn (CORE_SLEEPHOLDREQn),
+ .WICENREQ (CORE_WICENREQ),
+ .CDBGPWRUPACK (CORE_CDBGPWRUPACK),
+
+ // Power management outputs
+ .SLEEPHOLDACKn (CORE_SLEEPHOLDACKn),
+ .WICENACK (CORE_WICENACK),
+ .CDBGPWRUPREQ (CORE_CDBGPWRUPREQ),
+
+ .WAKEUP (CORE_WAKEUP),
+ .WICSENSE ( ),
+ .GATEHCLK (CORE_GATEHCLK),
+ .SYSRESETREQ (CORE_SYSRESETREQ),
+
+ // System bus
+ .HADDR (HADDR),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HBURST (HBURST),
+ .HPROT (HPROT),
+ .HMASTLOCK (HMASTLOCK),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HRDATA (HRDATA),
+ .HREADY (HREADY),
+ .HRESP (HRESP),
+ .HMASTER ( ),
+
+ .CODEHINTDE (CORE_CODEHINTDE),
+ .SPECHTRANS (CORE_SPECHTRANS),
+ .CODENSEQ (CORE_CODENSEQ),
+
+ // Interrupts
+ .IRQ (CORE_IRQ[31:0]),
+ .NMI (CORE_NMI),
+ .IRQLATENCY (8'h00),
+
+ .ECOREVNUM (28'h0),
+
+ // Systick
+ .STCLKEN (CORE_STCLKEN),
+ .STCALIB (CORE_STCALIB),
+
+ // Debug - JTAG or Serial wire
+ .nTRST (1'b1),
+ .SWDITMS (CORE_SWDI),
+ .SWCLKTCK (CORE_SWCLK),
+ .TDI (1'b0),
+ .TDO ( ),
+ .nTDOEN ( ),
+ .SWDO (CORE_SWDO),
+ .SWDOEN (CORE_SWDOEN),
+
+ .DBGRESTART (1'b0), // Unused - Multi-Core synchronous restart from halt
+ .DBGRESTARTED ( ), // Unused - Multi-Core synchronous restart from halt
+
+ // Event communication
+ .TXEV (CORE_TXEV),
+ .RXEV (CORE_RXEV),
+ .EDBGRQ (1'b0), // Unused - Multi-Core synchronous halt request
+
+ // Status output - TODO: Map into APB Register Block
+ .HALTED ( ),
+ .LOCKUP (CORE_LOCKUP),
+ .SLEEPING (CORE_SLEEPING),
+ .SLEEPDEEP (CORE_SLEEPDEEP)
+ );
+
+endmodule
diff --git a/src/verilog/slcorem0_prmu.v b/src/verilog/slcorem0_prmu.v
new file mode 100644
index 0000000..baf39ec
--- /dev/null
+++ b/src/verilog/slcorem0_prmu.v
@@ -0,0 +1,155 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 PRMU - Cortex-M0 CPU Power and Reset Management Unit
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module slcorem0_prmu #(
+ parameter CLKGATE_PRESENT = 0
+)(
+ // Input Clocks and Resets
+ input wire SYS_FCLK, // Free running clock
+ input wire SYS_SYSRESETn, // System Reset
+ input wire SYS_SCANENABLE, // Scan Mode Enable
+ input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // Generated Clocks and Resets
+ output wire CORE_SCLK, // System clock
+ output wire CORE_HCLK, // AHB Clock
+ output wire CORE_HRESETn, // AHB Reset
+ output wire CORE_DCLK, // Debug clock
+ output wire CORE_DBGRESETn, // Debug reset
+
+ output wire SYS_HCLK, // Power on reset
+ output wire SYS_HRESETn, // Power on reset
+ output wire SYS_PORESETn, // Power on reset
+
+ // System Reset Request
+ input wire SYS_SYSRESETREQ, // System Reset Request
+
+ // Power Management Control Signals
+ input wire SYS_PMUENABLE, // PMU Enable from System Register
+ input wire CORE_WAKEUP, // Wakeup Signaling from Core
+ input wire CORE_SLEEPDEEP, // Debug Power Up Request
+ input wire CORE_GATEHCLK, // Control Signal from Core to Control Clock Gating of HCLK
+
+ // Power Management Request signals
+ input wire CORE_CDBGPWRUPREQ, // Core Debug Power Up Request
+ output wire CORE_WICENREQ, // WIC enable request from PMU
+ output wire CORE_SLEEPHOLDREQn, // Core Sleep Hold Request
+
+ // System Reset Request Signals
+ output wire SYS_PRMURESETREQ, // Power and Reset Management System Reset Request
+ output wire SYS_PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
+
+ // Power Management Ackowledge signals
+ input wire CORE_WICENACK, // Wake-on-Interrupt Enable ACK from Core
+ input wire CORE_SLEEPHOLDACKn, // Sleep Hold Acknowledgement
+ output wire CORE_CDBGPWRUPACK // Core Debug Power Up Acknowledge
+);
+
+ // -------------------------------
+ // Cortex-M0 Control System Reset Req
+ // -------------------------------
+ wire CORE_RSTCTLHRESETREQ;
+ wire CORE_PMUHRESETREQ;
+
+ assign SYS_PRMURESETREQ = CORE_PMUHRESETREQ | CORE_RSTCTLHRESETREQ;
+
+ // -------------------------------
+ // Core Power Down Detection
+ // -------------------------------
+ // System Power Down Signals
+ wire CORE_SYSPWRDOWN;
+ wire CORE_SYSPWRDOWNACK;
+
+ // Debug Power Down Signals
+ wire CORE_DBGPWRDOWN;
+ wire CORE_DBGPWRDOWNACK;
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign CORE_SYSPWRDOWNACK = CORE_SYSPWRDOWN;
+ assign CORE_DBGPWRDOWNACK = CORE_DBGPWRDOWN;
+
+ // -------------------------------
+ // Core Power Management Unit
+ // -------------------------------
+ // Connectivity - Clock Generation
+ wire CORE_HCLKG; // Gated Core HCLK
+ wire CORE_DCLKG; // Gated Core DCLK
+ wire CORE_SCLKG; // Gated Core SCLK
+
+ assign CORE_HCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_HCLKG;
+ assign CORE_DCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_DCLKG;
+ assign CORE_SCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_SCLKG;
+
+ // System HCLK needs to be assigned to System Free-running Clock
+ // so other managers can still access bus when CPU is sleeping
+ assign SYS_HCLK = SYS_FCLK;
+
+ // Power Management Unit Instantiation
+ cortexm0_pmu u_cortexm0_pmu (
+ // Power Management Unit Inputs
+ .FCLK (SYS_FCLK),
+ .PORESETn (SYS_PORESETn),
+ .HRESETREQ (SYS_SYSRESETREQ), // from Cores / Watchdog / Debug Controller
+ .PMUENABLE (SYS_PMUENABLE), // from System Controller
+ .WICENACK (CORE_WICENACK), // from WIC in integration
+
+ .WAKEUP (CORE_WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CORE_CDBGPWRUPREQ),
+
+ .SLEEPDEEP (CORE_SLEEPDEEP),
+ .SLEEPHOLDACKn (CORE_SLEEPHOLDACKn),
+ .GATEHCLK (CORE_GATEHCLK),
+ .SYSPWRDOWNACK (CORE_SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (CORE_DBGPWRDOWNACK),
+ .CGBYPASS (SYS_TESTMODE),
+
+ // Power Management Unit Outputs
+ .HCLK (CORE_HCLKG),
+ .DCLK (CORE_DCLKG),
+ .SCLK (CORE_SCLKG),
+ .WICENREQ (CORE_WICENREQ),
+ .CDBGPWRUPACK (CORE_CDBGPWRUPACK),
+ .SYSISOLATEn ( ),
+ .SYSRETAINn ( ),
+ .SYSPWRDOWN (CORE_SYSPWRDOWN),
+ .DBGISOLATEn ( ),
+ .DBGPWRDOWN (CORE_DBGPWRDOWN),
+ .SLEEPHOLDREQn (CORE_SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
+ .PMUHRESETREQ (CORE_PMUHRESETREQ)
+ );
+
+ // -------------------------------
+ // Reset Control
+ // -------------------------------
+ slcorem0_rstctrl u_rstctrl (
+ // Inputs
+ .SYS_GLOBALRESETn (SYS_SYSRESETn),
+ .SYS_FCLK (SYS_FCLK),
+ .SYS_HCLK (SYS_HCLK),
+ .CORE_HCLK (CORE_HCLK),
+ .CORE_DCLK (CORE_DCLK),
+ .SYS_SYSRESETREQ (SYS_SYSRESETREQ),
+ .CORE_PMUHRESETREQ (CORE_PMUHRESETREQ),
+ .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
+ .SYS_RSTBYPASS (SYS_TESTMODE),
+ .SYS_SE (SYS_SCANENABLE),
+
+ // Outputs
+ .SYS_HRESETREQ (CORE_RSTCTLHRESETREQ),
+ .SYS_PORESETn (SYS_PORESETn),
+ .SYS_HRESETn (SYS_HRESETn),
+ .CORE_HRESETn (CORE_HRESETn),
+ .CORE_DBGRESETn (CORE_DBGRESETn)
+ );
+endmodule
\ No newline at end of file
diff --git a/src/verilog/slcorem0_rstctrl.v b/src/verilog/slcorem0_rstctrl.v
new file mode 100644
index 0000000..78dd4aa
--- /dev/null
+++ b/src/verilog/slcorem0_rstctrl.v
@@ -0,0 +1,138 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 Reset Control - Cortex-M0 Reset Control
+// - Added additional reset synchroniser to allow for synchronisation of both
+// Core and System versions of HRESETn (system works when CPU is powered down)
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2009 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// SVN Information
+//
+// Checked In : $Date: 2009-03-21 16:43:18 +0000 (Sat, 21 Mar 2009) $
+//
+// Revision : $Revision: 104871 $
+//
+// Release Information : Cortex-M0-AT510-r0p0-00rel0
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// CORTEX-M0 EXAMPLE RESET CONTROLLER
+// This module is designed as an example reset controller for the Cortex-M0
+// // processor It takes a global reset that can be asynchronously asserted
+// and generates from it synchronously asserted and deasserted resets based
+// on synchronous reset requests
+// This module is intended to interface to the example PMU provided (cortexm0_pmu.v)
+// You can modify this module to suit your requirements
+//-----------------------------------------------------------------------------
+
+module slcorem0_rstctrl
+ (/*AUTOARG*/
+ // Outputs
+ SYS_PORESETn, SYS_HRESETn, CORE_HRESETn, CORE_DBGRESETn, SYS_HRESETREQ,
+ // Inputs
+ SYS_GLOBALRESETn, SYS_FCLK, CORE_HCLK, CORE_DCLK, SYS_HCLK, SYS_SYSRESETREQ,
+ CORE_PMUHRESETREQ, SYS_PMUDBGRESETREQ, SYS_RSTBYPASS, SYS_SE
+ );
+
+ input SYS_GLOBALRESETn; // Global asynchronous reset
+ input SYS_FCLK; // System Free running clock
+ input SYS_HCLK; // AHB clock (connect to HCLK of non-cortex m0 devices)
+ input CORE_HCLK; // AHB clock (connect to HCLK of CORTEXM0INTEGRATION)
+ input CORE_DCLK; // Debug clock (connect to DCLK of CORTEXM0INTEGRATION)
+ input SYS_SYSRESETREQ; // Synchronous (to HCLK) request for HRESETn from system
+ input CORE_PMUHRESETREQ; // Synchronous (to CORE_HCLK) request for HRESETn from PMU
+ input SYS_PMUDBGRESETREQ; // Synchronous (to CORE_DCLK) request for DBGRESETn from PMU
+ input SYS_RSTBYPASS; // Reset synchroniser bypass (for DFT)
+ input SYS_SE; // Scan Enable (for DFT)
+
+ output SYS_HRESETREQ; // Synchronous (to FCLK) indication of HRESET request
+ output SYS_PORESETn; // Connect to PORESETn of CORTEXM0INTEGRATION
+ output SYS_HRESETn; // Connect to HRESETn of AHB System
+ output CORE_HRESETn; // Connect to HRESETn of CORTEXM0INTEGRATION
+ output CORE_DBGRESETn; // Connect to DBGRESETn of CORTEXM0INTEGRATION
+
+ // Sample synchronous requests to assert HRESETn
+ // Sources:
+ // 1 - System (SYSRESETREQ)
+ // 2 - PMU (PMUHRESETREQ)
+ wire h_reset_req_in = SYS_SYSRESETREQ | CORE_PMUHRESETREQ;
+
+ cm0_rst_send_set u_hreset_req
+ (.RSTn (SYS_PORESETn),
+ .CLK (SYS_FCLK),
+ .RSTREQIN (h_reset_req_in),
+ .RSTREQOUT (SYS_HRESETREQ)
+ );
+
+ // Sample synchronous requests to assert DBGRESETn
+ wire dbg_reset_req_sync;
+
+ cm0_rst_send_set u_dbgreset_req
+ (.RSTn (SYS_PORESETn),
+ .CLK (SYS_FCLK),
+ .RSTREQIN (SYS_PMUDBGRESETREQ),
+ .RSTREQOUT (dbg_reset_req_sync)
+ );
+
+ // --------------------
+ // Reset synchronisers
+ // --------------------
+
+ cm0_rst_sync u_sys_poresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (1'b0),
+ .CLK (SYS_FCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (SYS_PORESETn)
+ );
+
+ cm0_rst_sync u_sys_hresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (SYS_HRESETREQ),
+ .CLK (SYS_HCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (SYS_HRESETn)
+ );
+
+ cm0_rst_sync u_core_hresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (SYS_HRESETREQ),
+ .CLK (CORE_HCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (CORE_HRESETn)
+ );
+
+ cm0_rst_sync u_core_dbgresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (dbg_reset_req_sync),
+ .CLK (CORE_DCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (CORE_DBGRESETn)
+ );
+
+endmodule // cortexm0_rst_ctl
+
+
+
diff --git a/src/verilog/slcorem0_stclkctrl.v b/src/verilog/slcorem0_stclkctrl.v
new file mode 100644
index 0000000..4f7c443
--- /dev/null
+++ b/src/verilog/slcorem0_stclkctrl.v
@@ -0,0 +1,89 @@
+//-----------------------------------------------------------------------------
+// SLCore-M0 SysTick controller adapted from Arm CMSDK Simple control for SysTick signals for Cortex-M processor
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple control for SysTick signals for Cortex-M processor
+//-----------------------------------------------------------------------------
+
+module slcorem0_stclkctrl #(
+ // Ratio between FCLK and SysTck reference clock
+ parameter DIV_RATIO = 18'd01000,
+
+ // Divide by half for each phase
+ parameter DIVIDER_RELOAD = (DIV_RATIO>>1)-1
+ )(
+ input wire FCLK, // Free running clock
+ input wire SYSRESETn, // System reset
+ output wire STCLKEN, // SysTick clock
+ output wire [25:0] STCALIB // SysTick calibration
+ );
+
+ reg [17:0] reg_clk_divider;
+ reg reg_stclken;
+
+ assign STCALIB[25] = 1'b0; // NoRef - reference clock provided
+ assign STCALIB[24] = 1'b1; // Skew - reference info not available
+ assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value set to 0, indicate this value is not used
+
+ // Divider
+ wire [17:0] reg_clk_div_min1 = reg_clk_divider - 1;
+ always @(posedge FCLK or negedge SYSRESETn)
+ begin
+ if (~SYSRESETn)
+ reg_clk_divider <= {18{1'b0}};
+ else
+ begin
+ if (|reg_clk_divider)
+ reg_clk_divider <= reg_clk_div_min1[17:0];
+ else
+ reg_clk_divider <= DIVIDER_RELOAD[17:0];
+ end
+ end
+
+ // Toggle register
+ always @(posedge FCLK or negedge SYSRESETn)
+ begin
+ if (~SYSRESETn)
+ reg_stclken <= 1'b0;
+ else
+ begin
+ if (reg_clk_divider==18'h00000)
+ reg_stclken <= ~reg_stclken;
+ end
+ end
+
+ // Connect to top level
+ assign STCLKEN = reg_stclken;
+
+endmodule
+
--
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