diff --git a/flist/slcorem0.flist b/flist/slcorem0_ip.flist
similarity index 51%
rename from flist/slcorem0.flist
rename to flist/slcorem0_ip.flist
index a319ca1ee2f2265a03c9d038233a9cd20b214f2c..4adc97d16d50ca87436ed7ec777f548e9a2ea479 100644
--- a/flist/slcorem0.flist
+++ b/flist/slcorem0_ip.flist
@@ -20,18 +20,4 @@ $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_prmu.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_stclkctrl.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_rstctrl.v
-
-// =============    Cortex M0 IP search path    =============
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
--y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
-
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+$(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_integration.v