diff --git a/src/verilog/slcorem0.v b/src/verilog/slcorem0.v
index a215da64b353541e64f0e8e06535d4d49e6b6721..89b91be9bdc01641631f6ca4be12a97493f70d65 100644
--- a/src/verilog/slcorem0.v
+++ b/src/verilog/slcorem0.v
@@ -32,8 +32,8 @@ module slcorem0 #(
input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
// System Reset Request Signals
- input wire SYS_SYSRESETREQ, // System Request from System Managers
- output wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
+ input wire SYS_SYSRESETREQ, // System Request from System Managers
+ output wire CORE_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
// Generated Clocks and Resets
output wire SYS_PORESETn, // System Power On Reset
@@ -41,8 +41,8 @@ module slcorem0 #(
output wire SYS_HRESETn, // AHB and System reset
// Power Management Signals
- input wire SYS_PMUENABLE, // Power Management Enable
- output wire SYS_PMUDBGRESETREQ, // Power Management Debug Reset Req
+ input wire CORE_PMUENABLE, // Power Management Enable
+ output wire CORE_PMUDBGRESETREQ, // Power Management Debug Reset Req
// AHB Lite port
output wire [31:0] HADDR, // Address bus
@@ -121,7 +121,7 @@ module slcorem0 #(
.SYS_SYSRESETREQ (SYS_SYSRESETREQ), // System Reset Request
// Power Management Control Signals
- .SYS_PMUENABLE (SYS_PMUENABLE), // PMU Enable from System Register
+ .CORE_PMUENABLE (CORE_PMUENABLE), // PMU Enable from System Register
.CORE_WAKEUP (CORE_WAKEUP), // Wake-up Signaling from Core
.CORE_SLEEPDEEP (CORE_SLEEPDEEP), // Debug Power Up Request
.CORE_GATEHCLK (CORE_GATEHCLK), // Control Signal from Core to Control Clock Gating of HCLK
@@ -131,8 +131,8 @@ module slcorem0 #(
.CORE_WICENREQ (CORE_WICENREQ), // Core WIC enable request from PMU
.CORE_SLEEPHOLDREQn (CORE_SLEEPHOLDREQn), // Core Sleep Hold Request
- .SYS_PRMURESETREQ (SYS_PRMURESETREQ), // Core Control System Reset Request
- .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ), // Core Power Management Unit Debug Reset Request
+ .CORE_PRMURESETREQ (CORE_PRMURESETREQ), // Core Control System Reset Request
+ .CORE_PMUDBGRESETREQ (CORE_PMUDBGRESETREQ), // Core Power Management Unit Debug Reset Request
// Power Management Ackowledge signals
.CORE_WICENACK (CORE_WICENACK), // Wake-on-Interrupt Enable ACK from Core
diff --git a/src/verilog/slcorem0_prmu.v b/src/verilog/slcorem0_prmu.v
index 3fc0f25fa135ccf0d0f0864466d0aa08f9a5be9a..d7dbea6c40832f49341bee3bea8a4a86fe43266d 100644
--- a/src/verilog/slcorem0_prmu.v
+++ b/src/verilog/slcorem0_prmu.v
@@ -33,7 +33,7 @@ module slcorem0_prmu #(
input wire SYS_SYSRESETREQ, // System Reset Request
// Power Management Control Signals
- input wire SYS_PMUENABLE, // PMU Enable from System Register
+ input wire CORE_PMUENABLE, // PMU Enable from System Register
input wire CORE_WAKEUP, // Wakeup Signaling from Core
input wire CORE_SLEEPDEEP, // Debug Power Up Request
input wire CORE_GATEHCLK, // Control Signal from Core to Control Clock Gating of HCLK
@@ -44,8 +44,8 @@ module slcorem0_prmu #(
output wire CORE_SLEEPHOLDREQn, // Core Sleep Hold Request
// System Reset Request Signals
- output wire SYS_PRMURESETREQ, // Power and Reset Management System Reset Request
- output wire SYS_PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
+ output wire CORE_PRMURESETREQ, // Power and Reset Management System Reset Request
+ output wire CORE_PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
// Power Management Ackowledge signals
input wire CORE_WICENACK, // Wake-on-Interrupt Enable ACK from Core
@@ -59,7 +59,7 @@ module slcorem0_prmu #(
wire CORE_RSTCTLHRESETREQ;
wire CORE_PMUHRESETREQ;
- assign SYS_PRMURESETREQ = CORE_PMUHRESETREQ | CORE_RSTCTLHRESETREQ;
+ assign CORE_PRMURESETREQ = CORE_PMUHRESETREQ | CORE_RSTCTLHRESETREQ;
// -------------------------------
// Core Power Down Detection
@@ -100,7 +100,7 @@ module slcorem0_prmu #(
.FCLK (SYS_FCLK),
.PORESETn (SYS_PORESETn),
.HRESETREQ (SYS_SYSRESETREQ), // from Cores / Watchdog / Debug Controller
- .PMUENABLE (SYS_PMUENABLE), // from System Controller
+ .PMUENABLE (CORE_PMUENABLE), // from System Controller
.WICENACK (CORE_WICENACK), // from WIC in integration
.WAKEUP (CORE_WAKEUP), // from WIC in integration
@@ -125,7 +125,7 @@ module slcorem0_prmu #(
.DBGISOLATEn ( ),
.DBGPWRDOWN (CORE_DBGPWRDOWN),
.SLEEPHOLDREQn (CORE_SLEEPHOLDREQn),
- .PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
+ .PMUDBGRESETREQ (CORE_PMUDBGRESETREQ),
.PMUHRESETREQ (CORE_PMUHRESETREQ)
);
@@ -134,16 +134,16 @@ module slcorem0_prmu #(
// -------------------------------
slcorem0_rstctrl u_rstctrl (
// Inputs
- .SYS_GLOBALRESETn (SYS_SYSRESETn),
- .SYS_FCLK (SYS_FCLK),
- .SYS_HCLK (SYS_HCLK),
- .CORE_HCLK (CORE_HCLK),
- .CORE_DCLK (CORE_DCLK),
- .SYS_SYSRESETREQ (SYS_SYSRESETREQ),
- .CORE_PMUHRESETREQ (CORE_PMUHRESETREQ),
- .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
- .SYS_RSTBYPASS (SYS_TESTMODE),
- .SYS_SE (SYS_SCANENABLE),
+ .SYS_GLOBALRESETn (SYS_SYSRESETn),
+ .SYS_FCLK (SYS_FCLK),
+ .SYS_HCLK (SYS_HCLK),
+ .CORE_HCLK (CORE_HCLK),
+ .CORE_DCLK (CORE_DCLK),
+ .SYS_SYSRESETREQ (SYS_SYSRESETREQ),
+ .CORE_PMUHRESETREQ (CORE_PMUHRESETREQ),
+ .CORE_PMUDBGRESETREQ (CORE_PMUDBGRESETREQ),
+ .SYS_RSTBYPASS (SYS_TESTMODE),
+ .SYS_SE (SYS_SCANENABLE),
// Outputs
.SYS_HRESETREQ (CORE_RSTCTLHRESETREQ),
diff --git a/src/verilog/slcorem0_rstctrl.v b/src/verilog/slcorem0_rstctrl.v
index 78dd4aa00c8ed6b752bb74670dabd1691a58a355..6d26026d5e8d6b81e099942d06db3cd638203f62 100644
--- a/src/verilog/slcorem0_rstctrl.v
+++ b/src/verilog/slcorem0_rstctrl.v
@@ -49,7 +49,7 @@ module slcorem0_rstctrl
SYS_PORESETn, SYS_HRESETn, CORE_HRESETn, CORE_DBGRESETn, SYS_HRESETREQ,
// Inputs
SYS_GLOBALRESETn, SYS_FCLK, CORE_HCLK, CORE_DCLK, SYS_HCLK, SYS_SYSRESETREQ,
- CORE_PMUHRESETREQ, SYS_PMUDBGRESETREQ, SYS_RSTBYPASS, SYS_SE
+ CORE_PMUHRESETREQ, CORE_PMUDBGRESETREQ, SYS_RSTBYPASS, SYS_SE
);
input SYS_GLOBALRESETn; // Global asynchronous reset
@@ -59,7 +59,7 @@ module slcorem0_rstctrl
input CORE_DCLK; // Debug clock (connect to DCLK of CORTEXM0INTEGRATION)
input SYS_SYSRESETREQ; // Synchronous (to HCLK) request for HRESETn from system
input CORE_PMUHRESETREQ; // Synchronous (to CORE_HCLK) request for HRESETn from PMU
- input SYS_PMUDBGRESETREQ; // Synchronous (to CORE_DCLK) request for DBGRESETn from PMU
+ input CORE_PMUDBGRESETREQ; // Synchronous (to CORE_DCLK) request for DBGRESETn from PMU
input SYS_RSTBYPASS; // Reset synchroniser bypass (for DFT)
input SYS_SE; // Scan Enable (for DFT)
@@ -88,7 +88,7 @@ module slcorem0_rstctrl
cm0_rst_send_set u_dbgreset_req
(.RSTn (SYS_PORESETn),
.CLK (SYS_FCLK),
- .RSTREQIN (SYS_PMUDBGRESETREQ),
+ .RSTREQIN (CORE_PMUDBGRESETREQ),
.RSTREQOUT (dbg_reset_req_sync)
);